FC2カウンター FPGAの部屋 Spartan-3A Starter KitでMIGを使用する4(UCFを変更してロード)
FC2ブログ

FPGAやCPLDの話題やFPGA用のツールの話題などです。 マニアックです。 日記も書きます。

FPGAの部屋

FPGAの部屋の有用と思われるコンテンツのまとめサイトを作りました。Xilinx ISEの初心者の方には、FPGAリテラシーおよびチュートリアルのページをお勧めいたします。

Spartan-3A Starter KitでMIGを使用する4(UCFを変更してロード)

Spartan-3A Starter KitでMIGを使用する3(ボードの信号では生成できなかった)”の続き。

twitterで@osamu_takeuchiさんからMIGのピン配置変更についてのやり方を教えていただいたので、もう一度やってみることにした。参照サイト、”電気回路/HDL/Xilinx Memory Interface Generator (MIG) による DDR2 SDRAM のアクセス

それによると、MIGで一度生成したIPのUCFを希望のピン配置に書き換えて、MIG Output OptionダイアログでVerify UCF and Update Design and UCFのラジオボタンを選択するそうだ。
MIG_17_110509.png

早速やってみることにした。mig_3_61_4.ucfのLOC制約をSpartan-3A Starter Kitのピン配置に合わせて書き換えた。変更した部分を下に示す。

NET "cntrl0_ddr2_ck[0]" LOC = "M1" ; #bank 3
NET "cntrl0_ddr2_ck_n[0]" LOC = "M2" ; #bank 3
NET "cntrl0_ddr2_dm[0]" LOC = "J3" ; #bank 3
NET "cntrl0_ddr2_dm[1]" LOC = "E3" ; #bank 3
NET "cntrl0_ddr2_a[12]" LOC = "Y2" ; #bank 3
NET "cntrl0_ddr2_a[11]" LOC = "V1" ; #bank 3
NET "cntrl0_ddr2_a[10]" LOC = "T3" ; #bank 3
NET "cntrl0_ddr2_a[9]" LOC = "W2" ; #bank 3
NET "cntrl0_ddr2_a[8]" LOC = "W1" ; #bank 3
NET "cntrl0_ddr2_a[7]" LOC = "Y1" ; #bank 3
NET "cntrl0_ddr2_a[6]" LOC = "U1" ; #bank 3
NET "cntrl0_ddr2_a[5]" LOC = "U4" ; #bank 3
NET "cntrl0_ddr2_a[4]" LOC = "U2" ; #bank 3
NET "cntrl0_ddr2_a[3]" LOC = "U3" ; #bank 3
NET "cntrl0_ddr2_a[2]" LOC = "R1" ; #bank 3
NET "cntrl0_ddr2_a[1]" LOC = "T4" ; #bank 3
NET "cntrl0_ddr2_a[0]" LOC = "R2" ; #bank 3
NET "cntrl0_ddr2_ba[1]" LOC = "R3" ; #bank 3
NET "cntrl0_ddr2_ba[0]" LOC = "P3" ; #bank 3
NET "cntrl0_ddr2_cke" LOC = "N3" ; #bank 3
NET "cntrl0_ddr2_cs_n" LOC = "M5" ; #bank 3
NET "cntrl0_ddr2_ras_n" LOC = "M3" ; #bank 3
NET "cntrl0_ddr2_cas_n" LOC = "M4" ; #bank 3
NET "cntrl0_ddr2_we_n" LOC = "N4" ; #bank 3
NET "cntrl0_ddr2_odt" LOC = "P1" ; #bank 3
NET "cntrl0_ddr2_dq[15]" LOC = "F3"; #bank 3
NET "cntrl0_ddr2_dq[14]" LOC = "G3"; #bank 3
NET "cntrl0_ddr2_dq[13]" LOC = "F1"; #bank 3
NET "cntrl0_ddr2_dq[12]" LOC = "H5"; #bank 3
NET "cntrl0_ddr2_dq[11]" LOC = "H6"; #bank 3
NET "cntrl0_ddr2_dq[10]" LOC = "G1"; #bank 3
NET "cntrl0_ddr2_dq[9]" LOC = "G4"; #bank 3
NET "cntrl0_ddr2_dq[8]" LOC = "F2"; #bank 3
NET "cntrl0_ddr2_dq[7]" LOC = "H2"; #bank 3
NET "cntrl0_ddr2_dq[6]" LOC = "K4"; #bank 3
NET "cntrl0_ddr2_dq[5]" LOC = "L1"; #bank 3
NET "cntrl0_ddr2_dq[4]" LOC = "L5"; #bank 3
NET "cntrl0_ddr2_dq[3]" LOC = "L3"; #bank 3
NET "cntrl0_ddr2_dq[2]" LOC = "K1"; #bank 3
NET "cntrl0_ddr2_dq[1]" LOC = "K5"; #bank 3
NET "cntrl0_ddr2_dq[0]" LOC = "H1"; #bank 3
NET "cntrl0_ddr2_dqs[1]" LOC = "K6"; #bank 3
NET "cntrl0_ddr2_dqs_n[1]" LOC = "J5"; #bank 3
NET "cntrl0_ddr2_dqs[0]" LOC = "K3"; #bank 3
NET "cntrl0_ddr2_dqs_n[0]" LOC = "K2"; #bank 3
NET "cntrl0_rst_dqs_div_in" LOC = "H4"; #bank 3
NET "cntrl0_rst_dqs_div_out" LOC = "H3"; #bank 3
NET "reset_in_n" LOC = "T15" ; #bank 3


Project ManagerのIPのmig_3_61_4をダブルクリックして、MIGのダイアログを出す。
MIG Output OptionダイアログでVerify UCF and Update Design and UCFのラジオボタンを選択する。
MIG_33_110512.png

Load mig prj and UCF FileでLoad UCF Fileに書き換えたUCFファイを指定する。
MIG_34_110512.png

Summaryが出た。
MIG_35_110512.png

次に進んだら、大量にワーニングやエラーが出てしまった。
MIG_36_110512.png

エラーが出ているのでFinishボタンをクリックすると終了してしまった。

ワーニングやエラーの内容を示す。

Verification Report

Generated by MIG Version 3.6.1 on 金 5 13 05:35:49 2011
Reading design libraries of xc3s700a-fg484... successful !

/*******************************************************/
/* Controller 0
/*******************************************************/
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/five-slice_x3y27" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/four-slice_x2y26" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/one-slice_x2y27" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/six-slice_x3y26" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/three-slice_x2y26" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/two-slice_x2y27" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/five-slice_x1y27" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/four-slice_x0y26" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/one-slice_x0y27" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/six-slice_x1y26" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/three-slice_x0y26" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/two-slice_x0y27" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/five-g" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/four-f" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/one-f" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/six-g" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/three-g" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/two-g" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/five-g" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/four-f" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/one-f" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/six-g" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/three-g" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/two-g" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_0_wr_addr_inst/bit0-slice_x1y22" for Fifo write address or write enable of dqs[1] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_0_wr_addr_inst/bit1-slice_x1y22" for Fifo write address or write enable of dqs[1] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_0_wr_addr_inst/bit2-slice_x1y23" for Fifo write address or write enable of dqs[1] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_0_wr_addr_inst/bit3-slice_x1y23" for Fifo write address or write enable of dqs[1] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_1_wr_addr_inst/bit0-slice_x3y22" for Fifo write address or write enable of dqs[1] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_1_wr_addr_inst/bit1-slice_x3y22" for Fifo write address or write enable of dqs[1] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_1_wr_addr_inst/bit2-slice_x3y23" for Fifo write address or write enable of dqs[1] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_1_wr_addr_inst/bit3-slice_x3y23" for Fifo write address or write enable of dqs[1] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_en[1].fifo_0_wr_en_inst-slice_x1y25" for Fifo write address or write enable of dqs[1] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_en[1].fifo_1_wr_en_inst-slice_x3y25" for Fifo write address or write enable of dqs[1] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit7-slice_x2y30" allocated for dq[15] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit7-slice_x2y31" allocated for dq[15] is invalid.
ERROR: Trying to allocate dq[15] to a wrong PAD in an IO tile in the bank 3. All the even dq
signals (e.g. dq[0],dq[2]) should be allocated to the top pad and odd dq signals to
the bottom pad in an IO tile in the bank 3 for the selected Spartan device. Use FPGA
editor to know the PAD info of any pin.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit6-slice_x0y30" allocated for dq[14] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit6-slice_x0y31" allocated for dq[14] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit5-slice_x2y28" allocated for dq[13] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit5-slice_x2y29" allocated for dq[13] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit4-slice_x0y28" allocated for dq[12] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit4-slice_x0y29" allocated for dq[12] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit3-slice_x2y22" allocated for dq[11] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit3-slice_x2y23" allocated for dq[11] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit2-slice_x0y20" allocated for dq[10] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit2-slice_x0y21" allocated for dq[10] is invalid.
ERROR: Trying to allocate dq[10] to a wrong PAD in an IO tile in the bank 3. All the even dq
signals (e.g. dq[0],dq[2]) should be allocated to the top pad and odd dq signals to
the bottom pad in an IO tile in the bank 3 for the selected Spartan device. Use FPGA
editor to know the PAD info of any pin.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit1-slice_x2y20" allocated for dq[9] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit1-slice_x2y21" allocated for dq[9] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit0-slice_x0y18" allocated for dq[8] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit0-slice_x0y19" allocated for dq[8] is invalid.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/five-slice_x3y7" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/four-slice_x2y6" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/one-slice_x2y7" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/six-slice_x3y6" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/three-slice_x2y6" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/two-slice_x2y7" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/five-slice_x1y7" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/four-slice_x0y6" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/one-slice_x0y7" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/six-slice_x1y6" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/three-slice_x0y6" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/two-slice_x0y7" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/five-g" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/four-f" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/one-f" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/six-g" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/three-g" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/two-g" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/five-g" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/four-f" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/one-f" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/six-g" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/three-g" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/two-g" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_0_wr_addr_inst/bit0-slice_x1y2" for Fifo write address or write enable of dqs[0] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_0_wr_addr_inst/bit1-slice_x1y2" for Fifo write address or write enable of dqs[0] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_0_wr_addr_inst/bit2-slice_x1y3" for Fifo write address or write enable of dqs[0] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_0_wr_addr_inst/bit3-slice_x1y3" for Fifo write address or write enable of dqs[0] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_1_wr_addr_inst/bit0-slice_x3y2" for Fifo write address or write enable of dqs[0] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_1_wr_addr_inst/bit1-slice_x3y2" for Fifo write address or write enable of dqs[0] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_1_wr_addr_inst/bit2-slice_x3y3" for Fifo write address or write enable of dqs[0] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_1_wr_addr_inst/bit3-slice_x3y3" for Fifo write address or write enable of dqs[0] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_en[0].fifo_0_wr_en_inst-slice_x1y5" for Fifo write address or write enable of dqs[0] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_en[0].fifo_1_wr_en_inst-slice_x3y5" for Fifo write address or write enable of dqs[0] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit7-slice_x2y12" allocated for dq[7] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit7-slice_x2y13" allocated for dq[7] is invalid.
ERROR: Trying to allocate dq[7] to a wrong PAD in an IO tile in the bank 3. All the even dq
signals (e.g. dq[0],dq[2]) should be allocated to the top pad and odd dq signals to
the bottom pad in an IO tile in the bank 3 for the selected Spartan device. Use FPGA
editor to know the PAD info of any pin.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit6-slice_x0y12" allocated for dq[6] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit6-slice_x0y13" allocated for dq[6] is invalid.
ERROR: Trying to allocate dq[6] to a wrong PAD in an IO tile in the bank 3. All the even dq
signals (e.g. dq[0],dq[2]) should be allocated to the top pad and odd dq signals to
the bottom pad in an IO tile in the bank 3 for the selected Spartan device. Use FPGA
editor to know the PAD info of any pin.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit5-slice_x2y10" allocated for dq[5] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit5-slice_x2y11" allocated for dq[5] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit4-slice_x0y10" allocated for dq[4] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit4-slice_x0y11" allocated for dq[4] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit3-slice_x2y4" allocated for dq[3] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit3-slice_x2y5" allocated for dq[3] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit2-slice_x0y4" allocated for dq[2] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit2-slice_x0y5" allocated for dq[2] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit1-slice_x2y2" allocated for dq[1] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit1-slice_x2y3" allocated for dq[1] is invalid.
ERROR: Trying to allocate dq[1] to a wrong PAD in an IO tile in the bank 3. All the even dq
signals (e.g. dq[0],dq[2]) should be allocated to the top pad and odd dq signals to
the bottom pad in an IO tile in the bank 3 for the selected Spartan device. Use FPGA
editor to know the PAD info of any pin.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit0-slice_x0y2" allocated for dq[0] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit0-slice_x0y3" allocated for dq[0] is invalid.
ERROR: Trying to allocate dq[0] to a wrong PAD in an IO tile in the bank 3. All the even dq
signals (e.g. dq[0],dq[2]) should be allocated to the top pad and odd dq signals to
the bottom pad in an IO tile in the bank 3 for the selected Spartan device. Use FPGA
editor to know the PAD info of any pin.
WARNING: The signal reset_in_n is missing or allocated to invalid I/O.
WARNING:
Slice location constraint for delayed rst_dqs_div_out signal is not correct.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/five-slice_x1y14" for delayed rst_dqs_div_in signal is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/four-slice_x1y14" for delayed rst_dqs_div_in signal is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/one-slice_x0y15" for delayed rst_dqs_div_in signal is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/six-slice_x1y15" for delayed rst_dqs_div_in signal is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/three-slice_x0y15" for delayed rst_dqs_div_in signal is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/two-slice_x0y14" for delayed rst_dqs_div_in signal is invalid.

Verification completed. Found the following warnings.
Number of warnings in the input UCF = 108.

Verification completed. Found the following errors.
Number of errors in the input UCF = 6.


dqのパッド位置が悪いと言われている気がするが、もう少し、LOCだけのUCFとかでやってみようと思う。
  1. 2011年05月13日 05:48 |
  2. MIG
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