FC2カウンター FPGAの部屋 カメラ・インターフェースIPにAXI4 Lite Slave インターフェースを追加3(MPD, MUIファイルの作製)
FC2ブログ

FPGAやCPLDの話題やFPGA用のツールの話題などです。 マニアックです。 日記も書きます。

FPGAの部屋

FPGAの部屋の有用と思われるコンテンツのまとめサイトを作りました。Xilinx ISEの初心者の方には、FPGAリテラシーおよびチュートリアルのページをお勧めいたします。

カメラ・インターフェースIPにAXI4 Lite Slave インターフェースを追加3(MPD, MUIファイルの作製)

前回、シミュレーションを行なって、AXI4 Lite Slave インターフェースを追加したカメラ・インターフェースIPがうまく動作したようだった。そこで、MPDファイルとMUIファイルを作製した。

カメラ・インターフェースIPにAXI4 Lite Slave インターフェースを追加したので、MPDファイルとMUIファイルを書き換えた。下にMPDファイル (mt9d111_inf_axi_master_v2_1_0.mpd) を示す。(2013/04/07: s_axi_lite_awport と s_axi_lite_arport を削除しました。削除しなくても問題ないです。ChipScoepe AXI Monitor の信号には、s_axi_lite_awport と s_axi_lite_arport が存在します。詳しい経緯は”AXI4 Master IP にAXI4 Lite Slave を追加1(インプリメント)”を参照のこと)
(2013/04/20: s_axi_lite_rdata のVEC の値が間違っていたので、修正しました。詳しくは、”AXI4 Master IP にAXI4 Lite Slave を追加9(バグフィックス)”を参照のこと)


#-- DISCLAIMER OF LIABILITY
#--
#-- This file contains proprietary and confidential information of
#-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
#-- from Xilinx, and may be used, copied and/or disclosed only
#-- pursuant to the terms of a valid license agreement with Xilinx.
#--
#-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
#-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
#-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
#-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
#-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
#-- does not warrant that functions included in the Materials will
#-- meet the requirements of Licensee, or that the operation of the
#-- Materials will be uninterrupted or error-free, or that defects
#-- in the Materials will be corrected. Furthermore, Xilinx does
#-- not warrant or make any representations regarding use, or the
#-- results of the use, of the Materials in terms of correctness,
#-- accuracy, reliability or otherwise.
#--
#-- Xilinx products are not designed or intended to be fail-safe,
#-- or for use in any application requiring fail-safe performance,
#-- such as life-support or safety devices or systems, Class III
#-- medical devices, nuclear facilities, applications related to
#-- the deployment of airbags, or any other applications that could
#-- lead to death, personal injury or severe property or
#-- environmental damage (individually and collectively, "critical
#-- applications"). Customer assumes the sole risk and liability
#-- of any use of Xilinx products in critical applications,
#-- subject only to applicable laws and regulations governing
#-- limitations on product liability.
#--
#-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
#--
#-- This disclaimer and copyright notice must be retained as part
#-- of this file at all times.
#--###################################################################
##
## Name : mt9d111_inf_axi_master
## Desc : Microprocessor Peripheral Description
## : Automatically generated by PsfUtility
##
###################################################################

BEGIN mt9d111_inf_axi_master

## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION STYLE = MIX
OPTION DESC = mt9d111_inf_axi_master
OPTION LONG_DESC = An AXI Master Camera Interface
OPTION HDL = MIXED
OPTION RUN_NGCBUILD = FALSE

IO_INTERFACE IO_IF = mt9d111_inf

## Bus Interfaces
BUS_INTERFACE BUS = S_AXI_LITE, BUS_STD = AXI, BUS_TYPE = SLAVE
BUS_INTERFACE BUS = M_AXI, BUS_STD = AXI, BUS_TYPE = MASTER

## Generics for VHDL or Parameters for Verilog
PARAMETER C_S_AXI_LITE_ADDR_WIDTH = 9, DT = INTEGER, BUS = S_AXI_LITE
PARAMETER C_S_AXI_LITE_DATA_WIDTH = 32, DT = INTEGER, BUS = S_AXI_LITE
PARAMETER C_BASEADDR = 0xffffffff, DT = STD_LOGIC_VECTOR(31 downto 0), PAIR = C_HIGHADDR, ADDRESS = BASE, BUS = S_AXI_LITE, MIN_SIZE = 0x1000, ASSIGNMENT = REQUIRE, TYPE = NON_HDL
PARAMETER C_HIGHADDR = 0x00000000, DT = STD_LOGIC_VECTOR(31 downto 0), PAIR = C_BASEADDR, ADDRESS = HIGH, BUS = S_AXI_LITE, ASSIGNMENT = REQUIRE, TYPE = NON_HDL
PARAMETER C_S_AXI_LITE_PROTOCOL = AXI4LITE, DT = STRING, BUS = S_AXI_LITE, ASSIGNMENT = CONSTANT, TYPE = NON_HDL
PARAMETER C_S_AXI_LITE_SUPPORTS_READ = 1, DT = INTEGER, RANGE = (0,1), BUS = S_AXI_LITE, TYPE = NON_HDL
PARAMETER C_S_AXI_LITE_SUPPORTS_WRITE = 1, DT = INTEGER, RANGE = (0,1), BUS = S_AXI_LITE, TYPE = NON_HDL

PARAMETER C_M_AXI_SUPPORTS_THREADS = 0, DT = integer, RANGE = (0,1), TYPE = NON_HDL, BUS = M_AXI
PARAMETER C_M_AXI_THREAD_ID_WIDTH = 1, DT = integer, RANGE = (1:16), BUS = M_AXI
PARAMETER C_M_AXI_ADDR_WIDTH = 32, DT = integer, ASSIGNMENT = CONSTANT, BUS = M_AXI
PARAMETER C_M_AXI_DATA_WIDTH = 64, DT = integer, RANGE = (32, 64, 128, 256), BUS = M_AXI
PARAMETER C_M_AXI_PROTOCOL = AXI4, DT = string, TYPE = NON_HDL, VALUES = (AXI4 = AXI4, AXI4Lite = AXI4Lite), BUS = M_AXI
# Max number of write commands able to be issued without responses
# In this example, issued writes + unread writes will throttle write address channel
PARAMETER C_INTERCONNECT_M_AXI_WRITE_ISSUING = 8, DT = INTEGER, BUS = M_AXI
#Read Issuing in this example HDL will go as high as write issuing parameter
PARAMETER C_INTERCONNECT_M_AXI_READ_ISSUING = 8, DT = INTEGER, BUS = M_AXI, TYPE = NON_HDL
PARAMETER C_M_AXI_SUPPORTS_READ = 1, DT = integer, RANGE = (0,1), BUS = M_AXI #,TYPE = NON_HDL
PARAMETER C_M_AXI_SUPPORTS_WRITE = 1, DT = integer, RANGE = (0,1), BUS = M_AXI #,TYPE = NON_HDL
PARAMETER C_M_AXI_SUPPORTS_USER_SIGNALS = 0, DT = integer, RANGE = (0,1), TYPE = NON_HDL, BUS = M_AXI
PARAMETER C_M_AXI_AWUSER_WIDTH = 1, DT = integer, ISVALID = (C_M_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = M_AXI
PARAMETER C_M_AXI_ARUSER_WIDTH = 1, DT = integer, ISVALID = (C_M_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = M_AXI
PARAMETER C_M_AXI_WUSER_WIDTH = 1, DT = integer, ISVALID = (C_M_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = M_AXI
PARAMETER C_M_AXI_RUSER_WIDTH = 1, DT = integer, ISVALID = (C_M_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = M_AXI
PARAMETER C_M_AXI_BUSER_WIDTH = 1, DT = integer, ISVALID = (C_M_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = M_AXI
PARAMETER C_M_AXI_SUPPORTS_NARROW_BURST = 0, DT = integer, RANGE = (0,1), TYPE = NON_HDL, BUS = M_AXI

# Example Parameters
# Base address of targeted slave
PARAMETER C_M_AXI_TARGET = 0x00000000, DT = std_logic_vector(31 downto 0)
# Burst length for transactions, in C_M_AXI_DATA_WIDTHs
PARAMETER C_M_AXI_BURST_LEN = 16, DT = integer
# Number of address bits to test before wrapping
PARAMETER C_OFFSET_WIDTH = 9, DT = integer
PARAMETER C_DISPLAY_START_ADDRESS = 0x1A000000, DT = std_logic_vector(31 downto 0)
PARAMETER C_UPSIDE_DOWN = 0, DT = INTEGER, VALUES = (1= TRUE, 0= FALSE)

## Ports
PORT s_axi_lite_aclk = "", DIR = I, SIGIS = CLK, BUS = S_AXI_LITE
PORT M_AXI_ACLK = "", BUS = M_AXI, DIR = I, SIGIS = CLK
PORT ARESETN = ARESETN, BUS = M_AXI:S_AXI_LITE, DIR = I, SIGIS = RST

PORT s_axi_lite_awvalid = AWVALID, DIR = I, BUS = S_AXI_LITE
PORT s_axi_lite_awready = AWREADY, DIR = O, BUS = S_AXI_LITE
PORT s_axi_lite_awaddr = AWADDR, DIR = I, VEC = [C_S_AXI_LITE_ADDR_WIDTH-1:0], BUS = S_AXI_LITE, ENDIAN = LITTLE
PORT s_axi_lite_wvalid = WVALID, DIR = I, BUS = S_AXI_LITE
PORT s_axi_lite_wready = WREADY, DIR = O, BUS = S_AXI_LITE
PORT s_axi_lite_wdata = WDATA, DIR = I, VEC = [C_S_AXI_LITE_DATA_WIDTH-1:0], BUS = S_AXI_LITE, ENDIAN = LITTLE
PORT s_axi_lite_bresp = BRESP, DIR = O, VEC = [1:0], BUS = S_AXI_LITE, ENDIAN = LITTLE
PORT s_axi_lite_bvalid = BVALID, DIR = O, BUS = S_AXI_LITE
PORT s_axi_lite_bready = BREADY, DIR = I, BUS = S_AXI_LITE
PORT s_axi_lite_arvalid = ARVALID, DIR = I, BUS = S_AXI_LITE
PORT s_axi_lite_arready = ARREADY, DIR = O, BUS = S_AXI_LITE
PORT s_axi_lite_araddr = ARADDR, DIR = I, VEC = [C_S_AXI_LITE_ADDR_WIDTH-1:0], BUS = S_AXI_LITE, ENDIAN = LITTLE
PORT s_axi_lite_rvalid = RVALID, DIR = O, BUS = S_AXI_LITE
PORT s_axi_lite_rready = RREADY, DIR = I, BUS = S_AXI_LITE
PORT s_axi_lite_rdata = RDATA, DIR = O, VEC = [C_S_AXI_LITE_DATA_WIDTH-1:0], BUS = S_AXI_LITE, ENDIAN = LITTLE
PORT s_axi_lite_rresp = RRESP, DIR = O, VEC = [1:0], BUS = S_AXI_LITE, ENDIAN = LITTLE

PORT M_AXI_AWID = AWID, BUS = M_AXI, DIR = O, VEC = [(C_M_AXI_THREAD_ID_WIDTH-1):0], ENDIAN = LITTLE
PORT M_AXI_AWADDR = AWADDR, BUS = M_AXI, DIR = O, VEC = [(C_M_AXI_ADDR_WIDTH-1):0], ENDIAN = LITTLE
PORT M_AXI_AWLEN = AWLEN, BUS = M_AXI, DIR = O, VEC = [7:0], ENDIAN = LITTLE
PORT M_AXI_AWSIZE = AWSIZE, BUS = M_AXI, DIR = O, VEC = [2:0], ENDIAN = LITTLE
PORT M_AXI_AWBURST = AWBURST, BUS = M_AXI, DIR = O, VEC = [1:0], ENDIAN = LITTLE
PORT M_AXI_AWLOCK = AWLOCK, BUS = M_AXI, DIR = O #, VEC = [1:0], ENDIAN = LITTLE
PORT M_AXI_AWCACHE = AWCACHE, BUS = M_AXI, DIR = O, VEC = [3:0], ENDIAN = LITTLE
PORT M_AXI_AWPROT = AWPROT, BUS = M_AXI, DIR = O, VEC = [2:0], ENDIAN = LITTLE
PORT M_AXI_AWQOS = AWQOS, BUS = M_AXI, DIR = O, VEC = [3:0], ENDIAN = LITTLE
PORT M_AXI_AWUSER = AWUSER, BUS = M_AXI, DIR = O, VEC = [C_M_AXI_AWUSER_WIDTH-1:0], ENDIAN = LITTLE
PORT M_AXI_AWVALID = AWVALID, BUS = M_AXI, DIR = O
PORT M_AXI_AWREADY = AWREADY, BUS = M_AXI, DIR = I
PORT M_AXI_WDATA = WDATA, BUS = M_AXI, DIR = O, VEC = [(C_M_AXI_DATA_WIDTH-1):0], ENDIAN = LITTLE
PORT M_AXI_WSTRB = WSTRB, BUS = M_AXI, DIR = O, VEC = [((C_M_AXI_DATA_WIDTH/8) -1):0], ENDIAN = LITTLE
PORT M_AXI_WLAST = WLAST, BUS = M_AXI, DIR = O
PORT M_AXI_WUSER = WUSER, BUS = M_AXI, DIR = O, VEC = [(C_M_AXI_WUSER_WIDTH-1):0], ENDIAN = LITTLE
PORT M_AXI_WVALID = WVALID, BUS = M_AXI, DIR = O
PORT M_AXI_WREADY = WREADY, BUS = M_AXI, DIR = I
PORT M_AXI_BID = BID, BUS = M_AXI, DIR = I, VEC = [(C_M_AXI_THREAD_ID_WIDTH-1):0], ENDIAN = LITTLE
PORT M_AXI_BRESP = BRESP, BUS = M_AXI, DIR = I, VEC = [1:0], ENDIAN = LITTLE
PORT M_AXI_BUSER = BUSER, BUS = M_AXI, DIR = I, VEC = [(C_M_AXI_BUSER_WIDTH-1):0], ENDIAN = LITTLE
PORT M_AXI_BVALID = BVALID, BUS = M_AXI, DIR = I
PORT M_AXI_BREADY = BREADY, BUS = M_AXI, DIR = O
PORT M_AXI_ARID = ARID, BUS = M_AXI, DIR = O, VEC = [(C_M_AXI_THREAD_ID_WIDTH-1):0], ENDIAN = LITTLE
PORT M_AXI_ARADDR = ARADDR, BUS = M_AXI, DIR = O, VEC = [(C_M_AXI_ADDR_WIDTH-1):0], ENDIAN = LITTLE
PORT M_AXI_ARLEN = ARLEN, BUS = M_AXI, DIR = O, VEC = [7:0], ENDIAN = LITTLE
PORT M_AXI_ARSIZE = ARSIZE, BUS = M_AXI, DIR = O, VEC = [2:0], ENDIAN = LITTLE
PORT M_AXI_ARBURST = ARBURST, BUS = M_AXI, DIR = O, VEC = [1:0], ENDIAN = LITTLE
PORT M_AXI_ARLOCK = ARLOCK, BUS = M_AXI, DIR = O, VEC = [1:0], ENDIAN = LITTLE
PORT M_AXI_ARCACHE = ARCACHE, BUS = M_AXI, DIR = O, VEC = [3:0], ENDIAN = LITTLE
PORT M_AXI_ARPROT = ARPROT, BUS = M_AXI, DIR = O, VEC = [2:0], ENDIAN = LITTLE
PORT M_AXI_ARQOS = ARQOS, BUS = M_AXI, DIR = O, VEC = [3:0], ENDIAN = LITTLE
PORT M_AXI_ARUSER = ARUSER, BUS = M_AXI, DIR = O, VEC = [(C_M_AXI_ARUSER_WIDTH-1):0], ENDIAN = LITTLE
PORT M_AXI_ARVALID = ARVALID, BUS = M_AXI, DIR = O
PORT M_AXI_ARREADY = ARREADY, BUS = M_AXI, DIR = I
PORT M_AXI_RID = RID, BUS = M_AXI, DIR = I, VEC = [(C_M_AXI_THREAD_ID_WIDTH-1):0], ENDIAN = LITTLE
PORT M_AXI_RDATA = RDATA, BUS = M_AXI, DIR = I, VEC = [(C_M_AXI_DATA_WIDTH-1):0], ENDIAN = LITTLE
PORT M_AXI_RRESP = RRESP, BUS = M_AXI, DIR = I, VEC = [1:0], ENDIAN = LITTLE
PORT M_AXI_RLAST = RLAST, BUS = M_AXI, DIR = I
PORT M_AXI_RUSER = RUSER, BUS = M_AXI, DIR = I, VEC = [(C_M_AXI_RUSER_WIDTH-1):0], ENDIAN = LITTLE
PORT M_AXI_RVALID = RVALID, BUS = M_AXI, DIR = I
PORT M_AXI_RREADY = RREADY, BUS = M_AXI, DIR = O

#Example IO port
PORT init_done = "", DIR = I, IO_IF = mt9d111_inf, IO_IS = init_done
PORT wr_error = "", DIR = O, IO_IF = mt9d111_inf, IO_IS = wr_error
PORT pclk_from_pll = "", DIR = I, SIGIS = CLK, IO_IF = mt9d111_inf, IO_IS = pclk_from_pll
PORT pclk = "", DIR = I, SIGIS = CLK, IO_IF = mt9d111_inf, IO_IS = pclk
PORT xck = "", DIR =O, SIGIS = CLK, IO_IF = mt9d111_inf, IO_IS = xck
PORT href = "", DIR = I, IO_IF = mt9d111_inf, IO_IS = href
PORT vsync = "", DIR = I, IO_IF = mt9d111_inf, IO_IS = vsync
PORT cam_data = "", DIR = I, VEC = [7:0], IO_IF = mt9d111_inf, IO_IS = cam_data
PORT standby = "", DIR = O, IO_IF = mt9d111_inf, IO_IS = standby
PORT pfifo_overflow = "", DIR = O, IO_IF = mt9d111_inf, IO_IS = pfifo_overflow
PORT pfifo_underflow = "", DIR = O, IO_IF = mt9d111_inf, IO_IS = pfifo_underflow

END


次に、MUIファイル (mt9d111_inf_axi_master_v2_1_0.mui) を示す。

<?xml version="1.0" encoding="ISO-8859-1"?>

<!--
###############################################################################
## DISCLAIMER OF LIABILITY
##
## This file contains proprietary and confidential information of
## Xilinx, Inc. ("Xilinx"), that is distributed under a license
## from Xilinx, and may be used, copied and/or disclosed only
## pursuant to the terms of a valid license agreement with Xilinx.
##
## XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
## ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
## EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
## LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
## MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
## does not warrant that functions included in the Materials will
## meet the requirements of Licensee, or that the operation of the
## Materials will be uninterrupted or error-free, or that defects
## in the Materials will be corrected. Furthermore, Xilinx does
## not warrant or make any representations regarding use, or the
## results of the use, of the Materials in terms of correctness,
## accuracy, reliability or otherwise.
##
## Xilinx products are not designed or intended to be fail-safe,
## or for use in any application requiring fail-safe performance,
## such as life-support or safety devices or systems, Class III
## medical devices, nuclear facilities, applications related to
## the deployment of airbags, or any other applications that could
## lead to death, personal injury or severe property or
## environmental damage (individually and collectively, "critical
## applications"). Customer assumes the sole risk and liability
## of any use of Xilinx products in critical applications,
## subject only to applicable laws and regulations governing
## limitations on product liability.
##
## Copyright 2009 Xilinx, Inc.
## All rights reserved.
##
## This disclaimer and copyright notice must be retained as part
## of this file at all times.
##
###############################################################################
-->

<!DOCTYPE doc SYSTEM "../../ipdialog.dtd" [
    <!-- -->
    <!ENTITY C_M_AXI_SUPPORTS_THREADS '
    <widget id="C_M_AXI_SUPPORTS_THREADS">
        <key>C_M_AXI_SUPPORTS_THREADS</key>
        <label>C_M_AXI_SUPPORTS_THREADS</label>
        <tip></tip>
    </widget>
    '>
    <!ENTITY C_M_AXI_THREAD_ID_WIDTH '
    <widget id="C_M_AXI_THREAD_ID_WIDTH">
        <key>C_M_AXI_THREAD_ID_WIDTH</key>
        <label>C_M_AXI_THREAD_ID_WIDTH</label>
        <tip></tip>
    </widget>
    '>
    <!ENTITY C_HIGHADDR '
    <widget id="C_HIGHADDR">
            <key>C_HIGHADDR</key>
            <label>High Address</label>
            <tip></tip>
    </widget>
    '>
    <!ENTITY C_BASEADDR '
    <widget id="C_BASEADDR">
            <key>C_BASEADDR</key>
            <label>Base Address</label>
            <tip></tip>
    </widget>
    '>
    <!ENTITY C_S_AXI_LITE_ADDR_WIDTH '
    <widget id="C_S_AXI_LITE_ADDR_WIDTH">
                    <key>C_S_AXI_LITE_ADDR_WIDTH</key>
            <label>AXI Lite Address Width</label>
            <tip></tip>
    </widget>
    '>
    <!ENTITY C_S_AXI_LITE_DATA_WIDTH '
    <widget id="C_S_AXI_LITE_DATA_WIDTH">
                    <key>C_S_AXI_LITE_DATA_WIDTH</key>
            <label>AXI Lite Data Width</label>
            <tip></tip>
    </widget>
    '>
    <!ENTITY C_M_AXI_ADDR_WIDTH '
    <widget id="C_M_AXI_ADDR_WIDTH">
        <key>C_M_AXI_ADDR_WIDTH</key>
        <label>C_M_AXI_ADDR_WIDTH</label>
        <tip></tip>
    </widget>
    '>
    <!ENTITY C_M_AXI_DATA_WIDTH '
    <widget id="C_M_AXI_DATA_WIDTH">
        <key>C_M_AXI_DATA_WIDTH</key>
        <label>C_M_AXI_DATA_WIDTH</label>
        <tip></tip>
    </widget>
    '>
    <!ENTITY C_M_AXI_PROTOCOL '
    <widget id="C_M_AXI_PROTOCOL">
                    <key>C_M_AXI_PROTOCOL</key>
            <label>AXI Master Protocol</label>
            <tip></tip>
    </widget>
    '>
    <!ENTITY C_S_AXI_LITE_PROTOCOL '
    <widget id="C_S_AXI_LITE_PROTOCOL">
                    <key>C_S_AXI_LITE_PROTOCOL</key>
            <label>AXI Lite Protocol</label>
            <tip></tip>
    </widget>
    '>
    <!ENTITY C_USE_ADVANCED_PORTS '
    <widget id="C_USE_ADVANCED_PORTS">
        <key>C_USE_ADVANCED_PORTS</key>
        <label>C_USE_ADVANCED_PORTS</label>
        <tip></tip>
    </widget>
    '>
    <!ENTITY C_S_AXI_LITE_SUPPORTS_READ '
    <widget id="C_S_AXI_LITE_SUPPORTS_READ">
                    <key>C_S_AXI_LITE_SUPPORTS_READ</key>
            <label>AXI Lite Supports Read Access</label>
            <tip></tip>
    </widget>
    '>
    <!ENTITY C_S_AXI_LITE_SUPPORTS_WRITE '
    <widget id="C_S_AXI_LITE_SUPPORTS_WRITE">
                    <key>C_S_AXI_LITE_SUPPORTS_WRITE</key>
            <label>AXI Lite Supports Write Access</label>
            <tip></tip>
    </widget>
    '>    
    <!ENTITY C_M_AXI_SUPPORTS_READ '
    <widget id="C_M_AXI_SUPPORTS_READ">
        <key>C_M_AXI_SUPPORTS_READ</key>
        <label>C_M_AXI_SUPPORTS_READ</label>
        <tip></tip>
    </widget>
    '>
    <!ENTITY C_M_AXI_SUPPORTS_WRITE '
    <widget id="C_M_AXI_SUPPORTS_WRITE">
        <key>C_M_AXI_SUPPORTS_WRITE</key>
        <label>C_M_AXI_SUPPORTS_WRITE</label>
        <tip></tip>
    </widget>
    '>
    <!ENTITY C_M_AXI_SUPPORTS_USER_SIGNALS '
    <widget id="C_M_AXI_SUPPORTS_USER_SIGNALS">
        <key>C_M_AXI_SUPPORTS_USER_SIGNALS</key>
        <label>C_M_AXI_SUPPORTS_USER_SIGNALS</label>
        <tip></tip>
    </widget>
    '>
    <!ENTITY C_M_AXI_AWUSER_WIDTH '
    <widget id="C_M_AXI_AWUSER_WIDTH">
        <key>C_M_AXI_AWUSER_WIDTH</key>
        <label>C_M_AXI_AWUSER_WIDTH</label>
        <tip></tip>
    </widget>
    '>
    <!ENTITY C_M_AXI_ARUSER_WIDTH '
    <widget id=" C_M_AXI_ARUSER_WIDTH ">
        <key>C_M_AXI_ARUSER_WIDTH</key>
        <label>C_M_AXI_ARUSER_WIDTH</label>
        <tip></tip>
    </widget>
    '>
    <!ENTITY C_M_AXI_WUSER_WIDTH '
    <widget id="C_M_AXI_WUSER_WIDTH">
        <key>C_M_AXI_WUSER_WIDTH</key>
        <label>C_M_AXI_WUSER_WIDTH</label>
        <tip></tip>
    </widget>
    '>
    <!ENTITY C_M_AXI_RUSER_WIDTH '
    <widget id="C_M_AXI_RUSER_WIDTH">
        <key>C_M_AXI_RUSER_WIDTH</key>
        <label>C_M_AXI_RUSER_WIDTH</label>
        <tip></tip>
    </widget>
    '>
    <!ENTITY C_M_AXI_BUSER_WIDTH '
    <widget id="C_M_AXI_BUSER_WIDTH">
        <key>C_M_AXI_BUSER_WIDTH</key>
        <label>C_M_AXI_BUSER_WIDTH</label>
        <tip></tip>
    </widget>
    '>
    <!ENTITY C_M_AXI_SUPPORTS_NARROW_BURST '
    <widget id="C_M_AXI_SUPPORTS_NARROW_BURST">
        <key>C_M_AXI_SUPPORTS_NARROW_BURST</key>
        <label>C_M_AXI_SUPPORTS_NARROW_BURST</label>
        <tip></tip>
    </widget>
    '>
    <!ENTITY C_M_AXI_TARGET '
    <widget id="C_M_AXI_TARGET">
        <key>C_M_AXI_TARGET</key>
        <label>C_M_AXI_TARGET</label>
        <tip></tip>
    </widget>
    '>
    <!ENTITY C_M_AXI_BURST_LEN '
    <widget id="C_M_AXI_BURST_LEN">
        <key>C_M_AXI_BURST_LEN</key>
        <label>C_M_AXI_BURST_LEN</label>
        <tip></tip>
    </widget>
    '>
    <!ENTITY C_MAX_UNREAD_WRITES '
    <widget id="C_MAX_UNREAD_WRITES">
        <key>C_MAX_UNREAD_WRITES</key>
        <label>C_MAX_UNREAD_WRITES</label>
        <tip></tip>
    </widget>
    '>
    <!ENTITY C_OFFSET_WIDTH '
    <widget id="C_OFFSET_WIDTH">
        <key>C_OFFSET_WIDTH</key>
        <label>C_OFFSET_WIDTH</label>
        <tip></tip>
    </widget>
    '>
    <!ENTITY C_DISPLAY_START_ADDRESS '
    <widget id="C_DISPLAY_START_ADDRESS">
        <key>C_DISPLAY_START_ADDRESS</key>
        <label>C_DISPLAY_START_ADDRESS</label>
        <tip></tip>
    </widget>
    '>
    <!ENTITY C_UPSIDE_DOWN '
    <widget id="C_UPSIDE_DOWN">
        <key>C_UPSIDE_DOWN</key>
        <label>C_UPSIDE_DOWN</label>
        <tip></tip>
    </widget>
    '>
    
]>

<doc>
    <view id="User">
        <display>User</display>
        <group id="Common">
            <display>Common</display>
            <item>&C_M_AXI_TARGET;</item>
            <item>&C_M_AXI_BURST_LEN;</item>
            <item>&C_MAX_UNREAD_WRITES;</item>
            <item>&C_OFFSET_WIDTH;</item>
            <item>&C_DISPLAY_START_ADDRESS;</item>
            <item>&C_UPSIDE_DOWN;</item>
        </group>
    </view>
    <view id="System">
        <display>System</display>
        <group id="Addresses">
                <display>Addresses</display>
                <item>&C_BASEADDR;</item>
                <item>&C_HIGHADDR;</item>
        </group>
        <group id="AXI">
            <display>AXI</display>
            <item>&C_S_AXI_LITE_PROTOCOL;</item>
            <item>&C_S_AXI_LITE_ADDR_WIDTH;</item>
            <item>&C_S_AXI_LITE_DATA_WIDTH;</item>
            <item>&C_S_AXI_LITE_SUPPORTS_READ;</item>
            <item>&C_S_AXI_LITE_SUPPORTS_WRITE;</item>
            <item>&C_M_AXI_PROTOCOL;</item>
            <item>&C_M_AXI_ADDR_WIDTH;</item>
            <item>&C_M_AXI_DATA_WIDTH;</item>
            <item>&C_M_AXI_SUPPORTS_READ;</item>
            <item>&C_M_AXI_SUPPORTS_WRITE;</item>
            <item>&C_M_AXI_SUPPORTS_THREADS;</item>
            <item>&C_M_AXI_THREAD_ID_WIDTH;</item>
            <item>&C_M_AXI_SUPPORTS_NARROW_BURST;</item>
            <item>&C_M_AXI_SUPPORTS_USER_SIGNALS;</item>
            <item>&C_M_AXI_AWUSER_WIDTH;</item>
            <item>&C_M_AXI_ARUSER_WIDTH;</item>
            <item>&C_M_AXI_WUSER_WIDTH;</item>
            <item>&C_M_AXI_RUSER_WIDTH;</item>
            <item>&C_M_AXI_BUSER_WIDTH;</item>
        </group>
    </view>
    
</doc>

  1. 2013年04月02日 04:47 |
  2. 複数のAXI4 バスを持つIPの作製
  3. | トラックバック:0
  4. | コメント:0

コメント

コメントの投稿


管理者にだけ表示を許可する

トラックバック URL
http://marsee101.blog.fc2.com/tb.php/2425-cc554ddc
この記事にトラックバックする(FC2ブログユーザー)