FC2カウンター FPGAの部屋 reVISION-Zybo-Z7-20をやってみた8(Dense Non-Pyramidal Optical Flow)
FC2ブログ

FPGAやCPLDの話題やFPGA用のツールの話題などです。 マニアックです。 日記も書きます。

FPGAの部屋

FPGAの部屋の有用と思われるコンテンツのまとめサイトを作りました。Xilinx ISEの初心者の方には、FPGAリテラシーおよびチュートリアルのページをお勧めいたします。

reVISION-Zybo-Z7-20をやってみた8(Dense Non-Pyramidal Optical Flow)

reVISION-Zybo-Z7-20をやってみた7(Vivado と Vivado HLS)”の続き。

前回は、バイラテラル・フィルタのVivado と Vivado HLS のプロジェクトを見た。今回は、違うサンプルをやってみようと思う。やってみるのは、Dense Non-Pyramidal Optical Flow とする。

SDSoC で、File メニューからNew -> SDx Project... を選択した。

New SDx Project ダイアログが表示された。
デフォルトのApplication Project のまま、Next > ボタンをクリックした。

Project name に dnp_of と入力して、Next > ボタンをクリックした。
reVISION-Zybo-Z7-20_92_120328.png

Platform 画面では、zybo_z7_20 [custom] を選択して、Next > ボタンをクリックした。

System configuration は Linux を選択ということだったが、他は選べない。

Templates では、Dense Non-Pyramidal Optical Flow を選択した。
reVISION-Zybo-Z7-20_93_120328.png

dnp_of プロジェクトが生成された。
reVISION-Zybo-Z7-20_94_120328.png

トンカチ・ボタンをクリックして、Debug モードでビルド成功した。
reVISION-Zybo-Z7-20_100_120329.png

~/sdx_workspace/revisio_zybo_z7_20_ws/dnp_of/Debug/sd_card/ ディレクトリを表示する。
reVISION-Zybo-Z7-20_95_120329.png

Micro SD カードの ZYNQBOOT パーティションのファイルをすべて、新規作成した bilateral_ex ディレクトリに移動してから、 ~/sdx_workspace/revisio_zybo_z7_20_ws/dnp_of/Debug/sd_card/ ディレクトリのファイルをすべてコピーした。

Zybo-Z7-20 にMicro SD カードを挿入して、電源ONした。
sudo gtkterm
なお、sudo gtkterm & では、gtkterm が起動なかった。
gtkterm が起動したら次の設定を行った。

Configuration -> Portを選択する
Port:/dev/ttyUSB1、Baud Rate:115200を選択する


プロンプトが表示された。
ZYNQBOOT は /run/media/mmcblk0p1/ ディレクトリにマウントされていた。
/run/media/mmcblk0p1/ ディレクトリに入って、
./dnp_of.elf im0.jpg im1.jpg
を実行した。すると、out_0.png が生成された。

im0.jpg を示す。
reVISION-Zybo-Z7-20_97_120329.jpg

im1.jpg を示す。
reVISION-Zybo-Z7-20_98_120329.jpg

im0.jpg よりも im1.jpg の方が自動車が少し進んでいるが、背景は同じという画像になっている。
out_0.png を示す。
reVISION-Zybo-Z7-20_99_120329.jpg

自動車の部分だけ、色が付いている。これは差分で動いている物体がわかるように色付けされているのかな?
一応イケてるっぽい。。。

Vivado HLSのリポートの sds_xf_dense_npyr_optical_flow_accel.rpt を示す。

(c) Copyright 2012-2017 Xilinx, Inc. All Rights Reserved.
#-----------------------------------------------------------
# Tool version  : sds++ 2017.4 SW Build 2086221 on Fri Dec 15 20:55:10 MST 2017
# Start time    : Wed Mar 28 20:06:49 JST 2018
# Command line  : sds++ -DHLS_NO_XIL_FPO_LIB -D__ARM_PCS_VFP -Wall -O0 -g -I../src -I/home/masaaki/reVISION-Zybo-Z7-20/sdsoc/zybo_z7_20/export/zybo_z7_20/sw/linux/linux/inc/include -c -fmessage-length=0 -MTsrc/xf_dense_npyr_optical_flow_accel.o -I/home/masaaki/reVISION-Zybo-Z7-20/sdsoc/zybo_z7_20/export/zybo_z7_20/sw/sysroot/usr/include/c++/6.2.1 -I/home/masaaki/reVISION-Zybo-Z7-20/sdsoc/zybo_z7_20/export/zybo_z7_20/sw/sysroot/usr/include/c++/6.2.1/arm-xilinx-linux-gnueabi -I/home/masaaki/reVISION-Zybo-Z7-20/sdsoc/zybo_z7_20/export/zybo_z7_20/sw/sysroot/usr/include/c++/6.2.1/backward -I/home/masaaki/reVISION-Zybo-Z7-20/sdsoc/zybo_z7_20/export/zybo_z7_20/sw/sysroot/usr/include -I/home/masaaki/reVISION-Zybo-Z7-20/sdsoc/zybo_z7_20/export/zybo_z7_20/sw/sysroot/usr/include/glib-2.0 -I/home/masaaki/reVISION-Zybo-Z7-20/sdsoc/zybo_z7_20/export/zybo_z7_20/sw/sysroot/usr/lib/glib-2.0/include -Wno-overloaded-virtual -Wno-unused-label -Wno-strict-overflow -Wno-uninitialized -Wno-unused-function -Wno-unused-variable -Wno-unknown-attributes -Wno-unused-local-typedefs -Wno-sign-compare -MMD -MP -MFsrc/xf_dense_npyr_optical_flow_accel.d -MTsrc/xf_dense_npyr_optical_flow_accel.o -o src/xf_dense_npyr_optical_flow_accel.o ../src/xf_dense_npyr_optical_flow_accel.cpp -sds-hw xf::DenseNonPyrLKOpticalFlow<25,0,2160,3840,1> xf_dense_npyr_optical_flow_accel.cpp -files /home/masaaki/reVISION-Zybo-Z7-20/sdsoc/zybo_z7_20/export/zybo_z7_20/sw/linux/linux/inc/include/imgproc/xf_dense_npyr_optical_flow.hpp -clkid 0 -sds-end -sds-sys-config linux -sds-proc linux -sds-pf /home/masaaki/reVISION-Zybo-Z7-20/sdsoc/zybo_z7_20/export/zybo_z7_20
# Log file      : /home/masaaki/sdx_workspaces/revisio_zybo_z7_20_ws/dnp_of/Debug/_sds/reports/sds_xf_dense_npyr_optical_flow_accel.log
# Journal file  : /home/masaaki/sdx_workspaces/revisio_zybo_z7_20_ws/dnp_of/Debug/_sds/reports/sds_xf_dense_npyr_optical_flow_accel.jou
# Report file   : /home/masaaki/sdx_workspaces/revisio_zybo_z7_20_ws/dnp_of/Debug/_sds/reports/sds_xf_dense_npyr_optical_flow_accel.rpt
#-----------------------------------------------------------

High-Level Synthesis
--------------------

  Vivado HLS Report : /home/masaaki/sdx_workspaces/revisio_zybo_z7_20_ws/dnp_of/Debug/_sds/vhls/w0_xf_DenseNonPyrLKOpticalFlow/solution/syn/report/w0_xf_DenseNonPyrLKOpticalFlow_csynth.rpt



================================================================
== Performance Estimates
================================================================
+ Timing (ns): 
    * Summary: 
    +--------+-------+----------+------------+
    |  Clock | Target| Estimated| Uncertainty|
    +--------+-------+----------+------------+
    |ap_clk  |  10.00|      8.93|        2.70|
    +--------+-------+----------+------------+

+ Latency (clock cycles): 
    * Summary: 
    +-------+---------+-------+---------+---------+
    |     Latency     |     Interval    | Pipeline|
    |  min  |   max   |  min  |   max   |   Type  |
    +-------+---------+-------+---------+---------+
    |  99850|  8400726|  99850|  8400726|   none  |
    +-------+---------+-------+---------+---------+

    + Detail: 
        * Instance: 
        +--------------------------+---------------+-------+---------+-------+---------+---------+
        |                          |               |     Latency     |     Interval    | Pipeline|
        |         Instance         |     Module    |  min  |   max   |  min  |   max   |   Type  |
        +--------------------------+---------------+-------+---------+-------+---------+---------+
        |grp_fpga_optflow8_fu_232  |fpga_optflow8  |  99849|  8400725|  99849|  8400725|   none  |
        +--------------------------+---------------+-------+---------+-------+---------+---------+

        * Loop: 
        N/A



================================================================
== Utilization Estimates
================================================================
* Summary: 
+-----------------+---------+-------+--------+-------+
|       Name      | BRAM_18K| DSP48E|   FF   |  LUT  |
+-----------------+---------+-------+--------+-------+
|DSP              |        -|      -|       -|      -|
|Expression       |        -|      -|       -|      -|
|FIFO             |        -|      -|       -|      -|
|Instance         |      180|     37|   14325|  18290|
|Memory           |        -|      -|       -|      -|
|Multiplexer      |        -|      -|       -|     51|
|Register         |        -|      -|       3|      -|
+-----------------+---------+-------+--------+-------+
|Total            |      180|     37|   14328|  18341|
+-----------------+---------+-------+--------+-------+
|Available        |      280|    220|  106400|  53200|
+-----------------+---------+-------+--------+-------+
|Utilization (%)  |       64|     16|      13|     34|
+-----------------+---------+-------+--------+-------+

+ Detail: 
    * Instance: 
    +--------------------------+---------------+---------+-------+-------+-------+
    |         Instance         |     Module    | BRAM_18K| DSP48E|   FF  |  LUT  |
    +--------------------------+---------------+---------+-------+-------+-------+
    |grp_fpga_optflow8_fu_232  |fpga_optflow8  |      180|     37|  14325|  18290|
    +--------------------------+---------------+---------+-------+-------+-------+
    |Total                     |               |      180|     37|  14325|  18290|
    +--------------------------+---------------+---------+-------+-------+-------+

    * DSP48: 
    N/A

    * Memory: 
    N/A

    * FIFO: 
    N/A

    * Expression: 
    N/A

    * Multiplexer: 
    +--------------------+----+-----------+-----+-----------+
    |        Name        | LUT| Input Size| Bits| Total Bits|
    +--------------------+----+-----------+-----+-----------+
    |ap_NS_fsm           |  15|          3|    1|          3|
    |flowx_data_write    |   9|          2|    1|          2|
    |flowy_data_write    |   9|          2|    1|          2|
    |frame0_data_V_read  |   9|          2|    1|          2|
    |frame1_data_V_read  |   9|          2|    1|          2|
    +--------------------+----+-----------+-----+-----------+
    |Total               |  51|         11|    5|         11|
    +--------------------+----+-----------+-----+-----------+

    * Register: 
    +------------------------------------------+---+----+-----+-----------+
    |                   Name                   | FF| LUT| Bits| Const Bits|
    +------------------------------------------+---+----+-----+-----------+
    |ap_CS_fsm                                 |  2|   0|    2|          0|
    |ap_reg_grp_fpga_optflow8_fu_232_ap_start  |  1|   0|    1|          0|
    +------------------------------------------+---+----+-----+-----------+
    |Total                                     |  3|   0|    3|          0|
    +------------------------------------------+---+----+-----+-----------+



================================================================
== Interface
================================================================
* Summary: 
+-----------------------+-----+-----+------------+--------------------------------+--------------+
|       RTL Ports       | Dir | Bits|  Protocol  |          Source Object         |    C Type    |
+-----------------------+-----+-----+------------+--------------------------------+--------------+
|ap_clk                 |  in |    1| ap_ctrl_hs | w0_xf_DenseNonPyrLKOpticalFlow | return value |
|ap_rst_n               |  in |    1| ap_ctrl_hs | w0_xf_DenseNonPyrLKOpticalFlow | return value |
|ap_start               |  in |    1| ap_ctrl_hs | w0_xf_DenseNonPyrLKOpticalFlow | return value |
|ap_done                | out |    1| ap_ctrl_hs | w0_xf_DenseNonPyrLKOpticalFlow | return value |
|ap_idle                | out |    1| ap_ctrl_hs | w0_xf_DenseNonPyrLKOpticalFlow | return value |
|ap_ready               | out |    1| ap_ctrl_hs | w0_xf_DenseNonPyrLKOpticalFlow | return value |
|frame0_allocatedFlag   |  in |    8|   ap_none  |      frame0_allocatedFlag      |    pointer   |
|frame0_rows            |  in |   32|   ap_none  |           frame0_rows          |    pointer   |
|frame0_cols            |  in |   32|   ap_none  |           frame0_cols          |    pointer   |
|frame0_size            |  in |   32|   ap_none  |           frame0_size          |    pointer   |
|frame0_data_V_dout     |  in |    8|   ap_fifo  |          frame0_data_V         |    pointer   |
|frame0_data_V_empty_n  |  in |    1|   ap_fifo  |          frame0_data_V         |    pointer   |
|frame0_data_V_read     | out |    1|   ap_fifo  |          frame0_data_V         |    pointer   |
|frame1_allocatedFlag   |  in |    8|   ap_none  |      frame1_allocatedFlag      |    pointer   |
|frame1_rows            |  in |   32|   ap_none  |           frame1_rows          |    pointer   |
|frame1_cols            |  in |   32|   ap_none  |           frame1_cols          |    pointer   |
|frame1_size            |  in |   32|   ap_none  |           frame1_size          |    pointer   |
|frame1_data_V_dout     |  in |    8|   ap_fifo  |          frame1_data_V         |    pointer   |
|frame1_data_V_empty_n  |  in |    1|   ap_fifo  |          frame1_data_V         |    pointer   |
|frame1_data_V_read     | out |    1|   ap_fifo  |          frame1_data_V         |    pointer   |
|flowx_allocatedFlag    |  in |    8|   ap_none  |       flowx_allocatedFlag      |    pointer   |
|flowx_rows             |  in |   32|   ap_none  |           flowx_rows           |    pointer   |
|flowx_cols             |  in |   32|   ap_none  |           flowx_cols           |    pointer   |
|flowx_size             |  in |   32|   ap_none  |           flowx_size           |    pointer   |
|flowx_data_din         | out |   32|   ap_fifo  |           flowx_data           |    pointer   |
|flowx_data_full_n      |  in |    1|   ap_fifo  |           flowx_data           |    pointer   |
|flowx_data_write       | out |    1|   ap_fifo  |           flowx_data           |    pointer   |
|flowy_allocatedFlag    |  in |    8|   ap_none  |       flowy_allocatedFlag      |    pointer   |
|flowy_rows             |  in |   32|   ap_none  |           flowy_rows           |    pointer   |
|flowy_cols             |  in |   32|   ap_none  |           flowy_cols           |    pointer   |
|flowy_size             |  in |   32|   ap_none  |           flowy_size           |    pointer   |
|flowy_data_din         | out |   32|   ap_fifo  |           flowy_data           |    pointer   |
|flowy_data_full_n      |  in |    1|   ap_fifo  |           flowy_data           |    pointer   |
|flowy_data_write       | out |    1|   ap_fifo  |           flowy_data           |    pointer   |
+-----------------------+-----+-----+------------+--------------------------------+--------------+


sds.rpt を示す。

(c) Copyright 2012-2017 Xilinx, Inc. All Rights Reserved.
#-----------------------------------------------------------
# Tool version  : sds++ 2017.4 SW Build 2086221 on Fri Dec 15 20:55:10 MST 2017
# Start time    : Wed Mar 28 20:08:47 JST 2018
# Command line  : sds++ --sysroot=/home/masaaki/reVISION-Zybo-Z7-20/sdsoc/zybo_z7_20/export/zybo_z7_20/sw/sysroot -L=/lib -L=/usr/lib -Wl,-rpath-link=/home/masaaki/reVISION-Zybo-Z7-20/sdsoc/zybo_z7_20/export/zybo_z7_20/sw/sysroot/lib,-rpath-link=/home/masaaki/reVISION-Zybo-Z7-20/sdsoc/zybo_z7_20/export/zybo_z7_20/sw/sysroot/usr/lib -sdcard ../data --remote_ip_cache /home/masaaki/sdx_workspaces/revisio_zybo_z7_20_ws/ip_cache -o dnp_of.elf ./src/xf_dense_npyr_optical_flow_accel.o ./src/xf_dense_npyr_optical_flow_tb.o -lglib-2.0 -ldrm -lv4l2subdev -lmediactl -lopencv_imgcodecs -lopencv_core -llzma -ltiff -lpng16 -lz -ljpeg -lopencv_imgproc -ldl -lrt -lwebp -lopencv_features2d -lopencv_flann -dmclkid 0 -sds-sys-config linux -sds-proc linux -sds-pf /home/masaaki/reVISION-Zybo-Z7-20/sdsoc/zybo_z7_20/export/zybo_z7_20
# Log file      : /home/masaaki/sdx_workspaces/revisio_zybo_z7_20_ws/dnp_of/Debug/_sds/reports/sds.log
# Journal file  : /home/masaaki/sdx_workspaces/revisio_zybo_z7_20_ws/dnp_of/Debug/_sds/reports/sds.jou
# Report file   : /home/masaaki/sdx_workspaces/revisio_zybo_z7_20_ws/dnp_of/Debug/_sds/reports/sds.rpt
#-----------------------------------------------------------

-------------------
Design Timing Check
-------------------

  Partition 0
  Vivado Log     : file not found : /home/masaaki/sdx_workspaces/revisio_zybo_z7_20_ws/dnp_of/Debug/_sds/p0/ipi/vivado.log
  Timing Summary : /home/masaaki/sdx_workspaces/revisio_zybo_z7_20_ws/dnp_of/Debug/_sds/p0/_vpl/ipi/imp/imp.runs/impl_1/updated_full_design_timing_summary_routed.rpt

  All user specified timing constraints are met.

Timing Summary Report

Timer Settings
--------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  false

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        



check_timing report

Table of Contents
1. checking no_clock
2. checking constant_clock
3. checking pulse_width_clock
4. checking unconstrained_internal_endpoints
5. checking no_input_delay
6. checking no_output_delay
7. checking multiple_clock
8. checking generated_clocks
9. checking loops
10. checking partial_input_delay
11. checking partial_output_delay
12. checking latch_loops

1. checking no_clock
 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/ar.ar_pipe/m_payload_i_reg[10]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/ar.ar_pipe/m_payload_i_reg[11]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/ar.ar_pipe/m_payload_i_reg[12]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/ar.ar_pipe/m_payload_i_reg[13]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/ar.ar_pipe/m_payload_i_reg[14]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/ar.ar_pipe/m_payload_i_reg[15]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/ar.ar_pipe/m_payload_i_reg[2]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/ar.ar_pipe/m_payload_i_reg[3]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/ar.ar_pipe/m_payload_i_reg[4]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/ar.ar_pipe/m_payload_i_reg[5]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/ar.ar_pipe/m_payload_i_reg[6]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/ar.ar_pipe/m_payload_i_reg[7]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/ar.ar_pipe/m_payload_i_reg[8]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/ar.ar_pipe/m_payload_i_reg[9]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/ar.ar_pipe/m_valid_i_reg/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/aw.aw_pipe/m_payload_i_reg[10]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/aw.aw_pipe/m_payload_i_reg[11]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/aw.aw_pipe/m_payload_i_reg[12]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/aw.aw_pipe/m_payload_i_reg[13]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/aw.aw_pipe/m_payload_i_reg[14]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/aw.aw_pipe/m_payload_i_reg[15]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/aw.aw_pipe/m_payload_i_reg[2]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/aw.aw_pipe/m_payload_i_reg[3]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/aw.aw_pipe/m_payload_i_reg[4]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/aw.aw_pipe/m_payload_i_reg[5]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/aw.aw_pipe/m_payload_i_reg[6]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/aw.aw_pipe/m_payload_i_reg[7]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/aw.aw_pipe/m_payload_i_reg[8]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/aw.aw_pipe/m_payload_i_reg[9]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/aw.aw_pipe/m_valid_i_reg/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/w.w_pipe/m_valid_i_reg/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/w0_xf_DenseNonPyrLKOpticalFlow_1_if/inst/adapter_i/axi_lite_if_i/axi_arready_reg/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/w0_xf_DenseNonPyrLKOpticalFlow_1_if/inst/adapter_i/axi_lite_if_i/axi_awready_reg/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/w0_xf_DenseNonPyrLKOpticalFlow_1_if/inst/adapter_i/axi_lite_if_i/axi_wready_reg/Q (HIGH)


2. checking constant_clock
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints
 There is 1 pin that is not constrained for maximum delay. (HIGH)

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay
 There are 19 input ports with no input delay specified. (HIGH)

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay
 There are 21 ports with no output delay specified. (HIGH)

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops
 There are 0 combinational loops in the design.


10. checking partial_input_delay
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay
 There are 0 ports with partial output delay specified.


12. checking latch_loops
 There are 0 combinational latch loops in the design through latch input



Design Timing Summary
---------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
      0.305        0.000                      0               117480        0.002        0.000                      0               117267        0.013        0.000                       0                 47485  


All user specified timing constraints are met.


Clock Summary
-------------

Clock                                      Waveform(ns)         Period(ns)      Frequency(MHz)
-----                                      ------------         ----------      --------------
clk_fpga_0                                 {0.000 5.000}        10.000          100.000         
  I                                        {0.000 1.000}        2.000           500.000         
    axi_dynclk_0_PXL_CLK_O                 {0.000 4.000}        10.000          100.000         
  mmcm_fbclk_out                           {0.000 5.000}        10.000          100.000         
clk_fpga_1                                 {0.000 3.749}        7.499           133.351         
clk_fpga_2                                 {0.000 2.500}        5.000           200.000         
hdmi_in_clk_p                              {0.000 4.200}        8.400           119.048         
  CLKFBIN                                  {0.000 4.200}        8.400           119.048         
  CLK_OUT_5x_hdmi_clk                      {0.000 0.840}        1.680           595.238         
    PixelClk_int                           {0.000 3.360}        8.400           119.048         
sys_clock                                  {0.000 4.000}        8.000           125.000         
  clk_out1_zybo_z7_20_clk_wiz_0_0          {0.000 41.667}       83.333          12.000          
  clkfbout_zybo_z7_20_clk_wiz_0_0          {0.000 4.000}        8.000           125.000         
zybo_z7_20_i/util_bufg_fclk1/U0/BUFG_O[0]  {0.000 3.750}        7.500           133.333         


-------------------
Data Motion Network
-------------------

Data motion network report generated in /home/masaaki/sdx_workspaces/revisio_zybo_z7_20_ws/dnp_of/Debug/_sds/reports
HTML file : /home/masaaki/sdx_workspaces/revisio_zybo_z7_20_ws/dnp_of/Debug/_sds/reports/data_motion.html

-------------------
Design Utilization
-------------------

  Partition 0
  Utilization Summary : /home/masaaki/sdx_workspaces/revisio_zybo_z7_20_ws/dnp_of/Debug/_sds/p0/_vpl/ipi/imp/imp.runs/impl_1/updated_full_design_utilization_placed.rpt

Utilization Design Information

Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Slice Logic Distribution
3. Memory
4. DSP
5. IO and GT Specific
6. Clocking
7. Specific Feature
8. Primitives
9. Black Boxes
10. Instantiated Netlists

1. Slice Logic
--------------

+----------------------------+-------+-------+-----------+-------+
|          Site Type         |  Used | Fixed | Available | Util% |
+----------------------------+-------+-------+-----------+-------+
| Slice LUTs                 | 29538 |     0 |     53200 | 55.52 |
|   LUT as Logic             | 27404 |     0 |     53200 | 51.51 |
|   LUT as Memory            |  2134 |     0 |     17400 | 12.26 |
|     LUT as Distributed RAM |   856 |     0 |           |       |
|     LUT as Shift Register  |  1278 |     0 |           |       |
| Slice Registers            | 43767 |     0 |    106400 | 41.13 |
|   Register as Flip Flop    | 43766 |     0 |    106400 | 41.13 |
|   Register as Latch        |     1 |     0 |    106400 | <0.01 |
| F7 Muxes                   |   500 |     0 |     26600 |  1.88 |
| F8 Muxes                   |    10 |     0 |     13300 |  0.08 |
+----------------------------+-------+-------+-----------+-------+


1.1 Summary of Registers by Type
--------------------------------

+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0     |            _ |           - |            - |
| 0     |            _ |           - |          Set |
| 0     |            _ |           - |        Reset |
| 0     |            _ |         Set |            - |
| 0     |            _ |       Reset |            - |
| 0     |          Yes |           - |            - |
| 367   |          Yes |           - |          Set |
| 506   |          Yes |           - |        Reset |
| 1586  |          Yes |         Set |            - |
| 41308 |          Yes |       Reset |            - |
+-------+--------------+-------------+--------------+


2. Slice Logic Distribution
---------------------------

+-------------------------------------------+-------+-------+-----------+-------+
|                 Site Type                 |  Used | Fixed | Available | Util% |
+-------------------------------------------+-------+-------+-----------+-------+
| Slice                                     | 11961 |     0 |     13300 | 89.93 |
|   SLICEL                                  |  8007 |     0 |           |       |
|   SLICEM                                  |  3954 |     0 |           |       |
| LUT as Logic                              | 27404 |     0 |     53200 | 51.51 |
|   using O5 output only                    |     0 |       |           |       |
|   using O6 output only                    | 21890 |       |           |       |
|   using O5 and O6                         |  5514 |       |           |       |
| LUT as Memory                             |  2134 |     0 |     17400 | 12.26 |
|   LUT as Distributed RAM                  |   856 |     0 |           |       |
|     using O5 output only                  |     0 |       |           |       |
|     using O6 output only                  |    72 |       |           |       |
|     using O5 and O6                       |   784 |       |           |       |
|   LUT as Shift Register                   |  1278 |     0 |           |       |
|     using O5 output only                  |   146 |       |           |       |
|     using O6 output only                  |   680 |       |           |       |
|     using O5 and O6                       |   452 |       |           |       |
| LUT Flip Flop Pairs                       | 16354 |     0 |     53200 | 30.74 |
|   fully used LUT-FF pairs                 |  3782 |       |           |       |
|   LUT-FF pairs with one unused LUT output | 11965 |       |           |       |
|   LUT-FF pairs with one unused Flip Flop  | 10614 |       |           |       |
| Unique Control Sets                       |  1717 |       |           |       |
+-------------------------------------------+-------+-------+-----------+-------+
* Note: Review the Control Sets Report for more information regarding control sets.


3. Memory
---------

+-------------------+------+-------+-----------+-------+
|     Site Type     | Used | Fixed | Available | Util% |
+-------------------+------+-------+-----------+-------+
| Block RAM Tile    |  128 |     0 |       140 | 91.43 |
|   RAMB36/FIFO*    |  119 |     0 |       140 | 85.00 |
|     FIFO36E1 only |    6 |       |           |       |
|     RAMB36E1 only |  113 |       |           |       |
|   RAMB18          |   18 |     0 |       280 |  6.43 |
|     RAMB18E1 only |   18 |       |           |       |
+-------------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1


4. DSP
------

+----------------+------+-------+-----------+-------+
|    Site Type   | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
| DSPs           |   37 |     0 |       220 | 16.82 |
|   DSP48E1 only |   37 |       |           |       |
+----------------+------+-------+-----------+-------+


5. IO and GT Specific
---------------------

+-----------------------------+------+-------+-----------+--------+
|          Site Type          | Used | Fixed | Available |  Util% |
+-----------------------------+------+-------+-----------+--------+
| Bonded IOB                  |   58 |    58 |       125 |  46.40 |
|   IOB Master Pads           |   29 |       |           |        |
|   IOB Slave Pads            |   26 |       |           |        |
| Bonded IPADs                |    2 |     2 |         2 | 100.00 |
| Bonded IOPADs               |  130 |   130 |       130 | 100.00 |
| PHY_CONTROL                 |    0 |     0 |         4 |   0.00 |
| PHASER_REF                  |    0 |     0 |         4 |   0.00 |
| OUT_FIFO                    |    0 |     0 |        16 |   0.00 |
| IN_FIFO                     |    0 |     0 |        16 |   0.00 |
| IDELAYCTRL                  |    1 |     0 |         4 |  25.00 |
| IBUFDS                      |    4 |     4 |       121 |   3.31 |
| PHASER_OUT/PHASER_OUT_PHY   |    0 |     0 |        16 |   0.00 |
| PHASER_IN/PHASER_IN_PHY     |    0 |     0 |        16 |   0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY |    3 |     3 |       200 |   1.50 |
|   IDELAYE2 only             |    3 |     3 |           |        |
| ILOGIC                      |    6 |     6 |       125 |   4.80 |
|   ISERDES                   |    6 |     6 |           |        |
| OLOGIC                      |    8 |     8 |       125 |   6.40 |
|   OSERDES                   |    8 |     8 |           |        |
+-----------------------------+------+-------+-----------+--------+


6. Clocking
-----------

+--------------+------+-------+-----------+-------+
|   Site Type  | Used | Fixed | Available | Util% |
+--------------+------+-------+-----------+-------+
| BUFGCTRL     |    6 |     0 |        32 | 18.75 |
| BUFIO        |    2 |     0 |        16 | 12.50 |
|   BUFIO only |    2 |     0 |           |       |
| MMCME2_ADV   |    2 |     0 |         4 | 50.00 |
| PLLE2_ADV    |    1 |     0 |         4 | 25.00 |
| BUFMRCE      |    0 |     0 |         8 |  0.00 |
| BUFHCE       |    0 |     0 |        72 |  0.00 |
| BUFR         |    2 |     0 |        16 | 12.50 |
+--------------+------+-------+-----------+-------+


7. Specific Feature
-------------------

+-------------+------+-------+-----------+--------+
|  Site Type  | Used | Fixed | Available |  Util% |
+-------------+------+-------+-----------+--------+
| BSCANE2     |    0 |     0 |         4 |   0.00 |
| CAPTUREE2   |    0 |     0 |         1 |   0.00 |
| DNA_PORT    |    0 |     0 |         1 |   0.00 |
| EFUSE_USR   |    0 |     0 |         1 |   0.00 |
| FRAME_ECCE2 |    0 |     0 |         1 |   0.00 |
| ICAPE2      |    0 |     0 |         2 |   0.00 |
| STARTUPE2   |    0 |     0 |         1 |   0.00 |
| XADC        |    1 |     1 |         1 | 100.00 |
+-------------+------+-------+-----------+--------+


8. Primitives
-------------

+------------+-------+----------------------+
|  Ref Name  |  Used |  Functional Category |
+------------+-------+----------------------+
| FDRE       | 41308 |         Flop & Latch |
| LUT3       |  9718 |                  LUT |
| LUT6       |  7369 |                  LUT |
| LUT4       |  5355 |                  LUT |
| LUT2       |  5113 |                  LUT |
| LUT5       |  4451 |                  LUT |
| CARRY4     |  1924 |           CarryLogic |
| FDSE       |  1586 |         Flop & Latch |
| SRL16E     |  1270 |   Distributed Memory |
| RAMD32     |  1184 |   Distributed Memory |
| LUT1       |   912 |                  LUT |
| FDCE       |   505 |         Flop & Latch |
| MUXF7      |   500 |                MuxFx |
| SRLC32E    |   460 |   Distributed Memory |
| RAMS32     |   392 |   Distributed Memory |
| FDPE       |   367 |         Flop & Latch |
| BIBUF      |   130 |                   IO |
| RAMB36E1   |   113 |         Block Memory |
| RAMD64E    |    64 |   Distributed Memory |
| DSP48E1    |    37 |     Block Arithmetic |
| IBUF       |    31 |                   IO |
| RAMB18E1   |    18 |         Block Memory |
| OBUF       |    13 |                   IO |
| OBUFT      |    11 |                   IO |
| MUXF8      |    10 |                MuxFx |
| OSERDESE2  |     8 |                   IO |
| ISERDESE2  |     6 |                   IO |
| FIFO36E1   |     6 |         Block Memory |
| BUFG       |     6 |                Clock |
| OBUFDS     |     4 |                   IO |
| IBUFDS     |     4 |                   IO |
| IDELAYE2   |     3 |                   IO |
| MMCME2_ADV |     2 |                Clock |
| BUFR       |     2 |                Clock |
| BUFIO      |     2 |                Clock |
| XADC       |     1 |               Others |
| PS7        |     1 | Specialized Resource |
| PLLE2_ADV  |     1 |                Clock |
| LDCE       |     1 |         Flop & Latch |
| IDELAYCTRL |     1 |                   IO |
+------------+-------+----------------------+


9. Black Boxes
--------------

+----------+------+
| Ref Name | Used |
+----------+------+


10. Instantiated Netlists
-------------------------

+--------------------------------------------------+------+
|                     Ref Name                     | Used |
+--------------------------------------------------+------+
| zybo_z7_20_xlconstant_1_0                        |    1 |
| zybo_z7_20_xlconcat_0_0                          |    1 |
| zybo_z7_20_xbar_4                                |    1 |
| zybo_z7_20_xbar_3                                |    1 |
| zybo_z7_20_xbar_2                                |    1 |
| zybo_z7_20_xbar_1                                |    1 |
| zybo_z7_20_xbar_0                                |    1 |
| zybo_z7_20_xadc_wiz_0_0                          |    1 |
| zybo_z7_20_w0_xf_DenseNonPyrLKOpticalFlow_1_if_0 |    1 |
| zybo_z7_20_w0_xf_DenseNonPyrLKOpticalFlow_1_0    |    1 |
| zybo_z7_20_v_vid_in_axi4s_0_0                    |    1 |
| zybo_z7_20_v_tc_out_0                            |    1 |
| zybo_z7_20_v_tc_in_0                             |    1 |
| zybo_z7_20_v_axi4s_vid_out_0_0                   |    1 |
| zybo_z7_20_util_bufg_fclk1_0                     |    1 |
| zybo_z7_20_sgdma2axis_dm_1_0                     |    1 |
| zybo_z7_20_sgdma2axis_dm_0_0                     |    1 |
| zybo_z7_20_sds_irq_const_0                       |    1 |
| zybo_z7_20_s02_regslice_1                        |    1 |
| zybo_z7_20_s02_regslice_0                        |    1 |
| zybo_z7_20_s01_regslice_2                        |    1 |
| zybo_z7_20_s01_regslice_1                        |    1 |
| zybo_z7_20_s01_regslice_0                        |    1 |
| zybo_z7_20_s01_data_fifo_1                       |    1 |
| zybo_z7_20_s01_data_fifo_0                       |    1 |
| zybo_z7_20_s00_regslice_5                        |    1 |
| zybo_z7_20_s00_regslice_4                        |    1 |
| zybo_z7_20_s00_regslice_3                        |    1 |
| zybo_z7_20_s00_regslice_2                        |    1 |
| zybo_z7_20_s00_regslice_1                        |    1 |
| zybo_z7_20_s00_regslice_0                        |    1 |
| zybo_z7_20_s00_data_fifo_2                       |    1 |
| zybo_z7_20_s00_data_fifo_1                       |    1 |
| zybo_z7_20_s00_data_fifo_0                       |    1 |
| zybo_z7_20_rgb2dvi_1_0                           |    1 |
| zybo_z7_20_pwm_rgb_0                             |    1 |
| zybo_z7_20_psr_fclk1_0                           |    1 |
| zybo_z7_20_psr_fclk0_0                           |    1 |
| zybo_z7_20_processing_system7_0_0                |    1 |
| zybo_z7_20_proc_sys_reset_0_0                    |    1 |
| zybo_z7_20_m02_regslice_0                        |    1 |
| zybo_z7_20_m01_regslice_0                        |    1 |
| zybo_z7_20_m00_regslice_3                        |    1 |
| zybo_z7_20_m00_regslice_2                        |    1 |
| zybo_z7_20_m00_regslice_1                        |    1 |
| zybo_z7_20_m00_regslice_0                        |    1 |
| zybo_z7_20_m00_data_fifo_1                       |    1 |
| zybo_z7_20_m00_data_fifo_0                       |    1 |
| zybo_z7_20_dvi2rgb_1_0                           |    1 |
| zybo_z7_20_dm_1_0                                |    1 |
| zybo_z7_20_dm_0_0                                |    1 |
| zybo_z7_20_clk_wiz_0_0                           |    1 |
| zybo_z7_20_axis_subset_converter_out_0           |    1 |
| zybo_z7_20_axis_subset_converter_in_0            |    1 |
| zybo_z7_20_axis2sgdma_dm_1_0                     |    1 |
| zybo_z7_20_axis2sgdma_dm_0_0                     |    1 |
| zybo_z7_20_axi_vdma_1_0                          |    1 |
| zybo_z7_20_axi_vdma_0_0                          |    1 |
| zybo_z7_20_axi_i2s_adi_0_0                       |    1 |
| zybo_z7_20_axi_gpio_video_0                      |    1 |
| zybo_z7_20_axi_gpio_sw_btn_0                     |    1 |
| zybo_z7_20_axi_gpio_led_0                        |    1 |
| zybo_z7_20_axi_gpio_eth_0                        |    1 |
| zybo_z7_20_axi_dynclk_0_0                        |    1 |
| zybo_z7_20_auto_us_df_1                          |    1 |
| zybo_z7_20_auto_us_df_0                          |    1 |
| zybo_z7_20_auto_ss_slid_1                        |    1 |
| zybo_z7_20_auto_ss_slid_0                        |    1 |
| zybo_z7_20_auto_pc_4                             |    1 |
| zybo_z7_20_auto_pc_3                             |    1 |
| zybo_z7_20_auto_pc_2                             |    1 |
| zybo_z7_20_auto_pc_1                             |    1 |
| zybo_z7_20_auto_pc_0                             |    1 |
+--------------------------------------------------+------+

  1. 2018年03月29日 05:02 |
  2. reVISION, xfOpenCV
  3. | トラックバック:0
  4. | コメント:0

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