FC2カウンター FPGAの部屋 2018年03月25日
FC2ブログ

FPGAやCPLDの話題やFPGA用のツールの話題などです。 マニアックです。 日記も書きます。

FPGAの部屋

FPGAの部屋の有用と思われるコンテンツのまとめサイトを作りました。Xilinx ISEの初心者の方には、FPGAリテラシーおよびチュートリアルのページをお勧めいたします。

reVISION-Zybo-Z7-20をやってみた5(バイラテラル・フィルタのサンプルのコンパイル)

reVISION-Zybo-Z7-20をやってみた4(SDx用プラットフォームの作成)”の続き。

前回は、SDx のプラットフォーム作成機能を使用して、ZYBO-Z7-20 の reVISION プラットフォームを作成した。今回は、そのZYBO-Z7-20 の reVISION プラットフォームを使用して、バイラテラル・フィルタのサンプルをやってみよう。

なお、この記事は、Digilent/reVISION-Zybo-Z7-20 を元にブログを書いている。
今回は、reVISION-Zybo-Z7-20/sdsoc/zybo_z7_20/ ディレクトリの README.txt を参考に進めていく。

SDx の環境を設定して、SYSROOT 環境変数をセットし、SDx を起動する。
source /opt/Xilinx/SDx/2017.4/settings64.sh
export SYSROOT=~/reVISION-Zybo-Z7-20/sdsoc/zybo_z7_20/export/zybo_z7_20/sw/sysroot
sdx &

reVISION-Zybo-Z7-20_54_120325.png

ワークスペースを設定する。ここでは、/home/masaaki/sdx_workspaces/revisio_zybo_z7_20_ws に設定した。現在、SDx のバグで空のワークスペースを指定する必要があるそうだ。
reVISION-Zybo-Z7-20_55_120325.png

SDx が起動した。
reVISION-Zybo-Z7-20_56_120325.png

Xilinx メニューから Add Custom Platform... を選択した。

Hardware Platform Repositories ダイアログが表示された。
Manage(Custom) タブで Add Custom Platform... ボタンをクリックする。
reVISION-Zybo-Z7-20_57_120325.png

Specify Custom Platform Location (Directory) ダイアログで、reVISION-Zybo-Z7-20/sdsoc/zybo_z7_20/export/zybo_z7_20/ ディレクトリを指定して、OK ボタンをクリックした。
reVISION-Zybo-Z7-20_58_120325.png

zybo_z7_20 が入った。OK ボタンをクリックした。
reVISION-Zybo-Z7-20_59_120325.png

これで、zybo_z7_20 のカスタムプラットフォームがSDx に追加されたはず。。。
バイラテラル・フィルタのサンプルを作成してみよう。

File メニューからNew -> SDx Project... を選択した。

New SDx Project ダイアログが表示された。
デフォルトのApplication Project のまま、Next > ボタンをクリックした。
reVISION-Zybo-Z7-20_60_120325.png

Project name に bilateral_ex と入力して、Next > ボタンをクリックした。
reVISION-Zybo-Z7-20_61_120325.png

Platform 画面では、zybo_z7_20 [custom] を選択して、Next > ボタンをクリックした。
reVISION-Zybo-Z7-20_62_120325.png

System configuration は Linux を選択ということだったが、他は選べない。
reVISION-Zybo-Z7-20_63_120325.png

Templates では、Bilateral を選択した。
reVISION-Zybo-Z7-20_64_120325.png

bilateral_ex プロジェクトが生成された。
reVISION-Zybo-Z7-20_65_120325.png

トンカチ・アイコンをクリックして、コンパイルを行った。
reVISION-Zybo-Z7-20_66_120325.png

1時間位かかって、コンパイルが終了した。
reVISION-Zybo-Z7-20_67_120325.png

sds.rpt を見てみる。
reVISION-Zybo-Z7-20_68_120325.png

revision_zybo_z7_20_ws/bilatreral_ex/Debug/sd_card/ ディレクトリを示す。
reVISION-Zybo-Z7-20_69_120325.png

sds.rpt を示す。

(c) Copyright 2012-2017 Xilinx, Inc. All Rights Reserved.
#-----------------------------------------------------------
# Tool version  : sds++ 2017.4 SW Build 2086221 on Fri Dec 15 20:55:10 MST 2017
# Start time    : Sun Mar 25 04:22:41 JST 2018
# Command line  : sds++ --sysroot=/home/masaaki/reVISION-Zybo-Z7-20/sdsoc/zybo_z7_20/export/zybo_z7_20/sw/sysroot -L=/lib -L=/usr/lib -Wl,-rpath-link=/home/masaaki/reVISION-Zybo-Z7-20/sdsoc/zybo_z7_20/export/zybo_z7_20/sw/sysroot/lib,-rpath-link=/home/masaaki/reVISION-Zybo-Z7-20/sdsoc/zybo_z7_20/export/zybo_z7_20/sw/sysroot/usr/lib -sdcard ../data --remote_ip_cache /home/masaaki/sdx_workspaces/revisio_zybo_z7_20_ws/ip_cache -o bilateral_ex.elf ./src/xf_bilateral_filter_accel.o ./src/xf_bilateral_filter_tb.o -lglib-2.0 -ldrm -lv4l2subdev -lmediactl -lopencv_imgcodecs -lopencv_core -llzma -ltiff -lpng16 -lz -ljpeg -lopencv_imgproc -ldl -lrt -lwebp -lopencv_features2d -lopencv_flann -lopencv_calib3d -dmclkid 0 -sds-sys-config linux -sds-proc linux -sds-pf /home/masaaki/reVISION-Zybo-Z7-20/sdsoc/zybo_z7_20/export/zybo_z7_20
# Log file      : /home/masaaki/sdx_workspaces/revisio_zybo_z7_20_ws/bilateral_ex/Debug/_sds/reports/sds.log
# Journal file  : /home/masaaki/sdx_workspaces/revisio_zybo_z7_20_ws/bilateral_ex/Debug/_sds/reports/sds.jou
# Report file   : /home/masaaki/sdx_workspaces/revisio_zybo_z7_20_ws/bilateral_ex/Debug/_sds/reports/sds.rpt
#-----------------------------------------------------------

-------------------
Design Timing Check
-------------------

  Partition 0
  Vivado Log     : file not found : /home/masaaki/sdx_workspaces/revisio_zybo_z7_20_ws/bilateral_ex/Debug/_sds/p0/ipi/vivado.log
  Timing Summary : /home/masaaki/sdx_workspaces/revisio_zybo_z7_20_ws/bilateral_ex/Debug/_sds/p0/_vpl/ipi/imp/imp.runs/impl_1/updated_full_design_timing_summary_routed.rpt

  All user specified timing constraints are met.

Timing Summary Report

Timer Settings
--------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  false

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        



check_timing report

Table of Contents
1. checking no_clock
2. checking constant_clock
3. checking pulse_width_clock
4. checking unconstrained_internal_endpoints
5. checking no_input_delay
6. checking no_output_delay
7. checking multiple_clock
8. checking generated_clocks
9. checking loops
10. checking partial_input_delay
11. checking partial_output_delay
12. checking latch_loops

1. checking no_clock
 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/ar.ar_pipe/m_payload_i_reg[10]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/ar.ar_pipe/m_payload_i_reg[11]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/ar.ar_pipe/m_payload_i_reg[12]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/ar.ar_pipe/m_payload_i_reg[13]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/ar.ar_pipe/m_payload_i_reg[14]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/ar.ar_pipe/m_payload_i_reg[15]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/ar.ar_pipe/m_payload_i_reg[2]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/ar.ar_pipe/m_payload_i_reg[3]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/ar.ar_pipe/m_payload_i_reg[4]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/ar.ar_pipe/m_payload_i_reg[5]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/ar.ar_pipe/m_payload_i_reg[6]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/ar.ar_pipe/m_payload_i_reg[7]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/ar.ar_pipe/m_payload_i_reg[8]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/ar.ar_pipe/m_payload_i_reg[9]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/ar.ar_pipe/m_valid_i_reg/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/aw.aw_pipe/m_payload_i_reg[10]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/aw.aw_pipe/m_payload_i_reg[11]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/aw.aw_pipe/m_payload_i_reg[12]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/aw.aw_pipe/m_payload_i_reg[13]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/aw.aw_pipe/m_payload_i_reg[14]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/aw.aw_pipe/m_payload_i_reg[15]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/aw.aw_pipe/m_payload_i_reg[2]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/aw.aw_pipe/m_payload_i_reg[3]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/aw.aw_pipe/m_payload_i_reg[4]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/aw.aw_pipe/m_payload_i_reg[5]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/aw.aw_pipe/m_payload_i_reg[6]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/aw.aw_pipe/m_payload_i_reg[7]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/aw.aw_pipe/m_payload_i_reg[8]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/aw.aw_pipe/m_payload_i_reg[9]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/aw.aw_pipe/m_valid_i_reg/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/axi_ic_processing_system7_0_M_AXI_GP1/m00_couplers/m00_regslice/inst/w.w_pipe/m_valid_i_reg/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/w0_xf_bilateralFilter_1_if/inst/adapter_i/axi_lite_if_i/axi_arready_reg/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/w0_xf_bilateralFilter_1_if/inst/adapter_i/axi_lite_if_i/axi_awready_reg/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: zybo_z7_20_i/w0_xf_bilateralFilter_1_if/inst/adapter_i/axi_lite_if_i/axi_wready_reg/Q (HIGH)


2. checking constant_clock
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints
 There is 1 pin that is not constrained for maximum delay. (HIGH)

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay
 There are 19 input ports with no input delay specified. (HIGH)

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay
 There are 21 ports with no output delay specified. (HIGH)

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops
 There are 0 combinational loops in the design.


10. checking partial_input_delay
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay
 There are 0 ports with partial output delay specified.


12. checking latch_loops
 There are 0 combinational latch loops in the design through latch input



Design Timing Summary
---------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
      0.423        0.000                      0                87494        0.051        0.000                      0                87281        0.013        0.000                       0                 36432  


All user specified timing constraints are met.


Clock Summary
-------------

Clock                                      Waveform(ns)         Period(ns)      Frequency(MHz)
-----                                      ------------         ----------      --------------
clk_fpga_0                                 {0.000 5.000}        10.000          100.000         
  I                                        {0.000 1.000}        2.000           500.000         
    axi_dynclk_0_PXL_CLK_O                 {0.000 4.000}        10.000          100.000         
  mmcm_fbclk_out                           {0.000 5.000}        10.000          100.000         
clk_fpga_1                                 {0.000 3.749}        7.499           133.351         
clk_fpga_2                                 {0.000 2.500}        5.000           200.000         
hdmi_in_clk_p                              {0.000 4.200}        8.400           119.048         
  CLKFBIN                                  {0.000 4.200}        8.400           119.048         
  CLK_OUT_5x_hdmi_clk                      {0.000 0.840}        1.680           595.238         
    PixelClk_int                           {0.000 3.360}        8.400           119.048         
sys_clock                                  {0.000 4.000}        8.000           125.000         
  clk_out1_zybo_z7_20_clk_wiz_0_0          {0.000 41.667}       83.333          12.000          
  clkfbout_zybo_z7_20_clk_wiz_0_0          {0.000 4.000}        8.000           125.000         
zybo_z7_20_i/util_bufg_fclk1/U0/BUFG_O[0]  {0.000 3.750}        7.500           133.333         


-------------------
Data Motion Network
-------------------

Data motion network report generated in /home/masaaki/sdx_workspaces/revisio_zybo_z7_20_ws/bilateral_ex/Debug/_sds/reports
HTML file : /home/masaaki/sdx_workspaces/revisio_zybo_z7_20_ws/bilateral_ex/Debug/_sds/reports/data_motion.html

-------------------
Design Utilization
-------------------

  Partition 0
  Utilization Summary : /home/masaaki/sdx_workspaces/revisio_zybo_z7_20_ws/bilateral_ex/Debug/_sds/p0/_vpl/ipi/imp/imp.runs/impl_1/updated_full_design_utilization_placed.rpt

Utilization Design Information

Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Slice Logic Distribution
3. Memory
4. DSP
5. IO and GT Specific
6. Clocking
7. Specific Feature
8. Primitives
9. Black Boxes
10. Instantiated Netlists

1. Slice Logic
--------------

+----------------------------+-------+-------+-----------+-------+
|          Site Type         |  Used | Fixed | Available | Util% |
+----------------------------+-------+-------+-----------+-------+
| Slice LUTs                 | 21009 |     0 |     53200 | 39.49 |
|   LUT as Logic             | 19537 |     0 |     53200 | 36.72 |
|   LUT as Memory            |  1472 |     0 |     17400 |  8.46 |
|     LUT as Distributed RAM |   832 |     0 |           |       |
|     LUT as Shift Register  |   640 |     0 |           |       |
| Slice Registers            | 33711 |     0 |    106400 | 31.68 |
|   Register as Flip Flop    | 33710 |     0 |    106400 | 31.68 |
|   Register as Latch        |     1 |     0 |    106400 | <0.01 |
| F7 Muxes                   |   415 |     0 |     26600 |  1.56 |
| F8 Muxes                   |     9 |     0 |     13300 |  0.07 |
+----------------------------+-------+-------+-----------+-------+


1.1 Summary of Registers by Type
--------------------------------

+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0     |            _ |           - |            - |
| 0     |            _ |           - |          Set |
| 0     |            _ |           - |        Reset |
| 0     |            _ |         Set |            - |
| 0     |            _ |       Reset |            - |
| 0     |          Yes |           - |            - |
| 324   |          Yes |           - |          Set |
| 455   |          Yes |           - |        Reset |
| 1014  |          Yes |         Set |            - |
| 31918 |          Yes |       Reset |            - |
+-------+--------------+-------------+--------------+


2. Slice Logic Distribution
---------------------------

+-------------------------------------------+-------+-------+-----------+-------+
|                 Site Type                 |  Used | Fixed | Available | Util% |
+-------------------------------------------+-------+-------+-----------+-------+
| Slice                                     |  9828 |     0 |     13300 | 73.89 |
|   SLICEL                                  |  6608 |     0 |           |       |
|   SLICEM                                  |  3220 |     0 |           |       |
| LUT as Logic                              | 19537 |     0 |     53200 | 36.72 |
|   using O5 output only                    |     2 |       |           |       |
|   using O6 output only                    | 15265 |       |           |       |
|   using O5 and O6                         |  4270 |       |           |       |
| LUT as Memory                             |  1472 |     0 |     17400 |  8.46 |
|   LUT as Distributed RAM                  |   832 |     0 |           |       |
|     using O5 output only                  |     0 |       |           |       |
|     using O6 output only                  |    72 |       |           |       |
|     using O5 and O6                       |   760 |       |           |       |
|   LUT as Shift Register                   |   640 |     0 |           |       |
|     using O5 output only                  |    63 |       |           |       |
|     using O6 output only                  |   243 |       |           |       |
|     using O5 and O6                       |   334 |       |           |       |
| LUT Flip Flop Pairs                       | 11470 |     0 |     53200 | 21.56 |
|   fully used LUT-FF pairs                 |  3028 |       |           |       |
|   LUT-FF pairs with one unused LUT output |  7936 |       |           |       |
|   LUT-FF pairs with one unused Flip Flop  |  7105 |       |           |       |
| Unique Control Sets                       |  1406 |       |           |       |
+-------------------------------------------+-------+-------+-----------+-------+
* Note: Review the Control Sets Report for more information regarding control sets.


3. Memory
---------

+-------------------+------+-------+-----------+-------+
|     Site Type     | Used | Fixed | Available | Util% |
+-------------------+------+-------+-----------+-------+
| Block RAM Tile    | 34.5 |     0 |       140 | 24.64 |
|   RAMB36/FIFO*    |   24 |     0 |       140 | 17.14 |
|     FIFO36E1 only |    6 |       |           |       |
|     RAMB36E1 only |   18 |       |           |       |
|   RAMB18          |   21 |     0 |       280 |  7.50 |
|     RAMB18E1 only |   21 |       |           |       |
+-------------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1


4. DSP
------

+----------------+------+-------+-----------+-------+
|    Site Type   | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
| DSPs           |   19 |     0 |       220 |  8.64 |
|   DSP48E1 only |   19 |       |           |       |
+----------------+------+-------+-----------+-------+


5. IO and GT Specific
---------------------

+-----------------------------+------+-------+-----------+--------+
|          Site Type          | Used | Fixed | Available |  Util% |
+-----------------------------+------+-------+-----------+--------+
| Bonded IOB                  |   58 |    58 |       125 |  46.40 |
|   IOB Master Pads           |   29 |       |           |        |
|   IOB Slave Pads            |   26 |       |           |        |
| Bonded IPADs                |    2 |     2 |         2 | 100.00 |
| Bonded IOPADs               |  130 |   130 |       130 | 100.00 |
| PHY_CONTROL                 |    0 |     0 |         4 |   0.00 |
| PHASER_REF                  |    0 |     0 |         4 |   0.00 |
| OUT_FIFO                    |    0 |     0 |        16 |   0.00 |
| IN_FIFO                     |    0 |     0 |        16 |   0.00 |
| IDELAYCTRL                  |    1 |     0 |         4 |  25.00 |
| IBUFDS                      |    4 |     4 |       121 |   3.31 |
| PHASER_OUT/PHASER_OUT_PHY   |    0 |     0 |        16 |   0.00 |
| PHASER_IN/PHASER_IN_PHY     |    0 |     0 |        16 |   0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY |    3 |     3 |       200 |   1.50 |
|   IDELAYE2 only             |    3 |     3 |           |        |
| ILOGIC                      |    6 |     6 |       125 |   4.80 |
|   ISERDES                   |    6 |     6 |           |        |
| OLOGIC                      |    8 |     8 |       125 |   6.40 |
|   OSERDES                   |    8 |     8 |           |        |
+-----------------------------+------+-------+-----------+--------+


6. Clocking
-----------

+--------------+------+-------+-----------+-------+
|   Site Type  | Used | Fixed | Available | Util% |
+--------------+------+-------+-----------+-------+
| BUFGCTRL     |    6 |     0 |        32 | 18.75 |
| BUFIO        |    2 |     0 |        16 | 12.50 |
|   BUFIO only |    2 |     0 |           |       |
| MMCME2_ADV   |    2 |     0 |         4 | 50.00 |
| PLLE2_ADV    |    1 |     0 |         4 | 25.00 |
| BUFMRCE      |    0 |     0 |         8 |  0.00 |
| BUFHCE       |    0 |     0 |        72 |  0.00 |
| BUFR         |    2 |     0 |        16 | 12.50 |
+--------------+------+-------+-----------+-------+


7. Specific Feature
-------------------

+-------------+------+-------+-----------+--------+
|  Site Type  | Used | Fixed | Available |  Util% |
+-------------+------+-------+-----------+--------+
| BSCANE2     |    0 |     0 |         4 |   0.00 |
| CAPTUREE2   |    0 |     0 |         1 |   0.00 |
| DNA_PORT    |    0 |     0 |         1 |   0.00 |
| EFUSE_USR   |    0 |     0 |         1 |   0.00 |
| FRAME_ECCE2 |    0 |     0 |         1 |   0.00 |
| ICAPE2      |    0 |     0 |         2 |   0.00 |
| STARTUPE2   |    0 |     0 |         1 |   0.00 |
| XADC        |    1 |     1 |         1 | 100.00 |
+-------------+------+-------+-----------+--------+


8. Primitives
-------------

+------------+-------+----------------------+
|  Ref Name  |  Used |  Functional Category |
+------------+-------+----------------------+
| FDRE       | 31918 |         Flop & Latch |
| LUT3       |  6113 |                  LUT |
| LUT6       |  5724 |                  LUT |
| LUT5       |  3828 |                  LUT |
| LUT4       |  3735 |                  LUT |
| LUT2       |  3520 |                  LUT |
| RAMD32     |  1148 |   Distributed Memory |
| CARRY4     |  1122 |           CarryLogic |
| FDSE       |  1014 |         Flop & Latch |
| LUT1       |   887 |                  LUT |
| SRL16E     |   879 |   Distributed Memory |
| FDCE       |   454 |         Flop & Latch |
| MUXF7      |   415 |                MuxFx |
| RAMS32     |   380 |   Distributed Memory |
| FDPE       |   324 |         Flop & Latch |
| BIBUF      |   130 |                   IO |
| SRLC32E    |    95 |   Distributed Memory |
| RAMD64E    |    64 |   Distributed Memory |
| IBUF       |    31 |                   IO |
| RAMB18E1   |    21 |         Block Memory |
| DSP48E1    |    19 |     Block Arithmetic |
| RAMB36E1   |    18 |         Block Memory |
| OBUF       |    13 |                   IO |
| OBUFT      |    11 |                   IO |
| MUXF8      |     9 |                MuxFx |
| OSERDESE2  |     8 |                   IO |
| ISERDESE2  |     6 |                   IO |
| FIFO36E1   |     6 |         Block Memory |
| BUFG       |     6 |                Clock |
| OBUFDS     |     4 |                   IO |
| IBUFDS     |     4 |                   IO |
| IDELAYE2   |     3 |                   IO |
| MMCME2_ADV |     2 |                Clock |
| BUFR       |     2 |                Clock |
| BUFIO      |     2 |                Clock |
| XADC       |     1 |               Others |
| PS7        |     1 | Specialized Resource |
| PLLE2_ADV  |     1 |                Clock |
| LDCE       |     1 |         Flop & Latch |
| IDELAYCTRL |     1 |                   IO |
+------------+-------+----------------------+


9. Black Boxes
--------------

+----------+------+
| Ref Name | Used |
+----------+------+


10. Instantiated Netlists
-------------------------

+-----------------------------------------+------+
|                 Ref Name                | Used |
+-----------------------------------------+------+
| zybo_z7_20_xlconstant_1_0               |    1 |
| zybo_z7_20_xlconcat_0_0                 |    1 |
| zybo_z7_20_xbar_4                       |    1 |
| zybo_z7_20_xbar_3                       |    1 |
| zybo_z7_20_xbar_2                       |    1 |
| zybo_z7_20_xbar_1                       |    1 |
| zybo_z7_20_xbar_0                       |    1 |
| zybo_z7_20_xadc_wiz_0_0                 |    1 |
| zybo_z7_20_w0_xf_bilateralFilter_1_if_0 |    1 |
| zybo_z7_20_w0_xf_bilateralFilter_1_0    |    1 |
| zybo_z7_20_v_vid_in_axi4s_0_0           |    1 |
| zybo_z7_20_v_tc_out_0                   |    1 |
| zybo_z7_20_v_tc_in_0                    |    1 |
| zybo_z7_20_v_axi4s_vid_out_0_0          |    1 |
| zybo_z7_20_util_bufg_fclk1_0            |    1 |
| zybo_z7_20_sgdma2axis_dm_0_0            |    1 |
| zybo_z7_20_sds_irq_const_0              |    1 |
| zybo_z7_20_s01_regslice_2               |    1 |
| zybo_z7_20_s01_regslice_1               |    1 |
| zybo_z7_20_s01_regslice_0               |    1 |
| zybo_z7_20_s00_regslice_4               |    1 |
| zybo_z7_20_s00_regslice_3               |    1 |
| zybo_z7_20_s00_regslice_2               |    1 |
| zybo_z7_20_s00_regslice_1               |    1 |
| zybo_z7_20_s00_regslice_0               |    1 |
| zybo_z7_20_s00_data_fifo_2              |    1 |
| zybo_z7_20_s00_data_fifo_1              |    1 |
| zybo_z7_20_s00_data_fifo_0              |    1 |
| zybo_z7_20_rgb2dvi_1_0                  |    1 |
| zybo_z7_20_pwm_rgb_0                    |    1 |
| zybo_z7_20_psr_fclk1_0                  |    1 |
| zybo_z7_20_psr_fclk0_0                  |    1 |
| zybo_z7_20_processing_system7_0_0       |    1 |
| zybo_z7_20_proc_sys_reset_0_0           |    1 |
| zybo_z7_20_m02_regslice_0               |    1 |
| zybo_z7_20_m01_regslice_0               |    1 |
| zybo_z7_20_m00_regslice_3               |    1 |
| zybo_z7_20_m00_regslice_2               |    1 |
| zybo_z7_20_m00_regslice_1               |    1 |
| zybo_z7_20_m00_regslice_0               |    1 |
| zybo_z7_20_m00_data_fifo_1              |    1 |
| zybo_z7_20_m00_data_fifo_0              |    1 |
| zybo_z7_20_dvi2rgb_1_0                  |    1 |
| zybo_z7_20_dm_1_0                       |    1 |
| zybo_z7_20_dm_0_0                       |    1 |
| zybo_z7_20_clk_wiz_0_0                  |    1 |
| zybo_z7_20_axis_subset_converter_out_0  |    1 |
| zybo_z7_20_axis_subset_converter_in_0   |    1 |
| zybo_z7_20_axis2sgdma_dm_1_0            |    1 |
| zybo_z7_20_axi_vdma_1_0                 |    1 |
| zybo_z7_20_axi_vdma_0_0                 |    1 |
| zybo_z7_20_axi_i2s_adi_0_0              |    1 |
| zybo_z7_20_axi_gpio_video_0             |    1 |
| zybo_z7_20_axi_gpio_sw_btn_0            |    1 |
| zybo_z7_20_axi_gpio_led_0               |    1 |
| zybo_z7_20_axi_gpio_eth_0               |    1 |
| zybo_z7_20_axi_dynclk_0_0               |    1 |
| zybo_z7_20_auto_us_df_1                 |    1 |
| zybo_z7_20_auto_us_df_0                 |    1 |
| zybo_z7_20_auto_ss_slid_0               |    1 |
| zybo_z7_20_auto_pc_4                    |    1 |
| zybo_z7_20_auto_pc_3                    |    1 |
| zybo_z7_20_auto_pc_2                    |    1 |
| zybo_z7_20_auto_pc_1                    |    1 |
| zybo_z7_20_auto_pc_0                    |    1 |
+-----------------------------------------+------+

  1. 2018年03月25日 14:35 |
  2. reVISION, xfOpenCV
  3. | トラックバック:0
  4. | コメント:0