`default_nettype none
`timescale 100ps / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:51:13 06/19/2013
// Design Name: reg_set_axi_lite_master
// Module Name: D:/HDL/FndtnISEWork/Zynq-7000/ZedBoard/test/reg_set_axi_lite_master/reg_set_axi_lite_master_tb.v
// Project Name: reg_set_axi_lite_master
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: reg_set_axi_lite_master
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module reg_set_axi_lite_master_tb;
// Inputs
wire M_AXI_ACLK;
wire M_AXI_ARESETN;
wire M_AXI_AWREADY;
wire M_AXI_WREADY;
wire [1:0] M_AXI_BRESP;
wire M_AXI_BVALID;
wire M_AXI_ARREADY;
wire [31:0] M_AXI_RDATA;
wire [1:0] M_AXI_RRESP;
wire M_AXI_RVALID;
reg init_done;
// Outputs
wire [31:0] M_AXI_AWADDR;
wire [2:0] M_AXI_AWPROT;
wire M_AXI_AWVALID;
wire [31:0] M_AXI_WDATA;
wire [3:0] M_AXI_WSTRB;
wire M_AXI_WVALID;
wire M_AXI_BREADY;
wire [31:0] M_AXI_ARADDR;
wire [2:0] M_AXI_ARPROT;
wire M_AXI_ARVALID;
wire M_AXI_RREADY;
// Instantiate the Unit Under Test (UUT)
reg_set_axi_lite_master uut (
.M_AXI_ACLK(M_AXI_ACLK),
.M_AXI_ARESETN(M_AXI_ARESETN),
.M_AXI_AWADDR(M_AXI_AWADDR),
.M_AXI_AWPROT(M_AXI_AWPROT),
.M_AXI_AWVALID(M_AXI_AWVALID),
.M_AXI_AWREADY(M_AXI_AWREADY),
.M_AXI_WDATA(M_AXI_WDATA),
.M_AXI_WSTRB(M_AXI_WSTRB),
.M_AXI_WVALID(M_AXI_WVALID),
.M_AXI_WREADY(M_AXI_WREADY),
.M_AXI_BRESP(M_AXI_BRESP),
.M_AXI_BVALID(M_AXI_BVALID),
.M_AXI_BREADY(M_AXI_BREADY),
.M_AXI_ARADDR(M_AXI_ARADDR),
.M_AXI_ARPROT(M_AXI_ARPROT),
.M_AXI_ARVALID(M_AXI_ARVALID),
.M_AXI_ARREADY(M_AXI_ARREADY),
.M_AXI_RDATA(M_AXI_RDATA),
.M_AXI_RRESP(M_AXI_RRESP),
.M_AXI_RVALID(M_AXI_RVALID),
.M_AXI_RREADY(M_AXI_RREADY),
.init_done(init_done)
);
axi_lite_slave_BFM axi_lite_slave_BFM_i (
.M_AXI_ACLK(M_AXI_ACLK),
.M_AXI_ARESETN(M_AXI_ARESETN),
.M_AXI_AWADDR(M_AXI_AWADDR),
.M_AXI_AWPROT(M_AXI_AWPROT),
.M_AXI_AWVALID(M_AXI_AWVALID),
.M_AXI_AWREADY(M_AXI_AWREADY),
.M_AXI_WDATA(M_AXI_WDATA),
.M_AXI_WSTRB(M_AXI_WSTRB),
.M_AXI_WVALID(M_AXI_WVALID),
.M_AXI_WREADY(M_AXI_WREADY),
.M_AXI_BRESP(M_AXI_BRESP),
.M_AXI_BVALID(M_AXI_BVALID),
.M_AXI_BREADY(M_AXI_BREADY),
.M_AXI_ARADDR(M_AXI_ARADDR),
.M_AXI_ARPROT(M_AXI_ARPROT),
.M_AXI_ARVALID(M_AXI_ARVALID),
.M_AXI_ARREADY(M_AXI_ARREADY),
.M_AXI_RDATA(M_AXI_RDATA),
.M_AXI_RRESP(M_AXI_RRESP),
.M_AXI_RVALID(M_AXI_RVALID),
.M_AXI_RREADY(M_AXI_RREADY)
);
initial begin
// Initialize Inputs
init_done = 1'b0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
init_done = 1'b1;
end
// ACLK のインスタンス
clk_gen #(
.CLK_PERIOD(100), // 10nsec, 100MHz
.CLK_DUTY_CYCLE(0.5),
.CLK_OFFSET(0),
.START_STATE(1'b0)
) ACLKi (
.clk_out(M_AXI_ACLK)
);
// reset_gen のインスタンス
reset_gen #(
.RESET_STATE(1'b0),
.RESET_TIME(1000) // 100nsec
) RESETi (
.reset_out(M_AXI_ARESETN)
);
endmodule
module clk_gen #(
parameter CLK_PERIOD = 100,
parameter real CLK_DUTY_CYCLE = 0.5,
parameter CLK_OFFSET = 0,
parameter START_STATE = 1'b0 )
(
output reg clk_out
);
begin
initial begin
#CLK_OFFSET;
forever
begin
clk_out = START_STATE;
#(CLK_PERIOD-(CLK_PERIOD*CLK_DUTY_CYCLE)) clk_out = ~START_STATE;
#(CLK_PERIOD*CLK_DUTY_CYCLE);
end
end
end
endmodule
module reset_gen #(
parameter RESET_STATE = 1'b1,
parameter RESET_TIME = 100 )
(
output reg reset_out
);
begin
initial begin
reset_out = RESET_STATE;
#RESET_TIME;
reset_out = ~RESET_STATE;
end
end
endmodule
`default_nettype wire
//
// AXI Lite Master 用 AXI Slave Bus Fuction Model (BFM)
// axi_lite_slave_BFM.v
// AXI Master用 AXI Slave Bus Function Mode (BFM)へのラッパー
//
// 2013/06/19
//
`default_nettype none
module axi_lite_slave_BFM # (
parameter integer C_M_AXI_ADDR_WIDTH = 32,
parameter integer C_M_AXI_DATA_WIDTH = 32,
parameter C_M_AXI_AxSIZE = 3'b010, // 4バイト
parameter integer C_OFFSET_WIDTH = 10, // 割り当てるRAMのアドレスのビット幅
parameter integer WRITE_RANDOM_WAIT = 0, // Write Transaction のデータ転送の時にランダムなWaitを発生させる=1, Waitしない=0
parameter integer WR_BVALID_RANDOM_WAIT = 0, // Write Transaction の時のM_AXI_BVALID をランダムにWaitする=1, Waitしない=0
parameter integer READ_RANDOM_WAIT = 0 // Read Transaction のデータ転送の時にランダムなWaitを発生させる=1, Waitしない=0
) (
// System Signals
input wire M_AXI_ACLK,
input wire M_AXI_ARESETN,
// Master Interface Write Address
input wire [C_M_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
input wire [3-1:0] M_AXI_AWPROT,
input wire M_AXI_AWVALID,
output wire M_AXI_AWREADY,
// Master Interface Write Data
input wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
input wire [C_M_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
input wire M_AXI_WVALID,
output wire M_AXI_WREADY,
// Master Interface Write Response
output wire [2-1:0] M_AXI_BRESP,
output wire M_AXI_BVALID,
input wire M_AXI_BREADY,
// Master Interface Read Address
input wire [C_M_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
input wire [3-1:0] M_AXI_ARPROT,
input wire M_AXI_ARVALID,
output wire M_AXI_ARREADY,
// Master Interface Read Data
input wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY
);
// Instantiate the Unit Under Test (UUT_slave)
axi_slave_bfm #(
.C_M_AXI_ADDR_WIDTH(C_M_AXI_ADDR_WIDTH),
.C_M_AXI_DATA_WIDTH(C_M_AXI_DATA_WIDTH),
.C_OFFSET_WIDTH(C_OFFSET_WIDTH),
.C_M_AXI_BURST_LEN(1),
.WRITE_RANDOM_WAIT(WRITE_RANDOM_WAIT),
.WR_BVALID_RANDOM_WAIT(WR_BVALID_RANDOM_WAIT),
.READ_RANDOM_WAIT(READ_RANDOM_WAIT)
) axi_slave_bfm_i (
.ACLK(M_AXI_ACLK),
.ARESETN(M_AXI_ARESETN),
.M_AXI_AWID(1'b0),
.M_AXI_AWADDR(M_AXI_AWADDR),
.M_AXI_AWLEN(8'd0), // 1 Word
.M_AXI_AWSIZE(C_M_AXI_AxSIZE),
.M_AXI_AWBURST(2'b01), // INCR (アドレスをインクリメント))
.M_AXI_AWLOCK(1'b0), // ノーマル・アクセス
.M_AXI_AWCACHE(4'b0010), // Normal Non-cacheable Non-bufferable
.M_AXI_AWPROT(M_AXI_AWPROT),
.M_AXI_AWQOS(4'b0000), // default
.M_AXI_AWUSER(),
.M_AXI_AWVALID(M_AXI_AWVALID),
.M_AXI_AWREADY(M_AXI_AWREADY),
.M_AXI_WDATA(M_AXI_WDATA),
.M_AXI_WSTRB(M_AXI_WSTRB),
.M_AXI_WLAST(1'b1),
.M_AXI_WUSER(),
.M_AXI_WVALID(M_AXI_WVALID),
.M_AXI_WREADY(M_AXI_WREADY),
.M_AXI_BID(),
.M_AXI_BRESP(M_AXI_BRESP),
.M_AXI_BUSER(),
.M_AXI_BVALID(M_AXI_BVALID),
.M_AXI_BREADY(M_AXI_BREADY),
.M_AXI_ARID(1'b0),
.M_AXI_ARADDR(M_AXI_ARADDR),
.M_AXI_ARLEN(8'd0), // 1 Word
.M_AXI_ARSIZE(C_M_AXI_AxSIZE),
.M_AXI_ARBURST(2'b01), // INCR (アドレスをインクリメント)
.M_AXI_ARLOCK(2'b00), // ノーマル・アクセス
.M_AXI_ARCACHE(4'b0010), // Normal Non-cacheable Non-bufferable
.M_AXI_ARPROT(M_AXI_ARPROT),
.M_AXI_ARQOS(4'b0000), // default
.M_AXI_ARUSER(),
.M_AXI_ARVALID(M_AXI_ARVALID),
.M_AXI_ARREADY(M_AXI_ARREADY),
.M_AXI_RID(),
.M_AXI_RDATA(M_AXI_RDATA),
.M_AXI_RRESP(M_AXI_RRESP),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(M_AXI_RVALID),
.M_AXI_RREADY(M_AXI_RREADY)
);
endmodule
`default_nettype wire
00000010
12345678
00000020
11223344
00000030
55667788
ffffffff
///////////////////////////////////////////////////////////////////////////////
//
// AXI4/Lite Master
//
////////////////////////////////////////////////////////////////////////////
//
// Structure:
// reg_set_axi_lite_master
//
////////////////////////////////////////////////////////////////////////////
`default_nettype none
module reg_set_axi_lite_master # (
parameter integer C_M_AXI_ADDR_WIDTH = 32,
parameter integer C_M_AXI_DATA_WIDTH = 32
)(
// System Signals
input wire M_AXI_ACLK,
input wire M_AXI_ARESETN,
// Master Interface Write Address
output wire [C_M_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [3-1:0] M_AXI_AWPROT,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
// Master Interface Write Data
output wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_M_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
// Master Interface Write Response
input wire [2-1:0] M_AXI_BRESP,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Master Interface Read Address
output wire [C_M_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [3-1:0] M_AXI_ARPROT,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
// Master Interface Read Data
input wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY,
input wire init_done
);
reg [31:0] rom [0:255];
reg [31:0] rom_dout;
initial begin
$readmemh("vdma_reg_set.txt", rom, 0, 255);
end
reg reset_1b, reset;
reg [31:0] reg_addr;
reg [31:0] reg_data;
reg [7:0] rom_addr;
reg awvalid;
reg wvalid;
reg bready;
localparam RESP_OKAY = 2'b00,
RESP_EXOKAY = 2'b01,
RESP_SLVERR = 2'b10,
RESP_DECERR = 2'b11;
localparam IDLE_RRSM = 3'b000,
ADDRESS_READ = 3'b001,
DATA_READ = 3'b011,
REG_SET_DATA_VALID = 3'b010,
END_RRSM = 3'b110;
reg [2:0] rrsm_cs;
localparam IDLE_ADDR = 2'b00,
AWVALID_ASSERT = 2'b01,
AWVALID_HOLD_OFF = 2'b11;
reg [1:0] addr_cs;
localparam IDLE_DATA = 2'b00,
WVALID_ASSERT = 2'b01,
WVALID_HOLD_OFF = 2'b11;
reg [1:0] data_cs;
localparam IDLE_RESP = 1'b0,
BREADY_ASSERT = 1'b1;
reg resp_cs;
reg reg_data_valid;
reg rom_read_done;
// Read is not implement
assign M_AXI_ARADDR = 0;
assign M_AXI_ARPROT = 3'd0;
assign M_AXI_ARVALID = 1'b0;
assign M_AXI_RDATA = 0;
assign M_AXI_RREADY = 1'b1;
assign M_AXI_WSTRB = 4'b1111;
assign M_AXI_AWPROT = 3'b000;
// reset
always @(posedge M_AXI_ACLK) begin
reset_1b <= ~M_AXI_ARESETN | ~init_done;
reset <= reset_1b;
end
// instantiaton of rom
always @(posedge M_AXI_ACLK) begin
rom_dout <= rom[rom_addr];
end
// rom read State Machine
always @(posedge M_AXI_ACLK) begin
if (reset) begin
rrsm_cs <= IDLE_RRSM;
reg_data_valid <= 1'b0;
end else begin
case (rrsm_cs)
IDLE_RRSM :
rrsm_cs <= ADDRESS_READ;
ADDRESS_READ :
rrsm_cs <= DATA_READ;
DATA_READ : begin
if (rom_dout == 32'hFFFF_FFFF) begin // end
rrsm_cs <= END_RRSM;
reg_data_valid <= 1'b0;
end else begin
rrsm_cs <= REG_SET_DATA_VALID;
reg_data_valid <= 1'b1;
end
end
REG_SET_DATA_VALID : begin
if (rom_read_done) begin
rrsm_cs <= ADDRESS_READ;
reg_data_valid <= 1'b0;
end
end
END_RRSM :
rrsm_cs <= END_RRSM;
endcase
end
end
// rom_addr
always @(posedge M_AXI_ACLK) begin
if (reset) begin
rom_addr <= 8'd0;
end else begin
if (rrsm_cs == ADDRESS_READ) // Data
rom_addr <= rom_addr + 8'd1;
else if (rrsm_cs == REG_SET_DATA_VALID && rom_read_done) // Address
rom_addr <= rom_addr + 8'd1;
end
end
// AXI4 Lite Master Address
always @(posedge M_AXI_ACLK) begin
if (reset) begin
reg_addr <= 32'd0;
end else begin
if (rrsm_cs == DATA_READ)
reg_addr <= rom_dout;
end
end
assign M_AXI_AWADDR = reg_addr;
// AXI4 Lite Master WDATA
always @(posedge M_AXI_ACLK) begin
if (reset) begin
reg_data <= 32'd0;
end else begin
if (rrsm_cs == REG_SET_DATA_VALID)
reg_data <= rom_dout;
end
end
assign M_AXI_WDATA = reg_data;
// AXI Lite Master Address State Machine
always @(posedge M_AXI_ACLK) begin
if (reset) begin
addr_cs <= IDLE_ADDR;
awvalid <= 1'b0;
end else begin
case (addr_cs)
IDLE_ADDR :
if (rrsm_cs == REG_SET_DATA_VALID) begin
addr_cs <= AWVALID_ASSERT;
awvalid <= 1'b1;
end
AWVALID_ASSERT :
if (M_AXI_AWREADY) begin
addr_cs <= AWVALID_HOLD_OFF;
awvalid <= 1'b0;
end
AWVALID_HOLD_OFF :
if (rrsm_cs != REG_SET_DATA_VALID)
addr_cs <= IDLE_ADDR;
endcase
end
end
assign M_AXI_AWVALID = awvalid;
// AXI Lite Master Data State Machine
always @(posedge M_AXI_ACLK) begin
if (reset) begin
data_cs <= IDLE_DATA;
wvalid <= 1'b0;
rom_read_done <= 1'b0;
end else begin
case (data_cs)
IDLE_DATA : begin
rom_read_done <= 1'b0;
if (rrsm_cs == REG_SET_DATA_VALID) begin
data_cs <= WVALID_ASSERT;
wvalid <= 1'b1;
end
end
WVALID_ASSERT :
if (M_AXI_WREADY) begin
wvalid <= 1'b0;
rom_read_done <= 1'b1;
data_cs <= WVALID_HOLD_OFF;
end
WVALID_HOLD_OFF : begin
rom_read_done <= 1'b0;
if (addr_cs == AWVALID_HOLD_OFF)
data_cs <= IDLE_DATA;
end
endcase
end
end
assign M_AXI_WVALID = wvalid;
// bready State Machine
always @(posedge M_AXI_ACLK) begin
if (reset) begin
resp_cs <= IDLE_RESP;
bready <= 1'b0;
end else begin
case (resp_cs)
IDLE_RESP :
if (M_AXI_WREADY && data_cs == WVALID_ASSERT) begin
resp_cs <= BREADY_ASSERT;
bready <= 1'b1;
end
BREADY_ASSERT :
if (M_AXI_BVALID) begin
resp_cs <= IDLE_RESP;
bready <= 1'b0;
end
endcase
end
end
assign M_AXI_BREADY = bready;
endmodule
`default_nettype none
キャラクタROMをAXI4 Lite Slave として実装する1(AXI4 Lite バスの勉強)
キャラクタROMをAXI4 Lite Slave として実装する2(AXI4 Lite バスの勉強2)
VHDLでのブロックRAMや分散RAMの初期化(外部データファイル)
VHDLでのブロックRAMや分散RAMの初期化(16進数で書かれた外部データファイル)
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