// ラプラシアンフィルタ
// x0y0 x1y0 x2y0 -1 -1 -1
// x0y1 x1y1 x2y1 -1 8 -1
// x0y2 x1y2 x2y2 -1 -1 -1
public class laplacian_filter{
public int lap_filter(int x0y0, int x1y0, int x2y0, int x0y1, int x1y1, int x2y1, int x0y2, int x1y2, int x2y2){
int y;
y = -x0y0 -x1y0 -x2y0 -x0y1 +8*x1y1 -x2y1 -x0y2 -x1y2 -x2y2;
if (y<0)
y = 0;
else if (y>255)
y = 255;
return(y);
}
}
SYNTHESIJER ?= ../../bin
SOURCES = laplacian_filter.java
VHDL_SOURCES = $(SOURCES:.java=.vhd)
VERILOG_SOURCES = $(SOURCES:.java=.v)
all: $(SOURCES)
java -cp $(SYNTHESIJER) synthesijer.Main --verilog --vhdl $(SOURCES)
-- sim.vhd
-- Testbench for laplacian_filter.vhd
-- 2014/12/27 by marsee
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sim is
end sim;
architecture testbench of sim is
component laplacian_filter
port (
clk : in std_logic;
reset : in std_logic;
lap_filter_x0y0 : in signed(32-1 downto 0);
lap_filter_x1y0 : in signed(32-1 downto 0);
lap_filter_x2y0 : in signed(32-1 downto 0);
lap_filter_x0y1 : in signed(32-1 downto 0);
lap_filter_x1y1 : in signed(32-1 downto 0);
lap_filter_x2y1 : in signed(32-1 downto 0);
lap_filter_x0y2 : in signed(32-1 downto 0);
lap_filter_x1y2 : in signed(32-1 downto 0);
lap_filter_x2y2 : in signed(32-1 downto 0);
lap_filter_req : in std_logic;
lap_filter_busy : out std_logic;
lap_filter_return : out signed(32-1 downto 0)
);
end component;
constant clock_period : time := 10 ns;
constant delay : time := 1 ns;
signal clk : std_logic := '0';
signal reset : std_logic;
signal lap_filter_x0y0 : signed(32-1 downto 0);
signal lap_filter_x1y0 : signed(32-1 downto 0);
signal lap_filter_x2y0 : signed(32-1 downto 0);
signal lap_filter_x0y1 : signed(32-1 downto 0);
signal lap_filter_x1y1 : signed(32-1 downto 0);
signal lap_filter_x2y1 : signed(32-1 downto 0);
signal lap_filter_x0y2 : signed(32-1 downto 0);
signal lap_filter_x1y2 : signed(32-1 downto 0);
signal lap_filter_x2y2 : signed(32-1 downto 0);
signal lap_filter_req : std_logic;
signal lap_filter_busy : std_logic;
signal lap_filter_return : signed(32-1 downto 0);
begin
clk <= not clk after clock_period/2; -- clk = 100MHz, 10 ns
uut : laplacian_filter port map (
clk => clk,
reset => reset,
lap_filter_x0y0 => lap_filter_x0y0,
lap_filter_x1y0 => lap_filter_x1y0,
lap_filter_x2y0 => lap_filter_x2y0,
lap_filter_x0y1 => lap_filter_x0y1,
lap_filter_x1y1 => lap_filter_x1y1,
lap_filter_x2y1 => lap_filter_x2y1,
lap_filter_x0y2 => lap_filter_x0y2,
lap_filter_x1y2 => lap_filter_x1y2,
lap_filter_x2y2 => lap_filter_x2y2,
lap_filter_req => lap_filter_req,
lap_filter_busy => lap_filter_busy,
lap_filter_return => lap_filter_return
);
stimulus : process begin
reset <= '1';
lap_filter_x0y0 <= to_signed(0, 32);
lap_filter_x1y0 <= to_signed(0, 32);
lap_filter_x2y0 <= to_signed(0, 32);
lap_filter_x0y1 <= to_signed(0, 32);
lap_filter_x1y1 <= to_signed(0, 32);
lap_filter_x2y1 <= to_signed(0, 32);
lap_filter_x0y2 <= to_signed(0, 32);
lap_filter_x1y2 <= to_signed(0, 32);
lap_filter_x2y2 <= to_signed(0, 32);
lap_filter_req <= '0';
wait for 100 ns;
reset <= '0';
wait for 50 ns;
lap_filter_x0y0 <= to_signed(127, 32);
lap_filter_x1y0 <= to_signed(127, 32);
lap_filter_x2y0 <= to_signed(127, 32);
lap_filter_x0y1 <= to_signed(127, 32);
lap_filter_x1y1 <= to_signed(127, 32);
lap_filter_x2y1 <= to_signed(127, 32);
lap_filter_x0y2 <= to_signed(0, 32);
lap_filter_x1y2 <= to_signed(0, 32);
lap_filter_x2y2 <= to_signed(0, 32);
wait until clk'event and clk='1';
wait for delay;
lap_filter_req <= '1';
wait until clk'event and clk='1';
wait for delay;
lap_filter_req <= '0';
for i in 0 to 22 loop
wait until clk'event and clk='1';
wait for delay;
end loop;
lap_filter_x0y0 <= to_signed(127, 32);
lap_filter_x1y0 <= to_signed(127, 32);
lap_filter_x2y0 <= to_signed(127, 32);
lap_filter_x0y1 <= to_signed(127, 32);
lap_filter_x1y1 <= to_signed(81, 32);
lap_filter_x2y1 <= to_signed(127, 32);
lap_filter_x0y2 <= to_signed(0, 32);
lap_filter_x1y2 <= to_signed(0, 32);
lap_filter_x2y2 <= to_signed(0, 32);
wait until clk'event and clk='1';
wait for delay;
lap_filter_req <= '1';
wait until clk'event and clk='1';
wait for delay;
lap_filter_req <= '0';
wait for 1 us;
assert (false) report "Simulation End!" severity failure;
end process;
end testbench;
java -cp C:\Users\Masaaki\Documents\Synthesijer\synthesijer-20141211.jar synthesijer.Main --vhdl --verilog^
Test.java ^
Top.java
set_property PACKAGE_PIN L16 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property PACKAGE_PIN R18 [get_ports reset]
set_property IOSTANDARD LVCMOS33 [get_ports reset]
set_property PACKAGE_PIN M14 [get_ports flag_return]
set_property IOSTANDARD LVCMOS33 [get_ports flag_return]
となるはずだ。125MHz / (5000001カウント * 7クロック * 2状態) ≒ 1.8 Hz
public class Test2{
public boolean flag;
private int count;
public void run(){
while(true){
if (count <= 10){
count++;
} else {
count = 0;
flag = !flag;
}
}
}
}
make.bat を実行すると、Test2.vhd と Test2.v ができる。java -cp C:\Users\Masaaki\Documents\Synthesijer\synthesijer-20141211.jar synthesijer.Main --vhdl --verilog^
Test2.java
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Test2 is
port (
clk : in std_logic;
reset : in std_logic;
flag_in : in std_logic;
flag_we : in std_logic;
flag_out : out std_logic;
run_req : in std_logic;
run_busy : out std_logic
);
end Test2;
architecture RTL of Test2 is
signal clk_sig : std_logic;
signal reset_sig : std_logic;
signal flag_in_sig : std_logic;
signal flag_we_sig : std_logic;
signal flag_out_sig : std_logic;
signal run_req_sig : std_logic;
signal run_busy_sig : std_logic := '1';
signal class_flag_0000 : std_logic := '0';
signal class_flag_0000_mux : std_logic;
signal tmp_0001 : std_logic;
signal class_count_0001 : signed(32-1 downto 0) := (others => '0');
signal binary_expr_00002 : std_logic := '0';
signal unary_expr_00003 : signed(32-1 downto 0) := (others => '0');
signal unary_expr_00004 : std_logic := '0';
signal run_req_flag : std_logic;
signal run_req_local : std_logic := '0';
signal tmp_0002 : std_logic;
type Type_run_method is (
run_method_IDLE,
run_method_S_0000,
run_method_S_0001,
run_method_S_0002,
run_method_S_0003,
run_method_S_0004,
run_method_S_0005,
run_method_S_0006,
run_method_S_0007,
run_method_S_0008,
run_method_S_0009,
run_method_S_0010,
run_method_S_0012,
run_method_S_0013,
run_method_S_0014,
run_method_S_0015
);
signal run_method : Type_run_method := run_method_IDLE;
signal run_method_delay : signed(32-1 downto 0) := (others => '0');
signal tmp_0003 : std_logic;
signal tmp_0004 : std_logic;
signal tmp_0005 : std_logic;
signal tmp_0006 : std_logic;
signal tmp_0007 : std_logic;
signal tmp_0008 : signed(32-1 downto 0);
signal tmp_0009 : std_logic;
begin
clk_sig <= clk;
reset_sig <= reset;
flag_in_sig <= flag_in;
flag_we_sig <= flag_we;
flag_out <= flag_out_sig;
flag_out_sig <= class_flag_0000;
run_req_sig <= run_req;
run_busy <= run_busy_sig;
process(clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
run_busy_sig <= '1';
else
if run_method = run_method_S_0001 then
run_busy_sig <= run_req_flag;
end if;
end if;
end if;
end process;
-- expressions
tmp_0001 <= flag_in_sig when flag_we_sig = '1' else class_flag_0000;
tmp_0002 <= run_req_local or run_req_sig;
tmp_0003 <= '1' and '1';
tmp_0004 <= '1' and '0';
tmp_0005 <= '1' when binary_expr_00002 = '1' else '0';
tmp_0006 <= '1' when binary_expr_00002 = '0' else '0';
tmp_0007 <= '1' when class_count_0001 <= X"0000000a" else '0';
tmp_0008 <= class_count_0001 + X"00000001";
tmp_0009 <= not class_flag_0000;
-- sequencers
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
run_method <= run_method_IDLE;
run_method_delay <= (others => '0');
else
case (run_method) is
when run_method_IDLE =>
run_method <= run_method_S_0000;
when run_method_S_0000 =>
run_method <= run_method_S_0001;
run_method <= run_method_S_0001;
when run_method_S_0001 =>
if run_req_flag = '1' then
run_method <= run_method_S_0002;
end if;
when run_method_S_0002 =>
if tmp_0003 = '1' then
run_method <= run_method_S_0004;
elsif tmp_0004 = '1' then
run_method <= run_method_S_0003;
end if;
when run_method_S_0003 =>
run_method <= run_method_S_0015;
when run_method_S_0004 =>
run_method <= run_method_S_0005;
when run_method_S_0005 =>
if tmp_0005 = '1' then
run_method <= run_method_S_0007;
elsif tmp_0006 = '1' then
run_method <= run_method_S_0010;
end if;
when run_method_S_0006 =>
run_method <= run_method_S_0014;
when run_method_S_0007 =>
run_method <= run_method_S_0008;
when run_method_S_0008 =>
run_method <= run_method_S_0009;
when run_method_S_0009 =>
run_method <= run_method_S_0006;
when run_method_S_0010 =>
run_method <= run_method_S_0012;
when run_method_S_0012 =>
run_method <= run_method_S_0013;
when run_method_S_0013 =>
run_method <= run_method_S_0006;
when run_method_S_0014 =>
run_method <= run_method_S_0002;
when run_method_S_0015 =>
run_method <= run_method_S_0000;
when others => null;
end case;
end if;
end if;
end process;
process(clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
class_flag_0000 <= '0';
else
if run_method = run_method_S_0012 then
class_flag_0000 <= unary_expr_00004;
else
class_flag_0000 <= class_flag_0000_mux;
end if;
end if;
end if;
end process;
class_flag_0000_mux <= tmp_0001;
process(clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
class_count_0001 <= (others => '0');
else
if run_method = run_method_S_0008 then
class_count_0001 <= unary_expr_00003;
elsif run_method = run_method_S_0010 then
class_count_0001 <= X"00000000";
end if;
end if;
end if;
end process;
process(clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
binary_expr_00002 <= '0';
else
if run_method = run_method_S_0004 then
binary_expr_00002 <= tmp_0007;
end if;
end if;
end if;
end process;
process(clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
unary_expr_00003 <= (others => '0');
else
if run_method = run_method_S_0007 then
unary_expr_00003 <= tmp_0008;
end if;
end if;
end if;
end process;
process(clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
unary_expr_00004 <= '0';
else
if run_method = run_method_S_0010 then
unary_expr_00004 <= tmp_0009;
end if;
end if;
end if;
end process;
run_req_flag <= tmp_0002;
end RTL;
public class Test{
public boolean flag;
private int count;
public void run(){
while(true){
count++;
if(count > 10){
//if(count > 5000000){
count = 0;
flag = !flag;
}
}
}
}
となる。現在の動作クロックは 100MHz で 10 nsec なので、1カウント分の平均的なクロック数は800 /11 ≒ 72.7 nsec
となった。どうやら run_method_S_0011 の時に、flag_out が変化するようだ。ステートを遷移して行って判定を行いながら結果を出力しているのか?ユーザーズ・マニュアルが欲しいと思った。72.7 / 10 = 7.27 クロック
`default_nettype none
`timescale 1ns / 100ps
// Test_tb.v
// 2014/12/17
//
module Test_tb;
parameter DELAY = 1;
wire clk;
wire reset;
reg flag_in;
reg flag_we;
wire flag_out;
reg run_req;
wire run_busy;
Test uut_Test (
.clk(clk),
.reset(reset),
.flag_in(flag_in),
.flag_we(flag_we),
.flag_out(flag_out),
.run_req(run_req),
.run_busy(run_busy)
);
initial begin
// Initialize Inputs
flag_in <= 1'b0;
flag_we <= 1'b0;
run_req <= 1'b1;
end
// clk_gen のインスタンス(clk)
clk_gen #(
.CLK_PERIOD(10), // 10nsec, 100MHz
.CLK_DUTY_CYCLE(0.5),
.CLK_OFFSET(0),
.START_STATE(1'b0)
) ACLKi (
.clk_out(clk)
);
// reset_gen のインスタンス
reset_gen #(
.RESET_STATE(1'b1),
.RESET_TIME(100) // 100nsec
) RESET_ARESETN (
.reset_out(reset),
.init_done()
);
endmodule
module clk_gen #(
parameter CLK_PERIOD = 100,
parameter real CLK_DUTY_CYCLE = 0.5,
parameter CLK_OFFSET = 0,
parameter START_STATE = 1'b0 )
(
output reg clk_out
);
begin
initial begin
#CLK_OFFSET;
forever
begin
clk_out = START_STATE;
#(CLK_PERIOD-(CLK_PERIOD*CLK_DUTY_CYCLE)) clk_out = ~START_STATE;
#(CLK_PERIOD*CLK_DUTY_CYCLE);
end
end
end
endmodule
module reset_gen #(
parameter RESET_STATE = 1'b1,
parameter RESET_TIME = 100 )
(
output reg reset_out,
output reg init_done
);
begin
initial begin
reset_out = RESET_STATE;
init_done = 1'b0;
#RESET_TIME;
reset_out = ~RESET_STATE;
init_done = 1'b1;
end
end
endmodule
`default_nettype wire
public class Test{
public boolean flag;
private int count;
public void run(){
while(true){
count++;
if(count > 5000000){
count = 0;
flag = !flag;
}
}
}
}
コマンドを実行すると Test.vhd ファイルを出力した。java -cp synthesijer-20141211.jar synthesijer.Main Test.java
ibrary IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Test is
port (
clk : in std_logic;
reset : in std_logic;
flag_in : in std_logic;
flag_we : in std_logic;
flag_out : out std_logic;
run_req : in std_logic;
run_busy : out std_logic
);
end Test;
architecture RTL of Test is
signal clk_sig : std_logic;
signal reset_sig : std_logic;
signal flag_in_sig : std_logic;
signal flag_we_sig : std_logic;
signal flag_out_sig : std_logic;
signal run_req_sig : std_logic;
signal run_busy_sig : std_logic := '1';
signal class_flag_0000 : std_logic := '0';
signal class_flag_0000_mux : std_logic;
signal tmp_0001 : std_logic;
signal class_count_0001 : signed(32-1 downto 0) := (others => '0');
signal unary_expr_00002 : signed(32-1 downto 0) := (others => '0');
signal binary_expr_00003 : std_logic := '0';
signal unary_expr_00004 : std_logic := '0';
signal run_req_flag : std_logic;
signal run_req_local : std_logic := '0';
signal tmp_0002 : std_logic;
type Type_run_method is (
run_method_IDLE,
run_method_S_0000,
run_method_S_0001,
run_method_S_0002,
run_method_S_0003,
run_method_S_0004,
run_method_S_0005,
run_method_S_0006,
run_method_S_0007,
run_method_S_0008,
run_method_S_0009,
run_method_S_0011,
run_method_S_0012,
run_method_S_0013,
run_method_S_0014
);
signal run_method : Type_run_method := run_method_IDLE;
signal run_method_delay : signed(32-1 downto 0) := (others => '0');
signal tmp_0003 : std_logic;
signal tmp_0004 : std_logic;
signal tmp_0005 : std_logic;
signal tmp_0006 : std_logic;
signal tmp_0007 : signed(32-1 downto 0);
signal tmp_0008 : std_logic;
signal tmp_0009 : std_logic;
begin
clk_sig <= clk;
reset_sig <= reset;
flag_in_sig <= flag_in;
flag_we_sig <= flag_we;
flag_out <= flag_out_sig;
flag_out_sig <= class_flag_0000;
run_req_sig <= run_req;
run_busy <= run_busy_sig;
process(clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
run_busy_sig <= '1';
else
if run_method = run_method_S_0001 then
run_busy_sig <= run_req_flag;
end if;
end if;
end if;
end process;
-- expressions
tmp_0001 <= flag_in_sig when flag_we_sig = '1' else class_flag_0000;
tmp_0002 <= run_req_local or run_req_sig;
tmp_0003 <= '1' and '1';
tmp_0004 <= '1' and '0';
tmp_0005 <= '1' when binary_expr_00003 = '1' else '0';
tmp_0006 <= '1' when binary_expr_00003 = '0' else '0';
tmp_0007 <= class_count_0001 + X"00000001";
tmp_0008 <= '1' when class_count_0001 > X"004c4b40" else '0';
tmp_0009 <= not class_flag_0000;
-- sequencers
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
run_method <= run_method_IDLE;
run_method_delay <= (others => '0');
else
case (run_method) is
when run_method_IDLE =>
run_method <= run_method_S_0000;
when run_method_S_0000 =>
run_method <= run_method_S_0001;
run_method <= run_method_S_0001;
when run_method_S_0001 =>
if run_req_flag = '1' then
run_method <= run_method_S_0002;
end if;
when run_method_S_0002 =>
if tmp_0003 = '1' then
run_method <= run_method_S_0004;
elsif tmp_0004 = '1' then
run_method <= run_method_S_0003;
end if;
when run_method_S_0003 =>
run_method <= run_method_S_0014;
when run_method_S_0004 =>
run_method <= run_method_S_0005;
when run_method_S_0005 =>
run_method <= run_method_S_0006;
when run_method_S_0006 =>
run_method <= run_method_S_0007;
when run_method_S_0007 =>
if tmp_0005 = '1' then
run_method <= run_method_S_0009;
elsif tmp_0006 = '1' then
run_method <= run_method_S_0008;
end if;
when run_method_S_0008 =>
run_method <= run_method_S_0013;
when run_method_S_0009 =>
run_method <= run_method_S_0011;
when run_method_S_0011 =>
run_method <= run_method_S_0012;
when run_method_S_0012 =>
run_method <= run_method_S_0008;
when run_method_S_0013 =>
run_method <= run_method_S_0002;
when run_method_S_0014 =>
run_method <= run_method_S_0000;
when others => null;
end case;
end if;
end if;
end process;
process(clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
class_flag_0000 <= '0';
else
if run_method = run_method_S_0011 then
class_flag_0000 <= unary_expr_00004;
else
class_flag_0000 <= class_flag_0000_mux;
end if;
end if;
end if;
end process;
class_flag_0000_mux <= tmp_0001;
process(clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
class_count_0001 <= (others => '0');
else
if run_method = run_method_S_0005 then
class_count_0001 <= unary_expr_00002;
elsif run_method = run_method_S_0009 then
class_count_0001 <= X"00000000";
end if;
end if;
end if;
end process;
process(clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
unary_expr_00002 <= (others => '0');
else
if run_method = run_method_S_0004 then
unary_expr_00002 <= tmp_0007;
end if;
end if;
end if;
end process;
process(clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
binary_expr_00003 <= '0';
else
if run_method = run_method_S_0006 then
binary_expr_00003 <= tmp_0008;
end if;
end if;
end if;
end process;
process(clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
unary_expr_00004 <= '0';
else
if run_method = run_method_S_0009 then
unary_expr_00004 <= tmp_0009;
end if;
end if;
end if;
end process;
run_req_flag <= tmp_0002;
end RTL;
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