PARAMETER RESOLUTION = 1, DT = INTEGER, RANGE = (0:4), VALUES = (0=VGA, 1=SVGA, 2=XGA, 3=SXGA, 4=HD)
BEGIN video_timing
## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION STYLE = HDL
OPTION DESC = video_timing
OPTION LONG_DESC = video_timing test IP
OPTION HDL = VHDL
OPTION RUN_NGCBUILD = FALSE
## Bus Interfaces
## Generics for VHDL or Parameters for Verilog
PARAMETER RESOLUTION = 1, DT = INTEGER, RANGE = (0:4), VALUES = (0=VGA, 1=SVGA, 2=XGA, 3=SXGA, 4=HD)
## Ports
PORT oH_ACTIVE_VIDEO = "", DIR = O, VEC=[10:0]
PORT oV_ACTIVE_VIDEO = "", DIR = O, VEC=[10:0]
END
lib video_timing_v1_00_a video_timing_pkg.vhd VHDL
lib video_timing_v1_00_a constant_test3.vhd VHDL
<?xml version="1.0" encoding="ISO-8859-1"?>
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-->
<!DOCTYPE doc SYSTEM "../../ipdialog.dtd" [
<!-- -->
<!ENTITY RESOLUTION '
<widget id="RESOLUTION">
<key>RESOLUTION</key>
<label>RESOLUTION</label>
<tip></tip>
</widget>
'>
]>
<doc>
<view id="Video Timing">
<display>Video Timing</display>
<group id="Video Timing">
<display>Video Timing</display>
<item>&RESOLUTION;</item>
</group>
</view>
</doc>
package video_timing_pkg is
subtype RESLUTION_TYPE is integer range 0 to 4;
type VIDEO_RECORD is record
H_ACTIVE_VIDEO : integer range 640 to 1920;
V_ACTIVE_VIDEO: integer range 480 to 1080;
end record VIDEO_RECORD;
type VIDEO_RECORD_A is array (RESLUTION_TYPE) of VIDEO_RECORD;
constant CONST_VIDEO_R : VIDEO_RECORD_A := (
0 => (H_ACTIVE_VIDEO => 640, V_ACTIVE_VIDEO => 480), -- VGA
1 => (H_ACTIVE_VIDEO => 800, V_ACTIVE_VIDEO => 600), -- SVGA
2 => (H_ACTIVE_VIDEO => 1024, V_ACTIVE_VIDEO => 768), -- XGA
3 => (H_ACTIVE_VIDEO => 1280, V_ACTIVE_VIDEO => 1024), -- SXGA
4 => (H_ACTIVE_VIDEO => 1920, V_ACTIVE_VIDEO => 1080) -- HD
);
end package video_timing_pkg;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use work.video_timing_pkg.all;
entity video_timing is
generic (
resolution : RESLUTION_TYPE := 1 -- SVGA
);
port (
oH_ACTIVE_VIDEO : out std_logic_vector(10 downto 0);
oV_ACTIVE_VIDEO : out std_logic_vector(10 downto 0)
);
begin
end entity video_timing;
architecture RTL of video_timing is
-- NOTE: Use elab-time constant via generic.
constant cACTIVE_VIDEO : VIDEO_RECORD := CONST_VIDEO_R(resolution);
constant H_ACTIVE_VIDEO : integer := cACTIVE_VIDEO.H_ACTIVE_VIDEO;
begin
-- NOTE: Use run-time parameter via port.
oH_ACTIVE_VIDEO <= std_logic_vector(TO_UNSIGNED(cACTIVE_VIDEO.H_ACTIVE_VIDEO, 11));
oV_ACTIVE_VIDEO <= std_logic_vector(TO_UNSIGNED(cACTIVE_VIDEO.V_ACTIVE_VIDEO, 11));
end architecture RTL;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
use work.video_timing_pkg.all;
ENTITY video_timing_tb IS
END video_timing_tb;
ARCHITECTURE behavior OF video_timing_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT video_timing
generic (
resolution : RESLUTION_TYPE := 1 -- SVGA
);
PORT(
oH_ACTIVE_VIDEO : OUT std_logic_vector(10 downto 0);
oV_ACTIVE_VIDEO : OUT std_logic_vector(10 downto 0)
);
END COMPONENT;
--Outputs
signal oH_ACTIVE_VIDEO : std_logic_vector(10 downto 0);
signal oV_ACTIVE_VIDEO : std_logic_vector(10 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: video_timing generic map (
resolution => 2 -- XGA
) PORT MAP (
oH_ACTIVE_VIDEO => oH_ACTIVE_VIDEO,
oV_ACTIVE_VIDEO => oV_ACTIVE_VIDEO
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
-- insert stimulus here
wait;
end process;
END;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
entity constant_test2 is
generic (
RESOLUTION : string := "VGA"
);
port (
oH_ACTIVE_VIDEO : out std_logic_vector(10 downto 0);
oV_ACTIVE_VIDEO : out std_logic_vector(10 downto 0)
);
begin
end entity constant_test2;
architecture RTL of constant_test2 is
pure function fH_ACTIVE_VIDEO (
iDUMMY : boolean
) return integer is
begin
if (RESOLUTION = "VGA") then return 640;
elsif (RESOLUTION = "SVGA") then return 800;
elsif (RESOLUTION = "XGA") then return 1024;
elsif (RESOLUTION = "SXGA") then return 1280;
elsif (RESOLUTION = "HD") then return 1920;
else return 1920;
end if;
end function fH_ACTIVE_VIDEO;
constant H_ACTIVE_VIDEO : integer := fH_ACTIVE_VIDEO(true);
pure function fV_ACTIVE_VIDEO (
iDUMMY : boolean
) return integer is
begin
if (RESOLUTION = "VGA") then return 480;
elsif (RESOLUTION = "SVGA") then return 600;
elsif (RESOLUTION = "XGA") then return 768;
elsif (RESOLUTION = "SXGA") then return 1024;
elsif (RESOLUTION = "HD") then return 1080;
else return 1080;
end if;
end function fV_ACTIVE_VIDEO;
constant V_ACTIVE_VIDEO : integer := fV_ACTIVE_VIDEO(true);
begin
oH_ACTIVE_VIDEO <= std_logic_vector(TO_UNSIGNED(H_ACTIVE_VIDEO, 11));
oV_ACTIVE_VIDEO <= std_logic_vector(TO_UNSIGNED(V_ACTIVE_VIDEO, 11));
end architecture RTL;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY constant_test2_tb IS
END constant_test2_tb;
ARCHITECTURE behavior OF constant_test2_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT constant_test2 GENERIC(
RESOLUTION : string := "VGA"
);
PORT(
oH_ACTIVE_VIDEO : OUT std_logic_vector(10 downto 0);
oV_ACTIVE_VIDEO : OUT std_logic_vector(10 downto 0)
);
END COMPONENT;
--Outputs
signal oH_ACTIVE_VIDEO : std_logic_vector(10 downto 0);
signal oV_ACTIVE_VIDEO : std_logic_vector(10 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: constant_test2 GENERIC MAP(
RESOLUTION => "SVGA"
) PORT MAP (
oH_ACTIVE_VIDEO => oH_ACTIVE_VIDEO,
oV_ACTIVE_VIDEO => oV_ACTIVE_VIDEO
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
-- insert stimulus here
wait;
end process;
END;
package ee_pkg is
type tRESOLUTION is (
VGA,
SVGA,
XGA,
SXGA,
HD
);
subtype tH_ACTIVE_VIDEO is integer range 640 to 1920;
type tH_ACTIVE_VIDEO_R is array (tRESOLUTION) of tH_ACTIVE_VIDEO;
constant cH_ACTIVE_VIDEO_R : tH_ACTIVE_VIDEO_R := (
VGA => 640,
SVGA => 800,
XGA => 1024,
SXGA => 1280,
HD => 1920
);
subtype tV_ACTIVE_VIDEO is integer range 480 to 1080;
type tV_ACTIVE_VIDEO_R is array (tRESOLUTION) of tV_ACTIVE_VIDEO;
constant cV_ACTIVE_VIDEO_R : tV_ACTIVE_VIDEO_R := (
VGA => 480,
SVGA => 600,
XGA => 768,
SXGA => 1024,
HD => 1080
);
end package ee_pkg;
use work.ee_pkg.all;
entity ee is
generic (
RESOLUTION : tRESOLUTION := XGA
);
port (
oH_ACTIVE_VIDEO : out integer;
oV_ACTIVE_VIDEO : out integer
);
begin
end entity ee;
architecture a of ee is
-- NOTE: Use elab-time constant via generic.
constant cH_ACTIVE_VIDEO : integer := cH_ACTIVE_VIDEO_R(RESOLUTION);
constant cV_ACTIVE_VIDEO : integer := cV_ACTIVE_VIDEO_R(RESOLUTION);
begin
-- NOTE: Use run-time parameter via port.
oH_ACTIVE_VIDEO <= cH_ACTIVE_VIDEO;
oV_ACTIVE_VIDEO <= cV_ACTIVE_VIDEO;
end architecture a;
package ee_pkg is
type tRESOLUTION is (
VGA,
SVGA,
XGA,
SXGA,
HD
);
subtype tH_ACTIVE_VIDEO is integer range 640 to 1920;
type tH_ACTIVE_VIDEO_R is array (tRESOLUTION) of tH_ACTIVE_VIDEO;
constant cH_ACTIVE_VIDEO_R : tH_ACTIVE_VIDEO_R := (
VGA => 640,
SVGA => 800,
XGA => 1024,
SXGA => 1280,
HD => 1920
);
subtype tV_ACTIVE_VIDEO is integer range 480 to 1080;
type tV_ACTIVE_VIDEO_R is array (tRESOLUTION) of tV_ACTIVE_VIDEO;
constant cV_ACTIVE_VIDEO_R : tV_ACTIVE_VIDEO_R := (
VGA => 480,
SVGA => 600,
XGA => 768,
SXGA => 1024,
HD => 1080
);
end package ee_pkg;
use work.ee_pkg.all;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY constant_test_tb IS
END constant_test_tb;
ARCHITECTURE behavior OF constant_test_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ee
generic (
RESOLUTION : tRESOLUTION
);
port (
oH_ACTIVE_VIDEO : out integer;
oV_ACTIVE_VIDEO : out integer
);
END COMPONENT;
--Outputs
signal oH_ACTIVE_VIDEO : integer;
signal oV_ACTIVE_VIDEO : integer;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ee generic map(
RESOLUTION => XGA
) PORT MAP (
oH_ACTIVE_VIDEO => oH_ACTIVE_VIDEO,
oV_ACTIVE_VIDEO => oV_ACTIVE_VIDEO
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
-- insert stimulus here
wait;
end process;
END;
package ee_pkg is
type tRESOLUTION is (
VGA,
SVGA,
XGA,
SXGA,
HD
);
type tACTIVE_VIDEO is record
H : integer range 640 to 1920;
V : integer range 480 to 1080;
end record tACTIVE_VIDEO;
type tACTIVE_VIDEO_R is array (tRESOLUTION) of tACTIVE_VIDEO;
constant cACTIVE_VIDEO_R : tACTIVE_VIDEO_R := (
VGA => (H => 640, V => 480),
SVGA => (H => 800, V => 600),
XGA => (H => 1024, V => 768),
SXGA => (H => 1280, V => 1024),
HD => (H => 1920, V => 1080)
);
end package ee_pkg;
use work.ee_pkg.all;
entity ee is
generic (
RESOLUTION : tRESOLUTION := XGA
);
port (
iRESOLUTION : in tRESOLUTION;
oACTIVE_VIDEO : out tACTIVE_VIDEO
);
begin
end entity ee;
architecture a of ee is
-- NOTE: Use elab-time constant via generic.
constant cACTIVE_VIDEO : tACTIVE_VIDEO := cACTIVE_VIDEO_R(RESOLUTION);
begin
-- NOTE: Use run-time parameter via port.
oACTIVE_VIDEO <= cACTIVE_VIDEO_R(iRESOLUTION);
end architecture a;
-- COS(), SIN() Test (cos_sin_test.vhd)
-- COS(), SIN() 符号1ビット、整数部1ビット、小数部8ビット
-- output は 256倍にしてある
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.math_real.all;
entity cos_sin_test is
port(
cos_sel : in std_logic_vector(2 downto 0);
sin_sel : in std_logic_vector(2 downto 0);
cos_output : out std_logic_vector(9 downto 0);
sin_output : out std_logic_vector(9 downto 0)
);
end cos_sin_test;
architecture RTL of cos_sin_test is
-- 符号1ビット、整数部1ビット、小数部8ビット
constant cos0_16 : std_logic_vector := std_logic_vector(to_signed((integer(cos((2.0*MATH_PI)*0.0/16.0) * 256.0)),10));
constant cos1_16 : std_logic_vector := std_logic_vector(to_signed((integer(cos((2.0*MATH_PI)*1.0/16.0) * 256.0)),10));
constant cos2_16 : std_logic_vector := std_logic_vector(to_signed((integer(cos((2.0*MATH_PI)*2.0/16.0) * 256.0)),10));
constant cos3_16 : std_logic_vector := std_logic_vector(to_signed((integer(cos((2.0*MATH_PI)*3.0/16.0) * 256.0)),10));
constant cos4_16 : std_logic_vector := std_logic_vector(to_signed((integer(cos((2.0*MATH_PI)*4.0/16.0) * 256.0)),10));
constant cos5_16 : std_logic_vector := std_logic_vector(to_signed((integer(cos((2.0*MATH_PI)*5.0/16.0) * 256.0)),10));
constant cos6_16 : std_logic_vector := std_logic_vector(to_signed((integer(cos((2.0*MATH_PI)*6.0/16.0) * 256.0)),10));
constant cos7_16 : std_logic_vector := std_logic_vector(to_signed((integer(cos((2.0*MATH_PI)*7.0/16.0) * 256.0)),10));
constant sin0_16 : std_logic_vector := std_logic_vector(to_signed((integer(sin((2.0*MATH_PI)*0.0/16.0) * 256.0)),10));
constant sin1_16 : std_logic_vector := std_logic_vector(to_signed((integer(sin((2.0*MATH_PI)*1.0/16.0) * 256.0)),10));
constant sin2_16 : std_logic_vector := std_logic_vector(to_signed((integer(sin((2.0*MATH_PI)*2.0/16.0) * 256.0)),10));
constant sin3_16 : std_logic_vector := std_logic_vector(to_signed((integer(sin((2.0*MATH_PI)*3.0/16.0) * 256.0)),10));
constant sin4_16 : std_logic_vector := std_logic_vector(to_signed((integer(sin((2.0*MATH_PI)*4.0/16.0) * 256.0)),10));
constant sin5_16 : std_logic_vector := std_logic_vector(to_signed((integer(sin((2.0*MATH_PI)*5.0/16.0) * 256.0)),10));
constant sin6_16 : std_logic_vector := std_logic_vector(to_signed((integer(sin((2.0*MATH_PI)*6.0/16.0) * 256.0)),10));
constant sin7_16 : std_logic_vector := std_logic_vector(to_signed((integer(sin((2.0*MATH_PI)*7.0/16.0) * 256.0)),10));
begin
process(cos_sel) begin
case cos_sel is
when "000" => cos_output <= cos0_16;
when "001" => cos_output <= cos1_16;
when "010" => cos_output <= cos2_16;
when "011" => cos_output <= cos3_16;
when "100" => cos_output <= cos4_16;
when "101" => cos_output <= cos5_16;
when "110" => cos_output <= cos6_16;
when others => cos_output <= cos7_16;
end case;
end process;
process(sin_sel) begin
case sin_sel is
when "000" => sin_output <= sin0_16;
when "001" => sin_output <= sin1_16;
when "010" => sin_output <= sin2_16;
when "011" => sin_output <= sin3_16;
when "100" => sin_output <= sin4_16;
when "101" => sin_output <= sin5_16;
when "110" => sin_output <= sin6_16;
when others => sin_output <= sin7_16;
end case;
end process;
end RTL;
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:06:54 07/12/2013
// Design Name: cos_sin_test
// Module Name: D:/HDL/FndISEWork/Kintex-7/TED_K7/test/cos_sin_test/cos_sin_test_tb.v
// Project Name: cos_sin_test
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: cos_sin_test
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module cos_sin_test_tb;
// Inputs
reg [2:0] cos_sel;
reg [2:0] sin_sel;
// Outputs
wire [9:0] cos_output;
wire [9:0] sin_output;
// Instantiate the Unit Under Test (UUT)
cos_sin_test uut (
.cos_sel(cos_sel),
.sin_sel(sin_sel),
.cos_output(cos_output),
.sin_output(sin_output)
);
initial begin
$monitor("%h %b %b", cos_sel, cos_output, sin_output);
// Initialize Inputs
cos_sel = 0;
sin_sel = 0;
// Wait 100 ns for global reset to finish
#100;
cos_sel = 1;
sin_sel = 1;
#100;
cos_sel = 2;
sin_sel = 2;
#100;
cos_sel = 3;
sin_sel = 3;
#100;
cos_sel = 4;
sin_sel = 4;
#100;
cos_sel = 5;
sin_sel = 5;
#100;
cos_sel = 6;
sin_sel = 6;
#100;
cos_sel = 7;
sin_sel = 7;
#100;
// Add stimulus here
end
initial $monitor("%h %b %b", cos_sel, cos_output, sin_output);
endmodule
-- COS(), SIN() Test (cos_sin_test.vhd)
-- COS(), SIN() 符号1ビット、整数部1ビット、小数部8ビット
-- output は 256倍にしてある
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- use ieee.std_logic_misc.all; -- NOTE: std_logic_misc is a legacy POS from Synopsys.
use ieee.math_real.all;
entity cos_sin_test is
-- FIXME: In VHDL-2002, predefined integer should be in [+(2**31)-1, -(2**31)+1] .
-- To restrict upper bound of SW and OW is worth to consider.
generic (
SW : integer range 1 to integer'high := 3;
OW : integer range 2 to integer'high := 10
);
port(
-- NOTE: Do not hard code any bit width for future use.
cos_sel : in std_logic_vector(SW-1 downto 0);
sin_sel : in std_logic_vector(SW-1 downto 0);
cos_output : out std_logic_vector(OW-1 downto 0);
sin_output : out std_logic_vector(OW-1 downto 0)
);
begin -- NOTE: Do not be lazy for typing "begin".
end entity cos_sin_test; -- NOTE: Do not be lazy for typing "entity".
architecture RTL of cos_sin_test is
-- NOTE: Calculate them into constant LUTs using SW and OW.
type tLUT is array (0 to 2**SW-1) of std_logic_vector(OW-1 downto 0);
pure function fCOS_LUT (
iDUMMY : boolean -- NOTE: Dummy argument for stupid simulator/synthesizer.
) return tLUT is
variable vCOS : real;
variable vCOS_LUT : tLUT;
begin
F_COS_LUT : for vSEL in tLUT'range loop
-- NOTE: Use round for better accuracy.
vCOS := round(cos(2.0 * MATH_PI * real(vSEL) / real(2**(SW+1))) * real(2**(OW-2)));
-- NOTE: Consider cos(...) = 1.0.
-- FIXME: Enlarge OW scheme if you don't like this clamp which produces a bit of
-- distortion at specific arguments.
vCOS_LUT(vSEL) := std_logic_vector(to_signed(integer(vCOS), OW));
end loop F_COS_LUT;
return vCOS_LUT;
end function fCOS_LUT;
pure function fSIN_LUT (
iDUMMY : boolean -- NOTE: Dummy argument for stupid simulator/synthesizer.
) return tLUT is
variable vSIN : real;
variable vSIN_LUT : tLUT;
begin
F_SIN_LUT : for vSEL in tLUT'range loop
-- NOTE: Use round for better accuracy.
vSIN := round(sin(2.0 * MATH_PI * real(vSEL) / real(2**(SW+1))) * real(2**(OW-2)));
-- NOTE: Consider sin(...) = 1.0.
-- FIXME: Enlarge OW scheme if you don't like this clamp which produces a bit of
-- distortion at specific arguments.
vSIN_LUT(vSEL) := std_logic_vector(to_signed(integer(vSIN), OW));
end loop F_SIN_LUT;
return vSIN_LUT;
end function fSIN_LUT;
constant cCOS_LUT : tLUT := fCOS_LUT(true);
constant cSIN_LUT : tLUT := fSIN_LUT(true);
begin
cos_output <= cCOS_LUT(to_integer(unsigned(cos_sel)));
sin_output <= cSIN_LUT(to_integer(unsigned(sin_sel)));
end architecture RTL; -- NOTE: Do not be lazy for typing "architecture".
if write_count=0 and M_AXI_WREADY='1' then -- 終了
if unsigned(write_count)=0 and M_AXI_WREADY='1' then -- 終了
function "=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
if unsigned(write_count)=natural(0) and M_AXI_WREADY='1' then -- 終了
write_count <= write_count - 1;
write_count <= std_logic_vector(unsigned(write_count) - 1);
function "-" (L: UNSIGNED;R: NATURAL) return UNSIGNED;
write_count <= std_logic_vector(unsigned(write_count) - natural(1));
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
function TO_INTEGER (ARG: UNSIGNED) return NATURAL;
function TO_INTEGER (ARG: SIGNED) return INTEGER;
function TO_UNSIGNED (ARG, SIZE: NATURAL) return UNSIGNED;
function TO_SIGNED (ARG: INTEGER; SIZE: NATURAL) return SIGNED;
function "+" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
function "+" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
function "+" (L: INTEGER; R: SIGNED) return SIGNED;
function "+" (L: SIGNED; R: INTEGER) return SIGNED;
7 mod 3 = 1 :3x2 +1 = 7
(-7) mod 3 = 2 :3x(-3) +2 = -7
7 mod (-3) = -2 :(-3)x(-3) -2 = 7
(-7) mod (-3) = -1 :(-3)x2 -1 = -7
7 rem 3 = 1 :3x2 +1 = 7
(-7) rem 3 = -1 :3x(-2) -1 = -7
7 rem (-3) = 1 :(-3)x(-2) +1 = 7
(-7) rem (-3) = -1 :(-3)x2 -1 = -7
日 | 月 | 火 | 水 | 木 | 金 | 土 |
---|---|---|---|---|---|---|
- | - | - | - | 1 | 2 | 3 |
4 | 5 | 6 | 7 | 8 | 9 | 10 |
11 | 12 | 13 | 14 | 15 | 16 | 17 |
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25 | 26 | 27 | 28 | 29 | 30 | - |