F1起動前準備&EC2インスタンスの起動
FPGAアクセラレーション体験
SDAccelによるF1アプリケーション開発
後⽚付けとまとめ
を変更する方法でもう一度やってみた。値は、expected_memory_usage=30000000
とした。expected_memory_usage=16000000
をexpected_memory_usage=30000000
に変更した。expected_memory_usage=16000000
[Common 17-348] Failed to get the license for feature 'Synthesis' and/or device 'xcvu9p-flgb2104'. Explanation: The license feature Synthesis could not be found.
Resolution: Check the status of your licenses in the Vivado License Manager. For debug help search Xilinx Support for "Licensing FAQ".
masaaki@masaaki-VirtualBox:~/aws-fpga$ source hdk_setup.sh
INFO: Using Vivado v2017.1 (64-bit)
INFO: Setting up environment variables
INFO: Using HDK shell version shell_v04151701
INFO: HDK shell is up-to-date
INFO: DDR4 model files in /home/masaaki/aws-fpga/hdk/common/verif/models/ddr4_model/ do NOT exist. Running model creation step.
INFO: Building in /home/masaaki/aws-fpga/ddr4_model_build
INFO: This could take 5-10 minutes, please be patient!
/home/masaaki/aws-fpga/hdk/common/verif/scripts/init.sh: 18: /home/masaaki/aws-fpga/hdk/common/verif/scripts/init.sh: [[: not found
/home/masaaki/aws-fpga/hdk/common/verif/scripts/init.sh: 23: /home/masaaki/aws-fpga/hdk/common/verif/scripts/init.sh: [[: not found
/home/masaaki/aws-fpga/hdk/common/verif/scripts/init.sh: 29: /home/masaaki/aws-fpga/hdk/common/verif/scripts/init.sh: [[: not found
****** Vivado v2017.1 (64-bit)
**** SW Build 1846317 on Fri Apr 14 18:54:47 MDT 2017
**** IP Build 1846188 on Fri Apr 14 20:52:08 MDT 2017
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
source /home/masaaki/aws-fpga/hdk/common/verif/scripts/init.tcl
# set_msg_config -severity INFO -suppress
# set_msg_config -severity STATUS -suppress
# set_msg_config -severity WARNING -suppress
CRITICAL WARNING: [Common 17-1355] You are suppressing all messages of type 'WARNING'. You may potentially disregard important DRC, CDC, and implementation messages that can negatively impact your design. If this is not desired, please run 'reset_msg_config -suppress -severity {WARNING}' to undo this change.
# set_msg_config -string {exportsim} -suppress
# set_msg_config -string {IP_Flow} -suppress
# create_project -force tmp_ddr ./tmp -part xcvu9p-flgb2104-2-i
# add_files -norecurse $::env(HDK_COMMON_DIR)/shell_stable/design/ip/ddr4_core/ddr4_core.xci
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2017.1/data/ip'.
add_files: Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 1308.211 ; gain = 213.969 ; free physical = 474 ; free virtual = 18367
# export_ip_user_files -of_objects [get_files $::env(HDK_COMMON_DIR)/shell_stable/design/ip/ddr4_core/ddr4_core.xci] -force -quiet
# open_example_project -force -dir ./tmp/tmp_ddr_ex [get_ips ddr4_core]
INFO: [IP_Flow 19-1686] Generating 'Examples' target for IP 'ddr4_core'...
INFO: [Device 21-403] Loading part xcvu9p-flgb2104-2-i
****** Vivado v2017.1 (64-bit)
**** SW Build 1846317 on Fri Apr 14 18:54:47 MDT 2017
**** IP Build 1846188 on Fri Apr 14 20:52:08 MDT 2017
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
source /home/masaaki/aws-fpga/hdk/common/shell_stable/design/ip/ddr4_core/ddr4_core_ex.tcl -notrace
INFO: [open_example_project] Creating new example project...
INFO: [open_example_project] Importing original IP ...
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2017.1/data/ip'.
import_ip: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1316.215 ; gain = 8.012 ; free physical = 219 ; free virtual = 17375
INFO: [open_example_project] Generating the example project IP ...
INFO: [open_example_project] Adding example synthesis HDL files ...
INFO: [open_example_project] Adding example XDC files ...
INFO: [open_example_project] Adding simulation HDL files ...
INFO: [open_example_project] Sourcing example extension scripts ...
Post processing the example_design
update_compile_order: Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1316.645 ; gain = 0.418 ; free physical = 311 ; free virtual = 17369
INFO: [open_example_project] Rebuilding all the top level IPs ...
INFO: [exportsim-Tcl-35] Exporting simulation files for "XSIM" (Xilinx Vivado Simulator)...
INFO: [exportsim-Tcl-29] Script generated: '/home/masaaki/aws-fpga/ddr4_model_build/tmp/tmp_ddr_ex/ddr4_core_ex/ddr4_core_ex.ip_user_files/sim_scripts/ddr4_core/xsim/ddr4_core.sh'
Generating merged BMM file for the design top 'sim_tb_top'...
Generating merged BMM file for the design top 'sim_tb_top'...
INFO: [exportsim-Tcl-35] Exporting simulation files for "MODELSIM" (Mentor Graphics ModelSim Simulator)...
INFO: [exportsim-Tcl-29] Script generated: '/home/masaaki/aws-fpga/ddr4_model_build/tmp/tmp_ddr_ex/ddr4_core_ex/ddr4_core_ex.ip_user_files/sim_scripts/ddr4_core/modelsim/ddr4_core.sh'
INFO: [exportsim-Tcl-35] Exporting simulation files for "QUESTA" (Mentor Graphics Questa Advanced Simulator)...
INFO: [exportsim-Tcl-29] Script generated: '/home/masaaki/aws-fpga/ddr4_model_build/tmp/tmp_ddr_ex/ddr4_core_ex/ddr4_core_ex.ip_user_files/sim_scripts/ddr4_core/questa/ddr4_core.sh'
INFO: [exportsim-Tcl-35] Exporting simulation files for "IES" (Cadence Incisive Enterprise Simulator)...
INFO: [exportsim-Tcl-29] Script generated: '/home/masaaki/aws-fpga/ddr4_model_build/tmp/tmp_ddr_ex/ddr4_core_ex/ddr4_core_ex.ip_user_files/sim_scripts/ddr4_core/ies/ddr4_core.sh'
INFO: [exportsim-Tcl-35] Exporting simulation files for "VCS" (Synopsys Verilog Compiler Simulator)...
INFO: [exportsim-Tcl-29] Script generated: '/home/masaaki/aws-fpga/ddr4_model_build/tmp/tmp_ddr_ex/ddr4_core_ex/ddr4_core_ex.ip_user_files/sim_scripts/ddr4_core/vcs/ddr4_core.sh'
INFO: [exportsim-Tcl-35] Exporting simulation files for "RIVIERA" (Aldec Riviera-PRO Simulator)...
INFO: [exportsim-Tcl-29] Script generated: '/home/masaaki/aws-fpga/ddr4_model_build/tmp/tmp_ddr_ex/ddr4_core_ex/ddr4_core_ex.ip_user_files/sim_scripts/ddr4_core/riviera/ddr4_core.sh'
INFO: [exportsim-Tcl-35] Exporting simulation files for "ACTIVEHDL" (Aldec Active-HDL Simulator)...
INFO: [exportsim-Tcl-29] Script generated: '/home/masaaki/aws-fpga/ddr4_model_build/tmp/tmp_ddr_ex/ddr4_core_ex/ddr4_core_ex.ip_user_files/sim_scripts/ddr4_core/activehdl/ddr4_core.sh'
INFO: [open_example_project] Open Example Project completed
INFO: [Common 17-206] Exiting Vivado at Sun Jul 9 18:03:27 2017...
open_example_project: Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 2018.074 ; gain = 678.875 ; free physical = 531 ; free virtual = 17600
# exit
INFO: [Common 17-206] Exiting Vivado at Sun Jul 9 18:03:28 2017...
Copying files to /home/masaaki/aws-fpga/hdk/common/verif/models/ddr4_model
Copying files to /home/masaaki/aws-fpga/hdk/common/verif/models/ddr4_rdimm_wrapper
INFO: DDR4 model build passed.
INFO: ATTENTION: Don't forget to set the CL_DIR variable for the directory of your Custom Logic.
INFO: AWS HDK setup PASSED.
masaaki@masaaki-VirtualBox:~/aws-fpga$
で、メモリは10GB 程度割り当てているのだが、だめだそうだ。ERROR: YOUR INSTANCE has less memory than is necessary for certain builds. This means that your builds will take longer than expected.
To change to an instance type with more memory, please check our instance resize guide: http://docs.aws.amazon.com/AWSEC2/latest/UserGuide/ec2-instance-resize.html
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