FC2カウンター FPGAの部屋 Vitis_Vision
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FPGAやCPLDの話題やFPGA用のツールの話題などです。 マニアックです。 日記も書きます。

FPGAの部屋

FPGAの部屋の有用と思われるコンテンツのまとめサイトを作りました。Xilinx ISEの初心者の方には、FPGAリテラシーおよびチュートリアルのページをお勧めいたします。

Vitis_Libraries/vision/L3/examples/stereopipeline/ をやってみた3

Vitis_Libraries/vision/L3/examples/stereopipeline/ をやってみた2”の続き。

Vitis_Libraries/vision/L3/examples/stereopipeline/ のVivado HLS や Vivado のプロジェクトを見た。今回は、Ultra96-V2 の実機で動作を確認してみよう。

Ultra96-V2 の電源をON して、PetaLinux を起動した。

Vitis_Libraries/vision/L3/examples/stereopipline/build/xclbin_ultra96v2_min2_hw/sd_card ディレクトリに行って、BOOT.BIN を Ultra96-V2 の /run/media/mmcblk0p1 に SFTP する。
scp BOOT.BIN 192.168.3.23:/run/media/mmcblk0p1
Vitis_Vision_93_200407.png

Ultra96-V2 のターミナルで /home/root にあった colordetect の sd_card ディレクトリを color_detect_sd_card に名前を変更した。

Vitis_Libraries/vision/L3/examples/stereopipeline/build ディレクトリに行って、 sd_card ディレクトリ以下をすべて Ultra96-V2 の /home/root にコピーした。
scp -r sd_card 192.168.3.23:/home/root
Vitis_Vision_94_200407.png

Vitis_Vision_95_200407.png

Ultra96-V2 のターミナルでみると、 /home/root ディレクトリの下に、 sd_card ディレクトリがコピーできている。
reboot を行った。

drm のメッセージとコンソールの表示メッセージを分けるために、ssh でログインした。
ssh 192.168.3.23 -X -l root

Ultra96-V2 のPetaLinux 上で zocl ドライバを起動した。
insmod /lib/modules/4.19.0-xilinx-v2019.2/extra/zocl.ko

XRT へのパスを通し、init.sh を実行形式にしてから init.sh を起動する。
export XILINX_XRT=/usr
cd sd_card
chmod +x init.sh
./init.sh

Vitis_Vision_96_200407.png

成功した。 hls_output.png が生成された。
ログを示す。

root@ultra96v2_min2:~/sd_card# ./init.sh
INFO: Running OpenCL section.
Found Platform
Platform Name: Xilinx
INFO: Device found - edge
XCLBIN File Name: krnl_stereopipeline
INFO: Importing xclbin_ultra96v2_min2_hw/krnl_stereopipeline.xclbin
Loading: 'xclbin_ultra96v2_min2_hw/krnl_stereopipeline.xclbin'
run complete !


ターミナル画面を示す。
Vitis_Vision_97_200407.png

ログを示す。

root@ultra96v2_min2:~# [  111.715443] zocl: loading out-of-tree module taints kernel.
[  111.724722] [drm] Probing for xlnx,zocl
[  111.728723] [drm] FPGA programming device pcap founded.
[  111.733956] [drm] PR Isolation addr 0x0
[  111.734724] [drm] Initialized zocl 2018.2.1 20180313 for a0000000.zyxclmm_drm on minor 1
[  158.828342] [drm] Pid 2204 opened device
[  158.832310] [drm] Pid 2204 closed device
[  158.847453] [drm] Pid 2204 opened device
[  159.147138] [drm] Finding IP_LAYOUT section header
[  159.147150] [drm] Section IP_LAYOUT details:
[  159.151965] [drm]   offset = 0x54fcf8
[  159.156224] [drm]   size = 0x58
[  159.159886] [drm] Finding DEBUG_IP_LAYOUT section header
[  159.163021] [drm] AXLF section DEBUG_IP_LAYOUT header not found
[  159.168326] [drm] Finding CONNECTIVITY section header
[  159.174243] [drm] Section CONNECTIVITY details:
[  159.179287] [drm]   offset = 0x54fd50
[  159.183807] [drm]   size = 0x7c
[  159.187468] [drm] Finding MEM_TOPOLOGY section header
[  159.190605] [drm] Section MEM_TOPOLOGY details:
[  159.195649] [drm]   offset = 0x54fc00
[  159.200169] [drm]   size = 0xf8
[  159.211895] [drm] No ERT scheduler on MPSoC, using KDS
[  159.220541] [drm] Fail to install CU 0 interrupt handler: -22. Fall back to polling mode.
[  159.228716] [drm] scheduler config ert(0)
[  159.228723] [drm]   cus(1)
[  159.232729] [drm]   slots(16)
[  159.235429] [drm]   num_cu_masks(1)
[  159.238387] [drm]   cu_shift(16)
[  159.241862] [drm]   cu_base(0xa0000000)
[  159.245083] [drm]   polling(1)
[  159.424457] [drm] Pid 2204 closed device


出力された画像ファイル hls_output.png を scp でホストパソコンに持ってきた。
scp 192.168.3.23:/home/root/sd_card/hls_output.png .
Vitis_Vision_98_200407.png

hls_output.png を示す。
Vitis_Vision_99_200407.png

元画像の left.png と right.png を Vitis_Libraries/vision/L3/examples/stereopipeline/data から引用する。
Vitis_Vision_100_200407.jpg

Vitis_Vision_101_200407.jpg
  1. 2020年04月07日 04:54 |
  2. Vitis_Vision
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Vitis_Libraries/vision/L3/examples/stereopipeline/ をやってみた2

Vitis_Libraries/vision/L3/examples/stereopipeline/ をやってみた1”の続き。

前回は、 Vitis_Libraries/vision/L3/examples/stereopipeline/ のビルドを行って成功した。今回は、 Vitis_Libraries/vision/L3/examples/stereopipeline/ のVivado HLS や Vivado のプロジェクトを見ていこう。

Vivado HLS 2019.2 のプロジェクトは Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/stereopipeline_accel/stereopipeline_accel/stereopipeline_accel に入っている。
Vivado HLS 2019.2 を立ち上げて、合成レポートを見た。
Vitis_Vision_91_200404.png
Vitis_Vision_92_200404.png

Latency の min は 6347629 クロックで、max は 8421228 クロックだった。画像は 1920 x 1080 ピクセル = 2073600 ピクセルなので、min の場合は
6347629 / 2073600 ≒ 3.06 クロック/ピクセルだった。
max の場合は
8421228 / 2073600 ≒ 4.06 クロック/ピクセルだった。
Detail -> Instance をみると、やはり StereoBM でそれだけのクロックがかかっている。

BRAM_18K は 80 %, DSP48E は 50 %, FF は 70 %, LUT はなんと 138 % でオーバーしている。これは Vivado で合成した時に減ったので、合成できているようだ。

次に、Vivado 2019.2 のプロジェクトを見てみよう。
Vivado のプロジェクトは Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/vivado/vpl/prj にある。
Vivado 2019.2 を立ち上げて、ブロックデザインを見た。
Vitis_Vision_86_200404.png

AXI4 Master ポートが 6 個でているのが分かる。

Address Editor 画面を示す。
Vitis_Vision_87_200404.png

Project Summary を示す。
Vitis_Vision_88_200404.png
Vitis_Vision_89_200404.png
Vitis_Vision_90_200404.png

LUT は 70 % でまだ余裕がある。やはり、Vivado HLS の合成レポートの LUT のリソース使用量は当てにならないようだ。
  1. 2020年04月04日 05:58 |
  2. Vitis_Vision
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Vitis_Libraries/vision/L3/examples/stereopipeline/ をやってみた1

前回、 Vitis_Libraries/vision/L3/examples/cornertracker/ をやってみたが、Ultra96-V2 の UltraScale++ MPSoC のリソースが足りずにインプリメンテーションでエラーがでてしまった。今回は、 Vitis_Libraries/vision/L3/examples/stereopipeline/ をやってみよう。

Vitis_Libraries/vision/L3/examples/colordetect/ をやったばかりで、環境は設定されている。その環境設定方法を示す。

1. Vitis のインストール・ディレクトリの settings64.sh を実行
source /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/settings64.sh

2. XRT の setenv.sh を実行
source /opt/xilinx/xrt/setup.sh

3. DEVICE 環境変数にプラットフォームの xpfm ファイルへのパスを設定する
export DEVICE=/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm

4. SYSROOT にプラットフォームの sysroot へのパスを設定する。
export SYSROOT=/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux


それでは、Vitis_Libraries/vision/L3/examples/stereopipeline/build ディレクトリに cd して、 xclbin を make する
make host xclbin TARGET=hw BOARD=Zynq ARCH=aarch64
を実行した。
するとエラーで終了した。
Vitis_Vision_77_200402.png

エラー内容は

ERROR: [v++ 82-216] Invalid integer value for clock.defaultFreqHz option: -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline

だった。
直前の v++ コマンドを示す。

v++ -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/xo_ultra96v2_min2_hw/stereopipeline_accel.xo --kernel stereopipeline_accel --compile /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_accel.cpp \
-I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/include -I. -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include -D__SDSVHLS__ -DHLS_NO_XIL_FPO_LIB --clock.defaultFreqHz -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline --target hw --platform /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm --temp_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw --save-temps --debug --kernel_frequency 300 --report_level 2 --xp


--clock.defaultFreqHz の後に動作周波数が記述されていなかった。

cornertracker の v++ コマンドを示す。

v++ -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/pyr_dense_optical_flow_accel.xo --kernel pyr_dense_optical_flow_accel --compile /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_pyr_dense_optical_flow_accel.cpp \
-I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/include -I. -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include -D__SDSVHLS__ -DHLS_NO_XIL_FPO_LIB --xp vivado_prop:run.impl_1.strategy=Performance_Explore --clock.defaultFreqHz 300000000 -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker --target hw --platform /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm --temp_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw --save-temps --debug --kernel_frequency 300 --report_level 2


--clock.defaultFreqHz 300000000 と --clock.defaultFreqHz の後ろに 300000000 の値が入っている。
ここがおかしいので Makefile を以下のように修正した。
Vitis_Vision_78_200402.png

他の値もいじってみたのだが、うまく行かずに 204 行目の後に

VPP_CFLAGS += --clock.defaultFreqHz 300000000

を追加して、 204 行目をコメントアウトした。
これで、
make host xclbin TARGET=hw BOARD=Zynq ARCH=aarch64
を実行したところ、成功した。
Vitis_Vision_79_200402.png

Vitis_Vision_80_200402.png

次に、 sd_card ディレクトリを作成するのだが、いつもエラーなっているので、予め Makefile を編集しておく。
Vitis_Vision_81_200403.png

451 行目の

$(B_NAME)/sw/$(XDEVICE)/xrt/image/*

を削除した。

make run TARGET=hw BOARD=Zynq ARCH=aarch64
を実行したところ、成功した。
Vitis_Vision_82_200403.png

Vitis_Libraries/vision/L3/examples/stereopipeline/build ディレクトリを示す。sd_card ディレクトリができている。
Vitis_Vision_83_200403.png

Vitis_Libraries/vision/L3/examples/stereopipeline/build/sd_card ディレクトリを示す。
Vitis_Vision_84_200403.png

BOOT.BIN ファイルも Vitis_Libraries/vision/L3/examples/stereopipeline/build/xclbin_ultra96v2_min2_hw/sd_card ディレクトリにできていた。
Vitis_Vision_85_200403.png

最後に、 make host xclbin TARGET=hw BOARD=Zynq ARCH=aarch64 実行時のログを示す。

masaaki@masaaki-H110M4-M01:/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build$ make host xclbin TARGET=hw BOARD=Zynq ARCH=aarch64
-e ----
Compiling object xf_stereo_pipeline_tb...
mkdir -p /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/obj_ultra96v2_min2
aarch64-linux-gnu-g++ -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/obj_ultra96v2_min2/xf_stereo_pipeline_tb.o -c /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_tb.cpp -D XDEVICE=ultra96v2_min2 -DVIVADO_HLS_SIM -D__SDSVHLS__ -DHLS_NO_XIL_FPO_LIB -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/include -I. -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2 -g --sysroot=/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux -D__ZYNQ -std=c++14 -fPIC -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline -I/opt/xilinx/xrt/include -Wall -Wno-unknown-pragmas -Wno-unused-label -pthread  -idirafter /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vivado/2019.2/include 
In file included from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include/common/xf_headers.hpp:30,
                 from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_tb.cpp:17:
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include/common/xf_sw_utils.hpp: 関数 ‘void xf::cv::analyzeDiff(cv::Mat&, int, float&)’ 内:
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include/common/xf_sw_utils.hpp:150:23: 警告: 変数 ‘v_tmp1’ が設定されましたが使用されていません [-Wunused-but-set-variable]
                 float v_tmp1;
                       ^~~~~~
In file included from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_tb.cpp:21:
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_tb.cpp: 関数 ‘int main(int, char**)’ 内:
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_tb.cpp:113:96: 警告: ISO C++ says that these are ambiguous, even though the worst conversion for the first is better than the worst conversion for the second:
 cl::Buffer imageToDeviceL(context, CL_MEM_READ_ONLY, rows * cols, NULL, &err));
                                                                             ^

/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2/xcl2.hpp:41:5: 備考: in definition of macro ‘OCL_CHECK’
     call;                                                           \
     ^~~~
In file included from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2/xcl2.hpp:48,
                 from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_tb.cpp:21:
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:3675:5: 備考: 候補 1: ‘cl::Buffer::Buffer(const cl::Context&, cl_mem_flags, cl::size_type, void*, cl_int*)’
     Buffer(
     ^~~~~~
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:8512:1: 備考: 候補 2: ‘cl::Buffer::Buffer(const cl::Context&, IteratorType, IteratorType, bool, bool, cl_int*) [with IteratorType = int; cl_int = int]’
 Buffer::Buffer(
 ^~~~~~
In file included from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_tb.cpp:21:
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_tb.cpp:114:96: 警告: ISO C++ says that these are ambiguous, even though the worst conversion for the first is better than the worst conversion for the second:
 cl::Buffer imageToDeviceR(context, CL_MEM_READ_ONLY, rows * cols, NULL, &err));
                                                                             ^

/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2/xcl2.hpp:41:5: 備考: in definition of macro ‘OCL_CHECK’
     call;                                                           \
     ^~~~
In file included from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2/xcl2.hpp:48,
                 from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_tb.cpp:21:
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:3675:5: 備考: 候補 1: ‘cl::Buffer::Buffer(const cl::Context&, cl_mem_flags, cl::size_type, void*, cl_int*)’
     Buffer(
     ^~~~~~
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:8512:1: 備考: 候補 2: ‘cl::Buffer::Buffer(const cl::Context&, IteratorType, IteratorType, bool, bool, cl_int*) [with IteratorType = int; cl_int = int]’
 Buffer::Buffer(
 ^~~~~~
In file included from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_tb.cpp:21:
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_tb.cpp:115:102: 警告: ISO C++ says that these are ambiguous, even though the worst conversion for the first is better than the worst conversion for the second:
 ffer imageFromDevice(context, CL_MEM_WRITE_ONLY, rows * cols * 2, NULL, &err));
                                                                             ^

/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2/xcl2.hpp:41:5: 備考: in definition of macro ‘OCL_CHECK’
     call;                                                           \
     ^~~~
In file included from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2/xcl2.hpp:48,
                 from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_tb.cpp:21:
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:3675:5: 備考: 候補 1: ‘cl::Buffer::Buffer(const cl::Context&, cl_mem_flags, cl::size_type, void*, cl_int*)’
     Buffer(
     ^~~~~~
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:8512:1: 備考: 候補 2: ‘cl::Buffer::Buffer(const cl::Context&, IteratorType, IteratorType, bool, bool, cl_int*) [with IteratorType = int; cl_int = int]’
 Buffer::Buffer(
 ^~~~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_tb.cpp:158:14: 警告: unused variable ‘start’ [-Wunused-variable]
     cl_ulong start = 0;
              ^~~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_tb.cpp:159:14: 警告: unused variable ‘end’ [-Wunused-variable]
     cl_ulong end = 0;
              ^~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_tb.cpp:160:12: 警告: unused variable ‘diff_prof’ [-Wunused-variable]
     double diff_prof = 0.0f;
            ^~~~~~~~~
-e ----
Compiling extra object /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/obj_ultra96v2_min2/xcl2.o...
mkdir -p /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/obj_ultra96v2_min2
aarch64-linux-gnu-g++ -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/obj_ultra96v2_min2/xcl2.o -c /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2/xcl2.cpp -D XDEVICE=ultra96v2_min2 -DVIVADO_HLS_SIM -D__SDSVHLS__ -DHLS_NO_XIL_FPO_LIB -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/include -I. -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2 -g --sysroot=/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux -D__ZYNQ -std=c++14 -fPIC -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline -I/opt/xilinx/xrt/include -Wall -Wno-unknown-pragmas -Wno-unused-label -pthread  -idirafter /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vivado/2019.2/include -I /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2
-e ----
Compiling host stereopipeline.exe...
mkdir -p /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/bin_ultra96v2_min2
aarch64-linux-gnu-g++ -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/bin_ultra96v2_min2/stereopipeline.exe /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/obj_ultra96v2_min2/xf_stereo_pipeline_tb.o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/obj_ultra96v2_min2/xcl2.o -D XDEVICE=ultra96v2_min2 -DVIVADO_HLS_SIM -D__SDSVHLS__ -DHLS_NO_XIL_FPO_LIB -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/include -I. -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2 -g --sysroot=/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux -D__ZYNQ -std=c++14 -fPIC -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline -I/opt/xilinx/xrt/include -Wall -Wno-unknown-pragmas -Wno-unused-label -pthread  -idirafter /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vivado/2019.2/include -L/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/lib -Wl,-rpath-link=/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/lib/ -L/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/opt/xilinx/xrt/lib -lopencv_imgcodecs -lopencv_core -lopencv_imgproc -lopencv_highgui -lopencv_calib3d -lopencv_features2d -lopencv_flann -pthread -L/opt/xilinx/xrt/lib -lxilinxopencl 
-e ----
Compiling kernel stereopipeline_accel...
mkdir -p /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/xo_ultra96v2_min2_hw
v++ -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/xo_ultra96v2_min2_hw/stereopipeline_accel.xo --kernel stereopipeline_accel --compile /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_accel.cpp \
 -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/include -I. -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include -D__SDSVHLS__ -DHLS_NO_XIL_FPO_LIB --clock.defaultFreqHz 300000000 -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline --target hw --platform /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm --temp_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw --save-temps --debug --kernel_frequency 300  --report_level 2 --xp vivado_prop:run.impl_1.strategy=Performance_Explore 
WARNING: [v++ 60-1600] The option 'xp' was used directly on the command line, where its usage is deprecated. To ensure input line works for supported operating systems or shells, v++ supports specification for some options in a configuration file. As an alternative, please use options 'advanced.*', 'vivado.*' in a configuration file. Use one or more configuration files along with section headers to define key-value pairs for the advanced properties or parameters. Specify a configuration file using '--config'.
INFO: [v++ 84-14] Sample config file already exists. To regenerate, remove file 'sample_compile.ini'.
Option Map File Used: '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/data/vitis/vpp/optMap.xml'

****** v++ v2019.2 (64-bit)
  **** SW Build 2700185 on Thu Oct 24 18:45:48 MDT 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

INFO: [v++ 60-1306] Additional information associated with this v++ compile can be found at:
 Reports: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/reports/stereopipeline_accel
 Log files: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/logs/stereopipeline_accel
Running Dispatch Server on port:46767
INFO: [v++ 60-1548] Creating build summary session with primary output /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/xo_ultra96v2_min2_hw/stereopipeline_accel.xo.compile_summary, at Thu Apr  2 20:05:40 2020
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Thu Apr  2 20:05:41 2020
Running Rule Check Server on port:42075
INFO: [v++ 60-1315] Creating rulecheck session with output '/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/reports/stereopipeline_accel/v++_compile_stereopipeline_accel_guidance.html', at Thu Apr  2 20:05:42 2020
INFO: [v++ 60-895]   Target platform: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm
INFO: [v++ 60-1578]   This platform contains Xilinx Shell Archive '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/hw/ultra96v2_min2.xsa'
INFO: [v++ 60-585] Compiling for hardware target
INFO: [v++ 60-423]   Target device: ultra96v2_min2
INFO: [v++ 60-242] Creating kernel: 'stereopipeline_accel'
INFO: [v++ 60-1616] Creating a HLS clock using kernel_frequency option: 300 MHz

===>The following messages were generated while  performing high-level synthesis for kernel: stereopipeline_accel Log file: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/stereopipeline_accel/stereopipeline_accel/vivado_hls.log :
INFO: [v++ 204-61] Option 'relax_ii_for_timing' is enabled, will increase II to preserve clock frequency constraints.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
WARNING: [v++ 204-69] Unable to schedule bus request on port 'irA_r' (/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_accel.cpp:57->/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_accel.cpp:31) due to limited memory ports. Please consider using a memory core with more ports or partitioning the array.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 4, Depth = 19.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
WARNING: [v++ 204-69] Unable to schedule bus request on port 'distC_r' (/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_accel.cpp:66->/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_accel.cpp:31) due to limited memory ports. Please consider using a memory core with more ports or partitioning the array.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 2, Depth = 17.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining loop 'L1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 4.
INFO: [v++ 204-61] Pipelining function 'xFComputeUndistortCoordinates'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 49.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [v++ 204-61] Pipelining loop 'Loop 2'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [v++ 204-61] Pipelining loop 'loop_height_loop_width'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 58.
INFO: [v++ 204-61] Pipelining loop 'memset_r1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining loop 'memset_r2'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining loop 'loop_width'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 30.
INFO: [v++ 204-61] Pipelining loop 'memset_r1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining loop 'memset_r2'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining loop 'loop_width'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 30.
INFO: [v++ 204-61] Pipelining function 'xFGradientX3x3<0, 3>'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining function 'xFGradientY3x3<0, 3>'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining function 'xFSobel3x3<1, 1, 0, 3>'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining loop 'Clear_Row_Loop'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining loop 'Col_Loop'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 7.
INFO: [v++ 204-61] Pipelining function 'xFImageClipUtility<1>'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining loop 'loop_col_clip'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 5.
INFO: [v++ 204-61] Pipelining loop 'loop_col_clip'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [v++ 204-61] Pipelining loop 'loop_col_clip'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 5.
INFO: [v++ 204-61] Pipelining loop 'loop_col_clip'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [v++ 204-61] Pipelining loop 'loop_row_loop_mux_loop_col'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 76.
INFO: [v++ 204-61] Pipelining function 'write'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [v++ 204-61] Pipelining loop 'L1'.
INFO: [v++ 204-61] Discarding stage scheduling solution.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 2, Depth = 4.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 200-790] **** Loop Constraint Status: All loop constraints were NOT satisfied.
INFO: [v++ 200-789] **** Estimated Fmax: 302.02 MHz
INFO: [v++ 60-594] Finished kernel compilation
INFO: [v++ 60-244] Generating system estimate report...
INFO: [v++ 60-1092] Generated system estimate report: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/reports/stereopipeline_accel/system_estimate_stereopipeline_accel.xtxt
Add Instance StereoBM_15_48_16_0_1_1080_1920_1_false_s StereoBM_15_48_16_0_1_1080_1920_1_false_U0 1224
Add Instance xFFindStereoCorrespondenceLBMNO_1080_1920_0_1_1_15_48_16_3_false_s grp_xFFindStereoCorrespondenceLBMNO_1080_1920_0_1_1_15_48_16_3_false_s_fu_202 202
Add Instance xFSADBlockMatching xFSADBlockMatching_U0 838
Add Instance Sobel_0_3_0_2_1080_1920_1_false_2551550 Sobel_0_3_0_2_1080_1920_1_false_2551550_U0 851
Add Instance xFSobelFilter3x3_0_2_1080_1920_1_0_3_1_1_5_1920_false_1557 grp_xFSobelFilter3x3_0_2_1080_1920_1_0_3_1_1_5_1920_false_1557_fu_94 94
Add Instance xFSobel3x3_1_1_0_3_s call_ret_xFSobel3x3_1_1_0_3_s_fu_426 426
Add Instance xFGradientX3x3_0_3_s GradientvaluesX_V_write_assign_xFGradientX3x3_0_3_s_fu_72 72
Add Instance xFGradientY3x3_0_3_s GradientvaluesY_V_write_assign_xFGradientY3x3_0_3_s_fu_88 88
Add Instance xFGradientX3x3_0_3_s GradientValuesX_0_V_xFGradientX3x3_0_3_s_fu_443 443
Add Instance xFGradientY3x3_0_3_s GradientValuesY_0_V_xFGradientY3x3_0_3_s_fu_459 459
Add Instance Sobel_0_3_0_2_1080_1920_1_false_1553 Sobel_0_3_0_2_1080_1920_1_false_1553_U0 861
Add Instance xFSobelFilter3x3_0_2_1080_1920_1_0_3_1_1_5_1920_false_1557 grp_xFSobelFilter3x3_0_2_1080_1920_1_0_3_1_1_5_1920_false_1557_fu_94 94
Add Instance xFSobel3x3_1_1_0_3_s call_ret_xFSobel3x3_1_1_0_3_s_fu_426 426
Add Instance xFGradientX3x3_0_3_s GradientvaluesX_V_write_assign_xFGradientX3x3_0_3_s_fu_72 72
Add Instance xFGradientY3x3_0_3_s GradientvaluesY_V_write_assign_xFGradientY3x3_0_3_s_fu_88 88
Add Instance xFGradientX3x3_0_3_s GradientValuesX_0_V_xFGradientX3x3_0_3_s_fu_443 443
Add Instance xFGradientY3x3_0_3_s GradientValuesY_0_V_xFGradientY3x3_0_3_s_fu_459 459
Add Instance xFImageClip_1080_1920_1_3_0_2_0_1920_256 xFImageClip_1080_1920_1_3_0_2_0_1920_256_U0 871
Add Instance xFImageClipUtility_1_s pix_1_i_i_xFImageClipUtility_1_s_fu_205 205
Add Instance xFImageClip_1080_1920_1_3_0_2_0_1920_s xFImageClip_1080_1920_1_3_0_2_0_1920_U0 882
Add Instance xFImageClipUtility_1_s pix_1_i_i_xFImageClipUtility_1_s_fu_173 173
Add Instance xFReadOutStream_1080_1920_1_3_0_2_1920_257 xFReadOutStream_1080_1920_1_3_0_2_1920_257_U0 891
Add Instance xFReadOutStream_1080_1920_1_3_0_2_1920_s xFReadOutStream_1080_1920_1_3_0_2_1920_U0 898
Add Instance xFFindStereoCorrespondenceLBMNO_Block_Mat_exit7_i10_proc xFFindStereoCorrespondenceLBMNO_Block_Mat_exit7_i10_proc_U0 905
Add Instance xFFindStereoCorrespondenceLBMNO_Loop_1_proc xFFindStereoCorrespondenceLBMNO_Loop_1_proc_U0 916
Add Instance write_r call_ln800_write_r_fu_101 101
Add Instance xFFindStereoCorrespondenceLBMNO_entry345 xFFindStereoCorrespondenceLBMNO_entry345_U0 924
Add Instance InitUndistortRectifyMapInverse_9_5_4_1080_1920_1_259 InitUndistortRectifyMapInverse_9_5_4_1080_1920_1_259_U0 1239
Add Instance xFInitUndistortRectifyMapInverseKernel grp_xFInitUndistortRectifyMapInverseKernel_fu_64 64
Add Instance xFComputeUndistortCoordinates grp_xFComputeUndistortCoordinates_fu_402 402
Add Instance InitUndistortRectifyMapInverse_9_5_4_1080_1920_1_s InitUndistortRectifyMapInverse_9_5_4_1080_1920_1_U0 1250
Add Instance xFInitUndistortRectifyMapInverseKernel grp_xFInitUndistortRectifyMapInverseKernel_fu_64 64
Add Instance xFComputeUndistortCoordinates grp_xFComputeUndistortCoordinates_fu_402 402
Add Instance remap_128_1_0_4_0_1080_1920_1_false_260 remap_128_1_0_4_0_1080_1920_1_false_260_U0 1261
Add Instance xFRemapLI_0_0_1_4_128_1080_1920_1_false_262 xFRemapLI_0_0_1_4_128_1080_1920_1_false_262_U0 102
Add Instance remap_128_1_0_4_0_1080_1920_1_false_Block_proc261 remap_128_1_0_4_0_1080_1920_1_false_Block_proc261_U0 116
Add Instance remap_128_1_0_4_0_1080_1920_1_false_s remap_128_1_0_4_0_1080_1920_1_false_U0 1271
Add Instance xFRemapLI_0_0_1_4_128_1080_1920_1_false_s xFRemapLI_0_0_1_4_128_1080_1920_1_false_U0 102
Add Instance remap_128_1_0_4_0_1080_1920_1_false_Block_proc remap_128_1_0_4_0_1080_1920_1_false_Block_proc_U0 116
Add Instance Loop_1_proc Loop_1_proc_U0 1281
Add Instance xfMat2Array_32_1_1080_1920_1_s xfMat2Array_32_1_1080_1920_1_U0 1295
Add Instance xfMat2Array_32_1_1080_1920_1_1 grp_xfMat2Array_32_1_1080_1920_1_1_fu_100 100
Add Instance xfMat2hlsStrm_32_1_1080_1920_1_2073600_33 xfMat2hlsStrm_32_1_1080_1920_1_2073600_33_U0 156
Add Instance hlsStrm2Array_32_1080_1920_1_1_16_1036800_s hlsStrm2Array_32_1080_1920_1_1_16_1036800_U0 172
Add Instance Array2xfMat_32_0_1080_1920_1_258 Array2xfMat_32_0_1080_1920_1_258_U0 1305
Add Instance Array2xfMat_32_0_1080_1920_1_s grp_Array2xfMat_32_0_1080_1920_1_s_fu_142 142
Add Instance hlsStrm2xfMat_32_0_1080_1920_1_2073600_s hlsStrm2xfMat_32_0_1080_1920_1_2073600_U0 136
Add Instance Array2hlsStrm_32_1080_1920_1_1_8_518400_s Array2hlsStrm_32_1080_1920_1_1_8_518400_U0 145
Add Instance Array2xfMat_32_0_1080_1920_1_1 Array2xfMat_32_0_1080_1920_1_1_U0 1317
Add Instance Array2xfMat_32_0_1080_1920_1_s grp_Array2xfMat_32_0_1080_1920_1_s_fu_142 142
Add Instance hlsStrm2xfMat_32_0_1080_1920_1_2073600_s hlsStrm2xfMat_32_0_1080_1920_1_2073600_U0 136
Add Instance Array2hlsStrm_32_1080_1920_1_1_8_518400_s Array2hlsStrm_32_1080_1920_1_1_8_518400_U0 145
Add Instance Loop_2_proc Loop_2_proc_U0 1329
Add Instance Block_Mat_exit172_proc Block_Mat_exit172_proc_U0 1339
Add Instance stereopipeline_accel_entry62 stereopipeline_accel_entry62_U0 1362
Add Instance stereopipeline_accel_entry784 stereopipeline_accel_entry784_U0 1402
INFO: [v++ 60-586] Created /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/xo_ultra96v2_min2_hw/stereopipeline_accel.xo
INFO: [v++ 60-791] Total elapsed time: 0h 4m 10s
-e ----
Compiling xclbin...
mkdir -p /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/xclbin_ultra96v2_min2_hw
v++ -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/xclbin_ultra96v2_min2_hw/krnl_stereopipeline.xclbin --link /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/xo_ultra96v2_min2_hw/stereopipeline_accel.xo \
 -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/include -I. -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include -D__SDSVHLS__ -DHLS_NO_XIL_FPO_LIB --clock.defaultFreqHz 300000000 -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline --target hw --platform /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm --temp_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw --save-temps --debug --kernel_frequency 300  --report_level 2 --optimize 2 --jobs 8 --xp "vivado_param:project.writeIntermediateCheckpoints=1" \
 --xp vivado_prop:run.impl_1.strategy=Performance_Explore  \
 
WARNING: [v++ 60-1600] The option 'xp' was used directly on the command line, where its usage is deprecated. To ensure input line works for supported operating systems or shells, v++ supports specification for some options in a configuration file. As an alternative, please use options 'advanced.*', 'vivado.*' in a configuration file. Use one or more configuration files along with section headers to define key-value pairs for the advanced properties or parameters. Specify a configuration file using '--config'.
INFO: [v++ 82-185] Check out the auto-generated 'sample_link.ini' configuration file. The file shows how to migrate from deprecated command line --xp switches to configuration file directives.
Option Map File Used: '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/data/vitis/vpp/optMap.xml'

****** v++ v2019.2 (64-bit)
  **** SW Build 2700185 on Thu Oct 24 18:45:48 MDT 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

INFO: [v++ 60-1306] Additional information associated with this v++ link can be found at:
 Reports: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/reports/link
 Log files: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/logs/link
Running Dispatch Server on port:40645
INFO: [v++ 60-1548] Creating build summary session with primary output /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/xclbin_ultra96v2_min2_hw/krnl_stereopipeline.xclbin.link_summary, at Thu Apr  2 20:09:53 2020
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Thu Apr  2 20:09:53 2020
Running Rule Check Server on port:43933
INFO: [v++ 60-1315] Creating rulecheck session with output '/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/reports/link/v++_link_krnl_stereopipeline_guidance.html', at Thu Apr  2 20:09:54 2020
INFO: [v++ 60-895]   Target platform: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm
INFO: [v++ 60-1578]   This platform contains Xilinx Shell Archive '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/hw/ultra96v2_min2.xsa'
INFO: [v++ 60-629] Linking for hardware target
INFO: [v++ 60-423]   Target device: ultra96v2_min2
INFO: [v++ 60-1332] Run 'run_link' status: Not started
INFO: [v++ 60-1443] [20:09:54] Run run_link: Step system_link: Started
INFO: [v++ 60-1453] Command Line: system_link --xo /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/xo_ultra96v2_min2_hw/stereopipeline_accel.xo -keep --config /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/syslinkConfig.ini --xpfm /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm --target hw --output_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int --temp_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/sys_link
INFO: [v++ 60-1454] Run Directory: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/run_link
INFO: [SYSTEM_LINK 82-76] Reading emulation BD and HPFM information
INFO: [SYSTEM_LINK 60-1316] Initiating connection to rulecheck server, at Thu Apr  2 20:09:55 2020
INFO: [SYSTEM_LINK 82-70] Extracting xo v3 file /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/xo_ultra96v2_min2_hw/stereopipeline_accel.xo
INFO: [KernelCheck 83-118] 'stereopipeline_accel' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'img_L' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'img_R' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'img_disp' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'cameraMA_l' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'cameraMA_r' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'distC_l' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'distC_r' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'irA_l' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'irA_r' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'bm_state_arr' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'rows' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'cols' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [SYSTEM_LINK 82-53] Creating IP database /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/sys_link/_sysl/.cdb/xd_ip_db.xml
INFO: [SYSTEM_LINK 82-38] [20:09:56] build_xd_ip_db started: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/bin/build_xd_ip_db -ip_search 0  -sds-pf /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/sys_link/ultra96v2_min2.hpfm -clkid 0 -ip /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/sys_link/iprepo/xilinx_com_hls_stereopipeline_accel_1_0,stereopipeline_accel -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/sys_link/_sysl/.cdb/xd_ip_db.xml
INFO: [SYSTEM_LINK 82-37] [20:09:59] build_xd_ip_db finished successfully
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 296.441 ; gain = 0.000 ; free physical = 11706 ; free virtual = 38418
INFO: [SYSTEM_LINK 82-51] Create system connectivity graph
INFO: [SYSTEM_LINK 82-102] Applying explicit connections to the system connectivity graph: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/sys_link/cfgraph/cfgen_cfgraph.xml
INFO: [SYSTEM_LINK 82-38] [20:09:59] cfgen started: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/bin/cfgen  -clock.defaultFreqHz 300000000 -dmclkid 0 -r /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/sys_link/cfgraph/cfgen_cfgraph.xml
INFO: [CFGEN 83-0] Kernel Specs: 
INFO: [CFGEN 83-0]   kernel: stereopipeline_accel, num: 1  {stereopipeline_accel_1}
INFO: [CFGEN 83-2226] Inferring mapping for argument stereopipeline_accel_1.img_L to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument stereopipeline_accel_1.img_R to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument stereopipeline_accel_1.img_disp to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument stereopipeline_accel_1.cameraMA_l to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument stereopipeline_accel_1.cameraMA_r to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument stereopipeline_accel_1.irA_l to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument stereopipeline_accel_1.irA_r to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument stereopipeline_accel_1.distC_l to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument stereopipeline_accel_1.distC_r to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument stereopipeline_accel_1.bm_state_arr to HP
INFO: [SYSTEM_LINK 82-37] [20:09:59] cfgen finished successfully
Time (s): cpu = 00:00:00.29 ; elapsed = 00:00:00.32 . Memory (MB): peak = 296.441 ; gain = 0.000 ; free physical = 11708 ; free virtual = 38420
INFO: [SYSTEM_LINK 82-52] Create top-level block diagram
INFO: [SYSTEM_LINK 82-38] [20:09:59] cf2bd started: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/bin/cf2bd  --linux --trace_buffer 1024 --input_file /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/sys_link/cfgraph/cfgen_cfgraph.xml --ip_db /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/sys_link/_sysl/.cdb/xd_ip_db.xml --cf_name dr --working_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/sys_link/_sysl/.xsd --temp_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/sys_link --output_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int
INFO: [CF2BD 82-31] Launching cf2xd: cf2xd -linux -trace-buffer 1024 -i /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/sys_link/cfgraph/cfgen_cfgraph.xml -r /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o dr.xml
INFO: [CF2BD 82-28] cf2xd finished successfully
INFO: [CF2BD 82-31] Launching cf_xsd: cf_xsd -disable-address-gen -dn dr -dp /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/sys_link/_sysl/.xsd
                                                                                
rlwrap: warning: your $TERM is 'xterm-256color' but rlwrap couldn't find it in the terminfo database. Expect some problems.: Inappropriate ioctl for device
INFO: [CF2BD 82-28] cf_xsd finished successfully
INFO: [SYSTEM_LINK 82-37] [20:10:01] cf2bd finished successfully
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 296.441 ; gain = 0.000 ; free physical = 11704 ; free virtual = 38420
INFO: [v++ 60-1441] [20:10:01] Run run_link: Step system_link: Completed
Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 679.691 ; gain = 0.000 ; free physical = 11726 ; free virtual = 38442
INFO: [v++ 60-1443] [20:10:01] Run run_link: Step cf2sw: Started
INFO: [v++ 60-1453] Command Line: cf2sw -sdsl /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/sdsl.dat -rtd /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/cf2sw.rtd -xclbin /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/xclbin_orig.xml -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/xclbin_orig.1.xml
INFO: [v++ 60-1454] Run Directory: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/run_link
INFO: [v++ 60-1441] [20:10:02] Run run_link: Step cf2sw: Completed
Time (s): cpu = 00:00:00.59 ; elapsed = 00:00:00.67 . Memory (MB): peak = 679.691 ; gain = 0.000 ; free physical = 11728 ; free virtual = 38444
INFO: [v++ 60-1443] [20:10:02] Run run_link: Step rtd2_system_diagram: Started
INFO: [v++ 60-1453] Command Line: rtd2SystemDiagram --rtdJsonFileName /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/cf2sw.rtd --diagramJsonFileName /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/systemDiagramModel.json --platformFilePath /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm --generatedByName v++ --generatedByVersion 2019.2 --generatedByChangeList 2700185 --generatedByTimeStamp Thu Oct 24 18:45:48 MDT 2019 --generatedByOptions /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/bin/unwrapped/lnx64.o/v++ -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/xclbin_ultra96v2_min2_hw/krnl_stereopipeline.xclbin --link /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/xo_ultra96v2_min2_hw/stereopipeline_accel.xo -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/include -I. -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include -D__SDSVHLS__ -DHLS_NO_XIL_FPO_LIB --clock.defaultFreqHz 300000000 -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline --target hw --platform /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm --temp_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw --save-temps --debug --kernel_frequency 300 --report_level 2 --optimize 2 --jobs 8 --xp vivado_param:project.writeIntermediateCheckpoints=1 --xp vivado_prop:run.impl_1.strategy=Performance_Explore  --generatedByXclbinName krnl_stereopipeline --kernelInfoDataFileName /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/kernel_info.dat
INFO: [v++ 60-1454] Run Directory: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/run_link
WARNING: [v++ 82-164] Unable to populate user region instance path.  The platform file does not contain a hardwarePlatform.devices..core.instPath entry.
INFO: [v++ 60-839] Read in kernel information from file '/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/kernel_info.dat'.
WARNING: [v++ 82-157] Unable to populate kernel available resources BRAM entry.
WARNING: [v++ 82-158] Unable to populate kernel available resources DSP entry.
WARNING: [v++ 82-163] Unable to populate user region available resources.  The platform file deos not contain a hardwarePlatform.devices..core.availableResources entry
INFO: [v++ 60-1441] [20:10:04] Run run_link: Step rtd2_system_diagram: Completed
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 679.691 ; gain = 0.000 ; free physical = 11728 ; free virtual = 38444
INFO: [v++ 60-1443] [20:10:04] Run run_link: Step vpl: Started
INFO: [v++ 60-1453] Command Line: vpl -t hw -f /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm -g -j 8 --kernel_frequency 300 -s --output_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int --log_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/logs/link --report_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/reports/link --config /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/vplConfig.ini -k /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/kernel_info.dat --webtalk_flag Vitis --temp_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link --no-info --tlog_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/.tlog/v++_link_krnl_stereopipeline --iprepo /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/xo/ip_repo/xilinx_com_hls_stereopipeline_accel_1_0 --messageDb /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/run_link/vpl.pb /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/dr.bd.tcl
INFO: [v++ 60-1454] Run Directory: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/run_link

****** vpl v2019.2 (64-bit)
  **** SW Build 2700185 on Thu Oct 24 18:45:48 MDT 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

INFO: [VPL 60-839] Read in kernel information from file '/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/kernel_info.dat'.
INFO: [VPL 60-423]   Target device: ultra96v2_min2
INFO: [VPL 60-1032] Extracting hardware platform to /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/vivado/vpl/.local/hw_platform
[20:10:15] Run vpl: Step create_project: Started
Creating Vivado project.
[20:10:24] Run vpl: Step create_project: Completed
[20:10:24] Run vpl: Step create_bd: Started
[20:10:34] Run vpl: Step create_bd: Completed
[20:10:34] Run vpl: Step update_bd: Started
[20:10:35] Run vpl: Step update_bd: Completed
[20:10:35] Run vpl: Step generate_target: Started
[20:11:11] Run vpl: Step generate_target: Completed
[20:11:11] Run vpl: Step config_hw_runs: Started
[20:11:13] Run vpl: Step config_hw_runs: Completed
[20:11:13] Run vpl: Step synth: Started
[20:12:14] Block-level synthesis in progress, 0 of 21 jobs complete, 8 jobs running.
[20:12:44] Block-level synthesis in progress, 0 of 21 jobs complete, 8 jobs running.
[20:13:16] Block-level synthesis in progress, 0 of 21 jobs complete, 8 jobs running.
[20:13:46] Block-level synthesis in progress, 0 of 21 jobs complete, 8 jobs running.
[20:14:16] Block-level synthesis in progress, 0 of 21 jobs complete, 8 jobs running.
[20:14:46] Block-level synthesis in progress, 0 of 21 jobs complete, 8 jobs running.
[20:15:17] Block-level synthesis in progress, 0 of 21 jobs complete, 8 jobs running.
[20:15:47] Block-level synthesis in progress, 1 of 21 jobs complete, 7 jobs running.
[20:16:18] Block-level synthesis in progress, 2 of 21 jobs complete, 6 jobs running.
[20:16:48] Block-level synthesis in progress, 2 of 21 jobs complete, 7 jobs running.
[20:17:18] Block-level synthesis in progress, 3 of 21 jobs complete, 7 jobs running.
[20:17:49] Block-level synthesis in progress, 5 of 21 jobs complete, 6 jobs running.
[20:18:19] Block-level synthesis in progress, 6 of 21 jobs complete, 5 jobs running.
[20:18:49] Block-level synthesis in progress, 7 of 21 jobs complete, 4 jobs running.
[20:19:20] Block-level synthesis in progress, 10 of 21 jobs complete, 4 jobs running.
[20:19:50] Block-level synthesis in progress, 12 of 21 jobs complete, 4 jobs running.
[20:20:21] Block-level synthesis in progress, 13 of 21 jobs complete, 3 jobs running.
[20:20:51] Block-level synthesis in progress, 18 of 21 jobs complete, 3 jobs running.
[20:21:21] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:21:51] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:22:22] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:22:52] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:23:22] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:23:52] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:24:22] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:24:52] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:25:23] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:25:53] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:26:23] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:26:53] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:27:23] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:27:53] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:28:24] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:28:54] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:29:24] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:29:54] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:30:24] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:30:54] Block-level synthesis in progress, 21 of 21 jobs complete, 0 jobs running.
[20:31:25] Top-level synthesis in progress.
[20:31:55] Top-level synthesis in progress.
[20:32:25] Top-level synthesis in progress.
[20:32:45] Run vpl: Step synth: Completed
[20:32:45] Run vpl: Step impl: Started
[20:35:47] Finished 2nd of 6 tasks (FPGA linking synthesized kernels to platform). Elapsed time: 00h 25m 42s 

[20:35:47] Starting logic optimization..
[20:35:47] Phase 1 Retarget
[20:35:47] Phase 2 Constant propagation
[20:35:47] Phase 3 Sweep
[20:36:18] Phase 4 BUFG optimization
[20:36:18] Phase 5 Shift Register Optimization
[20:36:18] Phase 6 Post Processing Netlist
[20:37:48] Finished 3rd of 6 tasks (FPGA logic optimization). Elapsed time: 00h 02m 00s 

[20:37:48] Starting logic placement..
[20:37:48] Phase 1 Placer Initialization
[20:37:48] Phase 1.1 Placer Initialization Netlist Sorting
[20:37:48] Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
[20:38:18] Phase 1.3 Build Placer Netlist Model
[20:38:18] Phase 1.4 Constrain Clocks/Macros
[20:38:18] Phase 2 Global Placement
[20:38:18] Phase 2.1 Floorplanning
[20:39:19] Phase 2.2 Global Placement Core
[20:40:49] Phase 2.2.1 Physical Synthesis In Placer
[20:41:20] Phase 3 Detail Placement
[20:41:20] Phase 3.1 Commit Multi Column Macros
[20:41:20] Phase 3.2 Commit Most Macros & LUTRAMs
[20:41:20] Phase 3.3 Area Swap Optimization
[20:41:20] Phase 3.4 Pipeline Register Optimization
[20:41:20] Phase 3.5 IO Cut Optimizer
[20:41:20] Phase 3.6 Fast Optimization
[20:41:50] Phase 3.7 Small Shape DP
[20:41:50] Phase 3.7.1 Small Shape Clustering
[20:41:50] Phase 3.7.2 Flow Legalize Slice Clusters
[20:41:50] Phase 3.7.3 Slice Area Swap
[20:42:20] Phase 3.7.4 Commit Slice Clusters
[20:42:20] Phase 3.8 Re-assign LUT pins
[20:42:20] Phase 3.9 Pipeline Register Optimization
[20:42:20] Phase 3.10 Fast Optimization
[20:42:50] Phase 4 Post Placement Optimization and Clean-Up
[20:42:50] Phase 4.1 Post Commit Optimization
[20:43:21] Phase 4.1.1 Post Placement Optimization
[20:43:21] Phase 4.1.1.1 BUFG Insertion
[20:44:21] Phase 4.2 Post Placement Cleanup
[20:44:21] Phase 4.3 Placer Reporting
[20:44:21] Phase 4.4 Final Placement Cleanup
[20:45:52] Finished 4th of 6 tasks (FPGA logic placement). Elapsed time: 00h 08m 03s 

[20:45:52] Starting logic routing..
[20:45:52] Phase 1 Build RT Design
[20:46:22] Phase 2 Router Initialization
[20:46:22] Phase 2.1 Create Timer
[20:46:22] Phase 2.2 Fix Topology Constraints
[20:46:22] Phase 2.3 Pre Route Cleanup
[20:46:22] Phase 2.4 Global Clock Net Routing
[20:46:22] Phase 2.5 Update Timing
[20:46:52] Phase 2.6 Update Timing for Bus Skew
[20:46:52] Phase 2.6.1 Update Timing
[20:47:23] Phase 3 Initial Routing
[20:47:53] Phase 4 Rip-up And Reroute
[20:47:53] Phase 4.1 Global Iteration 0
[21:10:05] Phase 4.2 Global Iteration 1
[21:13:06] Phase 4.3 Global Iteration 2
[21:14:37] Phase 4.4 Global Iteration 3
[21:15:07] Phase 5 Delay and Skew Optimization
[21:15:07] Phase 5.1 Delay CleanUp
[21:15:07] Phase 5.1.1 Update Timing
[21:15:37] Phase 5.2 Clock Skew Optimization
[21:15:37] Phase 6 Post Hold Fix
[21:15:37] Phase 6.1 Hold Fix Iter
[21:15:37] Phase 6.1.1 Update Timing
[21:15:37] Phase 7 Route finalize
[21:15:37] Phase 8 Verifying routed nets
[21:15:37] Phase 9 Depositing Routes
[21:15:37] Phase 10 Route finalize
[21:15:37] Phase 11 Post Router Timing
[21:16:08] Finished 5th of 6 tasks (FPGA routing). Elapsed time: 00h 30m 15s 

[21:16:08] Starting bitstream generation..
[21:18:39] Creating bitmap...
[21:18:53] Run vpl: Step impl: Completed
[21:18:53] Writing bitstream ./ultra96v2_min2_wrapper.bit...
[21:18:53] Finished 6th of 6 tasks (FPGA bitstream generation). Elapsed time: 00h 02m 45s 
[21:18:53] Run vpl: FINISHED. Run Status: impl Complete!
INFO: [v++ 60-1441] [21:18:53] Run run_link: Step vpl: Completed
Time (s): cpu = 00:00:27 ; elapsed = 01:08:50 . Memory (MB): peak = 679.691 ; gain = 0.000 ; free physical = 14757 ; free virtual = 39166
INFO: [v++ 60-1443] [21:18:53] Run run_link: Step rtdgen: Started
INFO: [v++ 60-1453] Command Line: rtdgen
INFO: [v++ 60-1454] Run Directory: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/run_link
INFO: [v++ 60-1453] Command Line: cf2sw -a /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/address_map.xml -sdsl /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/sdsl.dat -xclbin /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/xclbin_orig.xml -rtd /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/krnl_stereopipeline.rtd -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/krnl_stereopipeline.xml
INFO: [v++ 60-1618] Launching 
INFO: [v++ 60-1441] [21:18:56] Run run_link: Step rtdgen: Completed
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 679.691 ; gain = 0.000 ; free physical = 14771 ; free virtual = 39180
INFO: [v++ 60-1443] [21:18:56] Run run_link: Step xclbinutil: Started
INFO: [v++ 60-1453] Command Line: xclbinutil --add-section BITSTREAM:RAW:/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/system.bit --force --key-value SYS:mode:flat --add-section :JSON:/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/krnl_stereopipeline.rtd --add-section CLOCK_FREQ_TOPOLOGY:JSON:/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/krnl_stereopipeline_xml.rtd --add-section BUILD_METADATA:JSON:/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/krnl_stereopipeline_build.rtd --add-section EMBEDDED_METADATA:RAW:/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/krnl_stereopipeline.xml --add-section SYSTEM_METADATA:RAW:/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/systemDiagramModelSlrBaseAddress.json --key-value SYS:PlatformVBNV:vendor_Ultra96V2_ultra96v2_min2_1_0 --output /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/krnl_stereopipeline.xclbin
INFO: [v++ 60-1454] Run Directory: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/run_link
XRT Build Version: 2.3.1301
       Build Date: 2019-10-24 20:05:16
          Hash ID: 192e706aea53163a04c574f9b3fe9ed76b6ca471
Creating a default 'in-memory' xclbin image.

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Format : JSON
File   : 'mem_topology'

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Format : JSON
File   : 'ip_layout'

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Format : JSON
File   : 'connectivity'
WARNING: Skipping CLOCK_FREQ_TOPOLOGY section for count size is zero.
WARNING: Section 'CLOCK_FREQ_TOPOLOGY' content is empty.  No data in the given JSON file.

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Successfully wrote (5634244 bytes) to the output file: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/krnl_stereopipeline.xclbin
Leaving xclbinutil.
INFO: [v++ 60-1441] [21:18:56] Run run_link: Step xclbinutil: Completed
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.11 . Memory (MB): peak = 679.691 ; gain = 0.000 ; free physical = 14770 ; free virtual = 39188
INFO: [v++ 60-1443] [21:18:56] Run run_link: Step xclbinutilinfo: Started
INFO: [v++ 60-1453] Command Line: xclbinutil --quiet --info /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/krnl_stereopipeline.xclbin.info --input /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/krnl_stereopipeline.xclbin
INFO: [v++ 60-1454] Run Directory: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/run_link
INFO: [v++ 60-1441] [21:18:56] Run run_link: Step xclbinutilinfo: Completed
Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.06 . Memory (MB): peak = 679.691 ; gain = 0.000 ; free physical = 14790 ; free virtual = 39208
INFO: [v++ 60-244] Generating system estimate report...
INFO: [v++ 60-1092] Generated system estimate report: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/reports/link/system_estimate_krnl_stereopipeline.xtxt
INFO: [v++ 60-907] Packaging to directory: '/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/xclbin_ultra96v2_min2_hw/sd_card'
INFO: [v++ 60-586] Created /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/xclbin_ultra96v2_min2_hw/krnl_stereopipeline.xclbin
INFO: [v++ 60-1307] Run completed. Additional information can be found in:
 Guidance: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/reports/link/v++_link_krnl_stereopipeline_guidance.html
 Timing Report: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/reports/link/imp/ultra96v2_min2_wrapper_timing_summary_routed.rpt
 Vivado Log: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/logs/link/vivado.log
 Steps Log File: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/logs/link/link.steps.log

INFO: [v++ 60-791] Total elapsed time: 1h 9m 5s
masaaki@masaaki-H110M4-M01:/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build$ 

  1. 2020年04月03日 04:32 |
  2. Vitis_Vision
  3. | トラックバック:0
  4. | コメント:0

Vitis_Libraries/vision/L3/examples/cornertracker/をやってみた1

Vitis_Libraries/vision/L3/examples/colordetect/ に続いて、Vitis_Libraries/vision/L3/examples/cornertracker/ をやってみようと思う。

VITIS VISION LIBRARY USER GUIDE では、Corner Tracking Using Optical Flow で説明されているようだ。

Vitis_Libraries/vision/L3/examples/colordetect/ をやったばかりで、環境は設定されている。その環境設定方法を示す。

1. Vitis のインストール・ディレクトリの settings64.sh を実行
source /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/settings64.sh

2. XRT の setenv.sh を実行
source /opt/xilinx/xrt/setup.sh

3. DEVICE 環境変数にプラットフォームの xpfm ファイルへのパスを設定する
export DEVICE=/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm

4. SYSROOT にプラットフォームの sysroot へのパスを設定する。
export SYSROOT=/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux


それでは、Vitis_Libraries/vision/L3/examples/cornertracker/build ディレクトリに cd して、 xclbin を make する
make host xclbin TARGET=hw BOARD=Zynq ARCH=aarch64
を実行した。
Vitis_Vision_70_200402.png
Vitis_Vision_71_200402.png

エラーになってしまった。

[23:03:48] Run vpl: FINISHED. Run Status: impl ERROR
Design (This design requires more LUT as Logic cells than are available in the target device. This design requires 71617 of such cell types but only 70560 compatible sites are available in the target device.


ということで、デザインが FPGA に比べて大きいのが原因のようだ。

Vivado のプロジェクトが Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/vivado/vpl/prj にあるので、Vivado を起動してプロジェクトを読み込んだ。
ブロックデザインを示す。
Vitis_Vision_72_200402.png

Vitis_Libraries/vision/L3/examples/cornertracker/ にあるように 4 つの Vivado HLS で作成された IP が実装されている。

Address Editor の情報を示す。
Vitis_Vision_73_200402.png
Vitis_Vision_74_200402.png

Project Summary を示す。やはりエラーだった。
Vitis_Vision_75_200402.png

Vitis_Vision_76_200402.png

最後に make host xclbin TARGET=hw BOARD=Zynq ARCH=aarch64 のログを示す。

masaaki@masaaki-H110M4-M01:/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build$ make host xclbin TARGET=hw BOARD=Zynq ARCH=aarch64-e ----
Compiling object xf_corner_tracker_tb...
mkdir -p /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/obj_ultra96v2_min2
aarch64-linux-gnu-g++ -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/obj_ultra96v2_min2/xf_corner_tracker_tb.o -c /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp -D XDEVICE=ultra96v2_min2 -DVIVADO_HLS_SIM -D__SDSVHLS__ -DHLS_NO_XIL_FPO_LIB -I. -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2 -g --sysroot=/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux -D__ZYNQ -std=c++14 -fPIC -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker -I/opt/xilinx/xrt/include -Wall -Wno-unknown-pragmas -Wno-unused-label -pthread  -idirafter /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vivado/2019.2/include 
In file included from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include/common/xf_headers.hpp:30,
                 from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:17:
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include/common/xf_sw_utils.hpp: 関数 ‘void xf::cv::analyzeDiff(cv::Mat&, int, float&)’ 内:
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include/common/xf_sw_utils.hpp:150:23: 警告: 変数 ‘v_tmp1’ が設定されましたが使用されていません [-Wunused-but-set-variable]
                 float v_tmp1;
                       ^~~~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp: 関数 ‘int main(int, char**)’ 内:
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:321:118: 警告: ISO C++ says that these are ambiguous, even though the worst conversion for the first is better than the worst conversion for the second:
 ris.rows * inHarris.cols * CH_TYPE), (ap_uint<INPUT_PTR_WIDTH>*)inHarris.data);
                                                                              ^

In file included from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2/xcl2.hpp:48,
                 from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:25:
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:3675:5: 備考: 候補 1: ‘cl::Buffer::Buffer(const cl::Context&, cl_mem_flags, cl::size_type, void*, cl_int*)’
     Buffer(
     ^~~~~~
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:8512:1: 備考: 候補 2: ‘cl::Buffer::Buffer(const cl::Context&, IteratorType, IteratorType, bool, bool, cl_int*) [with IteratorType = int; cl_int = int]’
 Buffer::Buffer(
 ^~~~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:369:89: 警告: ISO C++ says that these are ambiguous, even though the worst conversion for the first is better than the worst conversion for the second:
                                (ap_uint<INPUT_PTR_WIDTH>*)imagepyr1[lvl].data);
                                                                              ^

In file included from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2/xcl2.hpp:48,
                 from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:25:
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:3675:5: 備考: 候補 1: ‘cl::Buffer::Buffer(const cl::Context&, cl_mem_flags, cl::size_type, void*, cl_int*)’
     Buffer(
     ^~~~~~
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:8512:1: 備考: 候補 2: ‘cl::Buffer::Buffer(const cl::Context&, IteratorType, IteratorType, bool, bool, cl_int*) [with IteratorType = int; cl_int = int]’
 Buffer::Buffer(
 ^~~~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:372:96: 警告: ISO C++ says that these are ambiguous, even though the worst conversion for the first is better than the worst conversion for the second:
                           (ap_uint<OUTPUT_PTR_WIDTH>*)imagepyr1[lvl + 1].data);
                                                                              ^

In file included from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2/xcl2.hpp:48,
                 from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:25:
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:3675:5: 備考: 候補 1: ‘cl::Buffer::Buffer(const cl::Context&, cl_mem_flags, cl::size_type, void*, cl_int*)’
     Buffer(
     ^~~~~~
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:8512:1: 備考: 候補 2: ‘cl::Buffer::Buffer(const cl::Context&, IteratorType, IteratorType, bool, bool, cl_int*) [with IteratorType = int; cl_int = int]’
 Buffer::Buffer(
 ^~~~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:375:89: 警告: ISO C++ says that these are ambiguous, even though the worst conversion for the first is better than the worst conversion for the second:
                                (ap_uint<INPUT_PTR_WIDTH>*)imagepyr2[lvl].data);
                                                                              ^

In file included from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2/xcl2.hpp:48,
                 from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:25:
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:3675:5: 備考: 候補 1: ‘cl::Buffer::Buffer(const cl::Context&, cl_mem_flags, cl::size_type, void*, cl_int*)’
     Buffer(
     ^~~~~~
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:8512:1: 備考: 候補 2: ‘cl::Buffer::Buffer(const cl::Context&, IteratorType, IteratorType, bool, bool, cl_int*) [with IteratorType = int; cl_int = int]’
 Buffer::Buffer(
 ^~~~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:378:96: 警告: ISO C++ says that these are ambiguous, even though the worst conversion for the first is better than the worst conversion for the second:
                           (ap_uint<OUTPUT_PTR_WIDTH>*)imagepyr2[lvl + 1].data);
                                                                              ^

In file included from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2/xcl2.hpp:48,
                 from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:25:
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:3675:5: 備考: 候補 1: ‘cl::Buffer::Buffer(const cl::Context&, cl_mem_flags, cl::size_type, void*, cl_int*)’
     Buffer(
     ^~~~~~
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:8512:1: 備考: 候補 2: ‘cl::Buffer::Buffer(const cl::Context&, IteratorType, IteratorType, bool, bool, cl_int*) [with IteratorType = int; cl_int = int]’
 Buffer::Buffer(
 ^~~~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:440:117: 警告: ISO C++ says that these are ambiguous, even though the worst conversion for the first is better than the worst conversion for the second:
 S - 1] * pyr_w[NUM_LEVELS - 1] * 4), (ap_uint<OUTPUT_PTR_WIDTH>*)flow_in.data);
                                                                              ^

In file included from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2/xcl2.hpp:48,
                 from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:25:
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:3675:5: 備考: 候補 1: ‘cl::Buffer::Buffer(const cl::Context&, cl_mem_flags, cl::size_type, void*, cl_int*)’
     Buffer(
     ^~~~~~
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:8512:1: 備考: 候補 2: ‘cl::Buffer::Buffer(const cl::Context&, IteratorType, IteratorType, bool, bool, cl_int*) [with IteratorType = int; cl_int = int]’
 Buffer::Buffer(
 ^~~~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:450:118: 警告: ISO C++ says that these are ambiguous, even though the worst conversion for the first is better than the worst conversion for the second:
 (pyr_h[l] * pyr_w[l] * CH_TYPE), (ap_uint<INPUT_PTR_WIDTH>*)imagepyr1[l].data);
                                                                              ^

In file included from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2/xcl2.hpp:48,
                 from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:25:
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:3675:5: 備考: 候補 1: ‘cl::Buffer::Buffer(const cl::Context&, cl_mem_flags, cl::size_type, void*, cl_int*)’
     Buffer(
     ^~~~~~
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:8512:1: 備考: 候補 2: ‘cl::Buffer::Buffer(const cl::Context&, IteratorType, IteratorType, bool, bool, cl_int*) [with IteratorType = int; cl_int = int]’
 Buffer::Buffer(
 ^~~~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:452:118: 警告: ISO C++ says that these are ambiguous, even though the worst conversion for the first is better than the worst conversion for the second:
 (pyr_h[l] * pyr_w[l] * CH_TYPE), (ap_uint<INPUT_PTR_WIDTH>*)imagepyr2[l].data);
                                                                              ^

In file included from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2/xcl2.hpp:48,
                 from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:25:
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:3675:5: 備考: 候補 1: ‘cl::Buffer::Buffer(const cl::Context&, cl_mem_flags, cl::size_type, void*, cl_int*)’
     Buffer(
     ^~~~~~
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:8512:1: 備考: 候補 2: ‘cl::Buffer::Buffer(const cl::Context&, IteratorType, IteratorType, bool, bool, cl_int*) [with IteratorType = int; cl_int = int]’
 Buffer::Buffer(
 ^~~~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:460:72: 警告: ISO C++ says that these are ambiguous, even though the worst conversion for the first is better than the worst conversion for the second:
                                   (ap_uint<OUTPUT_PTR_WIDTH>*)flow.data);
                                                                        ^
In file included from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2/xcl2.hpp:48,
                 from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:25:
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:3675:5: 備考: 候補 1: ‘cl::Buffer::Buffer(const cl::Context&, cl_mem_flags, cl::size_type, void*, cl_int*)’
     Buffer(
     ^~~~~~
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:8512:1: 備考: 候補 2: ‘cl::Buffer::Buffer(const cl::Context&, IteratorType, IteratorType, bool, bool, cl_int*) [with IteratorType = int; cl_int = int]’
 Buffer::Buffer(
 ^~~~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:473:21: 警告: unused variable ‘next_width’ [-Wunused-variable]
                 int next_width = (scale_up_flag == 1) ? pyr_w[l + 1] : pyr_w[l];
                     ^~~~~~~~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:447:17: 警告: unused variable ‘curr_width’ [-Wunused-variable]
             int curr_width = pyr_w[l];
                 ^~~~~~~~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:527:112: 警告: ISO C++ says that these are ambiguous, even though the worst conversion for the first is better than the worst conversion for the second:
 context, CL_MEM_USE_HOST_PTR | CL_MEM_READ_WRITE, ((MAXCORNERS)*8), listfixed);
                                                                              ^

In file included from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2/xcl2.hpp:48,
                 from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:25:
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:3675:5: 備考: 候補 1: ‘cl::Buffer::Buffer(const cl::Context&, cl_mem_flags, cl::size_type, void*, cl_int*)’
     Buffer(
     ^~~~~~
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:8512:1: 備考: 候補 2: ‘cl::Buffer::Buffer(const cl::Context&, IteratorType, IteratorType, bool, bool, cl_int*) [with IteratorType = int; cl_int = int]’
 Buffer::Buffer(
 ^~~~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:540:25: 警告: 書式 ‘%d’ は対応した ‘int’ 引数が予期されます [-Wformat=]
         fprintf(stderr, "\n flow_rows = %d flow_cols=%d num of corners=%d num_corners=%d harris_flag=%d", flow.rows,
                         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:566:29: 警告: comparison of integer expressions of different signedness: ‘int’ and ‘unsigned int’ [-Wsign-compare]
         for (int li = 0; li < params[0]; li++) {
                          ~~~^~~~~~~~~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:430:14: 警告: unused variable ‘name’ [-Wunused-variable]
         char name[50], name1[50];
              ^~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:430:24: 警告: unused variable ‘name1’ [-Wunused-variable]
         char name[50], name1[50];
                        ^~~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:431:14: 警告: unused variable ‘in_name’ [-Wunused-variable]
         char in_name[50], in_name1[50];
              ^~~~~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:431:27: 警告: unused variable ‘in_name1’ [-Wunused-variable]
         char in_name[50], in_name1[50];
                           ^~~~~~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:257:10: 警告: unused variable ‘list_name’ [-Wunused-variable]
     char list_name[50], list_fix_name[50];
          ^~~~~~~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:257:25: 警告: unused variable ‘list_fix_name’ [-Wunused-variable]
     char list_name[50], list_fix_name[50];
                         ^~~~~~~~~~~~~
In file included from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include/common/xf_common.hpp:20,
                 from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include/common/xf_sw_utils.hpp:20,
                 from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include/common/xf_headers.hpp:30,
                 from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:17:
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include/common/xf_structs.hpp: In instantiation of ‘unsigned char* xf::cv::Mat<T, ROWS, COLS, NPC>::copyFrom() [with int T = 0; int ROWS = 1080; int COLS = 1920; int NPC = 1]’:
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include/common/xf_sw_utils.hpp:50:16:   required from ‘void xf::cv::imwrite(const char*, xf::cv::Mat<T, ROWS, COLS, NPC>&) [with int _PTYPE = 0; int _ROWS = 1080; int _COLS = 1920; int _NPC = 1]’
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:605:60:   required from here
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include/common/xf_structs.hpp:831:9: 警告: unused variable ‘diff_ptr’ [-Wunused-variable]
     int diff_ptr = 0;
         ^~~~~~~~
-e ----
Compiling extra object /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/obj_ultra96v2_min2/xcl2.o...
mkdir -p /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/obj_ultra96v2_min2
aarch64-linux-gnu-g++ -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/obj_ultra96v2_min2/xcl2.o -c /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2/xcl2.cpp -D XDEVICE=ultra96v2_min2 -DVIVADO_HLS_SIM -D__SDSVHLS__ -DHLS_NO_XIL_FPO_LIB -I. -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2 -g --sysroot=/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux -D__ZYNQ -std=c++14 -fPIC -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker -I/opt/xilinx/xrt/include -Wall -Wno-unknown-pragmas -Wno-unused-label -pthread  -idirafter /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vivado/2019.2/include -I /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2
-e ----
Compiling host cornertracker.exe...
mkdir -p /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/bin_ultra96v2_min2
aarch64-linux-gnu-g++ -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/bin_ultra96v2_min2/cornertracker.exe /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/obj_ultra96v2_min2/xf_corner_tracker_tb.o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/obj_ultra96v2_min2/xcl2.o -D XDEVICE=ultra96v2_min2 -DVIVADO_HLS_SIM -D__SDSVHLS__ -DHLS_NO_XIL_FPO_LIB -I. -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2 -g --sysroot=/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux -D__ZYNQ -std=c++14 -fPIC -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker -I/opt/xilinx/xrt/include -Wall -Wno-unknown-pragmas -Wno-unused-label -pthread  -idirafter /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vivado/2019.2/include -L/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/lib -Wl,-rpath-link=/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/lib/ -L/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/opt/xilinx/xrt/lib -lopencv_imgcodecs -lopencv_videoio -lopencv_core -lopencv_imgproc -lopencv_highgui -lopencv_calib3d -lopencv_features2d -lopencv_flann -pthread -L/opt/xilinx/xrt/lib -lxilinxopencl 
-e ----
Compiling kernel pyr_dense_optical_flow_accel...
mkdir -p /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw
v++ -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/pyr_dense_optical_flow_accel.xo --kernel pyr_dense_optical_flow_accel --compile /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_pyr_dense_optical_flow_accel.cpp \
 -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/include -I. -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include -D__SDSVHLS__ -DHLS_NO_XIL_FPO_LIB  --xp vivado_prop:run.impl_1.strategy=Performance_Explore  --clock.defaultFreqHz 300000000  -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker --target hw --platform /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm --temp_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw --save-temps --debug --kernel_frequency 300  --report_level 2 
WARNING: [v++ 60-1600] The option 'xp' was used directly on the command line, where its usage is deprecated. To ensure input line works for supported operating systems or shells, v++ supports specification for some options in a configuration file. As an alternative, please use options 'advanced.*', 'vivado.*' in a configuration file. Use one or more configuration files along with section headers to define key-value pairs for the advanced properties or parameters. Specify a configuration file using '--config'.
INFO: [v++ 82-185] Check out the auto-generated 'sample_compile.ini' configuration file. The file shows how to migrate from deprecated command line --xp switches to configuration file directives.
Option Map File Used: '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/data/vitis/vpp/optMap.xml'

****** v++ v2019.2 (64-bit)
  **** SW Build 2700185 on Thu Oct 24 18:45:48 MDT 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

INFO: [v++ 60-1306] Additional information associated with this v++ compile can be found at:
 Reports: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/reports/pyr_dense_optical_flow_accel
 Log files: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/logs/pyr_dense_optical_flow_accel
Running Dispatch Server on port:35977
INFO: [v++ 60-1548] Creating build summary session with primary output /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/pyr_dense_optical_flow_accel.xo.compile_summary, at Wed Apr  1 22:19:22 2020
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Wed Apr  1 22:19:22 2020
Running Rule Check Server on port:46195
INFO: [v++ 60-1315] Creating rulecheck session with output '/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/reports/pyr_dense_optical_flow_accel/v++_compile_pyr_dense_optical_flow_accel_guidance.html', at Wed Apr  1 22:19:23 2020
INFO: [v++ 60-895]   Target platform: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm
INFO: [v++ 60-1578]   This platform contains Xilinx Shell Archive '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/hw/ultra96v2_min2.xsa'
INFO: [v++ 60-585] Compiling for hardware target
INFO: [v++ 60-423]   Target device: ultra96v2_min2
INFO: [v++ 60-242] Creating kernel: 'pyr_dense_optical_flow_accel'
INFO: [v++ 60-1616] Creating a HLS clock using kernel_frequency option: 300 MHz

===>The following messages were generated while  performing high-level synthesis for kernel: pyr_dense_optical_flow_accel Log file: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/pyr_dense_optical_flow_accel/pyr_dense_optical_flow_accel/vivado_hls.log :
INFO: [v++ 204-61] Option 'relax_ii_for_timing' is enabled, will increase II to preserve clock frequency constraints.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining loop 'L1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 4.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining loop 'L1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 4.
INFO: [v++ 204-61] Pipelining loop 'Loop 1.1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining function 'compute_result<16, 10, 45, 22, 48, 16>'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 11.
INFO: [v++ 204-61] Pipelining loop 'L3'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 2, Depth = 17.
INFO: [v++ 204-61] Pipelining loop 'Loop 1.1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [v++ 204-61] Pipelining loop 'Loop 1.1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [v++ 204-61] Pipelining function 'findIntensity'.
INFO: [v++ 204-61] Discarding stage scheduling solution.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 17.
INFO: [v++ 204-61] Pipelining loop 'L4'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 20.
INFO: [v++ 204-61] Pipelining loop 'Loop 1.1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining loop 'Loop 2.1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 9.
INFO: [v++ 204-61] Pipelining loop 'Loop 1.1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 168.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining loop 'read_lines.1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining loop 'Col_Loop'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 23.
INFO: [v++ 204-61] Pipelining loop 'Loop 1.1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [v++ 204-61] Pipelining loop 'L1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 2, Depth = 4.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 200-789] **** Estimated Fmax: 293.77 MHz
INFO: [v++ 60-594] Finished kernel compilation
INFO: [v++ 60-244] Generating system estimate report...
INFO: [v++ 60-1092] Generated system estimate report: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/reports/pyr_dense_optical_flow_accel/system_estimate_pyr_dense_optical_flow_accel.xtxt
Add Instance densePyrOpticalFlow_5_50_11_16_10_0_1080_1920_1_false_s densePyrOpticalFlow_5_50_11_16_10_0_1080_1920_1_false_U0 726
Add Instance xFLKOpticalFlowDenseKernel grp_xFLKOpticalFlowDenseKernel_fu_220 220
Add Instance find_flow find_flow_U0 1096
Add Instance auMedianBlur_1080_1920_0_0_0_0_5_25_16_10_false_200 auMedianBlur_1080_1920_0_0_0_0_5_25_16_10_false_200_U0 1118
Add Instance auMedian3x3_1080_1920_0_0_0_1922_5_25_16_10_false_s grp_auMedian3x3_1080_1920_0_0_0_1922_5_25_16_10_false_s_fu_136 136
Add Instance auMedianBlur_1080_1920_0_0_0_0_5_25_16_10_false_s auMedianBlur_1080_1920_0_0_0_0_5_25_16_10_false_U0 1129
Add Instance auMedian3x3_1080_1920_0_0_0_1922_5_25_16_10_false_s grp_auMedian3x3_1080_1920_0_0_0_1922_5_25_16_10_false_s_fu_94 94
Add Instance findGradients findGradients_U0 1138
Add Instance findIntensity grp_findIntensity_fu_1707 1707
Add Instance find_G_and_b_matrix find_G_and_b_matrix_U0 1158
Add Instance scale_up199 scale_up199_U0 1174
Add Instance process_r grp_process_r_fu_375 375
Add Instance compute_result_16_10_45_22_48_16_s grp_compute_result_16_10_45_22_48_16_s_fu_488 488
Add Instance load_data_1920_16_10_45_22_17_1_s grp_load_data_1920_16_10_45_22_17_1_s_fu_390 390
Add Instance scale_up scale_up_U0 1188
Add Instance process_r grp_process_r_fu_333 333
Add Instance compute_result_16_10_45_22_48_16_s grp_compute_result_16_10_45_22_48_16_s_fu_488 488
Add Instance load_data_1920_16_10_45_22_17_1_s grp_load_data_1920_16_10_45_22_17_1_s_fu_348 348
Add Instance split_stream_int_fixed_unsigned_short_1080_unsigned_short_1920_16_10_448 split_stream_int_fixed_unsigned_short_1080_unsigned_short_1920_16_10_448_U0 1200
Add Instance stitch_stream_fixed_int_unsigned_short_1080_unsigned_short_1920_16_10_s stitch_stream_fixed_int_unsigned_short_1080_unsigned_short_1920_16_10_U0 1238
Add Instance Array2xfMat_32_3_1080_1920_1_1 Array2xfMat_32_3_1080_1920_1_1_U0 742
Add Instance Array2xfMat_32_3_1080_1920_1_s grp_Array2xfMat_32_3_1080_1920_1_s_fu_100 100
Add Instance hlsStrm2xfMat_32_3_1080_1920_1_2073600_s hlsStrm2xfMat_32_3_1080_1920_1_2073600_U0 136
Add Instance Array2hlsStrm_32_1080_1920_1_1_32_2073600_s Array2hlsStrm_32_1080_1920_1_1_32_2073600_U0 145
Add Instance xfMat2Array_32_3_1080_1920_1_s xfMat2Array_32_3_1080_1920_1_U0 752
Add Instance xfMat2Array_32_3_1080_1920_1_1 grp_xfMat2Array_32_3_1080_1920_1_1_fu_100 100
Add Instance xfMat2hlsStrm_32_3_1080_1920_1_2073600_22 xfMat2hlsStrm_32_3_1080_1920_1_2073600_22_U0 156
Add Instance hlsStrm2Array_32_1080_1920_1_1_32_2073600_s hlsStrm2Array_32_1080_1920_1_1_32_2073600_U0 172
Add Instance Array2xfMat_32_0_1080_1920_1_1 Array2xfMat_32_0_1080_1920_1_1_U0 762
Add Instance Array2xfMat_32_0_1080_1920_1_s grp_Array2xfMat_32_0_1080_1920_1_s_fu_80 80
Add Instance hlsStrm2xfMat_32_0_1080_1920_1_2073600_s hlsStrm2xfMat_32_0_1080_1920_1_2073600_U0 136
Add Instance Array2hlsStrm_32_1080_1920_1_1_8_518400_s Array2hlsStrm_32_1080_1920_1_1_8_518400_U0 145
Add Instance Array2xfMat_32_0_1080_1920_1_201 Array2xfMat_32_0_1080_1920_1_201_U0 772
Add Instance Array2xfMat_32_0_1080_1920_1_s grp_Array2xfMat_32_0_1080_1920_1_s_fu_142 142
Add Instance hlsStrm2xfMat_32_0_1080_1920_1_2073600_s hlsStrm2xfMat_32_0_1080_1920_1_2073600_U0 136
Add Instance Array2hlsStrm_32_1080_1920_1_1_8_518400_s Array2hlsStrm_32_1080_1920_1_1_8_518400_U0 145
Add Instance Block_proc93651 Block_proc93651_U0 784
INFO: [v++ 60-586] Created /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/pyr_dense_optical_flow_accel.xo
INFO: [v++ 60-791] Total elapsed time: 0h 2m 53s
-e ----
Compiling kernel pyr_down_accel...
mkdir -p /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw
v++ -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/pyr_down_accel.xo --kernel pyr_down_accel --compile /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_pyr_down_accel.cpp \
 -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/include -I. -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include -D__SDSVHLS__ -DHLS_NO_XIL_FPO_LIB  --xp vivado_prop:run.impl_1.strategy=Performance_Explore  --clock.defaultFreqHz 300000000  -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker --target hw --platform /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm --temp_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw --save-temps --debug --kernel_frequency 300  --report_level 2 
WARNING: [v++ 60-1600] The option 'xp' was used directly on the command line, where its usage is deprecated. To ensure input line works for supported operating systems or shells, v++ supports specification for some options in a configuration file. As an alternative, please use options 'advanced.*', 'vivado.*' in a configuration file. Use one or more configuration files along with section headers to define key-value pairs for the advanced properties or parameters. Specify a configuration file using '--config'.
INFO: [v++ 84-14] Sample config file already exists. To regenerate, remove file 'sample_compile.ini'.
Option Map File Used: '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/data/vitis/vpp/optMap.xml'

****** v++ v2019.2 (64-bit)
  **** SW Build 2700185 on Thu Oct 24 18:45:48 MDT 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

INFO: [v++ 60-1306] Additional information associated with this v++ compile can be found at:
 Reports: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/reports/pyr_down_accel
 Log files: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/logs/pyr_down_accel
Running Dispatch Server on port:46365
INFO: [v++ 60-1548] Creating build summary session with primary output /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/pyr_down_accel.xo.compile_summary, at Wed Apr  1 22:22:18 2020
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Wed Apr  1 22:22:18 2020
Running Rule Check Server on port:34213
INFO: [v++ 60-1315] Creating rulecheck session with output '/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/reports/pyr_down_accel/v++_compile_pyr_down_accel_guidance.html', at Wed Apr  1 22:22:19 2020
INFO: [v++ 60-895]   Target platform: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm
INFO: [v++ 60-1578]   This platform contains Xilinx Shell Archive '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/hw/ultra96v2_min2.xsa'
INFO: [v++ 60-585] Compiling for hardware target
INFO: [v++ 60-423]   Target device: ultra96v2_min2
INFO: [v++ 60-242] Creating kernel: 'pyr_down_accel'
INFO: [v++ 60-1616] Creating a HLS clock using kernel_frequency option: 300 MHz

===>The following messages were generated while  performing high-level synthesis for kernel: pyr_down_accel Log file: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/pyr_down_accel/pyr_down_accel/vivado_hls.log :
INFO: [v++ 204-61] Option 'relax_ii_for_timing' is enabled, will increase II to preserve clock frequency constraints.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining loop 'L1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 4.
INFO: [v++ 204-61] Pipelining function 'read'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining loop 'read_lines.1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining loop 'Col_Loop'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 9.
INFO: [v++ 204-61] Pipelining function 'write'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [v++ 204-61] Pipelining loop 'L1'.
INFO: [v++ 204-61] Discarding stage scheduling solution.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 2, Depth = 4.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 200-789] **** Estimated Fmax: 411.02 MHz
INFO: [v++ 60-594] Finished kernel compilation
INFO: [v++ 60-244] Generating system estimate report...
INFO: [v++ 60-1092] Generated system estimate report: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/reports/pyr_down_accel/system_estimate_pyr_down_accel.xtxt
Add Instance pyrDown_0_1080_1920_1_false_94 pyrDown_0_1080_1920_1_false_94_U0 604
Add Instance xFpyrDownKernel_1080u_1920u_0u_1u_1_false_s grp_xFpyrDownKernel_1080u_1920u_0u_1u_1_false_s_fu_80 80
Add Instance xFPyrDownGaussianBlur_1080_1920_0_1_1_0_5_25_1_s xFPyrDownGaussianBlur_1080_1920_0_1_1_0_5_25_1_U0 194
Add Instance xf_pyrdown_gaussian_nxn_1080_1920_0_1_1_1922_5_25_1_s grp_xf_pyrdown_gaussian_nxn_1080_1920_0_1_1_1922_5_25_1_s_fu_122 122
Add Instance xFpyrDownKernel_1080u_1920u_0u_1u_1_false_Loop_2_proc97 xFpyrDownKernel_1080u_1920u_0u_1u_1_false_Loop_2_proc97_U0 204
Add Instance write_r call_ln67_write_r_fu_145 145
Add Instance xFpyrDownKernel_1080u_1920u_0u_1u_1_false_Loop_1_proc96 xFpyrDownKernel_1080u_1920u_0u_1u_1_false_Loop_1_proc96_U0 213
Add Instance read_r tmp_V_read_r_fu_142 142
Add Instance pyrDown_0_1080_1920_1_false_s pyrDown_0_1080_1920_1_false_U0 612
Add Instance xFpyrDownKernel_1080u_1920u_0u_1u_1_false_s grp_xFpyrDownKernel_1080u_1920u_0u_1u_1_false_s_fu_80 80
Add Instance xFPyrDownGaussianBlur_1080_1920_0_1_1_0_5_25_1_s xFPyrDownGaussianBlur_1080_1920_0_1_1_0_5_25_1_U0 194
Add Instance xf_pyrdown_gaussian_nxn_1080_1920_0_1_1_1922_5_25_1_s grp_xf_pyrdown_gaussian_nxn_1080_1920_0_1_1_1922_5_25_1_s_fu_122 122
Add Instance xFpyrDownKernel_1080u_1920u_0u_1u_1_false_Loop_2_proc97 xFpyrDownKernel_1080u_1920u_0u_1u_1_false_Loop_2_proc97_U0 204
Add Instance write_r call_ln67_write_r_fu_145 145
Add Instance xFpyrDownKernel_1080u_1920u_0u_1u_1_false_Loop_1_proc96 xFpyrDownKernel_1080u_1920u_0u_1u_1_false_Loop_1_proc96_U0 213
Add Instance read_r tmp_V_read_r_fu_142 142
Add Instance Array2xfMat_32_0_1080_1920_1_93 Array2xfMat_32_0_1080_1920_1_93_U0 620
Add Instance Array2xfMat_32_0_1080_1920_1_s grp_Array2xfMat_32_0_1080_1920_1_s_fu_142 142
Add Instance hlsStrm2xfMat_32_0_1080_1920_1_2073600_s hlsStrm2xfMat_32_0_1080_1920_1_2073600_U0 136
Add Instance Array2hlsStrm_32_1080_1920_1_1_8_518400_s Array2hlsStrm_32_1080_1920_1_1_8_518400_U0 145
Add Instance Array2xfMat_32_0_1080_1920_1_1 Array2xfMat_32_0_1080_1920_1_1_U0 632
Add Instance Array2xfMat_32_0_1080_1920_1_s grp_Array2xfMat_32_0_1080_1920_1_s_fu_142 142
Add Instance hlsStrm2xfMat_32_0_1080_1920_1_2073600_s hlsStrm2xfMat_32_0_1080_1920_1_2073600_U0 136
Add Instance Array2hlsStrm_32_1080_1920_1_1_8_518400_s Array2hlsStrm_32_1080_1920_1_1_8_518400_U0 145
Add Instance xfMat2Array_32_0_1080_1920_1_95 xfMat2Array_32_0_1080_1920_1_95_U0 644
Add Instance xfMat2Array_32_0_1080_1920_1_1 grp_xfMat2Array_32_0_1080_1920_1_1_fu_100 100
Add Instance xfMat2hlsStrm_32_0_1080_1920_1_2073600_13 xfMat2hlsStrm_32_0_1080_1920_1_2073600_13_U0 156
Add Instance hlsStrm2Array_32_1080_1920_1_1_8_518400_s hlsStrm2Array_32_1080_1920_1_1_8_518400_U0 172
Add Instance xfMat2Array_32_0_1080_1920_1_s xfMat2Array_32_0_1080_1920_1_U0 654
Add Instance xfMat2Array_32_0_1080_1920_1_1 grp_xfMat2Array_32_0_1080_1920_1_1_fu_100 100
Add Instance xfMat2hlsStrm_32_0_1080_1920_1_2073600_13 xfMat2hlsStrm_32_0_1080_1920_1_2073600_13_U0 156
Add Instance hlsStrm2Array_32_1080_1920_1_1_8_518400_s hlsStrm2Array_32_1080_1920_1_1_8_518400_U0 172
Add Instance Block_proc40 Block_proc40_U0 664
INFO: [v++ 60-586] Created /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/pyr_down_accel.xo
INFO: [v++ 60-791] Total elapsed time: 0h 1m 6s
-e ----
Compiling kernel cornerupdate_accel...
mkdir -p /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw
v++ -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/cornerupdate_accel.xo --kernel cornerupdate_accel --compile /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_cornerupdate_accel.cpp \
 -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/include -I. -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include -D__SDSVHLS__ -DHLS_NO_XIL_FPO_LIB  --xp vivado_prop:run.impl_1.strategy=Performance_Explore  --clock.defaultFreqHz 300000000  -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker --target hw --platform /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm --temp_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw --save-temps --debug --kernel_frequency 300  --report_level 2 -D__SDA_MEM_MAP__
WARNING: [v++ 60-1600] The option 'xp' was used directly on the command line, where its usage is deprecated. To ensure input line works for supported operating systems or shells, v++ supports specification for some options in a configuration file. As an alternative, please use options 'advanced.*', 'vivado.*' in a configuration file. Use one or more configuration files along with section headers to define key-value pairs for the advanced properties or parameters. Specify a configuration file using '--config'.
INFO: [v++ 84-14] Sample config file already exists. To regenerate, remove file 'sample_compile.ini'.
Option Map File Used: '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/data/vitis/vpp/optMap.xml'

****** v++ v2019.2 (64-bit)
  **** SW Build 2700185 on Thu Oct 24 18:45:48 MDT 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

INFO: [v++ 60-1306] Additional information associated with this v++ compile can be found at:
 Reports: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/reports/cornerupdate_accel
 Log files: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/logs/cornerupdate_accel
Running Dispatch Server on port:33547
INFO: [v++ 60-1548] Creating build summary session with primary output /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/cornerupdate_accel.xo.compile_summary, at Wed Apr  1 22:23:27 2020
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Wed Apr  1 22:23:27 2020
Running Rule Check Server on port:45645
INFO: [v++ 60-1315] Creating rulecheck session with output '/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/reports/cornerupdate_accel/v++_compile_cornerupdate_accel_guidance.html', at Wed Apr  1 22:23:28 2020
INFO: [v++ 60-895]   Target platform: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm
INFO: [v++ 60-1578]   This platform contains Xilinx Shell Archive '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/hw/ultra96v2_min2.xsa'
INFO: [v++ 60-585] Compiling for hardware target
INFO: [v++ 60-423]   Target device: ultra96v2_min2
INFO: [v++ 60-242] Creating kernel: 'cornerupdate_accel'
INFO: [v++ 60-1616] Creating a HLS clock using kernel_frequency option: 300 MHz

===>The following messages were generated while  performing high-level synthesis for kernel: cornerupdate_accel Log file: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/cornerupdate_accel/cornerupdate_accel/vivado_hls.log :
INFO: [v++ 204-61] Option 'relax_ii_for_timing' is enabled, will increase II to preserve clock frequency constraints.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
INFO: [v++ 204-61] Discarding stage scheduling solution.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 33.
INFO: [v++ 200-790] **** Loop Constraint Status: All loop constraints were satisfied.
INFO: [v++ 200-789] **** Estimated Fmax: 347.71 MHz
INFO: [v++ 60-594] Finished kernel compilation
INFO: [v++ 60-244] Generating system estimate report...
INFO: [v++ 60-1092] Generated system estimate report: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/reports/cornerupdate_accel/system_estimate_cornerupdate_accel.xtxt
Add Instance cornerUpdate_10000u_3u_1080u_1920u_1u_s grp_cornerUpdate_10000u_3u_1080u_1920u_1u_s_fu_120 120
INFO: [v++ 60-586] Created /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/cornerupdate_accel.xo
INFO: [v++ 60-791] Total elapsed time: 0h 0m 47s
-e ----
Compiling kernel cornerTracker...
mkdir -p /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw
v++ -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/cornerTracker.xo --kernel cornerTracker --compile /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_accel.cpp \
 -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/include -I. -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include -D__SDSVHLS__ -DHLS_NO_XIL_FPO_LIB  --xp vivado_prop:run.impl_1.strategy=Performance_Explore  --clock.defaultFreqHz 300000000  -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker --target hw --platform /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm --temp_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw --save-temps --debug --kernel_frequency 300  --report_level 2 
WARNING: [v++ 60-1600] The option 'xp' was used directly on the command line, where its usage is deprecated. To ensure input line works for supported operating systems or shells, v++ supports specification for some options in a configuration file. As an alternative, please use options 'advanced.*', 'vivado.*' in a configuration file. Use one or more configuration files along with section headers to define key-value pairs for the advanced properties or parameters. Specify a configuration file using '--config'.
INFO: [v++ 84-14] Sample config file already exists. To regenerate, remove file 'sample_compile.ini'.
Option Map File Used: '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/data/vitis/vpp/optMap.xml'

****** v++ v2019.2 (64-bit)
  **** SW Build 2700185 on Thu Oct 24 18:45:48 MDT 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

INFO: [v++ 60-1306] Additional information associated with this v++ compile can be found at:
 Reports: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/reports/cornerTracker
 Log files: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/logs/cornerTracker
Running Dispatch Server on port:35195
INFO: [v++ 60-1548] Creating build summary session with primary output /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/cornerTracker.xo.compile_summary, at Wed Apr  1 22:24:16 2020
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Wed Apr  1 22:24:16 2020
Running Rule Check Server on port:41237
INFO: [v++ 60-1315] Creating rulecheck session with output '/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/reports/cornerTracker/v++_compile_cornerTracker_guidance.html', at Wed Apr  1 22:24:17 2020
INFO: [v++ 60-895]   Target platform: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm
INFO: [v++ 60-1578]   This platform contains Xilinx Shell Archive '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/hw/ultra96v2_min2.xsa'
INFO: [v++ 60-585] Compiling for hardware target
INFO: [v++ 60-423]   Target device: ultra96v2_min2
INFO: [v++ 60-242] Creating kernel: 'cornerTracker'
INFO: [v++ 60-1616] Creating a HLS clock using kernel_frequency option: 300 MHz

===>The following messages were generated while  performing high-level synthesis for kernel: cornerTracker Log file: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/cornerTracker/cornerTracker/vivado_hls.log :
INFO: [v++ 204-61] Option 'relax_ii_for_timing' is enabled, will increase II to preserve clock frequency constraints.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining loop 'L1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 4.
INFO: [v++ 204-61] Pipelining function 'xFGradientX3x3<0, 3>'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining function 'xFGradientY3x3<0, 3>'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining function 'xFSobel3x3<1, 1, 0, 3>'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining loop 'Clear_Row_Loop'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining loop 'Col_Loop'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 7.
INFO: [v++ 204-61] Pipelining loop 'Col_Loop'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [v++ 204-61] Pipelining loop 'Col_Loop'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [v++ 204-61] Pipelining function 'xfExtractPixels<1, 5, 3>'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining loop 'Col_Loop'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 6.
INFO: [v++ 204-61] Pipelining loop 'Col_Loop'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 6.
INFO: [v++ 204-61] Pipelining loop 'Col_Loop'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 5.
INFO: [v++ 204-61] Pipelining function 'xFApplyMask3x3<3>'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 6.
INFO: [v++ 204-61] Pipelining loop 'bufColLoop'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining loop 'colLoop1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 12.
INFO: [v++ 204-61] Pipelining loop 'Col_Loop'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 12.
INFO: [v++ 204-61] Pipelining loop 'Col_Loop'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining function 'xfExtractPixels<1, 12, 5>'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining function 'xFFindMaxRad1<ap_int<32> >'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining function 'xFSuppressionRad1<1, 5, ap_uint<8> >'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining loop 'Col_Loop'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 7.
INFO: [v++ 204-61] Pipelining loop 'Clear_first_Row'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining loop 'Clear_Row_Loop'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 2, Depth = 9.
INFO: [v++ 204-61] Pipelining loop 'Loop 2'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 8.
INFO: [v++ 200-789] **** Estimated Fmax: 300.03 MHz
INFO: [v++ 60-594] Finished kernel compilation
INFO: [v++ 60-244] Generating system estimate report...
INFO: [v++ 60-1092] Generated system estimate report: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/reports/cornerTracker/system_estimate_cornerTracker.xtxt
Add Instance HarrisImg grp_HarrisImg_fu_168 168
Add Instance cornerHarris_3_3_1_0_1080_1920_1_false_s cornerHarris_3_3_1_0_1080_1920_1_false_U0 172
Add Instance xFCornerHarrisDetector_3_3_0_1080_1920_1_0_1_1_12_1920_5_12_false_s grp_xFCornerHarrisDetector_3_3_0_1080_1920_1_0_1_1_12_1920_5_12_false_s_fu_58 58
Add Instance xFMaxSuppression_5_0_1080_1920_5_0_1_12_1_303 xFMaxSuppression_5_0_1080_1920_5_0_1_12_1_303_U0 398
Add Instance xFMaxSuppressionRad1_5_0_1080_1920_5_0_1_12_1_1920_310 grp_xFMaxSuppressionRad1_5_0_1080_1920_5_0_1_12_1_1920_310_fu_38 38
Add Instance ProcessMax1_5_0_1080_1920_5_0_1_12_1_1920_311 grp_ProcessMax1_5_0_1080_1920_5_0_1_12_1_1920_311_fu_366 366
Add Instance xFSuppressionRad1_1_5_ap_uint_8_s call_ret_xFSuppressionRad1_1_5_ap_uint_8_s_fu_423 423
Add Instance xFFindMaxRad1_ap_int_32_s Max_xFFindMaxRad1_ap_int_32_s_fu_44 44
Add Instance xfExtractPixels_1_12_5_s call_ret3_xfExtractPixels_1_12_5_s_fu_436 436
Add Instance xfExtractPixels_1_12_5_s call_ret2_xfExtractPixels_1_12_5_s_fu_441 441
Add Instance xfExtractPixels_1_12_5_s call_ret4_xfExtractPixels_1_12_5_s_fu_446 446
Add Instance xFFindMaxRad1_ap_int_32_s grp_xFFindMaxRad1_ap_int_32_s_fu_400 400
Add Instance Sobel_0_3_0_2_1080_1920_1_false_302 Sobel_0_3_0_2_1080_1920_1_false_302_U0 407
Add Instance xFSobelFilter3x3_0_2_1080_1920_1_0_3_1_1_5_1920_false_312 grp_xFSobelFilter3x3_0_2_1080_1920_1_0_3_1_1_5_1920_false_312_fu_40 40
Add Instance xFSobel3x3_1_1_0_3_s call_ret_xFSobel3x3_1_1_0_3_s_fu_390 390
Add Instance xFGradientX3x3_0_3_s GradientvaluesX_V_write_assign_xFGradientX3x3_0_3_s_fu_72 72
Add Instance xFGradientY3x3_0_3_s GradientvaluesY_V_write_assign_xFGradientY3x3_0_3_s_fu_88 88
Add Instance xFGradientX3x3_0_3_s GradientValuesX_0_V_xFGradientX3x3_0_3_s_fu_407 407
Add Instance xFGradientY3x3_0_3_s GradientValuesY_0_V_xFGradientY3x3_0_3_s_fu_423 423
Add Instance boxFilter_0_3_2_1080_1920_1_false_208 boxFilter_0_3_2_1080_1920_1_false_208_U0 417
Add Instance xFBoxFilter3x3_2_1080_1920_3_1_5_5_1920_false_s grp_xFBoxFilter3x3_2_1080_1920_3_1_5_5_1920_false_s_fu_38 38
Add Instance xFApplyMask3x3_3_s grp_xFApplyMask3x3_3_s_fu_375 375
Add Instance boxFilter_0_3_2_1080_1920_1_false_209 boxFilter_0_3_2_1080_1920_1_false_209_U0 425
Add Instance xFBoxFilter3x3_2_1080_1920_3_1_5_5_1920_false_s grp_xFBoxFilter3x3_2_1080_1920_3_1_5_5_1920_false_s_fu_38 38
Add Instance xFApplyMask3x3_3_s grp_xFApplyMask3x3_3_s_fu_375 375
Add Instance boxFilter_0_3_2_1080_1920_1_false_s boxFilter_0_3_2_1080_1920_1_false_U0 433
Add Instance xFBoxFilter3x3_2_1080_1920_3_1_5_5_1920_false_s grp_xFBoxFilter3x3_2_1080_1920_3_1_5_5_1920_false_s_fu_38 38
Add Instance xFApplyMask3x3_3_s grp_xFApplyMask3x3_3_s_fu_375 375
Add Instance xFComputeScore_2_5_1080_1920_3_5_1_5_12_1920_s xFComputeScore_2_5_1080_1920_3_5_1_5_12_1920_U0 441
Add Instance xFThreshold_5_1080_1920_5_1_12_1920_s xFThreshold_5_1080_1920_5_1_12_1920_U0 454
Add Instance xFSquare_2_2_1080_1920_3_3_1_5_5_1920_int_207 xFSquare_2_2_1080_1920_3_3_1_5_5_1920_int_207_U0 465
Add Instance xfExtractPixels_1_5_3_s src_buf_0_V_xfExtractPixels_1_5_3_s_fu_137 137
Add Instance xFSquare_2_2_1080_1920_3_3_1_5_5_1920_int_s xFSquare_2_2_1080_1920_3_3_1_5_5_1920_int_U0 475
Add Instance xfExtractPixels_1_5_3_s src_buf_0_V_xfExtractPixels_1_5_3_s_fu_115 115
Add Instance xFMultiply_2_2_1080_1920_3_3_1_5_5_1920_int_s xFMultiply_2_2_1080_1920_3_3_1_5_5_1920_int_U0 483
Add Instance xfExtractPixels_1_5_3_s src_buf1_0_V_xfExtractPixels_1_5_3_s_fu_117 117
Add Instance xfExtractPixels_1_5_3_s src_buf2_0_V_xfExtractPixels_1_5_3_s_fu_123 123
Add Instance xFDuplicate_2_1080_1920_3_1_5_1920_206 xFDuplicate_2_1080_1920_3_1_5_1920_206_U0 492
Add Instance xFDuplicate_2_1080_1920_3_1_5_1920_s xFDuplicate_2_1080_1920_3_1_5_1920_U0 505
Add Instance xFCornerHarrisDetector_entry256 xFCornerHarrisDetector_entry256_U0 516
Add Instance xFCornerHarrisDetector_Block_Mat_exit7715_proc xFCornerHarrisDetector_Block_Mat_exit7715_proc_U0 542
Add Instance Array2xfMat_32_0_1080_1920_1_1 Array2xfMat_32_0_1080_1920_1_1_U0 182
Add Instance Array2xfMat_32_0_1080_1920_1_s grp_Array2xfMat_32_0_1080_1920_1_s_fu_76 76
Add Instance hlsStrm2xfMat_32_0_1080_1920_1_2073600_s hlsStrm2xfMat_32_0_1080_1920_1_2073600_U0 82
Add Instance Array2hlsStrm_32_1080_1920_1_1_8_518400_s Array2hlsStrm_32_1080_1920_1_1_8_518400_U0 91
Add Instance cornersImgToList_10000u_0u_1080u_1920u_1u_s cornersImgToList_10000u_0u_1080u_1920u_1u_U0 194
Add Instance HarrisImg_Block_Mat_exit72_proc27127 HarrisImg_Block_Mat_exit72_proc27127_U0 206
INFO: [v++ 60-586] Created /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/cornerTracker.xo
INFO: [v++ 60-791] Total elapsed time: 0h 1m 36s
-e ----
Compiling xclbin...
mkdir -p /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xclbin_ultra96v2_min2_hw
v++ -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xclbin_ultra96v2_min2_hw/krnl_cornertracker.xclbin --link /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/pyr_dense_optical_flow_accel.xo /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/pyr_down_accel.xo /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/cornerupdate_accel.xo /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/cornerTracker.xo \
 -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/include -I. -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include -D__SDSVHLS__ -DHLS_NO_XIL_FPO_LIB  --xp vivado_prop:run.impl_1.strategy=Performance_Explore  --clock.defaultFreqHz 300000000  -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker --target hw --platform /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm --temp_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw --save-temps --debug --kernel_frequency 300  --report_level 2 --optimize 2 --jobs 8 --xp "vivado_param:project.writeIntermediateCheckpoints=1" \
   -D__SDA_MEM_MAP__  \
    
WARNING: [v++ 60-1600] The option 'xp' was used directly on the command line, where its usage is deprecated. To ensure input line works for supported operating systems or shells, v++ supports specification for some options in a configuration file. As an alternative, please use options 'advanced.*', 'vivado.*' in a configuration file. Use one or more configuration files along with section headers to define key-value pairs for the advanced properties or parameters. Specify a configuration file using '--config'.
INFO: [v++ 82-185] Check out the auto-generated 'sample_link.ini' configuration file. The file shows how to migrate from deprecated command line --xp switches to configuration file directives.
Option Map File Used: '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/data/vitis/vpp/optMap.xml'

****** v++ v2019.2 (64-bit)
  **** SW Build 2700185 on Thu Oct 24 18:45:48 MDT 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

INFO: [v++ 60-1306] Additional information associated with this v++ link can be found at:
 Reports: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/reports/link
 Log files: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/logs/link
Running Dispatch Server on port:42571
INFO: [v++ 60-1548] Creating build summary session with primary output /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xclbin_ultra96v2_min2_hw/krnl_cornertracker.xclbin.link_summary, at Wed Apr  1 22:25:54 2020
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Wed Apr  1 22:25:54 2020
Running Rule Check Server on port:40987
INFO: [v++ 60-1315] Creating rulecheck session with output '/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/reports/link/v++_link_krnl_cornertracker_guidance.html', at Wed Apr  1 22:25:55 2020
INFO: [v++ 60-895]   Target platform: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm
INFO: [v++ 60-1578]   This platform contains Xilinx Shell Archive '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/hw/ultra96v2_min2.xsa'
INFO: [v++ 60-629] Linking for hardware target
INFO: [v++ 60-423]   Target device: ultra96v2_min2
INFO: [v++ 60-1332] Run 'run_link' status: Not started
INFO: [v++ 60-1443] [22:25:56] Run run_link: Step system_link: Started
INFO: [v++ 60-1453] Command Line: system_link --xo /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/pyr_dense_optical_flow_accel.xo --xo /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/pyr_down_accel.xo --xo /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/cornerupdate_accel.xo --xo /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/cornerTracker.xo -keep --config /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/int/syslinkConfig.ini --xpfm /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm --target hw --output_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/int --temp_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/sys_link
INFO: [v++ 60-1454] Run Directory: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/run_link
INFO: [SYSTEM_LINK 82-76] Reading emulation BD and HPFM information
INFO: [SYSTEM_LINK 60-1316] Initiating connection to rulecheck server, at Wed Apr  1 22:25:57 2020
INFO: [SYSTEM_LINK 82-70] Extracting xo v3 file /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/pyr_dense_optical_flow_accel.xo
INFO: [KernelCheck 83-118] 'pyr_dense_optical_flow_accel' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] '_current_img' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] '_next_image' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] '_streamFlowin' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] '_streamFlowout' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'level' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'scale_up_flag' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'scale_in' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'init_flag' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'cur_img_rows' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'cur_img_cols' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'next_img_rows' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'next_img_cols' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'flow_rows' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'flow_cols' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'flow_iter_rows' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'flow_iter_cols' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [SYSTEM_LINK 82-70] Extracting xo v3 file /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/pyr_down_accel.xo
INFO: [KernelCheck 83-118] 'pyr_down_accel' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'inImgPyr1' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'outImgPyr1' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'inImgPyr2' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'outImgPyr2' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'pyr_h' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'pyr_w' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'pyr_out_h' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'pyr_out_w' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [SYSTEM_LINK 82-70] Extracting xo v3 file /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/cornerupdate_accel.xo
INFO: [KernelCheck 83-118] 'cornerupdate_accel' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'list_fix' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'list' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'nCorners' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'flow_vectors' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'harris_flag' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'flow_rows' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'flow_cols' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [SYSTEM_LINK 82-70] Extracting xo v3 file /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/cornerTracker.xo
INFO: [KernelCheck 83-118] 'cornerTracker' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'inHarris' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'list' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'params' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'harris_rows' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'harris_cols' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [SYSTEM_LINK 82-53] Creating IP database /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/sys_link/_sysl/.cdb/xd_ip_db.xml
INFO: [SYSTEM_LINK 82-38] [22:25:58] build_xd_ip_db started: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/bin/build_xd_ip_db -ip_search 0  -sds-pf /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/sys_link/ultra96v2_min2.hpfm -clkid 0 -ip /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/sys_link/iprepo/xilinx_com_hls_pyr_down_accel_1_0,pyr_down_accel -ip /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/sys_link/iprepo/xilinx_com_hls_cornerTracker_1_0,cornerTracker -ip /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/sys_link/iprepo/xilinx_com_hls_cornerupdate_accel_1_0,cornerupdate_accel -ip /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/sys_link/iprepo/xilinx_com_hls_pyr_dense_optical_flow_accel_1_0,pyr_dense_optical_flow_accel -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/sys_link/_sysl/.cdb/xd_ip_db.xml
INFO: [SYSTEM_LINK 82-37] [22:26:02] build_xd_ip_db finished successfully
Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 296.445 ; gain = 0.000 ; free physical = 8124 ; free virtual = 38651
INFO: [SYSTEM_LINK 82-51] Create system connectivity graph
INFO: [SYSTEM_LINK 82-102] Applying explicit connections to the system connectivity graph: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/sys_link/cfgraph/cfgen_cfgraph.xml
INFO: [SYSTEM_LINK 82-38] [22:26:02] cfgen started: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/bin/cfgen  -clock.defaultFreqHz 300000000 -dmclkid 0 -r /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/sys_link/cfgraph/cfgen_cfgraph.xml
INFO: [CFGEN 83-0] Kernel Specs: 
INFO: [CFGEN 83-0]   kernel: cornerTracker, num: 1  {cornerTracker_1}
INFO: [CFGEN 83-0]   kernel: cornerupdate_accel, num: 1  {cornerupdate_accel_1}
INFO: [CFGEN 83-0]   kernel: pyr_dense_optical_flow_accel, num: 1  {pyr_dense_optical_flow_accel_1}
INFO: [CFGEN 83-0]   kernel: pyr_down_accel, num: 1  {pyr_down_accel_1}
INFO: [CFGEN 83-2226] Inferring mapping for argument cornerTracker_1.inHarris to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument cornerTracker_1.list to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument cornerTracker_1.params to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument cornerupdate_accel_1.list_fix to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument cornerupdate_accel_1.list to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument cornerupdate_accel_1.flow_vectors to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument pyr_dense_optical_flow_accel_1._current_img to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument pyr_dense_optical_flow_accel_1._next_image to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument pyr_dense_optical_flow_accel_1._streamFlowin to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument pyr_dense_optical_flow_accel_1._streamFlowout to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument pyr_down_accel_1.inImgPyr1 to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument pyr_down_accel_1.outImgPyr1 to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument pyr_down_accel_1.inImgPyr2 to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument pyr_down_accel_1.outImgPyr2 to HP
INFO: [SYSTEM_LINK 82-37] [22:26:02] cfgen finished successfully
Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:00.50 . Memory (MB): peak = 296.445 ; gain = 0.000 ; free physical = 8140 ; free virtual = 38667
INFO: [SYSTEM_LINK 82-52] Create top-level block diagram
INFO: [SYSTEM_LINK 82-38] [22:26:02] cf2bd started: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/bin/cf2bd  --linux --trace_buffer 1024 --input_file /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/sys_link/cfgraph/cfgen_cfgraph.xml --ip_db /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/sys_link/_sysl/.cdb/xd_ip_db.xml --cf_name dr --working_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/sys_link/_sysl/.xsd --temp_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/sys_link --output_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/int
INFO: [CF2BD 82-31] Launching cf2xd: cf2xd -linux -trace-buffer 1024 -i /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/sys_link/cfgraph/cfgen_cfgraph.xml -r /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o dr.xml
INFO: [CF2BD 82-28] cf2xd finished successfully
INFO: [CF2BD 82-31] Launching cf_xsd: cf_xsd -disable-address-gen -dn dr -dp /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/sys_link/_sysl/.xsd
                                                                                
rlwrap: warning: your $TERM is 'xterm-256color' but rlwrap couldn't find it in the terminfo database. Expect some problems.: Inappropriate ioctl for device
INFO: [CF2BD 82-28] cf_xsd finished successfully
INFO: [SYSTEM_LINK 82-37] [22:26:05] cf2bd finished successfully
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 296.445 ; gain = 0.000 ; free physical = 8132 ; free virtual = 38664
INFO: [v++ 60-1441] [22:26:05] Run run_link: Step system_link: Completed
Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 679.699 ; gain = 0.000 ; free physical = 8153 ; free virtual = 38686
INFO: [v++ 60-1443] [22:26:05] Run run_link: Step cf2sw: Started
INFO: [v++ 60-1453] Command Line: cf2sw -sdsl /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/int/sdsl.dat -rtd /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/int/cf2sw.rtd -xclbin /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/int/xclbin_orig.xml -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/int/xclbin_orig.1.xml
INFO: [v++ 60-1454] Run Directory: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/run_link
INFO: [v++ 60-1441] [22:26:06] Run run_link: Step cf2sw: Completed
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 679.699 ; gain = 0.000 ; free physical = 8151 ; free virtual = 38685
INFO: [v++ 60-1443] [22:26:06] Run run_link: Step rtd2_system_diagram: Started
INFO: [v++ 60-1453] Command Line: rtd2SystemDiagram --rtdJsonFileName /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/int/cf2sw.rtd --diagramJsonFileName /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/int/systemDiagramModel.json --platformFilePath /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm --generatedByName v++ --generatedByVersion 2019.2 --generatedByChangeList 2700185 --generatedByTimeStamp Thu Oct 24 18:45:48 MDT 2019 --generatedByOptions /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/bin/unwrapped/lnx64.o/v++ -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xclbin_ultra96v2_min2_hw/krnl_cornertracker.xclbin --link /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/pyr_dense_optical_flow_accel.xo /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/pyr_down_accel.xo /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/cornerupdate_accel.xo /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/cornerTracker.xo -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/include -I. -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include -D__SDSVHLS__ -DHLS_NO_XIL_FPO_LIB --xp vivado_prop:run.impl_1.strategy=Performance_Explore --clock.defaultFreqHz 300000000 -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker --target hw --platform /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm --temp_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw --save-temps --debug --kernel_frequency 300 --report_level 2 --optimize 2 --jobs 8 --xp vivado_param:project.writeIntermediateCheckpoints=1 -D__SDA_MEM_MAP__  --generatedByXclbinName krnl_cornertracker --kernelInfoDataFileName /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/int/kernel_info.dat
INFO: [v++ 60-1454] Run Directory: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/run_link
WARNING: [v++ 82-164] Unable to populate user region instance path.  The platform file does not contain a hardwarePlatform.devices..core.instPath entry.
INFO: [v++ 60-839] Read in kernel information from file '/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/int/kernel_info.dat'.
WARNING: [v++ 82-157] Unable to populate kernel available resources BRAM entry.
WARNING: [v++ 82-158] Unable to populate kernel available resources DSP entry.
WARNING: [v++ 82-157] Unable to populate kernel available resources BRAM entry.
WARNING: [v++ 82-158] Unable to populate kernel available resources DSP entry.
WARNING: [v++ 82-157] Unable to populate kernel available resources BRAM entry.
WARNING: [v++ 82-158] Unable to populate kernel available resources DSP entry.
WARNING: [v++ 82-163] Unable to populate user region available resources.  The platform file deos not contain a hardwarePlatform.devices..core.availableResources entry
INFO: [v++ 60-1441] [22:26:08] Run run_link: Step rtd2_system_diagram: Completed
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 679.699 ; gain = 0.000 ; free physical = 8152 ; free virtual = 38684
INFO: [v++ 60-1443] [22:26:08] Run run_link: Step vpl: Started
INFO: [v++ 60-1453] Command Line: vpl -t hw -f /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm -g -j 8 --kernel_frequency 300 -s --output_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/int --log_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/logs/link --report_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/reports/link --config /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/int/vplConfig.ini -k /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/int/kernel_info.dat --webtalk_flag Vitis --temp_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link --no-info --tlog_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/.tlog/v++_link_krnl_cornertracker --iprepo /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/int/xo/ip_repo/xilinx_com_hls_cornerupdate_accel_1_0 --iprepo /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/int/xo/ip_repo/xilinx_com_hls_pyr_down_accel_1_0 --iprepo /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/int/xo/ip_repo/xilinx_com_hls_cornerTracker_1_0 --iprepo /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/int/xo/ip_repo/xilinx_com_hls_pyr_dense_optical_flow_accel_1_0 --messageDb /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/run_link/vpl.pb /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/int/dr.bd.tcl
INFO: [v++ 60-1454] Run Directory: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/run_link

****** vpl v2019.2 (64-bit)
  **** SW Build 2700185 on Thu Oct 24 18:45:48 MDT 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

INFO: [VPL 60-839] Read in kernel information from file '/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/int/kernel_info.dat'.
INFO: [VPL 60-423]   Target device: ultra96v2_min2
INFO: [VPL 60-1032] Extracting hardware platform to /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/vivado/vpl/.local/hw_platform
[22:26:19] Run vpl: Step create_project: Started
Creating Vivado project.
[22:26:28] Run vpl: Step create_project: Completed
[22:26:28] Run vpl: Step create_bd: Started
[22:26:41] Run vpl: Step create_bd: Completed
[22:26:41] Run vpl: Step update_bd: Started
[22:26:43] Run vpl: Step update_bd: Completed
[22:26:43] Run vpl: Step generate_target: Started
[22:27:30] Run vpl: Step generate_target: Completed
[22:27:30] Run vpl: Step config_hw_runs: Started
[22:27:34] Run vpl: Step config_hw_runs: Completed
[22:27:34] Run vpl: Step synth: Started
[22:28:36] Block-level synthesis in progress, 0 of 49 jobs complete, 8 jobs running.
[22:29:06] Block-level synthesis in progress, 0 of 49 jobs complete, 8 jobs running.
[22:29:38] Block-level synthesis in progress, 0 of 49 jobs complete, 8 jobs running.
[22:30:08] Block-level synthesis in progress, 0 of 49 jobs complete, 8 jobs running.
[22:30:38] Block-level synthesis in progress, 0 of 49 jobs complete, 8 jobs running.
[22:31:09] Block-level synthesis in progress, 0 of 49 jobs complete, 8 jobs running.
[22:31:39] Block-level synthesis in progress, 0 of 49 jobs complete, 8 jobs running.
[22:32:10] Block-level synthesis in progress, 3 of 49 jobs complete, 5 jobs running.
[22:32:40] Block-level synthesis in progress, 3 of 49 jobs complete, 5 jobs running.
[22:33:10] Block-level synthesis in progress, 8 of 49 jobs complete, 3 jobs running.
[22:33:41] Block-level synthesis in progress, 9 of 49 jobs complete, 5 jobs running.
[22:34:11] Block-level synthesis in progress, 11 of 49 jobs complete, 5 jobs running.
[22:34:41] Block-level synthesis in progress, 12 of 49 jobs complete, 7 jobs running.
[22:35:12] Block-level synthesis in progress, 12 of 49 jobs complete, 8 jobs running.
[22:35:42] Block-level synthesis in progress, 12 of 49 jobs complete, 8 jobs running.
[22:36:13] Block-level synthesis in progress, 12 of 49 jobs complete, 8 jobs running.
[22:36:43] Block-level synthesis in progress, 13 of 49 jobs complete, 7 jobs running.
[22:37:14] Block-level synthesis in progress, 13 of 49 jobs complete, 7 jobs running.
[22:37:44] Block-level synthesis in progress, 14 of 49 jobs complete, 7 jobs running.
[22:38:15] Block-level synthesis in progress, 14 of 49 jobs complete, 7 jobs running.
[22:38:46] Block-level synthesis in progress, 15 of 49 jobs complete, 7 jobs running.
[22:39:16] Block-level synthesis in progress, 17 of 49 jobs complete, 5 jobs running.
[22:39:47] Block-level synthesis in progress, 17 of 49 jobs complete, 6 jobs running.
[22:40:18] Block-level synthesis in progress, 19 of 49 jobs complete, 6 jobs running.
[22:40:49] Block-level synthesis in progress, 19 of 49 jobs complete, 7 jobs running.
[22:41:20] Block-level synthesis in progress, 21 of 49 jobs complete, 6 jobs running.
[22:41:51] Block-level synthesis in progress, 22 of 49 jobs complete, 7 jobs running.
[22:42:21] Block-level synthesis in progress, 22 of 49 jobs complete, 7 jobs running.
[22:42:52] Block-level synthesis in progress, 23 of 49 jobs complete, 7 jobs running.
[22:43:23] Block-level synthesis in progress, 24 of 49 jobs complete, 7 jobs running.
[22:43:54] Block-level synthesis in progress, 25 of 49 jobs complete, 6 jobs running.
[22:44:25] Block-level synthesis in progress, 27 of 49 jobs complete, 6 jobs running.
[22:44:56] Block-level synthesis in progress, 27 of 49 jobs complete, 6 jobs running.
[22:45:27] Block-level synthesis in progress, 29 of 49 jobs complete, 6 jobs running.
[22:45:58] Block-level synthesis in progress, 33 of 49 jobs complete, 4 jobs running.
[22:46:29] Block-level synthesis in progress, 34 of 49 jobs complete, 3 jobs running.
[22:47:00] Block-level synthesis in progress, 39 of 49 jobs complete, 3 jobs running.
[22:47:31] Block-level synthesis in progress, 40 of 49 jobs complete, 2 jobs running.
[22:48:01] Block-level synthesis in progress, 46 of 49 jobs complete, 2 jobs running.
[22:48:32] Block-level synthesis in progress, 48 of 49 jobs complete, 1 job running.
[22:49:02] Block-level synthesis in progress, 48 of 49 jobs complete, 1 job running.
[22:49:32] Block-level synthesis in progress, 48 of 49 jobs complete, 1 job running.
[22:50:03] Block-level synthesis in progress, 48 of 49 jobs complete, 1 job running.
[22:50:33] Block-level synthesis in progress, 48 of 49 jobs complete, 1 job running.
[22:51:03] Block-level synthesis in progress, 48 of 49 jobs complete, 1 job running.
[22:51:34] Block-level synthesis in progress, 48 of 49 jobs complete, 1 job running.
[22:52:04] Block-level synthesis in progress, 48 of 49 jobs complete, 1 job running.
[22:52:34] Block-level synthesis in progress, 48 of 49 jobs complete, 1 job running.
[22:53:05] Block-level synthesis in progress, 48 of 49 jobs complete, 1 job running.
[22:53:35] Block-level synthesis in progress, 48 of 49 jobs complete, 1 job running.
[22:54:05] Block-level synthesis in progress, 48 of 49 jobs complete, 1 job running.
[22:54:36] Block-level synthesis in progress, 48 of 49 jobs complete, 1 job running.
[22:55:06] Block-level synthesis in progress, 48 of 49 jobs complete, 1 job running.
[22:55:37] Block-level synthesis in progress, 48 of 49 jobs complete, 1 job running.
[22:56:07] Block-level synthesis in progress, 49 of 49 jobs complete, 0 jobs running.
[22:56:37] Top-level synthesis in progress.
[22:57:08] Top-level synthesis in progress.
[22:57:38] Top-level synthesis in progress.
[22:58:08] Run vpl: Step synth: Completed
[22:58:08] Run vpl: Step impl: Started
[23:01:10] Finished 2nd of 6 tasks (FPGA linking synthesized kernels to platform). Elapsed time: 00h 35m 00s 

[23:01:10] Starting logic optimization..
[23:01:40] Phase 1 Retarget
[23:01:40] Phase 2 Constant propagation
[23:01:40] Phase 3 Sweep
[23:01:40] Phase 4 BUFG optimization
[23:01:40] Phase 5 Shift Register Optimization
[23:01:40] Phase 6 Post Processing Netlist
[23:03:48] Run vpl: Step impl: Failed
[23:03:48] Finished 3rd of 6 tasks (FPGA logic optimization). Elapsed time: 00h 02m 37s 

[23:03:48] Starting logic placement..
[23:03:48] Run vpl: FINISHED. Run Status: impl ERROR

===>The following messages were generated while processing /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/vivado/vpl/prj/prj.runs/impl_1 :
ERROR: [VPL UTLZ-1] Resource utilization: LUT as Logic over-utilized in Top Level Design (This design requires more LUT as Logic cells than are available in the target device. This design requires 71617 of such cell types but only 70560 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device. Please set tcl parameter "drc.disableLUTOverUtilError" to 1 to change this error to warning.)
ERROR: [VPL UTLZ-1] Resource utilization: Slice LUTs over-utilized in Top Level Design (This design requires more Slice LUTs cells than are available in the target device. This design requires 79831 of such cell types but only 70560 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device. Please set tcl parameter "drc.disableLUTOverUtilError" to 1 to change this error to warning.)
ERROR: [VPL 4-23] Error(s) found during DRC. Placer not run.
WARNING: [VPL 60-732] Link warning: No monitor points found for BD automation.
ERROR: [VPL 60-704] Integration error, problem implementing dynamic region, place_design ERROR, please look at the run log file '/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/vivado/vpl/prj/prj.runs/impl_1/runme.log' for more information
ERROR: [VPL 60-1328] Vpl run 'vpl' failed
ERROR: [VPL 60-806] Failed to finish platform linker
INFO: [v++ 60-1442] [23:03:49] Run run_link: Step vpl: Failed
Time (s): cpu = 00:00:21 ; elapsed = 00:37:41 . Memory (MB): peak = 679.699 ; gain = 0.000 ; free physical = 10742 ; free virtual = 34903
ERROR: [v++ 60-661] v++ link run 'run_link' failed
ERROR: [v++ 60-626] Kernel link failed to complete
ERROR: [v++ 60-703] Failed to finish linking
Makefile:315: recipe for target '/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xclbin_ultra96v2_min2_hw/krnl_cornertracker.xclbin' failed
make: *** [/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xclbin_ultra96v2_min2_hw/krnl_cornertracker.xclbin] Error 1
masaaki@masaaki-H110M4-M01:/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build$ 


  1. 2020年04月02日 05:09 |
  2. Vitis_Vision
  3. | トラックバック:0
  4. | コメント:0

Vitis_Libraries/vision/L3/examples/colordetect/をやってみた3

Vitis_Libraries/vision/L3/examples/colordetect/をやってみた2”の続き。

Vitis_Libraries/vision/L3/examples/colordetect/をやってみるということで、xclbin をビルドして、sd_card ディレクトリを作成させた。今回は、Vivado HLS プロジェクトと Vivado プロジェクトを確認した。今回は、Ultra96-V2 の実機で動作させてみよう。

Ultra96-V2 の電源をON して、PetaLinux を起動した。

Vitis_Libraries/vision/L3/examples/colordetect/build/xclbin_ultra96v2_min2_hw/sd_card ディレクトリに行って、BOOT.BIN を Ultra96-V2 の /run/media/mmcblk0p1 に SFTP する。
scp BOOT.BIN 192.168.3.23:/run/media/mmcblk0p1
Vitis_Vision_60_200331.png

Ultra96-V2 のターミナルで /home/root にあった resize の sd_card ディレクトリを resize_sd_card に名前を変更した。

Vitis_Libraries/vision/L3/examples/colordetect/build ディレクトリに行って、 sd_card ディレクトリ以下をすべて Ultra96-V2 の /home/root にコピーした。
scp -r sd_card 192.168.3.23:/home/root
Vitis_Vision_61_200331.png

Ultra96-V2 のターミナルでみると、 /home/root ディレクトリの下に、 sd_card ディレクトリがコピーできている。
reboot を行った。
Vitis_Vision_62_200331.png

Ultra96-V2 のPetaLinux 上で zocl ドライバを起動した。
insmod /lib/modules/4.19.0-xilinx-v2019.2/extra/zocl.ko

XRT へのパスを通し、init.sh を実行形式にしてから init.sh を起動する。
export XILINX_XRT=/usr
chmod +x init.sh
./init.sh

Vitis_Vision_63_200331.png

Vitis_Vision_64_200331.png

ログを示す。

root@ultra96v2_min2:~/sd_card# ./init.sh 
INFO: Thresholds loaded.
INFO: Running OpenCL section.
[  148.580915] [drm] Pid 2199 opened device
[  148.584874] [drm] Pid 2199 closed device
[  148.599875] [drm] Pid 2199 opened device
Found Platform
Platform Name: Xilinx
INFO: Device found - edge
XCLBIN File Name: krnl_colordetect
INFO: Importing xclbin_ultra96v2_min2_hw/krnl_colordetect.xclbin
Loading: 'xclbin_ultra96v2_min2_hw/krnl_colordetect.xclbin'
[  148.885583] [drm] Finding IP_LAYOUT section header
[  148.885595] [drm] Section IP_LAYOUT details:
[  148.890421] [drm]   offset = 0x54fcf8
[  148.894690] [drm]   size = 0x58
[  148.898375] [drm] Finding DEBUG_IP_LAYOUT section header
[  148.901505] [drm] AXLF section DEBUG_IP_LAYOUT header not found
[  148.906810] [drm] Finding CONNECTIVITY section header
[  148.912725] [drm] Section CONNECTIVITY details:
[  148.917770] [drm]   offset = 0x54fd50
[  148.922290] [drm]   size = 0x40
[  148.925949] [drm] Finding MEM_TOPOLOGY section header
[  148.929081] [drm] Section MEM_TOPOLOGY details:
[  148.934122] [drm]   offset = 0x54fc00
[  148.938643] [drm]   size = 0xf8
[  148.946261] [drm] No ERT scheduler on MPSoC, using KDS
[  148.954931] [drm] Fail to install CU 0 interrupt handler: -22. Fall back to polling mode.
[  148.963100] [drm] scheduler config ert(0)
[  148.963110] [drm]   cus(1)
[  148.967114] [drm]   slots(16)
[  148.969807] [drm]   num_cu_masks(1)
[  148.972765] [drm]   cu_shift(16)
[  148.976245] [drm]   cu_base(0xa0000000)
INFO: Verification results:
 Percentage of pixels above error thr[  148.979466] [drm]   polling(1)
eshold = 0%
[  149.751149] [drm] zocl_free_userptr_bo: obj 0x00000000ec26f684
[  149.755875] [drm] zocl_free_userptr_bo: obj 0x000000007590285b
[  149.762818] [drm] zocl_free_userptr_bo: obj 0x00000000bd481cc0
[  149.877791] [drm] Pid 2199 closed device
root@ultra96v2_min2:~/sd_card# 


INFO: Verification results:
Percentage of pixels above error threshold = 0%

なので、うまく行ったようだ。

出力された画像ファイル、 diff.png, output.png, outputref.png を SFTP でホスト・パソコンに持ってくる。
scp 192.168.3.23:/home/root/sd_card/diff.png .
scp 192.168.3.23:/home/root/sd_card/ouput.png .
scp 192.168.3.23:/home/root/sd_card/output.png .

Vitis_Vision_65_200331.png

元画像の colordetect_4k_input.jpeg を示す。
Vitis_Vision_66_200401.jpg

diff.png を示す。
Vitis_Vision_67_200401.jpg

output.png を示す。
Vitis_Vision_68_200401.jpg

outputref.png を示す。
Vitis_Vision_69_200401.jpg
  1. 2020年04月01日 05:05 |
  2. Vitis_Vision
  3. | トラックバック:0
  4. | コメント:0

Vitis_Libraries/vision/L3/examples/colordetect/をやってみた2

Vitis_Libraries/vision/L3/examples/colordetect/をやってみた1”の続き。

Vitis_Libraries/vision/L3/examples/colordetect/をやってみるということで、xclbin をビルドして、sd_card ディレクトリを作成させた。今回は、Vivado HLS プロジェクトと Vivado プロジェクトを見ていこう。

最初に Vivado HLS 2019.2 のプロジェクトから見ていこう。
Vivado HLS のプロジェクトは Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/color_detect/color_detect/color_detect に入っている。
Vitis_Vision_58_200331.png

C コードの合成レポートを示す。
Vitis_Vision_57_200330.png

Latency の max が 8330244 クロックだった。これは 4k 画像を処理したときだと思うので、3840 ピクセル x 2160 行 = 8294400 ピクセルの処理を行ったときなので、約 1.00 クロック / ピクセルとなり、優秀な結果だと思う。

Latency の Detail -> Instance を見ると、Latency の max は 4k 画像の総ピクセル数くらいの値になっているが、総合したクロック数が同じような値なのは、各関数がDATAFLOW 指示子により並列に実行されているからだ。

次に Vivado 2019.2 のプロジェクトを見ていこう。
Vivado プロジェクトは Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/vivado/vpl/prj ディレクトリにある。
Vitis_Vision_59_200331.png

ブロックデザインを示す。
Vitis_Vision_52_200330.png

m_axi_gmem0 から m_axi_gmem4 までの 5 つの AXI4 インターフェースの Master ポートがあるが、これは、xf_colordetect_accel.cpp で 5 つの AXI4 Master インターフェースが定義されているからだ。
xf_colordetect_accel.cpp の関数定義と入出力ポートの指示子の部分を引用する。

void color_detect(ap_uint<PTR_IN_WIDTH>* img_in,
                  unsigned char* low_thresh,
                  unsigned char* high_thresh,
                  unsigned char* process_shape,
                  ap_uint<PTR_OUT_WIDTH>* img_out,
                  int rows,
                  int cols) {
// clang-format off
    #pragma HLS INTERFACE m_axi      port=img_in        offset=slave  bundle=gmem0
   
    #pragma HLS INTERFACE m_axi      port=low_thresh    offset=slave  bundle=gmem1
    #pragma HLS INTERFACE s_axilite  port=low_thresh          bundle=control
    #pragma HLS INTERFACE m_axi      port=high_thresh   offset=slave  bundle=gmem2
    #pragma HLS INTERFACE s_axilite  port=high_thresh          bundle=control
 #pragma HLS INTERFACE s_axilite  port=rows          bundle=control
 #pragma HLS INTERFACE s_axilite  port=cols          bundle=control
    #pragma HLS INTERFACE m_axi      port=process_shape offset=slave  bundle=gmem3
    #pragma HLS INTERFACE s_axilite  port=process_shape         bundle=control
    #pragma HLS INTERFACE m_axi      port=img_out       offset=slave  bundle=gmem4
  
    #pragma HLS INTERFACE s_axilite  port=return              bundle=control


low_thresh, high_thresh, process_shape の 3 つのポートは AXI4 Master と AXI4 Lite Slave の双方に指定されている。こんなことができるのか。。。

前にやった Vitis_Libraries/vision/L2/examples/resize/xf_resize_accel.cpp の関数定義と入出力ポートの指示子の部分を引用する。

void resize_accel(ap_uint<INPUT_PTR_WIDTH>* img_inp,
                  ap_uint<OUTPUT_PTR_WIDTH>* img_out,
                  int rows_in,
                  int cols_in,
                  int rows_out,
                  int cols_out) {
// clang-format off
    #pragma HLS INTERFACE m_axi     port=img_inp  offset=slave bundle=gmem1
    #pragma HLS INTERFACE m_axi     port=img_out  offset=slave bundle=gmem2
    #pragma HLS INTERFACE s_axilite port=rows_in              bundle=control
    #pragma HLS INTERFACE s_axilite port=cols_in              bundle=control
    #pragma HLS INTERFACE s_axilite port=rows_out              bundle=control
    #pragma HLS INTERFACE s_axilite port=cols_out              bundle=control
    #pragma HLS INTERFACE s_axilite port=return                bundle=control


Vivado HLS の color_detect の impl/ip/drivers/src/xcolor_detect_color_detect.h を見ると、通常の m_axi 指示子の slave オプション付きと同じようだ。つまり、s_axilite 指示子は要らないんじゃないだろうか?

// control
// 0x00 : Control signals
//        bit 0  - ap_start (Read/Write/COH)
//        bit 1  - ap_done (Read/COR)
//        bit 2  - ap_idle (Read)
//        bit 3  - ap_ready (Read)
//        bit 7  - auto_restart (Read/Write)
//        others - reserved
// 0x04 : Global Interrupt Enable Register
//        bit 0  - Global Interrupt Enable (Read/Write)
//        others - reserved
// 0x08 : IP Interrupt Enable Register (Read/Write)
//        bit 0  - Channel 0 (ap_done)
//        bit 1  - Channel 1 (ap_ready)
//        others - reserved
// 0x0c : IP Interrupt Status Register (Read/TOW)
//        bit 0  - Channel 0 (ap_done)
//        bit 1  - Channel 1 (ap_ready)
//        others - reserved
// 0x10 : Data signal of img_in_V
//        bit 31~0 - img_in_V[31:0] (Read/Write)
// 0x14 : Data signal of img_in_V
//        bit 31~0 - img_in_V[63:32] (Read/Write)
// 0x18 : reserved
// 0x1c : Data signal of low_thresh
//        bit 31~0 - low_thresh[31:0] (Read/Write)
// 0x20 : Data signal of low_thresh
//        bit 31~0 - low_thresh[63:32] (Read/Write)
// 0x24 : reserved
// 0x28 : Data signal of high_thresh
//        bit 31~0 - high_thresh[31:0] (Read/Write)
// 0x2c : Data signal of high_thresh
//        bit 31~0 - high_thresh[63:32] (Read/Write)
// 0x30 : reserved
// 0x34 : Data signal of process_shape
//        bit 31~0 - process_shape[31:0] (Read/Write)
// 0x38 : Data signal of process_shape
//        bit 31~0 - process_shape[63:32] (Read/Write)
// 0x3c : reserved
// 0x40 : Data signal of img_out_V
//        bit 31~0 - img_out_V[31:0] (Read/Write)
// 0x44 : Data signal of img_out_V
//        bit 31~0 - img_out_V[63:32] (Read/Write)
// 0x48 : reserved
// 0x4c : Data signal of rows
//        bit 31~0 - rows[31:0] (Read/Write)
// 0x50 : reserved
// 0x54 : Data signal of cols
//        bit 31~0 - cols[31:0] (Read/Write)
// 0x58 : reserved
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)


という訳で、color detect の Vivado プロジェクトの Address Editor を示す。
Vitis_Vision_53_200330.png

Vivado のインプリメンテーション結果を示す。
Vitis_Vision_54_200330.png
Vitis_Vision_55_200330.png

リソース使用量のテーブルも示す。
Vitis_Vision_56_200330.png
  1. 2020年03月31日 05:02 |
  2. Vitis_Vision
  3. | トラックバック:0
  4. | コメント:0

Vitis_Libraries/vision/L3/examples/colordetect/をやってみた1

Vitis Vision ライブラリの resize をやってみた。CUI ではうまく行ったが Vitis GUI では、うまく行かなかった。
今回は、Vitis_Libraries/vision/L3/examples/colordetect/をやってみる。

これは、VITIS VISION LIBRARY USER GUIDEColor Detection によると、Vitisビジョンライブラリの4つのハードウェア関数を使用してるそうだ。

xf::cv::BGR2HSV
xf::cv::colorthresholding
xf::cv::erode
xf::cv::dilate


resize を CUI でやっているので、環境は整っている。どのように環境を設定したのか?をおさらいしてみよう。

1. Vitis のインストール・ディレクトリの settings64.sh を実行
source /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/settings64.sh

2. XRT の setenv.sh を実行
source /opt/xilinx/xrt/setup.sh

3. DEVICE 環境変数にプラットフォームの xpfm ファイルへのパスを設定する
export DEVICE=/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm

4. SYSROOT にプラットフォームの sysroot へのパスを設定する。
export SYSROOT=/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux


それでは、Vitis_Libraries/vision/L3/examples/colordetect/build ディレクトリに cd して、 xclbin を make する
make host xclbin TARGET=hw BOARD=Zynq ARCH=aarch64
を実行した。
Vitis_Vision_44_200330.png

全ログを示す。

masaaki@masaaki-H110M4-M01:/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build$ make host xclbin TARGET=hw BOARD=Zynq ARCH=aarch64
-e ----
Compiling object xf_colordetect_tb...
mkdir -p /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/obj_ultra96v2_min2
aarch64-linux-gnu-g++ -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/obj_ultra96v2_min2/xf_colordetect_tb.o -c /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/xf_colordetect_tb.cpp -D XDEVICE=ultra96v2_min2 -DVIVADO_HLS_SIM -D__SDSVHLS__ -DHLS_NO_XIL_FPO_LIB -I. -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2  -g --sysroot=/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux -D__ZYNQ -std=c++14 -fPIC -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect -I/opt/xilinx/xrt/include -Wall -Wno-unknown-pragmas -Wno-unused-label -pthread  -idirafter /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vivado/2019.2/include 
In file included from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include/common/xf_headers.hpp:30,
                 from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/xf_colordetect_tb.cpp:17:
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include/common/xf_sw_utils.hpp: 関数 ‘void xf::cv::analyzeDiff(cv::Mat&, int, float&)’ 内:
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include/common/xf_sw_utils.hpp:150:23: 警告: 変数 ‘v_tmp1’ が設定されましたが使用されていません [-Wunused-but-set-variable]
                 float v_tmp1;
                       ^~~~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/xf_colordetect_tb.cpp: 関数 ‘int main(int, char**)’ 内:
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/xf_colordetect_tb.cpp:146:14: 警告: unused variable ‘fileBufSize’ [-Wunused-variable]
     unsigned fileBufSize;
              ^~~~~~~~~~~
-e ----
Compiling object xf_colordetect_accel...
mkdir -p /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/obj_ultra96v2_min2
aarch64-linux-gnu-g++ -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/obj_ultra96v2_min2/xf_colordetect_accel.o -c /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/xf_colordetect_accel.cpp -D XDEVICE=ultra96v2_min2 -DVIVADO_HLS_SIM -D__SDSVHLS__ -DHLS_NO_XIL_FPO_LIB -I. -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2  -g --sysroot=/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux -D__ZYNQ -std=c++14 -fPIC -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect -I/opt/xilinx/xrt/include -Wall -Wno-unknown-pragmas -Wno-unused-label -pthread  -idirafter /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vivado/2019.2/include 
In file included from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/xf_colordetect_config.h:23,
                 from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/xf_colordetect_accel.cpp:17:
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include/common/xf_utility.hpp: In instantiation of ‘void xf::cv::accel_utils::hlsStrm2xfMat(hls::stream<ap_uint<_AP_W2> >&, xf::cv::Mat<MAT_T, ROWS, COLS, NPC>&, int) [with int PTR_WIDTH = 32; int MAT_T = 9; int ROWS = 2160; int COLS = 3840; int NPC = 1; int TRIPCOUNT = 8294400]’:
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include/common/xf_utility.hpp:312:9:   required from ‘void xf::cv::accel_utils::Array2xfMat(ap_uint<_AP_W2>*, xf::cv::Mat<MAT_T, ROWS, COLS, NPC>&) [with int PTR_WIDTH = 32; int MAT_T = 9; int ROWS = 2160; int COLS = 3840; int NPC = 1]’
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include/common/xf_utility.hpp:508:5:   required from ‘void xf::cv::Array2xfMat(ap_uint<_AP_W2>*, xf::cv::Mat<MAT_T, ROWS, COLS, NPC>&) [with int PTR_WIDTH = 32; int MAT_T = 9; int ROWS = 2160; int COLS = 3840; int NPC = 1]’
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/xf_colordetect_accel.cpp:86:85:   required from here
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include/common/xf_utility.hpp:270:17: 警告: unused variable ‘valid_bits_update’ [-Wunused-variable]
             int valid_bits_update;
                 ^~~~~~~~~~~~~~~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include/common/xf_utility.hpp:271:17: 警告: unused variable ‘valid_bits_tmp’ [-Wunused-variable]
             int valid_bits_tmp = valid_bits - K_size;
                 ^~~~~~~~~~~~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include/common/xf_utility.hpp:247:13: 警告: unused variable ‘strm_cnt_disply’ [-Wunused-variable]
         int strm_cnt_disply = 0;
             ^~~~~~~~~~~~~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include/common/xf_utility.hpp:293:13: 警告: unused variable ‘stop’ [-Wunused-variable]
         int stop = 0;
             ^~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include/common/xf_utility.hpp: In instantiation of ‘void xf::cv::accel_utils::xfMat2hlsStrm(xf::cv::Mat<MAT_T, ROWS, COLS, NPC>&, hls::stream<ap_uint<_AP_W2> >&, int) [with int PTR_WIDTH = 8; int MAT_T = 0; int ROWS = 2160; int COLS = 3840; int NPC = 1; int TRIPCOUNT = 8294400]’:
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include/common/xf_utility.hpp:452:9:   required from ‘void xf::cv::accel_utils::xfMat2Array(xf::cv::Mat<MAT_T, ROWS, COLS, NPC>&, ap_uint<_AP_W2>*) [with int PTR_WIDTH = 8; int MAT_T = 0; int ROWS = 2160; int COLS = 3840; int NPC = 1]’
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include/common/xf_utility.hpp:502:5:   required from ‘void xf::cv::xfMat2Array(xf::cv::Mat<MAT_T, ROWS, COLS, NPC>&, ap_uint<_AP_W2>*) [with int PTR_WIDTH = 8; int MAT_T = 0; int ROWS = 2160; int COLS = 3840; int NPC = 1]’
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/xf_colordetect_accel.cpp:106:89:   required from here
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include/common/xf_utility.hpp:365:13: 警告: unused variable ‘ddr_write_cycles’ [-Wunused-variable]
         int ddr_write_cycles = (((out_size_bits) + (PTR_WIDTH)-1) / (PTR_WIDTH));
             ^~~~~~~~~~~~~~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include/common/xf_utility.hpp:366:13: 警告: unused variable ‘ddr_write_cnt’ [-Wunused-variable]
         int ddr_write_cnt = 0;
             ^~~~~~~~~~~~~
-e ----
Compiling extra object /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/obj_ultra96v2_min2/xcl2.o...
mkdir -p /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/obj_ultra96v2_min2
aarch64-linux-gnu-g++ -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/obj_ultra96v2_min2/xcl2.o -c /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2/xcl2.cpp -D XDEVICE=ultra96v2_min2 -DVIVADO_HLS_SIM -D__SDSVHLS__ -DHLS_NO_XIL_FPO_LIB -I. -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2  -g --sysroot=/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux -D__ZYNQ -std=c++14 -fPIC -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect -I/opt/xilinx/xrt/include -Wall -Wno-unknown-pragmas -Wno-unused-label -pthread  -idirafter /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vivado/2019.2/include -I /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2
-e ----
Compiling host colordetect.exe...
mkdir -p /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/bin_ultra96v2_min2
aarch64-linux-gnu-g++ -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/bin_ultra96v2_min2/colordetect.exe /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/obj_ultra96v2_min2/xf_colordetect_tb.o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/obj_ultra96v2_min2/xf_colordetect_accel.o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/obj_ultra96v2_min2/xcl2.o -D XDEVICE=ultra96v2_min2 -DVIVADO_HLS_SIM -D__SDSVHLS__ -DHLS_NO_XIL_FPO_LIB -I. -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2  -g --sysroot=/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux -D__ZYNQ -std=c++14 -fPIC -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect -I/opt/xilinx/xrt/include -Wall -Wno-unknown-pragmas -Wno-unused-label -pthread  -idirafter /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vivado/2019.2/include -L/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/lib -Wl,-rpath-link=/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/lib/ -L/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/opt/xilinx/xrt/lib -lopencv_imgcodecs -lopencv_core -lopencv_imgproc -lopencv_highgui -lopencv_calib3d -lopencv_features2d -lopencv_flann -pthread -L/opt/xilinx/xrt/lib -lxilinxopencl 
-e ----
Compiling kernel color_detect...
mkdir -p /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/xo_ultra96v2_min2_hw
v++ -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/xo_ultra96v2_min2_hw/color_detect.xo --kernel color_detect --compile /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/xf_colordetect_accel.cpp \
 -I. -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include -D__SDSVHLS__ -DHLS_NO_XIL_FPO_LIB --clock.defaultFreqHz 300000000 -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect --target hw --platform /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm --temp_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw --save-temps --debug --kernel_frequency 300 --report_level 2 --xp vivado_prop:run.impl_1.strategy=Performance_Explore 
WARNING: [v++ 60-1600] The option 'xp' was used directly on the command line, where its usage is deprecated. To ensure input line works for supported operating systems or shells, v++ supports specification for some options in a configuration file. As an alternative, please use options 'advanced.*', 'vivado.*' in a configuration file. Use one or more configuration files along with section headers to define key-value pairs for the advanced properties or parameters. Specify a configuration file using '--config'.
INFO: [v++ 82-185] Check out the auto-generated 'sample_compile.ini' configuration file. The file shows how to migrate from deprecated command line --xp switches to configuration file directives.
Option Map File Used: '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/data/vitis/vpp/optMap.xml'

****** v++ v2019.2 (64-bit)
  **** SW Build 2700185 on Thu Oct 24 18:45:48 MDT 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

INFO: [v++ 60-1306] Additional information associated with this v++ compile can be found at:
 Reports: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/reports/color_detect
 Log files: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/logs/color_detect
Running Dispatch Server on port:33953
INFO: [v++ 60-1548] Creating build summary session with primary output /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/xo_ultra96v2_min2_hw/color_detect.xo.compile_summary, at Sun Mar 29 22:00:15 2020
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Sun Mar 29 22:00:15 2020
Running Rule Check Server on port:41639
INFO: [v++ 60-1315] Creating rulecheck session with output '/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/reports/color_detect/v++_compile_color_detect_guidance.html', at Sun Mar 29 22:00:16 2020
INFO: [v++ 60-895]   Target platform: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm
INFO: [v++ 60-1578]   This platform contains Xilinx Shell Archive '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/hw/ultra96v2_min2.xsa'
INFO: [v++ 60-585] Compiling for hardware target
INFO: [v++ 60-423]   Target device: ultra96v2_min2
INFO: [v++ 60-242] Creating kernel: 'color_detect'
INFO: [v++ 60-1616] Creating a HLS clock using kernel_frequency option: 300 MHz

===>The following messages were generated while  performing high-level synthesis for kernel: color_detect Log file: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/color_detect/color_detect/vivado_hls.log :
INFO: [v++ 204-61] Option 'relax_ii_for_timing' is enabled, will increase II to preserve clock frequency constraints.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining loop 'L1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 4.
INFO: [v++ 204-61] Pipelining function 'read'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining function 'write'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 16.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
WARNING: [v++ 204-69] Unable to schedule bus request on port 'low_thresh' (/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include/imgproc/xf_colorthresholding.hpp:144) due to limited memory ports. Please consider using a memory core with more ports or partitioning the array.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 3, Depth = 11.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining function 'xfExtractPixels<1, 1, 0>'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining loop 'Loop 2'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining loop 'Col_Loop'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 11.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining loop 'Loop 2'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining loop 'Col_Loop'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 11.
INFO: [v++ 204-61] Pipelining loop 'L1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 200-789] **** Estimated Fmax: 300.03 MHz
INFO: [v++ 60-594] Finished kernel compilation
INFO: [v++ 60-244] Generating system estimate report...
INFO: [v++ 60-1092] Generated system estimate report: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/reports/color_detect/system_estimate_color_detect.xtxt
Add Instance Array2xfMat_32_9_2160_3840_1_1 Array2xfMat_32_9_2160_3840_1_1_U0 808
Add Instance Array2xfMat_32_9_2160_3840_1_s grp_Array2xfMat_32_9_2160_3840_1_s_fu_142 142
Add Instance hlsStrm2xfMat_32_9_2160_3840_1_8294400_s hlsStrm2xfMat_32_9_2160_3840_1_8294400_U0 136
Add Instance Array2hlsStrm_32_2160_3840_1_3_8_6220800_s Array2hlsStrm_32_2160_3840_1_3_8_6220800_U0 145
Add Instance xfMat2Array_8_0_2160_3840_1_s xfMat2Array_8_0_2160_3840_1_U0 820
Add Instance xfMat2Array_8_0_2160_3840_1_1 grp_xfMat2Array_8_0_2160_3840_1_1_fu_96 96
Add Instance xfMat2hlsStrm_8_0_2160_3840_1_8294400_62 xfMat2hlsStrm_8_0_2160_3840_1_8294400_62_U0 156
Add Instance hlsStrm2Array_8_2160_3840_1_1_8_8294400_s hlsStrm2Array_8_2160_3840_1_1_8_8294400_U0 172
Add Instance colorthresholding_9_0_3_2160_3840_1_s colorthresholding_9_0_3_2160_3840_1_U0 830
Add Instance colorthresholding_9_0_3_2160_3840_1_Loop_1_proc colorthresholding_9_0_3_2160_3840_1_Loop_1_proc_U0 202
Add Instance xFInRange_9_0_2160_3840_15_0_1_9_1_3_s xFInRange_9_0_2160_3840_15_0_1_9_1_3_U0 212
Add Instance colorthresholding_9_0_3_2160_3840_1_entry14 colorthresholding_9_0_3_2160_3840_1_entry14_U0 240
Add Instance colorthresholding_9_0_3_2160_3840_1_entry253 colorthresholding_9_0_3_2160_3840_1_entry253_U0 250
Add Instance colorthresholding_Block_colorthresholding_9_0_3_2160_3840_1_exit_proc colorthresholding_Block_colorthresholding_9_0_3_2160_3840_1_exit_proc_U0 260
Add Instance bgr2hsv_9_2160_3840_1_s bgr2hsv_9_2160_3840_1_U0 844
Add Instance bgr2hsv_9_2160_3840_1_Loop_1_proc bgr2hsv_9_2160_3840_1_Loop_1_proc_U0 106
Add Instance write_r call_ln160_write_r_fu_246 246
Add Instance read_r in_pix_V_read_r_fu_253 253
Add Instance bgr2hsv_9_2160_3840_1_Block_codeRepl8_proc233 bgr2hsv_9_2160_3840_1_Block_codeRepl8_proc233_U0 122
Add Instance erode_0_0_2160_3840_0_3_3_1_1_176 erode_0_0_2160_3840_0_3_3_1_1_176_U0 858
Add Instance xferode_2160_3840_1_0_1_0_3841_3_3_s grp_xferode_2160_3840_1_0_1_0_3841_3_3_s_fu_80 80
Add Instance xfExtractPixels_1_1_0_s src_buf_temp_copy_extract_0_V_xfExtractPixels_1_1_0_s_fu_448 448
Add Instance xfExtractPixels_1_1_0_s src_buf_temp_copy_extract_0_V_1_xfExtractPixels_1_1_0_s_fu_453 453
Add Instance xfExtractPixels_1_1_0_s src_buf_temp_copy_extract_0_V_2_xfExtractPixels_1_1_0_s_fu_458 458
Add Instance dilate_0_0_2160_3840_0_3_3_1_1_177 dilate_0_0_2160_3840_0_3_3_1_1_177_U0 866
Add Instance xfdilate_2160_3840_1_0_1_0_3841_3_3_s grp_xfdilate_2160_3840_1_0_1_0_3841_3_3_s_fu_80 80
Add Instance xfExtractPixels_1_1_0_s src_buf_temp_copy_extract_0_V_xfExtractPixels_1_1_0_s_fu_448 448
Add Instance xfExtractPixels_1_1_0_s src_buf_temp_copy_extract_0_V_3_xfExtractPixels_1_1_0_s_fu_453 453
Add Instance xfExtractPixels_1_1_0_s src_buf_temp_copy_extract_0_V_4_xfExtractPixels_1_1_0_s_fu_458 458
Add Instance dilate_0_0_2160_3840_0_3_3_1_1_s dilate_0_0_2160_3840_0_3_3_1_1_U0 874
Add Instance xfdilate_2160_3840_1_0_1_0_3841_3_3_s grp_xfdilate_2160_3840_1_0_1_0_3841_3_3_s_fu_80 80
Add Instance xfExtractPixels_1_1_0_s src_buf_temp_copy_extract_0_V_xfExtractPixels_1_1_0_s_fu_448 448
Add Instance xfExtractPixels_1_1_0_s src_buf_temp_copy_extract_0_V_3_xfExtractPixels_1_1_0_s_fu_453 453
Add Instance xfExtractPixels_1_1_0_s src_buf_temp_copy_extract_0_V_4_xfExtractPixels_1_1_0_s_fu_458 458
Add Instance erode_0_0_2160_3840_0_3_3_1_1_s erode_0_0_2160_3840_0_3_3_1_1_U0 882
Add Instance xferode_2160_3840_1_0_1_0_3841_3_3_s grp_xferode_2160_3840_1_0_1_0_3841_3_3_s_fu_80 80
Add Instance xfExtractPixels_1_1_0_s src_buf_temp_copy_extract_0_V_xfExtractPixels_1_1_0_s_fu_448 448
Add Instance xfExtractPixels_1_1_0_s src_buf_temp_copy_extract_0_V_1_xfExtractPixels_1_1_0_s_fu_453 453
Add Instance xfExtractPixels_1_1_0_s src_buf_temp_copy_extract_0_V_2_xfExtractPixels_1_1_0_s_fu_458 458
Add Instance Block_Mat_exit717_proc83 Block_Mat_exit717_proc83_U0 890
INFO: [v++ 60-586] Created /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/xo_ultra96v2_min2_hw/color_detect.xo
INFO: [v++ 60-791] Total elapsed time: 0h 1m 8s
-e ----
Compiling xclbin...
mkdir -p /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/xclbin_ultra96v2_min2_hw
v++ -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/xclbin_ultra96v2_min2_hw/krnl_colordetect.xclbin --link /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/xo_ultra96v2_min2_hw/color_detect.xo \
 -I. -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include -D__SDSVHLS__ -DHLS_NO_XIL_FPO_LIB --clock.defaultFreqHz 300000000 -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect --target hw --platform /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm --temp_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw --save-temps --debug --kernel_frequency 300 --report_level 2 --optimize 2 --jobs 8 --xp "vivado_param:project.writeIntermediateCheckpoints=1" \
 --xp vivado_prop:run.impl_1.strategy=Performance_Explore  \
 
WARNING: [v++ 60-1600] The option 'xp' was used directly on the command line, where its usage is deprecated. To ensure input line works for supported operating systems or shells, v++ supports specification for some options in a configuration file. As an alternative, please use options 'advanced.*', 'vivado.*' in a configuration file. Use one or more configuration files along with section headers to define key-value pairs for the advanced properties or parameters. Specify a configuration file using '--config'.
INFO: [v++ 82-185] Check out the auto-generated 'sample_link.ini' configuration file. The file shows how to migrate from deprecated command line --xp switches to configuration file directives.
Option Map File Used: '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/data/vitis/vpp/optMap.xml'

****** v++ v2019.2 (64-bit)
  **** SW Build 2700185 on Thu Oct 24 18:45:48 MDT 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

INFO: [v++ 60-1306] Additional information associated with this v++ link can be found at:
 Reports: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/reports/link
 Log files: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/logs/link
Running Dispatch Server on port:35961
INFO: [v++ 60-1548] Creating build summary session with primary output /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/xclbin_ultra96v2_min2_hw/krnl_colordetect.xclbin.link_summary, at Sun Mar 29 22:01:26 2020
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Sun Mar 29 22:01:26 2020
Running Rule Check Server on port:35127
INFO: [v++ 60-1315] Creating rulecheck session with output '/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/reports/link/v++_link_krnl_colordetect_guidance.html', at Sun Mar 29 22:01:27 2020
INFO: [v++ 60-895]   Target platform: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm
INFO: [v++ 60-1578]   This platform contains Xilinx Shell Archive '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/hw/ultra96v2_min2.xsa'
INFO: [v++ 60-629] Linking for hardware target
INFO: [v++ 60-423]   Target device: ultra96v2_min2
INFO: [v++ 60-1332] Run 'run_link' status: Not started
INFO: [v++ 60-1443] [22:01:27] Run run_link: Step system_link: Started
INFO: [v++ 60-1453] Command Line: system_link --xo /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/xo_ultra96v2_min2_hw/color_detect.xo -keep --config /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/int/syslinkConfig.ini --xpfm /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm --target hw --output_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/int --temp_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/sys_link
INFO: [v++ 60-1454] Run Directory: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/run_link
INFO: [SYSTEM_LINK 82-76] Reading emulation BD and HPFM information
INFO: [SYSTEM_LINK 60-1316] Initiating connection to rulecheck server, at Sun Mar 29 22:01:28 2020
INFO: [SYSTEM_LINK 82-70] Extracting xo v3 file /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/xo_ultra96v2_min2_hw/color_detect.xo
INFO: [KernelCheck 83-118] 'color_detect' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'img_in' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'low_thresh' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'high_thresh' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'process_shape' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'img_out' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'rows' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'cols' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [SYSTEM_LINK 82-53] Creating IP database /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/sys_link/_sysl/.cdb/xd_ip_db.xml
INFO: [SYSTEM_LINK 82-38] [22:01:28] build_xd_ip_db started: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/bin/build_xd_ip_db -ip_search 0  -sds-pf /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/sys_link/ultra96v2_min2.hpfm -clkid 0 -ip /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/sys_link/iprepo/xilinx_com_hls_color_detect_1_0,color_detect -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/sys_link/_sysl/.cdb/xd_ip_db.xml
INFO: [SYSTEM_LINK 82-37] [22:01:32] build_xd_ip_db finished successfully
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 296.441 ; gain = 0.000 ; free physical = 11778 ; free virtual = 39256
INFO: [SYSTEM_LINK 82-51] Create system connectivity graph
INFO: [SYSTEM_LINK 82-102] Applying explicit connections to the system connectivity graph: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/sys_link/cfgraph/cfgen_cfgraph.xml
INFO: [SYSTEM_LINK 82-38] [22:01:32] cfgen started: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/bin/cfgen  -clock.defaultFreqHz 300000000 -dmclkid 0 -r /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/sys_link/cfgraph/cfgen_cfgraph.xml
INFO: [CFGEN 83-0] Kernel Specs: 
INFO: [CFGEN 83-0]   kernel: color_detect, num: 1  {color_detect_1}
INFO: [CFGEN 83-2226] Inferring mapping for argument color_detect_1.img_in to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument color_detect_1.low_thresh to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument color_detect_1.high_thresh to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument color_detect_1.process_shape to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument color_detect_1.img_out to HP
INFO: [SYSTEM_LINK 82-37] [22:01:32] cfgen finished successfully
Time (s): cpu = 00:00:00.27 ; elapsed = 00:00:00.34 . Memory (MB): peak = 296.441 ; gain = 0.000 ; free physical = 11779 ; free virtual = 39258
INFO: [SYSTEM_LINK 82-52] Create top-level block diagram
INFO: [SYSTEM_LINK 82-38] [22:01:32] cf2bd started: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/bin/cf2bd  --linux --trace_buffer 1024 --input_file /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/sys_link/cfgraph/cfgen_cfgraph.xml --ip_db /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/sys_link/_sysl/.cdb/xd_ip_db.xml --cf_name dr --working_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/sys_link/_sysl/.xsd --temp_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/sys_link --output_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/int
INFO: [CF2BD 82-31] Launching cf2xd: cf2xd -linux -trace-buffer 1024 -i /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/sys_link/cfgraph/cfgen_cfgraph.xml -r /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o dr.xml
INFO: [CF2BD 82-28] cf2xd finished successfully
INFO: [CF2BD 82-31] Launching cf_xsd: cf_xsd -disable-address-gen -dn dr -dp /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/sys_link/_sysl/.xsd
                                                                                
rlwrap: warning: your $TERM is 'xterm-256color' but rlwrap couldn't find it in the terminfo database. Expect some problems.: Inappropriate ioctl for device
INFO: [CF2BD 82-28] cf_xsd finished successfully
INFO: [SYSTEM_LINK 82-37] [22:01:34] cf2bd finished successfully
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 296.441 ; gain = 0.000 ; free physical = 11776 ; free virtual = 39258
INFO: [v++ 60-1441] [22:01:34] Run run_link: Step system_link: Completed
Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 679.691 ; gain = 0.000 ; free physical = 11794 ; free virtual = 39277
INFO: [v++ 60-1443] [22:01:34] Run run_link: Step cf2sw: Started
INFO: [v++ 60-1453] Command Line: cf2sw -sdsl /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/int/sdsl.dat -rtd /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/int/cf2sw.rtd -xclbin /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/int/xclbin_orig.xml -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/int/xclbin_orig.1.xml
INFO: [v++ 60-1454] Run Directory: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/run_link
INFO: [v++ 60-1441] [22:01:34] Run run_link: Step cf2sw: Completed
Time (s): cpu = 00:00:00.52 ; elapsed = 00:00:00.57 . Memory (MB): peak = 679.691 ; gain = 0.000 ; free physical = 11793 ; free virtual = 39276
INFO: [v++ 60-1443] [22:01:34] Run run_link: Step rtd2_system_diagram: Started
INFO: [v++ 60-1453] Command Line: rtd2SystemDiagram --rtdJsonFileName /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/int/cf2sw.rtd --diagramJsonFileName /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/int/systemDiagramModel.json --platformFilePath /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm --generatedByName v++ --generatedByVersion 2019.2 --generatedByChangeList 2700185 --generatedByTimeStamp Thu Oct 24 18:45:48 MDT 2019 --generatedByOptions /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/bin/unwrapped/lnx64.o/v++ -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/xclbin_ultra96v2_min2_hw/krnl_colordetect.xclbin --link /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/xo_ultra96v2_min2_hw/color_detect.xo -I. -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include -D__SDSVHLS__ -DHLS_NO_XIL_FPO_LIB --clock.defaultFreqHz 300000000 -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect --target hw --platform /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm --temp_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw --save-temps --debug --kernel_frequency 300 --report_level 2 --optimize 2 --jobs 8 --xp vivado_param:project.writeIntermediateCheckpoints=1 --xp vivado_prop:run.impl_1.strategy=Performance_Explore  --generatedByXclbinName krnl_colordetect --kernelInfoDataFileName /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/int/kernel_info.dat
INFO: [v++ 60-1454] Run Directory: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/run_link
WARNING: [v++ 82-164] Unable to populate user region instance path.  The platform file does not contain a hardwarePlatform.devices..core.instPath entry.
INFO: [v++ 60-839] Read in kernel information from file '/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/int/kernel_info.dat'.
WARNING: [v++ 82-157] Unable to populate kernel available resources BRAM entry.
WARNING: [v++ 82-158] Unable to populate kernel available resources DSP entry.
WARNING: [v++ 82-163] Unable to populate user region available resources.  The platform file deos not contain a hardwarePlatform.devices..core.availableResources entry
INFO: [v++ 60-1441] [22:01:36] Run run_link: Step rtd2_system_diagram: Completed
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 679.691 ; gain = 0.000 ; free physical = 11794 ; free virtual = 39277
INFO: [v++ 60-1443] [22:01:36] Run run_link: Step vpl: Started
INFO: [v++ 60-1453] Command Line: vpl -t hw -f /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm -g -j 8 --kernel_frequency 300 -s --output_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/int --log_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/logs/link --report_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/reports/link --config /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/int/vplConfig.ini -k /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/int/kernel_info.dat --webtalk_flag Vitis --temp_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link --no-info --tlog_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/.tlog/v++_link_krnl_colordetect --iprepo /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/int/xo/ip_repo/xilinx_com_hls_color_detect_1_0 --messageDb /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/run_link/vpl.pb /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/int/dr.bd.tcl
INFO: [v++ 60-1454] Run Directory: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/run_link

****** vpl v2019.2 (64-bit)
  **** SW Build 2700185 on Thu Oct 24 18:45:48 MDT 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

INFO: [VPL 60-839] Read in kernel information from file '/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/int/kernel_info.dat'.
INFO: [VPL 60-423]   Target device: ultra96v2_min2
INFO: [VPL 60-1032] Extracting hardware platform to /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/vivado/vpl/.local/hw_platform
[22:01:48] Run vpl: Step create_project: Started
Creating Vivado project.
[22:01:56] Run vpl: Step create_project: Completed
[22:01:56] Run vpl: Step create_bd: Started
[22:02:06] Run vpl: Step create_bd: Completed
[22:02:06] Run vpl: Step update_bd: Started
[22:02:07] Run vpl: Step update_bd: Completed
[22:02:07] Run vpl: Step generate_target: Started
[22:02:41] Run vpl: Step generate_target: Completed
[22:02:41] Run vpl: Step config_hw_runs: Started
[22:02:44] Run vpl: Step config_hw_runs: Completed
[22:02:44] Run vpl: Step synth: Started
[22:03:46] Block-level synthesis in progress, 0 of 19 jobs complete, 8 jobs running.
[22:04:16] Block-level synthesis in progress, 0 of 19 jobs complete, 8 jobs running.
[22:04:47] Block-level synthesis in progress, 0 of 19 jobs complete, 8 jobs running.
[22:05:17] Block-level synthesis in progress, 0 of 19 jobs complete, 8 jobs running.
[22:05:47] Block-level synthesis in progress, 0 of 19 jobs complete, 8 jobs running.
[22:06:18] Block-level synthesis in progress, 0 of 19 jobs complete, 8 jobs running.
[22:06:48] Block-level synthesis in progress, 0 of 19 jobs complete, 8 jobs running.
[22:07:19] Block-level synthesis in progress, 1 of 19 jobs complete, 7 jobs running.
[22:07:49] Block-level synthesis in progress, 2 of 19 jobs complete, 6 jobs running.
[22:08:19] Block-level synthesis in progress, 5 of 19 jobs complete, 5 jobs running.
[22:08:50] Block-level synthesis in progress, 9 of 19 jobs complete, 2 jobs running.
[22:09:20] Block-level synthesis in progress, 11 of 19 jobs complete, 4 jobs running.
[22:09:50] Block-level synthesis in progress, 11 of 19 jobs complete, 4 jobs running.
[22:10:21] Block-level synthesis in progress, 15 of 19 jobs complete, 4 jobs running.
[22:10:51] Block-level synthesis in progress, 15 of 19 jobs complete, 4 jobs running.
[22:11:21] Block-level synthesis in progress, 17 of 19 jobs complete, 2 jobs running.
[22:11:51] Block-level synthesis in progress, 17 of 19 jobs complete, 2 jobs running.
[22:12:21] Block-level synthesis in progress, 18 of 19 jobs complete, 1 job running.
[22:12:52] Top-level synthesis in progress.
[22:13:22] Top-level synthesis in progress.
[22:13:52] Top-level synthesis in progress.
[22:14:22] Top-level synthesis in progress.
[22:14:27] Run vpl: Step synth: Completed
[22:14:27] Run vpl: Step impl: Started
[22:16:28] Finished 2nd of 6 tasks (FPGA linking synthesized kernels to platform). Elapsed time: 00h 14m 50s 

[22:16:28] Starting logic optimization..
[22:16:58] Phase 1 Retarget
[22:16:58] Phase 2 Constant propagation
[22:16:58] Phase 3 Sweep
[22:16:58] Phase 4 BUFG optimization
[22:16:58] Phase 5 Shift Register Optimization
[22:16:58] Phase 6 Post Processing Netlist
[22:17:28] Finished 3rd of 6 tasks (FPGA logic optimization). Elapsed time: 00h 01m 00s 

[22:17:28] Starting logic placement..
[22:17:58] Phase 1 Placer Initialization
[22:17:58] Phase 1.1 Placer Initialization Netlist Sorting
[22:17:58] Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
[22:17:58] Phase 1.3 Build Placer Netlist Model
[22:17:58] Phase 1.4 Constrain Clocks/Macros
[22:17:58] Phase 2 Global Placement
[22:17:58] Phase 2.1 Floorplanning
[22:17:58] Phase 2.2 Global Placement Core
[22:18:29] Phase 2.2.1 Physical Synthesis In Placer
[22:18:29] Phase 3 Detail Placement
[22:18:29] Phase 3.1 Commit Multi Column Macros
[22:18:29] Phase 3.2 Commit Most Macros & LUTRAMs
[22:18:29] Phase 3.3 Area Swap Optimization
[22:18:29] Phase 3.4 Pipeline Register Optimization
[22:18:29] Phase 3.5 IO Cut Optimizer
[22:18:29] Phase 3.6 Fast Optimization
[22:18:29] Phase 3.7 Small Shape DP
[22:18:29] Phase 3.7.1 Small Shape Clustering
[22:18:59] Phase 3.7.2 Flow Legalize Slice Clusters
[22:18:59] Phase 3.7.3 Slice Area Swap
[22:18:59] Phase 3.7.4 Commit Slice Clusters
[22:18:59] Phase 3.8 Re-assign LUT pins
[22:18:59] Phase 3.9 Pipeline Register Optimization
[22:18:59] Phase 4 Post Placement Optimization and Clean-Up
[22:18:59] Phase 4.1 Post Commit Optimization
[22:18:59] Phase 4.1.1 Post Placement Optimization
[22:18:59] Phase 4.1.1.1 BUFG Insertion
[22:18:59] Phase 4.2 Post Placement Cleanup
[22:18:59] Phase 4.3 Placer Reporting
[22:18:59] Phase 4.4 Final Placement Cleanup
[22:19:29] Finished 4th of 6 tasks (FPGA logic placement). Elapsed time: 00h 02m 00s 

[22:19:29] Starting logic routing..
[22:19:29] Phase 1 Build RT Design
[22:19:59] Phase 2 Router Initialization
[22:19:59] Phase 2.1 Create Timer
[22:19:59] Phase 2.2 Fix Topology Constraints
[22:19:59] Phase 2.3 Pre Route Cleanup
[22:19:59] Phase 2.4 Global Clock Net Routing
[22:19:59] Phase 2.5 Update Timing
[22:19:59] Phase 2.6 Update Timing for Bus Skew
[22:19:59] Phase 2.6.1 Update Timing
[22:20:30] Phase 3 Initial Routing
[22:20:30] Phase 4 Rip-up And Reroute
[22:20:30] Phase 4.1 Global Iteration 0
[22:22:00] Phase 4.2 Global Iteration 1
[22:22:00] Phase 5 Delay and Skew Optimization
[22:22:00] Phase 5.1 Delay CleanUp
[22:22:00] Phase 5.1.1 Update Timing
[22:22:00] Phase 5.2 Clock Skew Optimization
[22:22:00] Phase 6 Post Hold Fix
[22:22:00] Phase 6.1 Hold Fix Iter
[22:22:00] Phase 6.1.1 Update Timing
[22:22:00] Phase 7 Route finalize
[22:22:00] Phase 8 Verifying routed nets
[22:22:00] Phase 9 Depositing Routes
[22:22:00] Phase 10 Route finalize
[22:22:00] Phase 11 Post Router Timing
[22:22:00] Finished 5th of 6 tasks (FPGA routing). Elapsed time: 00h 02m 31s 

[22:22:00] Starting bitstream generation..
[22:23:01] Creating bitmap...
[22:23:01] Writing bitstream ./ultra96v2_min2_wrapper.bit...
[22:23:01] Finished 6th of 6 tasks (FPGA bitstream generation). Elapsed time: 00h 01m 00s 
[22:23:07] Run vpl: Step impl: Completed
[22:23:07] Run vpl: FINISHED. Run Status: impl Complete!
INFO: [v++ 60-1441] [22:23:07] Run run_link: Step vpl: Completed
Time (s): cpu = 00:00:08 ; elapsed = 00:21:31 . Memory (MB): peak = 679.691 ; gain = 0.000 ; free physical = 14934 ; free virtual = 40171
INFO: [v++ 60-1443] [22:23:07] Run run_link: Step rtdgen: Started
INFO: [v++ 60-1453] Command Line: rtdgen
INFO: [v++ 60-1454] Run Directory: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/run_link
INFO: [v++ 60-1453] Command Line: cf2sw -a /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/int/address_map.xml -sdsl /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/int/sdsl.dat -xclbin /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/int/xclbin_orig.xml -rtd /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/int/krnl_colordetect.rtd -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/int/krnl_colordetect.xml
INFO: [v++ 60-1618] Launching 
INFO: [v++ 60-1441] [22:23:09] Run run_link: Step rtdgen: Completed
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 679.691 ; gain = 0.000 ; free physical = 14948 ; free virtual = 40186
INFO: [v++ 60-1443] [22:23:09] Run run_link: Step xclbinutil: Started
INFO: [v++ 60-1453] Command Line: xclbinutil --add-section BITSTREAM:RAW:/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/int/system.bit --force --key-value SYS:mode:flat --add-section :JSON:/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/int/krnl_colordetect.rtd --add-section CLOCK_FREQ_TOPOLOGY:JSON:/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/int/krnl_colordetect_xml.rtd --add-section BUILD_METADATA:JSON:/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/int/krnl_colordetect_build.rtd --add-section EMBEDDED_METADATA:RAW:/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/int/krnl_colordetect.xml --add-section SYSTEM_METADATA:RAW:/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/int/systemDiagramModelSlrBaseAddress.json --key-value SYS:PlatformVBNV:vendor_Ultra96V2_ultra96v2_min2_1_0 --output /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/int/krnl_colordetect.xclbin
INFO: [v++ 60-1454] Run Directory: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/run_link
XRT Build Version: 2.3.1301
       Build Date: 2019-10-24 20:05:16
          Hash ID: 192e706aea53163a04c574f9b3fe9ed76b6ca471
Creating a default 'in-memory' xclbin image.

Section: 'BITSTREAM'(0) was successfully added.
Size   : 5568794 bytes
Format : RAW
File   : '/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/int/system.bit'

Section: 'MEM_TOPOLOGY'(6) was successfully added.
Format : JSON
File   : 'mem_topology'

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Format : JSON
File   : 'ip_layout'

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Format : JSON
File   : 'connectivity'
WARNING: Skipping CLOCK_FREQ_TOPOLOGY section for count size is zero.
WARNING: Section 'CLOCK_FREQ_TOPOLOGY' content is empty.  No data in the given JSON file.

Section: 'CLOCK_FREQ_TOPOLOGY'(11) was empty.  No action taken.
Format : JSON
File   : '/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/int/krnl_colordetect_xml.rtd'

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Size   : 3853 bytes
Format : JSON
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Size   : 11880 bytes
Format : RAW
File   : '/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/int/systemDiagramModelSlrBaseAddress.json'
Successfully wrote (5608798 bytes) to the output file: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/int/krnl_colordetect.xclbin
Leaving xclbinutil.
INFO: [v++ 60-1441] [22:23:09] Run run_link: Step xclbinutil: Completed
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.27 . Memory (MB): peak = 679.691 ; gain = 0.000 ; free physical = 14940 ; free virtual = 40186
INFO: [v++ 60-1443] [22:23:09] Run run_link: Step xclbinutilinfo: Started
INFO: [v++ 60-1453] Command Line: xclbinutil --quiet --info /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/int/krnl_colordetect.xclbin.info --input /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/int/krnl_colordetect.xclbin
INFO: [v++ 60-1454] Run Directory: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/link/run_link
INFO: [v++ 60-1441] [22:23:10] Run run_link: Step xclbinutilinfo: Completed
Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.05 . Memory (MB): peak = 679.691 ; gain = 0.000 ; free physical = 14940 ; free virtual = 40186
INFO: [v++ 60-244] Generating system estimate report...
INFO: [v++ 60-1092] Generated system estimate report: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/reports/link/system_estimate_krnl_colordetect.xtxt
INFO: [v++ 60-907] Packaging to directory: '/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/xclbin_ultra96v2_min2_hw/sd_card'
INFO: [v++ 60-586] Created /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/xclbin_ultra96v2_min2_hw/krnl_colordetect.xclbin
INFO: [v++ 60-1307] Run completed. Additional information can be found in:
 Guidance: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/reports/link/v++_link_krnl_colordetect_guidance.html
 Timing Report: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/reports/link/imp/ultra96v2_min2_wrapper_timing_summary_routed.rpt
 Vivado Log: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/logs/link/vivado.log
 Steps Log File: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build/_x_ultra96v2_min2_hw/logs/link/link.steps.log

INFO: [v++ 60-791] Total elapsed time: 0h 21m 46s
masaaki@masaaki-H110M4-M01:/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/colordetect/build$ 


現在のVitis_Libraries/vision/L3/examples/colordetect/build ディレクトリの様子を示す。コマンド起動する前は Makefile だけだった。
Vitis_Vision_45_200330.png 

次に、sd_card ディレクトリを make する。
make run TARGET=hw BOARD=Zynq ARCH=aarch64
Vitis_Vision_46_200330.png

するとやはりエラーだった。
エラーを解消するには、下の Makefile のハイライトされた部分を削除すれば良い。Makefile の一部を引用する。
Vitis_Vision_47_200330.png

この部分を削除して、もう一度 make run TARGET=hw BOARD=Zynq ARCH=aarch64 を実行したところ、今度はエラーが発生しなかった。
Vitis_Vision_48_200330.png

Vitis_Libraries/vision/L3/examples/colordetect/build ディレクトリの内容を示す。
Vitis_Vision_50_200330.png

sd_card ディレクトリを表示してみよう。 Vitis_Libraries/vision/L3/examples/colordetect/build/sd_card ディレクトリの様子を示す。
Vitis_Vision_49_200330.png

xclbin_ultra96v2_min2_hw ディレクトリの下には、 krnl_colordetect.xclbin が入っている。

BOOT.BIN の在り処は、 Vitis_Libraries/vision/L3/examples/colordetect/build/xclbin_ultra96v2_min2_hw/sd_card だった。
Vitis_Vision_51_200330.png
  1. 2020年03月30日 04:44 |
  2. Vitis_Vision
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