// ----------------------------------------------------------------------------
// Smart High-Level Synthesis Tool Version 2021.2
// Copyright (c) 2015-2021 Microchip Technology Inc. All Rights Reserved.
// For support, please contact: smarthls@microchip.com
// Date: Sat Dec 25 04:12:11 2021
// ----------------------------------------------------------------------------
SmartHLS Summary Report for Project: axi_initiator.
Table of Contents
1. RTL Interface
2. Scheduling Result
3. Pipeline Result
4. Memory Usage
5. Accelerator Information
6. Resource Binding with Adaptive Latency
====== 1. RTL Interface ======
+-------------------------------------------------------------------------------------------+
| RTL Interface Generated by SmartHLS |
+-----------+----------------+------------------------+------------------+------------------+
| C++ Name | Interface Type | Signal Name | Signal Bit-width | Signal Direction |
+-----------+----------------+------------------------+------------------+------------------+
| | Control | clk | 1 | input |
| | | finish | 1 | output |
| | | ready | 1 | output |
| | | reset | 1 | input |
| | | start | 1 | input |
+-----------+----------------+------------------------+------------------+------------------+
| initiator | AXI Master | initiator_ar_addr | 32 | output |
| | | initiator_ar_burst | 2 | output |
| | | initiator_ar_len | 8 | output |
| | | initiator_ar_ready | 1 | input |
| | | initiator_ar_size | 3 | output |
| | | initiator_ar_valid | 1 | output |
| | | initiator_aw_addr | 32 | output |
| | | initiator_aw_burst | 2 | output |
| | | initiator_aw_len | 8 | output |
| | | initiator_aw_ready | 1 | input |
| | | initiator_aw_size | 3 | output |
| | | initiator_aw_valid | 1 | output |
| | | initiator_b_resp | 2 | input |
| | | initiator_b_resp_ready | 1 | output |
| | | initiator_b_resp_valid | 1 | input |
| | | initiator_r_data | 64 | input |
| | | initiator_r_last | 1 | input |
| | | initiator_r_ready | 1 | output |
| | | initiator_r_resp | 2 | input |
| | | initiator_r_valid | 1 | input |
| | | initiator_w_data | 64 | output |
| | | initiator_w_last | 1 | output |
| | | initiator_w_ready | 1 | input |
| | | initiator_w_strb | 8 | output |
| | | initiator_w_valid | 1 | output |
+-----------+----------------+------------------------+------------------+------------------+
The Verilog top-level module ports that are not listed in the above table are unused. Please tie the unused input ports to 0.
====== 2. Scheduling Result ======
Please use SmartHLS's schedule viewer to examine the schedule.
Basic Block Latencies:
+-----------------------------------------------------+
| Function: simple_initiator (non-pipelined function) |
+---------------------------+-------------------------+
| Basic Block | Cycle Latency |
+---------------------------+-------------------------+
| %for.body.lr.ph | 1 |
| %for.body | 2 |
| %for.end | 1 |
+---------------------------+-------------------------+
====== 3. Pipeline Result ======
+---------------------------------+------------------+-------------+------------------------------+---------------------+-----------------+-----------------+---------+
| Label | Function | Basic Block | Location in Source Code | Initiation Interval | Pipeline Length | Iteration Count | Latency |
+---------------------------------+------------------+-------------+------------------------------+---------------------+-----------------+-----------------+---------+
| for_loop_axi_initiator_cpp_13_5 | simple_initiator | %for.body | line 13 of axi_initiator.cpp | 1 | 2 | 256 | 257 |
+---------------------------------+------------------+-------------+------------------------------+---------------------+-----------------+-----------------+---------+
====== 4. Memory Usage ======
+----------------+
| Local Memories |
+----------------+
| None |
+----------------+
+-------------------------+
| Local Constant Memories |
+-------------------------+
| None |
+-------------------------+
+-----------------------+
| Shared Local Memories |
+-----------------------+
| None |
+-----------------------+
+------------------+
| Aliased Memories |
+------------------+
| None |
+------------------+
+-----------------------------------------------------------------------------------------------+
| I/O Memories |
+--------------------+-----------------------+---------------+-------------+------------+-------+
| Name | Accessing Function(s) | Type | Size [Bits] | Data Width | Depth |
+--------------------+-----------------------+---------------+-------------+------------+-------+
| initiator_ar_addr | simple_initiator | FIFO (LUTRAM) | 0 | 32 | 0 |
| initiator_ar_burst | simple_initiator | FIFO (LUTRAM) | 0 | 2 | 0 |
| initiator_ar_size | simple_initiator | FIFO (LUTRAM) | 0 | 3 | 0 |
| initiator_ar_len | simple_initiator | FIFO (LUTRAM) | 0 | 8 | 0 |
| initiator_r_data | simple_initiator | FIFO (LUTRAM) | 0 | 64 | 0 |
| initiator_r_resp | simple_initiator | FIFO (LUTRAM) | 0 | 2 | 0 |
| initiator_r_last | simple_initiator | FIFO (LUTRAM) | 0 | 1 | 0 |
| initiator_aw_addr | simple_initiator | FIFO (LUTRAM) | 0 | 32 | 0 |
| initiator_aw_burst | simple_initiator | FIFO (LUTRAM) | 0 | 2 | 0 |
| initiator_aw_size | simple_initiator | FIFO (LUTRAM) | 0 | 3 | 0 |
| initiator_aw_len | simple_initiator | FIFO (LUTRAM) | 0 | 8 | 0 |
| initiator_w_data | simple_initiator | FIFO (LUTRAM) | 0 | 64 | 0 |
| initiator_w_strb | simple_initiator | FIFO (LUTRAM) | 0 | 8 | 0 |
| initiator_w_last | simple_initiator | FIFO (LUTRAM) | 0 | 1 | 0 |
| initiator_b_resp | simple_initiator | FIFO (LUTRAM) | 0 | 2 | 0 |
+--------------------+-----------------------+---------------+-------------+------------+-------+
====== 5. Accelerator Information ======
No accelerator function is generated.
====== 6. Resource Binding with Adaptive Latency ======
Binding to resource with adaptive latency is disabled.
You can enable this feature by setting config parameter 'ADAPTIVE_LATENCY_BINDING' to 1.
==================================================================
===== Summary Report for RTL Simulation and FPGA Synthesis =====
==================================================================
Project name: axi_initiator
FPGA Vendor: MICROSEMI
Device Family: PolarFire
Device: MPF300TS-1FCG1152I
Table of Contents
1. Simulation Cycle Latency
2. Timing Result
3. Resource Usage
====== 1. Simulation Cycle Latency ======
Number of calls: 1
Cycle latency: 261
SW/HW co-simulation: PASS
====== 2. Timing Result ======
+--------------+---------------+-------------+-------------+----------+-------------+
| Clock Domain | Target Period | Target Fmax | Worst Slack | Period | Fmax |
+--------------+---------------+-------------+-------------+----------+-------------+
| clk | 10.000 ns | 100.000 MHz | 7.647 ns | 2.353 ns | 424.989 MHz |
+--------------+---------------+-------------+-------------+----------+-------------+
The reported Fmax is for the HLS core in isolation (from Libero's post-place-and-route timing analysis).
When the HLS core is integrated into a larger system, the system Fmax may be lower depending on the critical path of the system.
====== 3. Resource Usage ======
+--------------------------+---------------+--------+------------+
| Resource Type | Used | Total | Percentage |
+--------------------------+---------------+--------+------------+
| Fabric + Interface 4LUT* | 428 + 0 = 428 | 299544 | 0.14 |
| Fabric + Interface DFF* | 206 + 0 = 206 | 299544 | 0.07 |
| I/O Register | 0 | 1536 | 0.00 |
| User I/O | 0 | 512 | 0.00 |
| uSRAM | 0 | 2772 | 0.00 |
| LSRAM | 0 | 952 | 0.00 |
| Math | 0 | 924 | 0.00 |
+--------------------------+---------------+--------+------------+
* Interface 4LUTs and DFFs are occupied due to the uses of LSRAM, Math, and uSRAM.
Number of interface 4LUTs/DFFs = (36 * #.LSRAM) + (36 * #.Math) + (12 * #.uSRAM) = (36 * 0) + (36 * 0) + (12 * 0) = 0.
#include <hls/axi_interface.hpp>
1. AxiInterface クラスのインスタンスを作成し、テンプレートパラメータを使用してアドレス幅、データ幅、およびwstrb幅を指定します。
2. トップレベル関数を参照して、作成したインスタンスを渡します。例えば、
void MyTop(AxiInterface* ADDR: */ ap_uint<32>, /* DATA: */ ap_uint<64>, /* WSTRB: */ ap_uint<8>> &master);
3. ヘッダーで定義されているユーティリティ関数(API)を使用して、AXIマスターインターフェイスを制御します。
// Request to read data in burst.
axi_m_read_req<ap_uint<32>, ap_uint<64>, ap_uint<8>>(initiator, r_addr, AXIM_MAX_BURST_LEN);
// Request to write data in burst.
axi_m_write_req<ap_uint<32>, ap_uint<64>, ap_uint<8>>(initiator, w_addr, AXIM_MAX_BURST_LEN);
// Write back the data we read + 1.
ap_uint<64> data = axi_m_read_data<ap_uint<32>, ap_uint<64>>(initiator);
axi_m_write_data<ap_uint<32>, ap_uint<64>, ap_uint<8>>(initiator, ap_uint<64>(data + 1), ap_uint<8>(0xFF), is_last);
// After the last write, read the response code.
ap_uint<2> bresp = axi_m_write_resp(initiator);
AXI4スレーブインターフェイスと同じように、このAXI4マスターインターフェイスライブラリは、バーストの追加サポートを備えたAXI4-liteプロトコルのみをサポートします。
SW / HW協調シミュレーションはAXIマスターでサポートされていますが、カーネルが呼び出される前に、ソフトウェアでAXIマスターに対するAXIスレーブの応答をモデル化する必要があります。
sum_result = 101010366
xor_result = fefefeea
or_result = ffffffff
PASS
// ----------------------------------------------------------------------------
// Smart High-Level Synthesis Tool Version 2021.2
// Copyright (c) 2015-2021 Microchip Technology Inc. All Rights Reserved.
// For support, please contact: smarthls@microchip.com
// Date: Wed Dec 22 20:32:01 2021
// ----------------------------------------------------------------------------
SmartHLS Summary Report for Project: axi_target.
Table of Contents
1. RTL Interface
2. Scheduling Result
3. Pipeline Result
4. Memory Usage
5. Accelerator Information
6. Resource Binding with Adaptive Latency
====== 1. RTL Interface ======
+-------------------------------------------------------------------------------------------+
| RTL Interface Generated by SmartHLS |
+---------------+----------------+--------------------+------------------+------------------+
| C++ Name | Interface Type | Signal Name | Signal Bit-width | Signal Direction |
+---------------+----------------+--------------------+------------------+------------------+
| | Control | clk | 1 | input |
| | | finish | 1 | output |
| | | ready | 1 | output |
| | | reset | 1 | input |
| | | start | 1 | input |
+---------------+----------------+--------------------+------------------+------------------+
| target_memory | AXI Slave | axi_s_ar_addr | 32 | input |
| | | axi_s_ar_burst | 2 | input |
| | | axi_s_ar_len | 8 | input |
| | | axi_s_ar_ready | 1 | output |
| | | axi_s_ar_size | 3 | input |
| | | axi_s_ar_valid | 1 | input |
| | | axi_s_aw_addr | 32 | input |
| | | axi_s_aw_burst | 2 | input |
| | | axi_s_aw_len | 8 | input |
| | | axi_s_aw_ready | 1 | output |
| | | axi_s_aw_size | 3 | input |
| | | axi_s_aw_valid | 1 | input |
| | | axi_s_b_resp | 2 | output |
| | | axi_s_b_resp_ready | 1 | input |
| | | axi_s_b_resp_valid | 1 | output |
| | | axi_s_r_data | 64 | output |
| | | axi_s_r_last | 1 | output |
| | | axi_s_r_ready | 1 | input |
| | | axi_s_r_resp | 2 | output |
| | | axi_s_r_valid | 1 | output |
| | | axi_s_w_data | 64 | input |
| | | axi_s_w_last | 1 | input |
| | | axi_s_w_ready | 1 | output |
| | | axi_s_w_strb | 8 | input |
| | | axi_s_w_valid | 1 | input |
+---------------+----------------+--------------------+------------------+------------------+
The Verilog top-level module ports that are not listed in the above table are unused. Please tie the unused input ports to 0.
====== 2. Scheduling Result ======
Please use SmartHLS's schedule viewer to examine the schedule.
Basic Block Latencies:
+------------------------------------------------+
| Function: calc_kernel (non-pipelined function) |
+-----------------------+------------------------+
| Basic Block | Cycle Latency |
+-----------------------+------------------------+
| %entry | 7 |
+-----------------------+------------------------+
+-----------------------------------------------------+
| Function: calc_kernel_orig (non-pipelined function) |
+-------------------------+---------------------------+
| Basic Block | Cycle Latency |
+-------------------------+---------------------------+
| %entry | 5 |
+-------------------------+---------------------------+
+----------------------------------------------------+
| Function: target_memory_write (pipelined function) |
+--------------------------+-------------------------+
| Basic Block | Cycle Latency |
+--------------------------+-------------------------+
| %init.check.i | 3 |
+--------------------------+-------------------------+
+---------------------------------------------------+
| Function: target_memory_read (pipelined function) |
+-------------------------+-------------------------+
| Basic Block | Cycle Latency |
+-------------------------+-------------------------+
| %init.check.i | 5 |
+-------------------------+-------------------------+
====== 3. Pipeline Result ======
+---------------------+---------------------+---------------+--------------------------------+---------------------+-----------------+-----------------+---------+
| Label | Function | Basic Block | Location in Source Code | Initiation Interval | Pipeline Length | Iteration Count | Latency |
+---------------------+---------------------+---------------+--------------------------------+---------------------+-----------------+-----------------+---------+
| target_memory_write | target_memory_write | %init.check.i | line 115 of axi_slave.mmap.tmp | 1 | 3 | n/a | n/a |
| target_memory_read | target_memory_read | %init.check.i | line 119 of axi_slave.mmap.tmp | 1 | 5 | n/a | n/a |
+---------------------+---------------------+---------------+--------------------------------+---------------------+-----------------+-----------------+---------+
====== 4. Memory Usage ======
+--------------------------------------------------------------------------------------------------------------------------------------------+
| Local Memories |
+---------------------------------------------------------+-----------------------+-----------------------+-------------+------------+-------+
| Name | Accessing Function(s) | Type | Size [Bits] | Data Width | Depth |
+---------------------------------------------------------+-----------------------+-----------------------+-------------+------------+-------+
| axi_s_read_state | target_memory_read | Register | 1 | 1 | 1 |
| axi_s_read_word_addr | target_memory_read | Register | 32 | 32 | 1 |
| init_flag_ZGVZ10axi_s_readIN3hls7ap_uintILj32EEENS | target_memory_read | Register (Write-Only) | 1 | 1 | 1 |
| init_flag_ZGVZ10axi_s_readIN3hls7ap_uintILj32EEENS_var0 | target_memory_read | Register (Write-Only) | 1 | 1 | 1 |
| init_flag_ZGVZ11axi_s_writeIN3hls7ap_uintILj32EEEN | target_memory_write | Register (Write-Only) | 1 | 1 | 1 |
| init_flag_ZGVZ10axi_s_readIN3hls7ap_uintILj32EEENS_var1 | target_memory_read | Register (Write-Only) | 1 | 1 | 1 |
| axi_s_read_burst_len_minus1 | target_memory_read | Register | 8 | 8 | 1 |
| axi_s_read_count | target_memory_read | Register | 8 | 8 | 1 |
| axi_s_write_state | target_memory_write | Register | 1 | 1 | 1 |
| axi_s_write_word_addr | target_memory_write | Register | 32 | 32 | 1 |
| axi_s_write_count | target_memory_write | Register | 8 | 8 | 1 |
| init_flag_ZGVZ11axi_s_writeIN3hls7ap_uintILj32EEEN_var0 | target_memory_write | Register (Write-Only) | 1 | 1 | 1 |
+---------------------------------------------------------+-----------------------+-----------------------+-------------+------------+-------+
+-------------------------+
| Local Constant Memories |
+-------------------------+
| None |
+-------------------------+
+------------------------------------------------------------------------------------------------------------------------------------+
| Shared Local Memories |
+--------------------------+-----------------------------------------------------------+----------+-------------+------------+-------+
| Name | Accessing Function(s) | Type | Size [Bits] | Data Width | Depth |
+--------------------------+-----------------------------------------------------------+----------+-------------+------------+-------+
| target_memory_arr_a0 | calc_kernel_orig, target_memory_read, target_memory_write | Register | 8 | 8 | 1 |
| target_memory_arr_a1 | calc_kernel_orig, target_memory_read, target_memory_write | Register | 8 | 8 | 1 |
| target_memory_arr_a2 | calc_kernel_orig, target_memory_read, target_memory_write | Register | 8 | 8 | 1 |
| target_memory_arr_a3 | calc_kernel_orig, target_memory_read, target_memory_write | Register | 8 | 8 | 1 |
| target_memory_arr_a4 | calc_kernel_orig, target_memory_read, target_memory_write | Register | 8 | 8 | 1 |
| target_memory_arr_a5 | calc_kernel_orig, target_memory_read, target_memory_write | Register | 8 | 8 | 1 |
| target_memory_arr_a6 | calc_kernel_orig, target_memory_read, target_memory_write | Register | 8 | 8 | 1 |
| target_memory_arr_a7 | calc_kernel_orig, target_memory_read, target_memory_write | Register | 8 | 8 | 1 |
| target_memory_a | calc_kernel_orig, target_memory_read, target_memory_write | Register | 32 | 32 | 1 |
| target_memory_b | calc_kernel_orig, target_memory_read, target_memory_write | Register | 32 | 32 | 1 |
| target_memory_sum_result | calc_kernel_orig, target_memory_read, target_memory_write | Register | 64 | 64 | 1 |
| target_memory_xor_result | calc_kernel_orig, target_memory_read, target_memory_write | Register | 32 | 32 | 1 |
| target_memory_or_result | calc_kernel_orig, target_memory_read, target_memory_write | Register | 32 | 32 | 1 |
| target_memory_ctrl | target_memory_read, target_memory_write | Register | 1 | 1 | 1 |
+--------------------------+-----------------------------------------------------------+----------+-------------+------------+-------+
+------------------+
| Aliased Memories |
+------------------+
| None |
+------------------+
+-------------------------------------------------------------------------------------------+
| I/O Memories |
+----------------+-----------------------+---------------+-------------+------------+-------+
| Name | Accessing Function(s) | Type | Size [Bits] | Data Width | Depth |
+----------------+-----------------------+---------------+-------------+------------+-------+
| axi_s_ar_addr | target_memory_read | FIFO (LUTRAM) | 0 | 32 | 0 |
| axi_s_ar_burst | target_memory_read | FIFO (LUTRAM) | 0 | 2 | 0 |
| axi_s_ar_size | target_memory_read | FIFO (LUTRAM) | 0 | 3 | 0 |
| axi_s_ar_len | target_memory_read | FIFO (LUTRAM) | 0 | 8 | 0 |
| axi_s_r_data | target_memory_read | FIFO (LUTRAM) | 0 | 64 | 0 |
| axi_s_r_resp | target_memory_read | FIFO (LUTRAM) | 0 | 2 | 0 |
| axi_s_r_last | target_memory_read | FIFO (LUTRAM) | 0 | 1 | 0 |
| axi_s_aw_addr | target_memory_write | FIFO (LUTRAM) | 0 | 32 | 0 |
| axi_s_aw_burst | target_memory_write | FIFO (LUTRAM) | 0 | 2 | 0 |
| axi_s_aw_size | target_memory_write | FIFO (LUTRAM) | 0 | 3 | 0 |
| axi_s_aw_len | target_memory_write | FIFO (LUTRAM) | 0 | 8 | 0 |
| axi_s_w_data | target_memory_write | FIFO (LUTRAM) | 0 | 64 | 0 |
| axi_s_w_strb | target_memory_write | FIFO (LUTRAM) | 0 | 8 | 0 |
| axi_s_w_last | target_memory_write | FIFO (LUTRAM) | 0 | 1 | 0 |
| axi_s_b_resp | target_memory_write | FIFO (LUTRAM) | 0 | 2 | 0 |
+----------------+-----------------------+---------------+-------------+------------+-------+
====== 5. Accelerator Information ======
No accelerator function is generated.
====== 6. Resource Binding with Adaptive Latency ======
Binding to resource with adaptive latency is disabled.
You can enable this feature by setting config parameter 'ADAPTIVE_LATENCY_BINDING' to 1.
==================================================================
===== Summary Report for RTL Simulation and FPGA Synthesis =====
==================================================================
Project name: axi_target
FPGA Vendor: MICROSEMI
Device Family: PolarFire
Device: MPF300TS-1FCG1152I
Table of Contents
1. Simulation Cycle Latency
2. Timing Result
3. Resource Usage
====== 1. Simulation Cycle Latency ======
Number of calls: 1
Cycle latency: 17
SW/HW co-simulation: PASS
====== 2. Timing Result ======
+--------------+---------------+-------------+-------------+----------+-------------+
| Clock Domain | Target Period | Target Fmax | Worst Slack | Period | Fmax |
+--------------+---------------+-------------+-------------+----------+-------------+
| clk | 10.000 ns | 100.000 MHz | 7.625 ns | 2.375 ns | 421.053 MHz |
+--------------+---------------+-------------+-------------+----------+-------------+
The reported Fmax is for the HLS core in isolation (from Libero's post-place-and-route timing analysis).
When the HLS core is integrated into a larger system, the system Fmax may be lower depending on the critical path of the system.
====== 3. Resource Usage ======
+--------------------------+-----------------+--------+------------+
| Resource Type | Used | Total | Percentage |
+--------------------------+-----------------+--------+------------+
| Fabric + Interface 4LUT* | 985 + 0 = 985 | 299544 | 0.33 |
| Fabric + Interface DFF* | 1230 + 0 = 1230 | 299544 | 0.41 |
| I/O Register | 0 | 1536 | 0.00 |
| User I/O | 0 | 512 | 0.00 |
| uSRAM | 0 | 2772 | 0.00 |
| LSRAM | 0 | 952 | 0.00 |
| Math | 0 | 924 | 0.00 |
+--------------------------+-----------------+--------+------------+
* Interface 4LUTs and DFFs are occupied due to the uses of LSRAM, Math, and uSRAM.
Number of interface 4LUTs/DFFs = (36 * #.LSRAM) + (36 * #.Math) + (12 * #.uSRAM) = (36 * 0) + (36 * 0) + (12 * 0) = 0.
重要:AXI4スレーブにはいくつかの制限があります。
・SmartHLSモジュールは最大で1つのAXI4スレーブインターフェイスを持つことができ、AXI4スレーブインターフェイスタイプは、構造体データタイプのグローバル変数に対してのみ指定できます。
・複数のデータをAXI4スレーブインターフェイスの背後に配置する必要がある場合は、すべてのデータを含む新しい構造体タイプを定義してから、構造体タイプでグローバル変数をインスタンス化し、グローバル変数に上記のプラグマを指定できます。
・AXI4スレーブインターフェイスは常に32ビットアドレスと64ビットデータ幅を使用します。
・AXI4スレーブインターフェイスは、インクリメンタルバーストの追加サポートを備えたAXI4-liteプロトコルのみをサポートします。
・AxBURSTおよびAxSIZE入力信号は、スレーブロジックによって無視されます。
・AxBURSTおよびAxSIZE信号の実際の入力値に関係なく、AXI4スレーブは常にインクリメンタルバーストタイプ(AxBURST == 1)を使用し、転送あたりのサイズは8バイト(AxSIZE == 3)です。
・バイトイネーブル書き込み(WSTRBポート経由)は、構造体の要素に揃える必要があります。
・共通の構造体要素(の異なるバイト)に対応するWSTRBビットの場合、これらのWSTRBビットはすべて1またはすべて0である必要があります。
・たとえば、2つの「int」型整数(それぞれ4バイト、1つの64ビットAXIワードとして一緒にパック)にマップするワードアドレスに書き込む場合、WSTRBポートの上位4ビットはすべて1または0である必要があります。 、および同じことがWSTRBポートの下位4ビットにも当てはまります。つまり、どちらの 'int'型整数の部分バイトも更新できませんが、2つの 'int'型整数のいずれかのすべてのバイトを更新することはできます。
・SW / HW協調シミュレーションは、最上位機能がパイプライン化されていない場合にのみサポートされます。
・AXI4スレーブインターフェイスを使用する場合、最上位関数はvoid戻り型を使用する必要があります。
のプラグマを付けるようだ。#pragma HLS interface variable(target_memory) type(axi_slave) (注: concurrent_access(true|false) というオプションもあるようだ)
struct TargetLayout target_memory;
#ifndef __AXI_TARGET_H__
#define __AXI_TARGET_H__
#include <cstdint>
struct TargetLayout {
uint8_t arr[8];
uint32_t a;
uint32_t b;
uint64_t sum_result;
uint32_t xor_result;
uint32_t or_result;
};
#endif // __AXI_TARGET_H__
// ----------------------------------------------------------------------------
// Smart High-Level Synthesis Tool Version 2021.2
// Copyright (c) 2015-2021 Microchip Technology Inc. All Rights Reserved.
// For support, please contact: smarthls@microchip.com
// Date: Sun Dec 19 04:04:22 2021
// ----------------------------------------------------------------------------
SmartHLS Summary Report for Project: sobel_part3.
Table of Contents
1. RTL Interface
2. Scheduling Result
3. Pipeline Result
4. Memory Usage
5. Accelerator Information
6. Resource Binding with Adaptive Latency
====== 1. RTL Interface ======
+-------------------------------------------------------------------------------------------+
| RTL Interface Generated by SmartHLS |
+-------------+-------------------+-------------------+------------------+------------------+
| C++ Name | Interface Type | Signal Name | Signal Bit-width | Signal Direction |
+-------------+-------------------+-------------------+------------------+------------------+
| | Control | clk | 1 | input |
| | | finish | 1 | output |
| | | ready | 1 | output |
| | | reset | 1 | input |
| | | start | 1 | input |
+-------------+-------------------+-------------------+------------------+------------------+
| input_fifo | Input AXI Stream | input_fifo_ready | 1 | output |
| | | input_fifo_valid | 1 | input |
| | | input_fifo | 8 | input |
+-------------+-------------------+-------------------+------------------+------------------+
| output_fifo | Output AXI Stream | output_fifo_ready | 1 | input |
| | | output_fifo_valid | 1 | output |
| | | output_fifo | 8 | output |
+-------------+-------------------+-------------------+------------------+------------------+
The Verilog top-level module ports that are not listed in the above table are unused. Please tie the unused input ports to 0.
====== 2. Scheduling Result ======
Please use SmartHLS's schedule viewer to examine the schedule.
Basic Block Latencies:
+---------------------------------------------+
| Function: sobel_filter (pipelined function) |
+---------------------+-----------------------+
| Basic Block | Cycle Latency |
+---------------------+-----------------------+
| %init.check | 12 |
+---------------------+-----------------------+
====== 3. Pipeline Result ======
+--------------+--------------+-------------+-------------------------+---------------------+-----------------+-----------------+---------+
| Label | Function | Basic Block | Location in Source Code | Initiation Interval | Pipeline Length | Iteration Count | Latency |
+--------------+--------------+-------------+-------------------------+---------------------+-----------------+-----------------+---------+
| sobel_filter | sobel_filter | %init.check | line 12 of sobel.cpp | 1 | 12 | n/a | n/a |
+--------------+--------------+-------------+-------------------------+---------------------+-----------------+-----------------+---------+
====== 4. Memory Usage ======
+---------------------------------------------------------------------------------------------------------------------------------------+
| Local Memories |
+----------------------------------------------------+-----------------------+-----------------------+-------------+------------+-------+
| Name | Accessing Function(s) | Type | Size [Bits] | Data Width | Depth |
+----------------------------------------------------+-----------------------+-----------------------+-------------+------------+-------+
| sobel_filter_i | sobel_filter | Register | 32 | 32 | 1 |
| sobel_filter_j | sobel_filter | Register | 32 | 32 | 1 |
| sobel_filter_line_buffer_window_a0_a1 | sobel_filter | Register | 8 | 8 | 1 |
| sobel_filter_line_buffer_window_a0_a2 | sobel_filter | Register | 8 | 8 | 1 |
| sobel_filter_line_buffer_window_a1_a1 | sobel_filter | Register | 8 | 8 | 1 |
| sobel_filter_line_buffer_window_a1_a2 | sobel_filter | Register | 8 | 8 | 1 |
| sobel_filter_line_buffer_window_a2_a1 | sobel_filter | Register | 8 | 8 | 1 |
| sobel_filter_line_buffer_window_a2_a2 | sobel_filter | Register | 8 | 8 | 1 |
| sobel_filter_line_buffer_prev_row_index | sobel_filter | Register | 32 | 32 | 1 |
| sobel_filter_line_buffer_prev_row_a0_a0 | sobel_filter | RAM | 4096 | 8 | 512 |
| sobel_filter_line_buffer_prev_row_a1_a0 | sobel_filter | RAM | 4096 | 8 | 512 |
| sobel_filter_count | sobel_filter | Register | 32 | 32 | 1 |
| init_flag_ZGVZ12sobel_filterRN3hls4FIFOIhLb0EEES2_ | sobel_filter | Register (Write-Only) | 1 | 1 | 1 |
+----------------------------------------------------+-----------------------+-----------------------+-------------+------------+-------+
+-------------------------+
| Local Constant Memories |
+-------------------------+
| None |
+-------------------------+
+-----------------------+
| Shared Local Memories |
+-----------------------+
| None |
+-----------------------+
+------------------+
| Aliased Memories |
+------------------+
| None |
+------------------+
+-------------------------------------------------------------------------------------+
| I/O Memories |
+-------------+-----------------------+------------+-------------+------------+-------+
| Name | Accessing Function(s) | Type | Size [Bits] | Data Width | Depth |
+-------------+-----------------------+------------+-------------+------------+-------+
| input_fifo | sobel_filter | FIFO (REG) | 0 | 8 | 0 |
| output_fifo | sobel_filter | FIFO (REG) | 0 | 8 | 0 |
+-------------+-----------------------+------------+-------------+------------+-------+
====== 5. Accelerator Information ======
No accelerator function is generated.
====== 6. Resource Binding with Adaptive Latency ======
Binding to resource with adaptive latency is disabled.
You can enable this feature by setting config parameter 'ADAPTIVE_LATENCY_BINDING' to 1.
// ----------------------------------------------------------------------------
// Smart High-Level Synthesis Tool Version 2021.2
// Copyright (c) 2015-2021 Microchip Technology Inc. All Rights Reserved.
// For support, please contact: smarthls@microchip.com
// Date: Sat Dec 18 03:58:32 2021
// ----------------------------------------------------------------------------
SmartHLS Summary Report for Project: sobel_part3.
Table of Contents
1. RTL Interface
2. Scheduling Result
3. Pipeline Result
4. Memory Usage
5. Accelerator Information
6. Resource Binding with Adaptive Latency
====== 1. RTL Interface ======
+-------------------------------------------------------------------------------------------+
| RTL Interface Generated by SmartHLS |
+-------------+-------------------+-------------------+------------------+------------------+
| C++ Name | Interface Type | Signal Name | Signal Bit-width | Signal Direction |
+-------------+-------------------+-------------------+------------------+------------------+
| | Control | clk | 1 | input |
| | | finish | 1 | output |
| | | ready | 1 | output |
| | | reset | 1 | input |
| | | start | 1 | input |
+-------------+-------------------+-------------------+------------------+------------------+
| input_fifo | Input AXI Stream | input_fifo_ready | 1 | output |
| | | input_fifo_valid | 1 | input |
| | | input_fifo | 8 | input |
+-------------+-------------------+-------------------+------------------+------------------+
| output_fifo | Output AXI Stream | output_fifo_ready | 1 | input |
| | | output_fifo_valid | 1 | output |
| | | output_fifo | 8 | output |
+-------------+-------------------+-------------------+------------------+------------------+
The Verilog top-level module ports that are not listed in the above table are unused. Please tie the unused input ports to 0.
====== 2. Scheduling Result ======
Please use SmartHLS's schedule viewer to examine the schedule.
Basic Block Latencies:
+---------------------------------------------+
| Function: sobel_filter (pipelined function) |
+---------------------+-----------------------+
| Basic Block | Cycle Latency |
+---------------------+-----------------------+
| %init.check | 7 |
+---------------------+-----------------------+
====== 3. Pipeline Result ======
+--------------+--------------+-------------+-------------------------+---------------------+-----------------+-----------------+---------+
| Label | Function | Basic Block | Location in Source Code | Initiation Interval | Pipeline Length | Iteration Count | Latency |
+--------------+--------------+-------------+-------------------------+---------------------+-----------------+-----------------+---------+
| sobel_filter | sobel_filter | %init.check | line 12 of sobel.cpp | 1 | 7 | n/a | n/a |
+--------------+--------------+-------------+-------------------------+---------------------+-----------------+-----------------+---------+
====== 4. Memory Usage ======
+---------------------------------------------------------------------------------------------------------------------------------------+
| Local Memories |
+----------------------------------------------------+-----------------------+-----------------------+-------------+------------+-------+
| Name | Accessing Function(s) | Type | Size [Bits] | Data Width | Depth |
+----------------------------------------------------+-----------------------+-----------------------+-------------+------------+-------+
| sobel_filter_i | sobel_filter | Register | 32 | 32 | 1 |
| sobel_filter_j | sobel_filter | Register | 32 | 32 | 1 |
| sobel_filter_line_buffer_window_a0_a1 | sobel_filter | Register | 8 | 8 | 1 |
| sobel_filter_line_buffer_window_a0_a2 | sobel_filter | Register | 8 | 8 | 1 |
| sobel_filter_line_buffer_window_a1_a1 | sobel_filter | Register | 8 | 8 | 1 |
| sobel_filter_line_buffer_window_a1_a2 | sobel_filter | Register | 8 | 8 | 1 |
| sobel_filter_line_buffer_window_a2_a1 | sobel_filter | Register | 8 | 8 | 1 |
| sobel_filter_line_buffer_window_a2_a2 | sobel_filter | Register | 8 | 8 | 1 |
| sobel_filter_line_buffer_prev_row_index | sobel_filter | Register | 32 | 32 | 1 |
| sobel_filter_line_buffer_prev_row_a0_a0 | sobel_filter | RAM | 4096 | 8 | 512 |
| sobel_filter_line_buffer_prev_row_a1_a0 | sobel_filter | RAM | 4096 | 8 | 512 |
| sobel_filter_count | sobel_filter | Register | 32 | 32 | 1 |
| init_flag_ZGVZ12sobel_filterRN3hls4FIFOIhLb0EEES2_ | sobel_filter | Register (Write-Only) | 1 | 1 | 1 |
+----------------------------------------------------+-----------------------+-----------------------+-------------+------------+-------+
+-------------------------+
| Local Constant Memories |
+-------------------------+
| None |
+-------------------------+
+-----------------------+
| Shared Local Memories |
+-----------------------+
| None |
+-----------------------+
+------------------+
| Aliased Memories |
+------------------+
| None |
+------------------+
+-------------------------------------------------------------------------------------+
| I/O Memories |
+-------------+-----------------------+------------+-------------+------------+-------+
| Name | Accessing Function(s) | Type | Size [Bits] | Data Width | Depth |
+-------------+-----------------------+------------+-------------+------------+-------+
| input_fifo | sobel_filter | FIFO (REG) | 0 | 8 | 0 |
| output_fifo | sobel_filter | FIFO (REG) | 0 | 8 | 0 |
+-------------+-----------------------+------------+-------------+------------+-------+
====== 5. Accelerator Information ======
No accelerator function is generated.
====== 6. Resource Binding with Adaptive Latency ======
Binding to resource with adaptive latency is disabled.
You can enable this feature by setting config parameter 'ADAPTIVE_LATENCY_BINDING' to 1.
==================================================================
===== Summary Report for RTL Simulation and FPGA Synthesis =====
==================================================================
Project name: sobel_part3
FPGA Vendor: MICROSEMI
Device Family: SmartFusion2
Device: M2S010-VF256
Table of Contents
1. Simulation Cycle Latency
2. Timing Result
3. Resource Usage
====== 1. Simulation Cycle Latency ======
Number of calls: 262,658
Cycle latency: 262,667
SW/HW co-simulation: PASS
====== 2. Timing Result ======
+--------------+---------------+-------------+-------------+----------+-------------+
| Clock Domain | Target Period | Target Fmax | Worst Slack | Period | Fmax |
+--------------+---------------+-------------+-------------+----------+-------------+
| clk | 10.000 ns | 100.000 MHz | 5.076 ns | 4.924 ns | 203.087 MHz |
+--------------+---------------+-------------+-------------+----------+-------------+
The reported Fmax is for the HLS core in isolation (from Libero's post-place-and-route timing analysis).
When the HLS core is integrated into a larger system, the system Fmax may be lower depending on the critical path of the system.
====== 3. Resource Usage ======
+--------------------------+-----------------+-------+------------+
| Resource Type | Used | Total | Percentage |
+--------------------------+-----------------+-------+------------+
| Fabric + Interface 4LUT* | 453 + 288 = 741 | 12084 | 6.13 |
| Fabric + Interface DFF* | 378 + 288 = 666 | 12084 | 5.51 |
| I/O Register | 0 | 414 | 0.00 |
| User I/O | 0 | 138 | 0.00 |
| RAM64x18 | 8 | 22 | 36.36 |
| RAM1K18 | 0 | 21 | 0.00 |
| MACC | 0 | 22 | 0.00 |
+--------------------------+-----------------+-------+------------+
* Interface 4LUTs and DFFs are occupied due to the uses of MACC, RAM1K18, and RAM64x18.
Number of interface 4LUTs/DFFs = (36 * #.MACC) + (36 * #.RAM1K18) + (36 * #.RAM64x18) = (36 * 0) + (36 * 0) + (36 * 8) = 288.
日 | 月 | 火 | 水 | 木 | 金 | 土 |
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18 | 19 | 20 | 21 | 22 | 23 | 24 |
25 | 26 | 27 | 28 | 29 | 30 | - |