ERROR:Route:472 -
This design is unrouteable.
To evaluate the problem please use fpga_editor.
Routing Conflict 1:
Net:GLOBAL_LOGIC0 on pin SR on location OLOGIC_X0Y111
Net:SYS_RST_IBUF_1 on pin SR on location ILOGIC_X0Y111
Conflict detected on wire: PINFEED(-63835,80448)
Routing Conflict 2:
Net:GLOBAL_LOGIC0 on pin SR on location OLOGIC_X0Y113
Net:SYS_RST_IBUF_1 on pin SR on location ILOGIC_X0Y113
Conflict detected on wire: PINFEED(-63835,84320)
// Instantiate DQS DDR registers
generate
genvar n;
for (n=DDR2_DQS_DM_WIDTH-1; n>=0; n=n-1) begin: WRDATA_DQS
OSERDES # (
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("DDR"),
.DATA_WIDTH(4),
.INIT_OQ(1'b0),
.INIT_TQ(1'b1),
.SERDES_MODE("MASTER"),
.SRVAL_OQ(1'b0),
.SRVAL_TQ(1'b1),
.TRISTATE_WIDTH(4)
) WRDATA_DDR2_OUT (
.OQ(dqs_oq[n]),
.SHIFTOUT1(),
.SHIFTOUT2(),
.TQ(dqs_tq[n]),
.CLK(clk),
.CLKDIV(clk100MHz),
.D1(dqs_oserdes_d_1d[n*4]),
.D2(dqs_oserdes_d_1d[n*4+1]),
.D3(dqs_oserdes_d_1d[n*4+2]),
.D4(dqs_oserdes_d_1d[n*4+3]),
.D5(),
.D6(),
.OCE(1'b1),
.REV(1'b0),
.SHIFTIN1(1'b0),
.SHIFTIN2(1'b0),
// .SR(dqs_reset_3d[n]),
.SR(1'b0),
.T1(dqs_oserdes_t_1d[n*4]),
.T2(dqs_oserdes_t_1d[n*4+1]),
.T3(dqs_oserdes_t_1d[n*4+2]),
.T4(dqs_oserdes_t_1d[n*4+3]),
.TCE(1'b1)
);
ISERDES #(
.BITSLIP_ENABLE("TRUE"),
.DATA_RATE("DDR"),
.DATA_WIDTH(4),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.IOBDELAY_TYPE("FIXED"),
.IOBDELAY_VALUE(32),
.NUM_CE(1),
.SERDES_MODE("MASTER")
) DQS_DDR2_IN (
.O(ddr2_dqsin_out[n]),
.Q1(),
.Q2(),
.Q3(),
.Q4(),
.Q5(),
.Q6(),
.SHIFTOUT1(),
.SHIFTOUT2(),
.BITSLIP(1'b0),
.CE1(1'b1),
.CE2(1'b1),
.CLK(1'b0),
.CLKDIV(1'b0),
.D(ddr2_dqsin[n]),
.DLYCE(1'b0),
.DLYINC(1'b0),
.DLYRST(1'b0),
.OCLK(1'b0),
.REV(1'b0),
.SHIFTIN1(1'b0),
.SHIFTIN2(1'b0),
.SR(reset)
);
BUFIO DQS_DDR2_IN_BUFIO (
.I(ddr2_dqsin_out[n]),
.O(ddr2_dqsin_bufio[n])
);
IOBUF DDD2_DQS_BUF (
.O(ddr2_dqsin[n]),
.IO(ddr2_dqs[n]),
.I(dqs_oq[n]),
.T(dqs_tq[n])
);
end
endgenerate
Routing Conflict 1:
Net:ddr2_sdram_cont_inst/clk90 on pin CLK on location OLOGIC_X0Y97
Net:clk on pin OCLK on location ILOGIC_X0Y97
Conflict detected on wire: BOUNCEIN(-63349,57088)
`default_nettype none
`timescale 1ps/1ps
module serial_parallel_converter_tb;
reg Din = 1'b0;
reg clk_in = 1'b0;
reg rst = 1'b1; // reset
reg bitslip = 1'b1; // bitslip mode
reg enable = 1'b0;
wire [9:0] recv_data;
wire [9:0] q_out;
wire [9:0] para10bits;
wire outbit;
integer i;
parameter PERIOD = 5000; // 5ns, 200MHz
parameter real DUTY_CYCLE = 0.5;
parameter OFFSET = 0;
initial // Clock process for clk
begin
#OFFSET;
forever
begin
clk_in = 1'b0;
#(PERIOD-(PERIOD*DUTY_CYCLE)) clk_in = 1'b1;
#(PERIOD*DUTY_CYCLE);
end
end
serial_parallel_converter UUT (
.Din(Din),
.clk_in(clk_in),
.rst(rst),
.bitslip(bitslip),
.enable(enable),
.recv_data(recv_data),
.q_out(q_out)
);
initial begin // 10bitを出力
#100000; // GSRリセットを待つ
#(PERIOD);
rst = 1'b0;
#(PERIOD);
enable = 1'b1;
@(posedge UUT.clkdiv); // clkdivの立ち上がりまでWait
#(PERIOD); // 1clk_inの半分の時間を進める
#(PERIOD/4);
Out10bits(10'b01_0100_1010);
Out10bits(10'b01_0100_1010);
Out10bits(10'b01_0100_1010);
Out10bits(10'b01_0100_1010);
Out10bits(10'b01_0100_1010);
Out10bits(10'b01_0100_1010);
Out10bits(10'b01_0100_1010);
Out10bits(10'b01_0100_1010);
Out10bits(10'b01_0100_1010);
Out10bits(10'b01_0100_1010);
Out10bits(10'b01_0100_1010);
Out10bits(10'b01_0100_1010);
Out10bits(10'b01_0100_1010);
Out10bits(10'b01_0100_1010);
Out10bits(10'b01_0100_1010);
Out10bits(10'b01_0100_1010);
Out10bits(10'b01_0100_1010);
Out10bits(10'b01_0100_1010);
Out10bits(10'b01_0100_1010);
Out10bits(10'b01_0100_1010);
Out10bits(10'b01_0100_1010);
Out10bits(10'b01_0100_1010);
Out10bits(10'b01_0100_1010);
Out10bits(10'b01_0100_1010);
Out10bits(10'b01_0100_1010);
Out10bits(10'b01_0100_1010);
Out10bits(10'b01_0100_1010);
Out10bits(10'b01_0100_1010);
#100000
$stop;
end
task Out10bits;
input [9:0] para10bits;
integer i;
begin
for (i=0; i<10; i=i+1)
Out1bit(para10bits[9-i]);
end
endtask
task Out1bit;
input outbit;
begin
Din = outbit;
#(PERIOD/2);
end
endtask
initial begin // データがあってから7つ数えてbitslipを0に。
// 10'b01_0100_1010の1つ前の立ち上がりでbitslipを0にする必要がある
@(posedge UUT.clkdiv);
while (recv_data != 10'b01_0100_1010)
@(posedge UUT.clkdiv);
for (i=0; i<10; i=i+1) begin
@(posedge UUT.clkdiv);
if (i==7) begin
#1000;
bitslip = 1'b0;
end
end
end
endmodule
`default_nettype wire
`default_nettype none
`timescale 1ps/1ps
module serial_parallel_converter (
Din,
clk_in,
rst,
bitslip,
enable,
recv_data,
q_out
);
input Din;
input clk_in;
input rst;
input bitslip;
input enable;
output [9:0] recv_data;
output [9:0] q_out;
wire Din;
wire clk_in;
wire rst;
wire bitslip;
wire enable;
wire [9:0] recv_data;
wire [9:0] q_out;
wire iserdes_clkout;
wire iobclk;
wire clkdiv;
wire shiftdata1;
wire shiftdata2;
wire [9:0] data_internal;
reg [9:0] data;
// Instantiate ISERDES for forwarded clock
ISERDES fwd_clk (
.O(iserdes_clkout),
.Q1(),
.Q2(),
.Q3(),
.Q4(),
.Q5(),
.Q6(),
.SHIFTOUT1(),
.SHIFTOUT2(),
.BITSLIP(1'b0),
.CE1(1'b1),
.CE2(1'b1),
.CLK(iobclk),
.CLKDIV(clkdiv),
.D(clk_in),
.DLYCE(1'b0),
.DLYINC(1'b0),
.DLYRST(1'b0),
.OCLK(1'b0),
.REV(1'b0),
.SHIFTIN1(1'b0),
.SHIFTIN2(1'b0),
.SR(rst)
);
defparam fwd_clk.BITSLIP_ENABLE = "TRUE";
defparam fwd_clk.DATA_RATE = "DDR";
defparam fwd_clk.DATA_WIDTH = 4;
defparam fwd_clk.INTERFACE_TYPE = "NETWORKING";
defparam fwd_clk.IOBDELAY = "NONE";
defparam fwd_clk.IOBDELAY_TYPE = "DEFAULT";
defparam fwd_clk.IOBDELAY_VALUE = 0;
defparam fwd_clk.NUM_CE = 1;
defparam fwd_clk.SERDES_MODE = "MASTER";
// Instantiate Master ISERDES for data channel
// 1:10 Deserialization Factor
ISERDES data_chan_master (
.O(),
.Q1(data_internal[0]),
.Q2(data_internal[1]),
.Q3(data_internal[2]),
.Q4(data_internal[3]),
.Q5(data_internal[4]),
.Q6(data_internal[5]),
.SHIFTOUT1(shiftdata1),
.SHIFTOUT2(shiftdata2),
.BITSLIP(bitslip),
.CE1(enable),
.CE2(1'b1),
.CLK(iobclk),
.CLKDIV(clkdiv),
.D(Din),
.DLYCE(1'b0),
.DLYINC(1'b0),
.DLYRST(1'b0),
.OCLK(1'b0),
.REV(1'b0),
.SHIFTIN1(1'b0),
.SHIFTIN2(1'b0),
.SR(rst)
);
defparam data_chan_master.BITSLIP_ENABLE = "TRUE";
defparam data_chan_master.DATA_RATE = "DDR";
defparam data_chan_master.DATA_WIDTH = 10;
defparam data_chan_master.INTERFACE_TYPE = "NETWORKING";
defparam data_chan_master.IOBDELAY = "NONE";
defparam data_chan_master.IOBDELAY_TYPE = "DEFAULT";
defparam data_chan_master.IOBDELAY_VALUE = 0;
defparam data_chan_master.NUM_CE = 1;
defparam data_chan_master.SERDES_MODE = "MASTER";
//
// Instantiate Slave ISERDES for data channel
// 1:10 Deserialization Factor
ISERDES data_chan_slave (
.O(),
.Q1(),
.Q2(),
.Q3(data_internal[6]),
.Q4(data_internal[7]),
.Q5(data_internal[8]),
.Q6(data_internal[9]),
.SHIFTOUT1(),
.SHIFTOUT2(),
.BITSLIP(bitslip),
.CE1(enable),
.CE2(1'b1),
.CLK(iobclk),
.CLKDIV(clkdiv),
.D(1'b0),
.DLYCE(1'b0),
.DLYINC(1'b0),
.DLYRST(1'b0),
.OCLK(1'b0),
.REV(1'b0),
.SHIFTIN1(shiftdata1),
.SHIFTIN2(shiftdata2),
.SR(rst)
);
defparam data_chan_slave.BITSLIP_ENABLE = "TRUE";
defparam data_chan_slave.DATA_RATE = "DDR";
defparam data_chan_slave.DATA_WIDTH = 10;
defparam data_chan_slave.INIT_Q1 = 1'b0;
defparam data_chan_slave.INIT_Q2 = 1'b0;
defparam data_chan_slave.INIT_Q3 = 1'b0;
defparam data_chan_slave.INIT_Q4 = 1'b0;
defparam data_chan_slave.INTERFACE_TYPE = "NETWORKING";
defparam data_chan_slave.IOBDELAY = "NONE";
defparam data_chan_slave.IOBDELAY_TYPE = "DEFAULT";
defparam data_chan_slave.IOBDELAY_VALUE = 0;
defparam data_chan_slave.NUM_CE = 1;
defparam data_chan_slave.SERDES_MODE = "SLAVE";
defparam data_chan_slave.SRVAL_Q1 = 1'b0;
defparam data_chan_slave.SRVAL_Q2 = 1'b0;
defparam data_chan_slave.SRVAL_Q3 = 1'b0;
defparam data_chan_slave.SRVAL_Q4 = 1'b0;
//
BUFIO bufio1 (
.O(iobclk),
.I(iserdes_clkout)
);
// To get a 1:10 deserialization factor in DDR mode,
// set the clock divide factor to "5"
BUFR bufr1 (
.O(clkdiv),
.CE(1'b1),
.CLR(1'b0),
.I(iobclk)
);
defparam bufr1.BUFR_DIVIDE = "5";
always @(posedge rst, posedge clkdiv) begin
if (rst)
data <= 0;
else
data <= data_internal;
end
assign q_out = data;
assign recv_data = data_internal;
endmodule
`default_nettype none
`timescale 1ps/1ps
module serial_parallel_converter_tb;
reg Din = 1'b0;
reg clk_in = 1'b0;
reg rst = 1'b1; // reset
// reg bitslip = 1'b1; // bitslip mode
reg enable = 1'b0;
wire [9:0] recv_data;
wire [9:0] q_out;
wire [9:0] para10bits;
wire outbit;
integer j;
parameter PERIOD = 5000; // 5ns, 200MHz
parameter real DUTY_CYCLE = 0.5;
parameter OFFSET = 0;
initial // Clock process for clk
begin
#OFFSET;
forever
begin
clk_in = 1'b0;
#(PERIOD-(PERIOD*DUTY_CYCLE)) clk_in = 1'b1;
#(PERIOD*DUTY_CYCLE);
end
end
serial_parallel_converter UUT (
.Din(Din),
.clk_in(clk_in),
.rst(rst),
.bitslip(1'b0),
.enable(enable),
.recv_data(recv_data),
.q_out(q_out)
);
initial begin // 10bitを出力
#100000; // GSRリセットを待つ
#(PERIOD);
rst = 1'b0;
#(PERIOD);
enable = 1'b1;
@(posedge UUT.clkdiv); // clkdivの立ち上がりまでWait
#(PERIOD/2); // 1clk_inの半分の時間を進める
#(PERIOD/4);
Out10bits(10'b01_0100_1010);
Out10bits(10'b01_0100_1010);
Out10bits(10'b01_0100_1010);
Out10bits(10'b10_0101_1011);
#100000
$stop;
end
task Out10bits;
input [9:0] para10bits;
integer i;
begin
for (i=0; i<10; i=i+1)
Out1bit(para10bits[9-i]);
end
endtask
task Out1bit;
input outbit;
begin
Din = outbit;
#(PERIOD/2);
end
endtask
// always @* begin // q_outが10'b01_0100_1010の1つ前の10'b10_1001_0100になったらbitslipを0にする
// if (recv_data == 10'b10_1001_0100)
// bitslip = 1'b0;
// end
endmodule
`default_nettype wire
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