Target Device : xc3s500e Target Package : fg320 Target Speed : -4 Mapper Version : spartan3e -- $Revision: 1.36 $ Mapped Date : SUN 18 MAR 20:14:54 2007
Design Summary -------------- Number of errors: 0 Number of warnings: 2 Logic Utilization: Number of Slice Flip Flops: 575 out of 9,312 6% Number of 4 input LUTs: 517 out of 9,312 5% Logic Distribution: Number of occupied Slices: 581 out of 4,656 12% Number of Slices containing only related logic: 581 out of 581 100% Number of Slices containing unrelated logic: 0 out of 581 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number of 4 input LUTs: 804 out of 9,312 8% Number used as logic: 517 Number used as a route-thru: 63 Number used for Dual Port RAMs: 172 (Two LUTs used per Dual Port RAM) Number used for 32x1 RAMs: 52 (Two LUTs used per 32x1 RAM) Number of bonded IOBs: 66 out of 232 28% IOB Flip Flops: 49 Number of ODDR2s used: 38 Number of DDR_ALIGNMENT = NONE 38 Number of Block RAMs: 1 out of 20 5% Number of GCLKs: 6 out of 24 25% Number of DCMs: 3 out of 4 75%
Total equivalent gate count for design: 113,976 Additional JTAG gate count for IOBs: 3,168 Peak Memory Usage: 165 MB
次にVirtex4は下のようになった。
Target Device : xc4vlx15 Target Package : sf363 Target Speed : -10 Mapper Version : virtex4 -- $Revision: 1.36 $ Mapped Date : SUN 18 MAR 12:50:36 2007
Design Summary -------------- Number of errors: 0 Number of warnings: 4 Logic Utilization: Number of Slice Flip Flops: 577 out of 12,288 4% Number of 4 input LUTs: 609 out of 12,288 4% Logic Distribution: Number of occupied Slices: 608 out of 6,144 9% Number of Slices containing only related logic: 608 out of 608 100% Number of Slices containing unrelated logic: 0 out of 608 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number of 4 input LUTs: 896 out of 12,288 7% Number used as logic: 609 Number used as a route-thru: 63 Number used for Dual Port RAMs: 172 (Two LUTs used per Dual Port RAM) Number used for 32x1 RAMs: 52 (Two LUTs used per 32x1 RAM) Number of bonded IOBs: 66 out of 240 27% Number of BUFG/BUFGCTRLs: 6 out of 32 18% Number used as BUFGs: 6 Number used as BUFGCTRLs: 0 Number of FIFO16/RAMB16s: 1 out of 48 2% Number used as FIFO16s: 0 Number used as RAMB16s: 1 Number of DCM_ADVs: 3 out of 4 75%
Total equivalent gate count for design: 93,429 Additional JTAG gate count for IOBs: 3,168 Peak Memory Usage: 210 MB
最後にVirtex5は下のようになった。
Target Device : xc5vlx30 Target Package : ff324 Target Speed : -1 Mapper Version : virtex5 -- $Revision: 1.36 $ Mapped Date : SUN 18 MAR 13:10:3 2007
Design Summary -------------- Number of errors: 0 Number of warnings: 3 Slice Logic Utilization: Number of Slice Registers: 584 out of 19,200 3% Number used as Flip Flops: 584 Number of Slice LUTs: 692 out of 19,200 3% Number used as logic: 561 out of 19,200 2% Number using O6 output only: 476 Number using O5 output only: 56 Number using O5 and O6: 29 Number used as Memory: 124 out of 5,120 2% Number used as Dual Port RAM: 106 Number using O6 output only: 6 Number using O5 output only: 34 Number using O5 and O6: 66 Number used as Single Port RAM: 18 Number using O6 output only: 18 Number used as exclusive route-thru: 7 Number of route-thrus: 64 out of 38,400 1% Number using O6 output only: 63 Number using O5 output only: 1
Slice Logic Distribution: Number of occupied Slices: 306 out of 4,800 6% Number of LUT Flip Flop pairs used: 881 Number with an unused Flip Flop: 297 out of 881 33% Number with an unused LUT: 189 out of 881 21% Number of fully used LUT-FF pairs: 395 out of 881 44% Number of unique control sets: 47
A LUT Flip Flop pair for this architecture represents one LUT paired with one Flip Flop within a slice. A control set is a unique combination of clock, reset, set, and enable signals for a registered element. The Slice Logic Distribution report is not meaningful if the design is over-mapped for a non-slice resource or if Placement fails.
IO Utilization: Number of bonded IOBs: 66 out of 220 30% IOB Flip Flops: 70
Specific Feature Utilization: Number of BlockRAM/FIFO: 1 out of 32 3% Number using BlockRAM only: 1 Total primitives used: Number of 18k BlockRAM used: 1 Total Memory used (KB): 18 out of 1,152 1% Number of BUFG/BUFGCTRLs: 6 out of 32 18% Number used as BUFGs: 6 Number of DCM_ADVs: 3 out of 4 75%
Total equivalent gate count for design: 119,969 Additional JTAG gate count for IOBs: 3,168 Peak Memory Usage: 403 MB
NET "CLKIN1_IN" TNM_NET = CLKIN1_IN; TIMESPEC TS_CLKIN1_IN = PERIOD "CLKIN1_IN" 10 ns INPUT_JITTER 100 ps;
これでインプリメントしてPARリポートを見てみると動作周波数ごとに Worst Case Slack、Best Case Achievable、Timing Errors が表示される。これは動作周波数というかクロック周期の制約をあたえたからだが。ISE9.1iから表示が変わって、 Worst Case Slackの値の意味が良くわからない。SETUPの方は Best Case Achievable(クリティカルパス)をクロック周期から引いた値みたいだが、(SETUPだからそうか?)HOLDの方が良くわからない。マニュアルやアンサー・サーチを見てみたが良くわからないし。今のところナゾである。わかる方は教えてください。