ad : inout std_logic_vector(63 downto 0); -- アドレスとデータ
signal pcix_dout_ena, master_dout_ena : std_logic;
attribute syn_useioff of pcix_dout_ena : signal is true;
process(reset, pcix_clk) begin -- ADのイネーブルをIOBに入れる
if reset='1' then
pcix_dout_ena <= '0';
elsif pcix_clk'event and pcix_clk='1' then
pcix_dout_ena <= target_dout_ena or master_dout_ena;
end if;
end process;
process(pcix_dout, pcix_dout_ena) begin -- PCIX_ADへの出力トライステート・バッファ
if pcix_dout_ena='1' then
ad <= pcix_dout;
else
ad <= (others => 'Z');
end if;
end process;
Timing constraint: COMP "pcix_ad(10)" OFFSET = OUT 3.8 ns AFTER COMP "pcix_clk";
2 items analyzed, 0 timing errors detected.
Minimum allowable offset is 3.086ns.
--------------------------------------------------------------------------------
Slack: 0.714ns (requirement - (clock arrival + clock path + data path + uncertainty))
Source: pcix_inst/pcix_dout[10] (FF)
Destination: pcix_ad(10) (PAD)
Source Clock: clk_dcm rising at 0.645ns
Requirement: 3.800ns
Data Path Delay: 2.715ns (Levels of Logic = 0)
Clock Path Delay: -0.274ns (Levels of Logic = 3)
Clock Uncertainty: 0.000ns
Clock Path: pcix_clk to pcix_inst/pcix_dout[10]
Delay type Delay(ns) Logical Resource(s)
---------------------------- -------------------
Tiopi 0.921 pcix_clk
dcm_pcix_inst/CLKIN_IBUFG_INST
net (fanout=1) 0.431 dcm_pcix_inst/CLKIN_IBUFG
Tdcmino -4.145 dcm_pcix_inst/DCM_INST
net (fanout=1) 1.185 dcm_pcix_inst/CLK0_BUF
Tgi0o 0.057 dcm_pcix_inst/CLK0_BUFG_INST
net (fanout=681) 1.277 clk_dcm
---------------------------- ---------------------------
Total -0.274ns (-3.167ns logic, 2.893ns route)
Data Path: pcix_inst/pcix_dout[10] to pcix_ad(10)
Delay type Delay(ns) Logical Resource(s)
---------------------------- -------------------
Tiockp 2.715 pcix_inst/pcix_dout[10]
pcix_ad_iobuf[10]/OBUFT
pcix_ad(10)
---------------------------- ---------------------------
Total 2.715ns (2.715ns logic, 0.000ns route)
(100.0% logic, 0.0% route)
signal pcix_dout_ena : std_logic_vector(63 downto 0);
attribute syn_useioff of pcix_dout_ena : signal is true;
attribute syn_keep of pcix_dout_ena : signal is true;
process(pcix_clk) begin -- ADのイネーブルをIOBに入れる
if pcix_clk'event and pcix_clk='1' then
for i in 63 downto 0 loop
if reset='1' then
pcix_dout_ena(i) <= '0';
else
pcix_dout_ena(i) <= target_dout_ena or master_dout_ena;
end if;
end loop;
end if;
end process;
process(pcix_dout, pcix_dout_ena) begin -- PCIX_ADへの出力トライステート・バッファ
for i in 63 downto 0 loop
if pcix_dout_ena(i)='1' then
ad(i) <= pcix_dout(i);
else
ad(i) <= 'Z';
end if;
end loop;
end process;
Timing constraint: COMP "pcix_ad(10)" OFFSET = OUT 3.8 ns AFTER COMP "pcix_clk";
2 items analyzed, 1 timing error detected.
Minimum allowable offset is 3.946ns.
--------------------------------------------------------------------------------
Slack: -0.146ns (requirement - (clock arrival + clock path + data path + uncertainty))
Source: pcix_inst/pcix_dout_ena[0] (FF)
Destination: pcix_ad(10) (PAD)
Source Clock: clk_dcm rising at 0.645ns
Requirement: 3.800ns
Data Path Delay: 3.588ns (Levels of Logic = 1)
Clock Path Delay: -0.287ns (Levels of Logic = 3)
Clock Uncertainty: 0.000ns
Timing Improvement Wizard
Clock Path: pcix_clk to pcix_inst/pcix_dout_ena[0]
Delay type Delay(ns) Logical Resource(s)
---------------------------- -------------------
Tiopi 0.921 pcix_clk
dcm_pcix_inst/CLKIN_IBUFG_INST
net (fanout=1) 0.431 dcm_pcix_inst/CLKIN_IBUFG
Tdcmino -4.145 dcm_pcix_inst/DCM_INST
net (fanout=1) 1.185 dcm_pcix_inst/CLK0_BUF
Tgi0o 0.057 dcm_pcix_inst/CLK0_BUFG_INST
net (fanout=687) 1.264 clk_dcm
---------------------------- ---------------------------
Total -0.287ns (-3.167ns logic, 2.880ns route)
Data Path: pcix_inst/pcix_dout_ena[0] to pcix_ad(10)
Delay type Delay(ns) Logical Resource(s)
---------------------------- -------------------
Tcko 0.374 pcix_inst/pcix_dout_ena[0]
net (fanout=64) 0.629 pcix_inst/pcix_dout_ena_1(0)
Tiotp 2.585 pcix_ad_iobuf[10]/OBUFT
pcix_ad(10)
---------------------------- ---------------------------
Total 3.588ns (2.959ns logic, 0.629ns route)
(82.5% logic, 17.5% route)
Design Summary
--------------
Number of errors: 0
Number of warnings: 2
Logic Utilization:
Number of Slice Flip Flops: 575 out of 9,312 6%
Number of 4 input LUTs: 512 out of 9,312 5%
Logic Distribution:
Number of occupied Slices: 582 out of 4,656 12%
Number of Slices containing only related logic: 582 out of 582 100%
Number of Slices containing unrelated logic: 0 out of 582 0%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs: 800 out of 9,312 8%
Number used as logic: 512
Number used as a route-thru: 64
Number used for Dual Port RAMs: 172
(Two LUTs used per Dual Port RAM)
Number used for 32x1 RAMs: 52
(Two LUTs used per 32x1 RAM)
Number of bonded IOBs: 66 out of 232 28%
IOB Flip Flops: 49
Number of ODDR2s used: 38
Number of DDR_ALIGNMENT = NONE 38
Number of Block RAMs: 1 out of 20 5%
Number of GCLKs: 6 out of 24 25%
Number of DCMs: 3 out of 4 75%
Total equivalent gate count for design: 113,940
Additional JTAG gate count for IOBs: 3,168
Peak Memory Usage: 161 MB
Total REAL time to MAP completion: 20 secs
Total CPU time to MAP completion: 19 secs
Design Summary
--------------
Number of errors: 0
Number of warnings: 2
Logic Utilization:
Number of Slice Flip Flops: 576 out of 9,312 6%
Number of 4 input LUTs: 459 out of 9,312 4%
Logic Distribution:
Number of occupied Slices: 576 out of 4,656 12%
Number of Slices containing only related logic: 576 out of 576 100%
Number of Slices containing unrelated logic: 0 out of 576 0%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs: 747 out of 9,312 8%
Number used as logic: 459
Number used as a route-thru: 64
Number used for Dual Port RAMs: 172
(Two LUTs used per Dual Port RAM)
Number used for 32x1 RAMs: 52
(Two LUTs used per 32x1 RAM)
Number of bonded IOBs: 66 out of 232 28%
IOB Flip Flops: 49
Number of ODDR2s used: 38
Number of DDR_ALIGNMENT = NONE 38
Number of Block RAMs: 1 out of 20 5%
Number of GCLKs: 6 out of 24 25%
Number of DCMs: 3 out of 4 75%
Total equivalent gate count for design: 113,633
Additional JTAG gate count for IOBs: 3,168
Peak Memory Usage: 160 MB
Total REAL time to MAP completion: 20 secs
Total CPU time to MAP completion: 19 secs
------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
------------------------------------------------------------------------------------------------------
* TS_ddr_sdram_cont_inst_dcm_module_inst_cl | SETUP | -1.741ns| 9.241ns| 88| 60600
k_node = PERIOD TIMEGRP "ddr_sdra | HOLD | 0.902ns| | 0| 0
m_cont_inst_dcm_module_inst_clk_node" | | | | |
TS_dcm100_inst_CLK2X_BUF HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
* TS_dcm100_inst_CLK0_BUF = PERIOD TIMEGRP | SETUP | -0.017ns| 15.034ns| 1| 17
"dcm100_inst_CLK0_BUF" TS_clk HIGH | HOLD | 0.758ns| | 0| 0
50% | | | | |
------------------------------------------------------------------------------------------------------
TS_dcm100_inst_CLK2X_BUF = PERIOD TIMEGRP | SETUP | 0.056ns| 7.444ns| 0| 0
"dcm100_inst_CLK2X_BUF" TS_clk / 2 | HOLD | 1.369ns| | 0| 0
HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_ddr_sdram_cont_inst_dcm_module_inst_cl | SETUP | 0.298ns| 6.904ns| 0| 0
k90_node = PERIOD TIMEGRP "ddr_sd | HOLD | 2.397ns| | 0| 0
ram_cont_inst_dcm_module_inst_clk90_node" | | | | |
TS_dcm100_inst_CLK2X_BUF PHASE 1 | | | | |
.875 ns HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_ddr_sdram_cont_inst_clk1_161 = PERIOD | SETUP | 0.810ns| 4.952ns| 0| 0
TIMEGRP "ddr_sdram_cont_inst_clk1 | HOLD | 1.431ns| | 0| 0
_161" TS_dcm100_inst_CLK2X_BUF * 16 HIGH | | | | |
50% | | | | |
------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
------------------------------------------------------------------------------------------------------
* TS_ddr_sdram_cont_inst_dcm_module_inst_cl | SETUP | -1.248ns| 8.748ns| 76| 41070
k_node = PERIOD TIMEGRP "ddr_sdra | HOLD | 0.926ns| | 0| 0
m_cont_inst_dcm_module_inst_clk_node" | | | | |
TS_dcm100_inst_CLK2X_BUF HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
* TS_dcm100_inst_CLK0_BUF = PERIOD TIMEGRP | SETUP | -0.434ns| 15.868ns| 1| 434
"dcm100_inst_CLK0_BUF" TS_clk HIGH | HOLD | 0.765ns| | 0| 0
50% | | | | |
------------------------------------------------------------------------------------------------------
TS_ddr_sdram_cont_inst_dcm_module_inst_cl | SETUP | 0.233ns| 7.034ns| 0| 0
k90_node = PERIOD TIMEGRP "ddr_sd | HOLD | 2.449ns| | 0| 0
ram_cont_inst_dcm_module_inst_clk90_node" | | | | |
TS_dcm100_inst_CLK2X_BUF PHASE 1 | | | | |
.875 ns HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_dcm100_inst_CLK2X_BUF = PERIOD TIMEGRP | SETUP | 0.394ns| 7.106ns| 0| 0
"dcm100_inst_CLK2X_BUF" TS_clk / 2 | HOLD | 1.421ns| | 0| 0
HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_ddr_sdram_cont_inst_clk1_161 = PERIOD | SETUP | 0.887ns| 4.959ns| 0| 0
TIMEGRP "ddr_sdram_cont_inst_clk1 | HOLD | 1.382ns| | 0| 0
_161" TS_dcm100_inst_CLK2X_BUF * 16 HIGH | | | | |
50% | | | | |
always @(posedge clk) begin
if (reset) begin
pre_cnt[PRE_CNT_WIDTH-1 : 1] <= 0;
pre_cnt[0] <= 1'b1; // 最初に0だとint_cntがダウンカウントするので
end else begin
if (int_cnt != 0) // int_cntが0までカウント
pre_cnt <= pre_cnt + 1;
else begin
pre_cnt[PRE_CNT_WIDTH-1 : 1] <= 0;
pre_cnt[0] <= 1'b1; // 最初に0だとint_cntがダウンカウントするので
end
end
end
always @(posedge clk) begin
if (reset) begin
pre_cnt[PRE_CNT_WIDTH-1 : 1] <= 0;
pre_cnt[0] <= 1'b1; // 最初に0だとint_cntがダウンカウントするので
else if (int_cnt != 0) // int_cntが0までカウント
pre_cnt <= pre_cnt + 1;
else begin
pre_cnt[PRE_CNT_WIDTH-1 : 1] <= 0;
pre_cnt[0] <= 1'b1; // 最初に0だとint_cntがダウンカウントするので
end
end
process(reset, clk) begin -- Lighting frequency is 1KHz
if reset='1' then
lcnt <= (others => '0');
elsif clk'event and clk='1' then
if lcnt = conv_std_logic_vector(clk_frequency, 16) then
lcnt <= (others => '0');
else
lcnt <= lcnt + 1;
end if;
end if;
end process;
process(clk) begin -- Lighting frequency is 1KHz
if clk'event and clk='1' then
if reset='1' then
lcnt <= (others => '0');
elsif lcnt = conv_std_logic_vector(clk_frequency, 16) then
lcnt <= (others => '0');
else
lcnt <= lcnt + 1;
end if;
end if;
end process;
Design Summary
--------------
Number of errors: 0
Number of warnings: 2
Logic Utilization:
Number of Slice Flip Flops: 22 out of 3,840 1%
Number of 4 input LUTs: 72 out of 3,840 1%
Logic Distribution:
Number of occupied Slices: 46 out of 1,920 2%
Number of Slices containing only related logic: 46 out of 46 100%
Number of Slices containing unrelated logic: 0 out of 46 0%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs: 87 out of 3,840 2%
Number used as logic: 72
Number used as a route-thru: 15
Number of bonded IOBs: 19 out of 173 10%
IOB Flip Flops: 5
Number of GCLKs: 1 out of 8 12%
Total equivalent gate count for design: 750
Additional JTAG gate count for IOBs: 912
Peak Memory Usage: 135 MB
Total REAL time to MAP completion: 10 secs
Total CPU time to MAP completion: 6 secs
Design Summary
--------------
Number of errors: 0
Number of warnings: 2
Logic Utilization:
Number of Slice Flip Flops: 22 out of 3,840 1%
Number of 4 input LUTs: 33 out of 3,840 1%
Logic Distribution:
Number of occupied Slices: 27 out of 1,920 1%
Number of Slices containing only related logic: 27 out of 27 100%
Number of Slices containing unrelated logic: 0 out of 27 0%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs: 48 out of 3,840 1%
Number used as logic: 33
Number used as a route-thru: 15
Number of bonded IOBs: 19 out of 173 10%
IOB Flip Flops: 5
Number of GCLKs: 1 out of 8 12%
Total equivalent gate count for design: 507
Additional JTAG gate count for IOBs: 912
Peak Memory Usage: 135 MB
Total REAL time to MAP completion: 11 secs
Total CPU time to MAP completion: 7 secs
`default_nettype none
`timescale 1ns / 1ps
module reset_test(clk, reset, a, b, c, d, e, q);
input clk;
input reset;
input a;
input b;
input c;
input d;
input e;
output q;
wire clk, reset, a, b, c, d, e;
reg q;
always @(posedge clk)
if (reset)
q <= 1'b0;
else
q <= a | (b&c&d&e);
endmodule
INST "q" IOB = FALSE;
always @(posedge reset, posedge clk)
日 | 月 | 火 | 水 | 木 | 金 | 土 |
---|---|---|---|---|---|---|
- | - | - | - | - | 1 | 2 |
3 | 4 | 5 | 6 | 7 | 8 | 9 |
10 | 11 | 12 | 13 | 14 | 15 | 16 |
17 | 18 | 19 | 20 | 21 | 22 | 23 |
24 | 25 | 26 | 27 | 28 | 29 | 30 |