`ifdef COCOTB_SIM
initial begin
$dumpfile ("test_pcie_s10.vcd");
$dumpvars (0, test_pcie_s10);
#1;
end
`endif
`ifdef COCOTB_SIM
initial begin
$dumpfile ("test_pcie_ptile.vcd");
$dumpvars (0, test_pcie_ptile);
#1;
end
`endif
`ifdef COCOTB_SIM
initial begin
$dumpfile ("test_rgmii_phy.vcd");
$dumpvars (0, test_rgmii_phy);
#1;
end
`endif
`ifdef COCOTB_SIM
initial begin
$dumpfile ("test_xgmii.vcd");
$dumpvars (0, test_xgmii);
#1;
end
`endif
`ifdef COCOTB_SIM
initial begin
$dumpfile ("test_eth_mac.vcd");
$dumpvars (0, test_eth_mac);
#1;
end
`endif
`ifdef COCOTB_SIM
initial begin
$dumpfile ("test_gmii_phy.vcd");
$dumpvars (0, test_gmii_phy);
#1;
end
`endif
masaaki@marsee101-notebook:~/Cocotb/cocotbext-axi/tests/test_square_axis2$ make
rm -f results.xml
make -f Makefile results.xml
make[1]: Entering directory '/home/masaaki/Cocotb/cocotbext-axi/tests/test_square_axis2'
mkdir -p sim_build
/usr/bin/iverilog -o sim_build/sim.vvp -D COCOTB_SIM=1 -s test_square_axis2 -f sim_build/cmds.f -g2012 test_square_axis2.v test_square_axis2_control_s_axi.v test_square_axis2_flow_control_loop_pipe.v test_square_axis2_mul_32s_32s_32_2_1.v test_square_axis2_regslice_both.v
rm -f results.xml
MODULE=test_square_axis2 TESTCASE= TOPLEVEL=test_square_axis2 TOPLEVEL_LANG=verilog \
/usr/bin/vvp -M /usr/local/lib/python3.10/dist-packages/cocotb/libs -m libcocotbvpi_icarus sim_build/sim.vvp
-.--ns INFO gpi ..mbed/gpi_embed.cpp:76 in set_program_name_in_venv Did not detect Python virtual environment. Using system-wide Python interpreter
-.--ns INFO gpi ../gpi/GpiCommon.cpp:101 in gpi_print_registered_impl VPI registered
0.00ns INFO cocotb Running on Icarus Verilog version 11.0 (stable)
0.00ns INFO cocotb Running tests with cocotb v1.8.0 from /usr/local/lib/python3.10/dist-packages/cocotb
0.00ns INFO cocotb Seeding Python random module with 1687378922
0.00ns INFO cocotb.regression Found test test_square_axis2.test_square_axil
0.00ns INFO cocotb.regression running test_square_axil (1/1)
0.00ns INFO ...test_square_axis2.s_axi_control AXI lite master (write)
0.00ns INFO ...test_square_axis2.s_axi_control cocotbext-axi version 0.1.24
0.00ns INFO ...test_square_axis2.s_axi_control Copyright (c) 2020 Alex Forencich
0.00ns INFO ...test_square_axis2.s_axi_control https://github.com/alexforencich/cocotbext-axi
0.00ns INFO ...test_square_axis2.s_axi_control Reset de-asserted
0.00ns INFO ...test_square_axis2.s_axi_control Reset de-asserted
0.00ns INFO ...test_square_axis2.s_axi_control Reset de-asserted
0.00ns INFO ...test_square_axis2.s_axi_control AXI lite master configuration:
0.00ns INFO ...test_square_axis2.s_axi_control Address width: 5 bits
0.00ns INFO ...test_square_axis2.s_axi_control Byte size: 8 bits
0.00ns INFO ...test_square_axis2.s_axi_control Data width: 32 bits (4 bytes)
0.00ns INFO ...test_square_axis2.s_axi_control AXI lite master signals:
0.00ns INFO ...test_square_axis2.s_axi_control awaddr width: 5 bits
0.00ns INFO ...test_square_axis2.s_axi_control awprot: not present
0.00ns INFO ...test_square_axis2.s_axi_control awready width: 1 bits
0.00ns INFO ...test_square_axis2.s_axi_control awvalid width: 1 bits
0.00ns INFO ...test_square_axis2.s_axi_control wdata width: 32 bits
0.00ns INFO ...test_square_axis2.s_axi_control wready width: 1 bits
0.00ns INFO ...test_square_axis2.s_axi_control wstrb width: 4 bits
0.00ns INFO ...test_square_axis2.s_axi_control wvalid width: 1 bits
0.00ns INFO ...test_square_axis2.s_axi_control bready width: 1 bits
0.00ns INFO ...test_square_axis2.s_axi_control bresp: not present
0.00ns INFO ...test_square_axis2.s_axi_control bvalid width: 1 bits
0.00ns INFO ...test_square_axis2.s_axi_control Reset de-asserted
0.00ns INFO ...test_square_axis2.s_axi_control AXI lite master (read)
0.00ns INFO ...test_square_axis2.s_axi_control cocotbext-axi version 0.1.24
0.00ns INFO ...test_square_axis2.s_axi_control Copyright (c) 2020 Alex Forencich
0.00ns INFO ...test_square_axis2.s_axi_control https://github.com/alexforencich/cocotbext-axi
0.00ns INFO ...test_square_axis2.s_axi_control Reset de-asserted
0.00ns INFO ...test_square_axis2.s_axi_control Reset de-asserted
0.00ns INFO ...test_square_axis2.s_axi_control AXI lite master configuration:
0.00ns INFO ...test_square_axis2.s_axi_control Address width: 5 bits
0.00ns INFO ...test_square_axis2.s_axi_control Byte size: 8 bits
0.00ns INFO ...test_square_axis2.s_axi_control Data width: 32 bits (4 bytes)
0.00ns INFO ...test_square_axis2.s_axi_control AXI lite master signals:
0.00ns INFO ...test_square_axis2.s_axi_control araddr width: 5 bits
0.00ns INFO ...test_square_axis2.s_axi_control arprot: not present
0.00ns INFO ...test_square_axis2.s_axi_control arready width: 1 bits
0.00ns INFO ...test_square_axis2.s_axi_control arvalid width: 1 bits
0.00ns INFO ...test_square_axis2.s_axi_control rdata width: 32 bits
0.00ns INFO ...test_square_axis2.s_axi_control rready width: 1 bits
0.00ns INFO ...test_square_axis2.s_axi_control rresp: not present
0.00ns INFO ...test_square_axis2.s_axi_control rvalid width: 1 bits
0.00ns INFO ...test_square_axis2.s_axi_control Reset de-asserted
0.00ns INFO cocotb.test_square_axis2.in_r AXI stream source
0.00ns INFO cocotb.test_square_axis2.in_r cocotbext-axi version 0.1.24
0.00ns INFO cocotb.test_square_axis2.in_r Copyright (c) 2020 Alex Forencich
0.00ns INFO cocotb.test_square_axis2.in_r https://github.com/alexforencich/cocotbext-axi
0.00ns INFO cocotb.test_square_axis2.in_r AXI stream source configuration:
0.00ns INFO cocotb.test_square_axis2.in_r Byte size: 8 bits
0.00ns INFO cocotb.test_square_axis2.in_r Data width: 32 bits (4 bytes)
0.00ns INFO cocotb.test_square_axis2.in_r AXI stream source signals:
0.00ns INFO cocotb.test_square_axis2.in_r tdata width: 32 bits
0.00ns INFO cocotb.test_square_axis2.in_r tdest: not present
0.00ns INFO cocotb.test_square_axis2.in_r tid: not present
0.00ns INFO cocotb.test_square_axis2.in_r tkeep: not present
0.00ns INFO cocotb.test_square_axis2.in_r tlast: not present
0.00ns INFO cocotb.test_square_axis2.in_r tready width: 1 bits
0.00ns INFO cocotb.test_square_axis2.in_r tuser: not present
0.00ns INFO cocotb.test_square_axis2.in_r tvalid width: 1 bits
0.00ns INFO cocotb.test_square_axis2.in_r Reset de-asserted
0.00ns INFO cocotb.test_square_axis2.out_r AXI stream sink
0.00ns INFO cocotb.test_square_axis2.out_r cocotbext-axi version 0.1.24
0.00ns INFO cocotb.test_square_axis2.out_r Copyright (c) 2020 Alex Forencich
0.00ns INFO cocotb.test_square_axis2.out_r https://github.com/alexforencich/cocotbext-axi
0.00ns INFO cocotb.test_square_axis2.out_r AXI stream sink configuration:
0.00ns INFO cocotb.test_square_axis2.out_r Byte size: 8 bits
0.00ns INFO cocotb.test_square_axis2.out_r Data width: 32 bits (4 bytes)
0.00ns INFO cocotb.test_square_axis2.out_r AXI stream sink signals:
0.00ns INFO cocotb.test_square_axis2.out_r tdata width: 32 bits
0.00ns INFO cocotb.test_square_axis2.out_r tdest: not present
0.00ns INFO cocotb.test_square_axis2.out_r tid: not present
0.00ns INFO cocotb.test_square_axis2.out_r tkeep: not present
0.00ns INFO cocotb.test_square_axis2.out_r tlast: not present
0.00ns INFO cocotb.test_square_axis2.out_r tready width: 1 bits
0.00ns INFO cocotb.test_square_axis2.out_r tuser: not present
0.00ns INFO cocotb.test_square_axis2.out_r tvalid width: 1 bits
0.00ns INFO cocotb.test_square_axis2.out_r Reset de-asserted
VCD info: dumpfile test_square_axis2.vcd opened for output.
40.00ns INFO ...test_square_axis2.s_axi_control Write start addr: 0x00000000 prot: AxiProt.NONSECURE data: 01 00 00 00
70.00ns INFO ...test_square_axis2.s_axi_control Write complete addr: 0x00000000 prot: AxiProt.NONSECURE resp: AxiResp.OKAY length: 4
70.00ns INFO ...test_square_axis2.s_axi_control Read start addr: 0x00000000 prot: AxiProt.NONSECURE length: 1
80.00ns INFO cocotb.test_square_axis2.in_r TX frame: AxiStreamFrame(tdata=bytearray(b'\x00\x00\x00\x00'), tkeep=None, tid=None, tdest=None, tuser=1, sim_time_start=80000, sim_time_end=None)
90.00ns INFO cocotb.test_square_axis2.in_r TX frame: AxiStreamFrame(tdata=bytearray(b'\x01\x00\x00\x00'), tkeep=None, tid=None, tdest=None, tuser=0, sim_time_start=90000, sim_time_end=None)
100.00ns INFO cocotb.test_square_axis2.in_r TX frame: AxiStreamFrame(tdata=bytearray(b'\x02\x00\x00\x00'), tkeep=None, tid=None, tdest=None, tuser=0, sim_time_start=100000, sim_time_end=None)
100.00ns INFO ...test_square_axis2.s_axi_control Read complete addr: 0x00000000 prot: AxiProt.NONSECURE resp: AxiResp.OKAY data: 01
100.00ns INFO ...test_square_axis2.s_axi_control Read start addr: 0x00000000 prot: AxiProt.NONSECURE length: 1
110.00ns INFO cocotb.test_square_axis2.in_r TX frame: AxiStreamFrame(tdata=bytearray(b'\x03\x00\x00\x00'), tkeep=None, tid=None, tdest=None, tuser=0, sim_time_start=110000, sim_time_end=None)
120.00ns INFO cocotb.test_square_axis2.in_r TX frame: AxiStreamFrame(tdata=bytearray(b'\x04\x00\x00\x00'), tkeep=None, tid=None, tdest=None, tuser=0, sim_time_start=120000, sim_time_end=None)
130.00ns INFO cocotb.test_square_axis2.in_r TX frame: AxiStreamFrame(tdata=bytearray(b'\x05\x00\x00\x00'), tkeep=None, tid=None, tdest=None, tuser=0, sim_time_start=130000, sim_time_end=None)
130.00ns INFO cocotb.test_square_axis2.out_r RX frame: AxiStreamFrame(tdata=bytearray(b'\x00\x00\x00\x00'), tkeep=[], tid=[], tdest=[], tuser=[], sim_time_start=130000, sim_time_end=130000)
130.00ns INFO ...test_square_axis2.s_axi_control Read complete addr: 0x00000000 prot: AxiProt.NONSECURE resp: AxiResp.OKAY data: 01
130.00ns INFO ...test_square_axis2.s_axi_control Read start addr: 0x00000000 prot: AxiProt.NONSECURE length: 1
140.00ns INFO cocotb.test_square_axis2.in_r TX frame: AxiStreamFrame(tdata=bytearray(b'\x06\x00\x00\x00'), tkeep=None, tid=None, tdest=None, tuser=0, sim_time_start=140000, sim_time_end=None)
140.00ns INFO cocotb.test_square_axis2.out_r RX frame: AxiStreamFrame(tdata=bytearray(b'\x01\x00\x00\x00'), tkeep=[], tid=[], tdest=[], tuser=[], sim_time_start=140000, sim_time_end=140000)
150.00ns INFO cocotb.test_square_axis2.in_r TX frame: AxiStreamFrame(tdata=bytearray(b'\x07\x00\x00\x00'), tkeep=None, tid=None, tdest=None, tuser=0, sim_time_start=150000, sim_time_end=None)
150.00ns INFO cocotb.test_square_axis2.out_r RX frame: AxiStreamFrame(tdata=bytearray(b'\x04\x00\x00\x00'), tkeep=[], tid=[], tdest=[], tuser=[], sim_time_start=150000, sim_time_end=150000)
160.00ns INFO cocotb.test_square_axis2.in_r TX frame: AxiStreamFrame(tdata=bytearray(b'\x08\x00\x00\x00'), tkeep=None, tid=None, tdest=None, tuser=0, sim_time_start=160000, sim_time_end=None)
160.00ns INFO cocotb.test_square_axis2.out_r RX frame: AxiStreamFrame(tdata=bytearray(b'\t\x00\x00\x00'), tkeep=[], tid=[], tdest=[], tuser=[], sim_time_start=160000, sim_time_end=160000)
160.00ns INFO ...test_square_axis2.s_axi_control Read complete addr: 0x00000000 prot: AxiProt.NONSECURE resp: AxiResp.OKAY data: 01
160.00ns INFO ...test_square_axis2.s_axi_control Read start addr: 0x00000000 prot: AxiProt.NONSECURE length: 1
170.00ns INFO cocotb.test_square_axis2.in_r TX frame: AxiStreamFrame(tdata=bytearray(b'\t\x00\x00\x00'), tkeep=None, tid=None, tdest=None, tuser=0, sim_time_start=170000, sim_time_end=None)
170.00ns INFO cocotb.test_square_axis2.out_r RX frame: AxiStreamFrame(tdata=bytearray(b'\x10\x00\x00\x00'), tkeep=[], tid=[], tdest=[], tuser=[], sim_time_start=170000, sim_time_end=170000)
180.00ns INFO cocotb.test_square_axis2.out_r RX frame: AxiStreamFrame(tdata=bytearray(b'\x19\x00\x00\x00'), tkeep=[], tid=[], tdest=[], tuser=[], sim_time_start=180000, sim_time_end=180000)
190.00ns INFO cocotb.test_square_axis2.out_r RX frame: AxiStreamFrame(tdata=bytearray(b'$\x00\x00\x00'), tkeep=[], tid=[], tdest=[], tuser=[], sim_time_start=190000, sim_time_end=190000)
190.00ns INFO ...test_square_axis2.s_axi_control Read complete addr: 0x00000000 prot: AxiProt.NONSECURE resp: AxiResp.OKAY data: 01
190.00ns INFO ...test_square_axis2.s_axi_control Read start addr: 0x00000000 prot: AxiProt.NONSECURE length: 1
200.00ns INFO cocotb.test_square_axis2.out_r RX frame: AxiStreamFrame(tdata=bytearray(b'1\x00\x00\x00'), tkeep=[], tid=[], tdest=[], tuser=[], sim_time_start=200000, sim_time_end=200000)
210.00ns INFO cocotb.test_square_axis2.out_r RX frame: AxiStreamFrame(tdata=bytearray(b'@\x00\x00\x00'), tkeep=[], tid=[], tdest=[], tuser=[], sim_time_start=210000, sim_time_end=210000)
220.00ns INFO cocotb.test_square_axis2.out_r RX frame: AxiStreamFrame(tdata=bytearray(b'Q\x00\x00\x00'), tkeep=[], tid=[], tdest=[], tuser=[], sim_time_start=220000, sim_time_end=220000)
220.00ns INFO ...test_square_axis2.s_axi_control Read complete addr: 0x00000000 prot: AxiProt.NONSECURE resp: AxiResp.OKAY data: 08
220.00ns INFO ...test_square_axis2.s_axi_control Read start addr: 0x00000000 prot: AxiProt.NONSECURE length: 1
250.00ns INFO ...test_square_axis2.s_axi_control Read complete addr: 0x00000000 prot: AxiProt.NONSECURE resp: AxiResp.OKAY data: 06
i = 0 tdata = 0
i = 1 tdata = 1
i = 2 tdata = 4
i = 3 tdata = 9
i = 4 tdata = 16
i = 5 tdata = 25
i = 6 tdata = 36
i = 7 tdata = 49
i = 8 tdata = 64
i = 9 tdata = 81
250.00ns INFO cocotb.regression test_square_axil passed
250.00ns INFO cocotb.regression ********************************************************************************************
** TEST STATUS SIM TIME (ns) REAL TIME (s) RATIO (ns/s) **
********************************************************************************************
** test_square_axis2.test_square_axil PASS 250.00 0.04 6918.54 **
********************************************************************************************
** TESTS=1 PASS=1 FAIL=0 SKIP=0 250.00 0.21 1215.25 **
********************************************************************************************
make[1]: Leaving directory '/home/masaaki/Cocotb/cocotbext-axi/tests/test_square_axis2'
# Makefile (for test_square_axis)
# 2023/06/14 by marsee
SIM ?= icarus
VERILOG_SOURCES += test_square_axis2.v
VERILOG_SOURCES += test_square_axis2_control_s_axi.v
VERILOG_SOURCES += test_square_axis2_flow_control_loop_pipe.v
VERILOG_SOURCES += test_square_axis2_mul_32s_32s_32_2_1.v
VERILOG_SOURCES += test_square_axis2_regslice_both.v
TOPLEVEL = test_square_axis2
MODULE = test_square_axis2
include $(shell cocotb-config --makefiles)/Makefile.sim
# test_aquare_axi.py
# 2023/06/13 by marsee
# I created the software with reference to cocotbext-axi/tests/axil/test_axil.py.
# https://github.com/alexforencich/cocotbext-axi/blob/master/tests/axil/test_axil.py
# I created the software with reference to cocotbext-axi/tests/axis/test_axis.py.
# https://github.com/alexforencich/cocotbext-axi/blob/master/tests/axis/test_axis.py
import random
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import Timer, RisingEdge
from cocotbext.axi import AxiLiteBus, AxiLiteMaster, AxiLiteRam
from cocotbext.axi import AxiBus, AxiMaster, AxiRam
from cocotbext.axi import AxiStreamFrame, AxiStreamBus, AxiStreamSource, AxiStreamSink, AxiStreamMonitor
AP_DONE = 0x2
class TEST:
def __init__(self, dut):
self.dut = dut
cocotb.start_soon(Clock(dut.ap_clk, 10, units="ns").start())
self.axil_master = AxiLiteMaster(AxiLiteBus.from_prefix(dut, "s_axi_control"), dut.ap_clk)
self.axis_source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "in_r"), dut.ap_clk)
self.axis_sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "out_r"), dut.ap_clk)
@cocotb.test()
async def test_square_axis2(dut):
test = TEST(dut)
dut.ap_rst_n.value = 0; # Reset
await Timer(30, units='ns')
dut.ap_rst_n.value = 1; # Normal Operation
await Timer(10, units='ns')
ap_start = 1
await test.axil_master.write(0x00, ap_start.to_bytes(4,'little')) # ap_start
#await test.axil_master.read(0x00, 1)
for i in range(10):
data = i.to_bytes(4, 'little')
source_frame = AxiStreamFrame(data)
if i == 0:
source_frame.tuser = 1
else:
source_frame.tuser = 0
if i == 9:
source_frame.tlast = 1
else:
source_frame.tlast = 0
await test.axis_source.send(source_frame)
data = await test.axil_master.read(0x00, 1) # wait end
data_int = int.from_bytes(data, 'little')
while (data_int & AP_DONE) != AP_DONE:
data = await test.axil_master.read(0x00, 1)
data_int = int.from_bytes(data, 'little')
for i in range(10):
sink_frame = await test.axis_sink.recv()
#print(sink_frame)
tdata_ba = sink_frame.tdata
tuser = sink_frame.tuser
tdata = int.from_bytes(tdata_ba, 'little')
print('i = ', i, ' tdata = ', tdata)
assert tdata == i * i
assert test.axis_source.empty()
assert test.axis_sink.empty()
// ==============================================================
// Generated by Vitis HLS v2023.1
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// ==============================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="test_square_axis2_test_square_axis2,hls_ip_2023_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020-clg400-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=6.912000,HLS_SYN_LAT=14,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=674,HLS_SYN_LUT=436,HLS_VERSION=2023_1}" *)
module test_square_axis2 (
ap_clk,
ap_rst_n,
in_r_tvalid,
out_r_tready,
in_r_TDATA,
in_r_tready,
in_r_TKEEP,
in_r_TSTRB,
in_r_TUSER,
in_r_TLAST,
in_r_TID,
in_r_TDEST,
out_r_TDATA,
out_r_tvalid,
out_r_TKEEP,
out_r_TSTRB,
out_r_TUSER,
out_r_TLAST,
out_r_TID,
out_r_TDEST,
s_axi_control_AWVALID,
s_axi_control_AWREADY,
s_axi_control_AWADDR,
s_axi_control_WVALID,
s_axi_control_WREADY,
s_axi_control_WDATA,
s_axi_control_wstrb,
s_axi_control_ARVALID,
s_axi_control_ARREADY,
s_axi_control_ARADDR,
s_axi_control_RVALID,
s_axi_control_RREADY,
s_axi_control_RDATA,
s_axi_control_RRESP,
s_axi_control_BVALID,
s_axi_control_BREADY,
s_axi_control_BRESP,
interrupt
);
parameter ap_ST_fsm_pp0_stage0 = 1'd1;
parameter C_S_AXI_CONTROL_DATA_WIDTH = 32;
parameter C_S_AXI_CONTROL_ADDR_WIDTH = 5;
parameter C_S_AXI_DATA_WIDTH = 32;
parameter C_S_AXI_CONTROL_WSTRB_WIDTH = (32 / 8);
parameter C_S_AXI_WSTRB_WIDTH = (32 / 8);
input ap_clk;
input ap_rst_n;
input in_r_tvalid;
input out_r_tready;
input [31:0] in_r_TDATA;
output in_r_tready;
input [3:0] in_r_TKEEP;
input [3:0] in_r_TSTRB;
input [0:0] in_r_TUSER;
input [0:0] in_r_TLAST;
input [0:0] in_r_TID;
input [0:0] in_r_TDEST;
output [31:0] out_r_TDATA;
output out_r_tvalid;
output [3:0] out_r_TKEEP;
output [3:0] out_r_TSTRB;
output [0:0] out_r_TUSER;
output [0:0] out_r_TLAST;
output [0:0] out_r_TID;
output [0:0] out_r_TDEST;
input s_axi_control_AWVALID;
output s_axi_control_AWREADY;
input [C_S_AXI_CONTROL_ADDR_WIDTH - 1:0] s_axi_control_AWADDR;
input s_axi_control_WVALID;
output s_axi_control_WREADY;
input [C_S_AXI_CONTROL_DATA_WIDTH - 1:0] s_axi_control_WDATA;
input [C_S_AXI_CONTROL_WSTRB_WIDTH - 1:0] s_axi_control_wstrb;
input s_axi_control_ARVALID;
output s_axi_control_ARREADY;
input [C_S_AXI_CONTROL_ADDR_WIDTH - 1:0] s_axi_control_ARADDR;
output s_axi_control_RVALID;
input s_axi_control_RREADY;
output [C_S_AXI_CONTROL_DATA_WIDTH - 1:0] s_axi_control_RDATA;
output [1:0] s_axi_control_RRESP;
output s_axi_control_BVALID;
input s_axi_control_BREADY;
output [1:0] s_axi_control_BRESP;
output interrupt;
reg ap_rst_n_inv;
wire ap_start;
wire ap_done;
reg ap_idle;
(* fsm_encoding = "none" *) reg [0:0] ap_CS_fsm;
wire ap_CS_fsm_pp0_stage0;
wire ap_enable_reg_pp0_iter0;
reg ap_enable_reg_pp0_iter1;
reg ap_enable_reg_pp0_iter2;
reg ap_enable_reg_pp0_iter3;
reg ap_idle_pp0;
wire ap_ready;
wire [0:0] icmp_ln14_fu_142_p2;
reg ap_block_state1_pp0_stage0_iter0;
wire ap_block_state2_pp0_stage0_iter1;
wire regslice_both_out_r_V_data_V_U_apdone_blk;
reg ap_block_state3_pp0_stage0_iter2;
reg ap_block_state4_pp0_stage0_iter3;
wire ap_loop_exit_ready;
reg ap_loop_exit_ready_pp0_iter2_reg;
reg ap_block_pp0_stage0_subdone;
reg ap_condition_exit_pp0_iter0_stage0;
reg ap_ready_int;
reg in_r_TDATA_blk_n;
wire ap_block_pp0_stage0;
reg out_r_TDATA_blk_n;
reg [0:0] icmp_ln14_reg_194;
reg ap_block_pp0_stage0_11001;
reg [0:0] icmp_ln14_reg_194_pp0_iter1_reg;
reg signed [31:0] val_data_reg_198;
reg [3:0] val_keep_reg_204;
reg [3:0] val_keep_reg_204_pp0_iter1_reg;
reg [3:0] val_strb_reg_209;
reg [3:0] val_strb_reg_209_pp0_iter1_reg;
reg [0:0] val_user_reg_214;
reg [0:0] val_user_reg_214_pp0_iter1_reg;
reg [0:0] val_last_reg_219;
reg [0:0] val_last_reg_219_pp0_iter1_reg;
reg [0:0] val_id_reg_224;
reg [0:0] val_id_reg_224_pp0_iter1_reg;
reg [0:0] val_dest_reg_229;
reg [0:0] val_dest_reg_229_pp0_iter1_reg;
wire [31:0] grp_fu_129_p2;
reg [3:0] i_fu_82;
wire [3:0] i_2_fu_148_p2;
wire ap_loop_init;
reg [3:0] ap_sig_allocacmp_i_1;
reg ap_block_pp0_stage0_01001;
reg grp_fu_129_ce;
reg ap_done_reg;
wire ap_continue_int;
reg ap_done_int;
reg ap_loop_exit_ready_pp0_iter1_reg;
reg [0:0] ap_NS_fsm;
wire ap_enable_pp0;
wire ap_start_int;
wire regslice_both_in_r_V_data_V_U_apdone_blk;
wire [31:0] in_r_TDATA_int_regslice;
wire in_r_TVALID_int_regslice;
reg in_r_TREADY_int_regslice;
wire regslice_both_in_r_V_data_V_U_ack_in;
wire regslice_both_in_r_V_keep_V_U_apdone_blk;
wire [3:0] in_r_TKEEP_int_regslice;
wire regslice_both_in_r_V_keep_V_U_vld_out;
wire regslice_both_in_r_V_keep_V_U_ack_in;
wire regslice_both_in_r_V_strb_V_U_apdone_blk;
wire [3:0] in_r_TSTRB_int_regslice;
wire regslice_both_in_r_V_strb_V_U_vld_out;
wire regslice_both_in_r_V_strb_V_U_ack_in;
wire regslice_both_in_r_V_user_V_U_apdone_blk;
wire [0:0] in_r_TUSER_int_regslice;
wire regslice_both_in_r_V_user_V_U_vld_out;
wire regslice_both_in_r_V_user_V_U_ack_in;
wire regslice_both_in_r_V_last_V_U_apdone_blk;
wire [0:0] in_r_TLAST_int_regslice;
wire regslice_both_in_r_V_last_V_U_vld_out;
wire regslice_both_in_r_V_last_V_U_ack_in;
wire regslice_both_in_r_V_id_V_U_apdone_blk;
wire [0:0] in_r_TID_int_regslice;
wire regslice_both_in_r_V_id_V_U_vld_out;
wire regslice_both_in_r_V_id_V_U_ack_in;
wire regslice_both_in_r_V_dest_V_U_apdone_blk;
wire [0:0] in_r_TDEST_int_regslice;
wire regslice_both_in_r_V_dest_V_U_vld_out;
wire regslice_both_in_r_V_dest_V_U_ack_in;
reg out_r_TVALID_int_regslice;
wire out_r_TREADY_int_regslice;
wire regslice_both_out_r_V_data_V_U_vld_out;
wire regslice_both_out_r_V_keep_V_U_apdone_blk;
wire regslice_both_out_r_V_keep_V_U_ack_in_dummy;
wire regslice_both_out_r_V_keep_V_U_vld_out;
wire regslice_both_out_r_V_strb_V_U_apdone_blk;
wire regslice_both_out_r_V_strb_V_U_ack_in_dummy;
wire regslice_both_out_r_V_strb_V_U_vld_out;
wire regslice_both_out_r_V_user_V_U_apdone_blk;
wire regslice_both_out_r_V_user_V_U_ack_in_dummy;
wire regslice_both_out_r_V_user_V_U_vld_out;
wire regslice_both_out_r_V_last_V_U_apdone_blk;
wire regslice_both_out_r_V_last_V_U_ack_in_dummy;
wire regslice_both_out_r_V_last_V_U_vld_out;
wire regslice_both_out_r_V_id_V_U_apdone_blk;
wire regslice_both_out_r_V_id_V_U_ack_in_dummy;
wire regslice_both_out_r_V_id_V_U_vld_out;
wire regslice_both_out_r_V_dest_V_U_apdone_blk;
wire regslice_both_out_r_V_dest_V_U_ack_in_dummy;
wire regslice_both_out_r_V_dest_V_U_vld_out;
reg ap_condition_192;
wire ap_ce_reg;
wire [31:0] ap_return;
// power-on initialization
initial begin
#0 ap_CS_fsm = 1'd1;
#0 ap_enable_reg_pp0_iter1 = 1'b0;
#0 ap_enable_reg_pp0_iter2 = 1'b0;
#0 ap_enable_reg_pp0_iter3 = 1'b0;
#0 ap_done_reg = 1'b0;
end
test_square_axis2_control_s_axi #(
.C_S_AXI_ADDR_WIDTH( C_S_AXI_CONTROL_ADDR_WIDTH ),
.C_S_AXI_DATA_WIDTH( C_S_AXI_CONTROL_DATA_WIDTH ))
control_s_axi_U(
.AWVALID(s_axi_control_AWVALID),
.AWREADY(s_axi_control_AWREADY),
.AWADDR(s_axi_control_AWADDR),
.WVALID(s_axi_control_WVALID),
.WREADY(s_axi_control_WREADY),
.WDATA(s_axi_control_WDATA),
.WSTRB(s_axi_control_wstrb),
.ARVALID(s_axi_control_ARVALID),
.ARREADY(s_axi_control_ARREADY),
.ARADDR(s_axi_control_ARADDR),
.RVALID(s_axi_control_RVALID),
.RREADY(s_axi_control_RREADY),
.RDATA(s_axi_control_RDATA),
.RRESP(s_axi_control_RRESP),
.BVALID(s_axi_control_BVALID),
.BREADY(s_axi_control_BREADY),
.BRESP(s_axi_control_BRESP),
.ACLK(ap_clk),
.ARESET(ap_rst_n_inv),
.ACLK_EN(1'b1),
.ap_start(ap_start),
.interrupt(interrupt),
.ap_ready(ap_ready),
.ap_done(ap_done),
.ap_idle(ap_idle),
.ap_return(32'd0)
);
test_square_axis2_mul_32s_32s_32_2_1 #(
.ID( 1 ),
.NUM_STAGE( 2 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
mul_32s_32s_32_2_1_U1(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(val_data_reg_198),
.din1(val_data_reg_198),
.ce(grp_fu_129_ce),
.dout(grp_fu_129_p2)
);
test_square_axis2_flow_control_loop_pipe flow_control_loop_pipe_U(
.ap_clk(ap_clk),
.ap_rst(ap_rst_n_inv),
.ap_start(ap_start),
.ap_ready(ap_ready),
.ap_done(ap_done),
.ap_start_int(ap_start_int),
.ap_loop_init(ap_loop_init),
.ap_ready_int(ap_ready_int),
.ap_loop_exit_ready(ap_condition_exit_pp0_iter0_stage0),
.ap_loop_exit_done(ap_done_int),
.ap_continue_int(ap_continue_int),
.ap_done_int(ap_done_int),
.ap_continue(1'b1)
);
test_square_axis2_regslice_both #(
.DataWidth( 32 ))
regslice_both_in_r_V_data_V_U(
.ap_clk(ap_clk),
.ap_rst(ap_rst_n_inv),
.data_in(in_r_TDATA),
.vld_in(in_r_tvalid),
.ack_in(regslice_both_in_r_V_data_V_U_ack_in),
.data_out(in_r_TDATA_int_regslice),
.vld_out(in_r_TVALID_int_regslice),
.ack_out(in_r_TREADY_int_regslice),
.apdone_blk(regslice_both_in_r_V_data_V_U_apdone_blk)
);
test_square_axis2_regslice_both #(
.DataWidth( 4 ))
regslice_both_in_r_V_keep_V_U(
.ap_clk(ap_clk),
.ap_rst(ap_rst_n_inv),
.data_in(in_r_TKEEP),
.vld_in(in_r_tvalid),
.ack_in(regslice_both_in_r_V_keep_V_U_ack_in),
.data_out(in_r_TKEEP_int_regslice),
.vld_out(regslice_both_in_r_V_keep_V_U_vld_out),
.ack_out(in_r_TREADY_int_regslice),
.apdone_blk(regslice_both_in_r_V_keep_V_U_apdone_blk)
);
test_square_axis2_regslice_both #(
.DataWidth( 4 ))
regslice_both_in_r_V_strb_V_U(
.ap_clk(ap_clk),
.ap_rst(ap_rst_n_inv),
.data_in(in_r_TSTRB),
.vld_in(in_r_tvalid),
.ack_in(regslice_both_in_r_V_strb_V_U_ack_in),
.data_out(in_r_TSTRB_int_regslice),
.vld_out(regslice_both_in_r_V_strb_V_U_vld_out),
.ack_out(in_r_TREADY_int_regslice),
.apdone_blk(regslice_both_in_r_V_strb_V_U_apdone_blk)
);
test_square_axis2_regslice_both #(
.DataWidth( 1 ))
regslice_both_in_r_V_user_V_U(
.ap_clk(ap_clk),
.ap_rst(ap_rst_n_inv),
.data_in(in_r_TUSER),
.vld_in(in_r_tvalid),
.ack_in(regslice_both_in_r_V_user_V_U_ack_in),
.data_out(in_r_TUSER_int_regslice),
.vld_out(regslice_both_in_r_V_user_V_U_vld_out),
.ack_out(in_r_TREADY_int_regslice),
.apdone_blk(regslice_both_in_r_V_user_V_U_apdone_blk)
);
test_square_axis2_regslice_both #(
.DataWidth( 1 ))
regslice_both_in_r_V_last_V_U(
.ap_clk(ap_clk),
.ap_rst(ap_rst_n_inv),
.data_in(in_r_TLAST),
.vld_in(in_r_tvalid),
.ack_in(regslice_both_in_r_V_last_V_U_ack_in),
.data_out(in_r_TLAST_int_regslice),
.vld_out(regslice_both_in_r_V_last_V_U_vld_out),
.ack_out(in_r_TREADY_int_regslice),
.apdone_blk(regslice_both_in_r_V_last_V_U_apdone_blk)
);
test_square_axis2_regslice_both #(
.DataWidth( 1 ))
regslice_both_in_r_V_id_V_U(
.ap_clk(ap_clk),
.ap_rst(ap_rst_n_inv),
.data_in(in_r_TID),
.vld_in(in_r_tvalid),
.ack_in(regslice_both_in_r_V_id_V_U_ack_in),
.data_out(in_r_TID_int_regslice),
.vld_out(regslice_both_in_r_V_id_V_U_vld_out),
.ack_out(in_r_TREADY_int_regslice),
.apdone_blk(regslice_both_in_r_V_id_V_U_apdone_blk)
);
test_square_axis2_regslice_both #(
.DataWidth( 1 ))
regslice_both_in_r_V_dest_V_U(
.ap_clk(ap_clk),
.ap_rst(ap_rst_n_inv),
.data_in(in_r_TDEST),
.vld_in(in_r_tvalid),
.ack_in(regslice_both_in_r_V_dest_V_U_ack_in),
.data_out(in_r_TDEST_int_regslice),
.vld_out(regslice_both_in_r_V_dest_V_U_vld_out),
.ack_out(in_r_TREADY_int_regslice),
.apdone_blk(regslice_both_in_r_V_dest_V_U_apdone_blk)
);
test_square_axis2_regslice_both #(
.DataWidth( 32 ))
regslice_both_out_r_V_data_V_U(
.ap_clk(ap_clk),
.ap_rst(ap_rst_n_inv),
.data_in(grp_fu_129_p2),
.vld_in(out_r_TVALID_int_regslice),
.ack_in(out_r_TREADY_int_regslice),
.data_out(out_r_TDATA),
.vld_out(regslice_both_out_r_V_data_V_U_vld_out),
.ack_out(out_r_TREADY),
.apdone_blk(regslice_both_out_r_V_data_V_U_apdone_blk)
);
test_square_axis2_regslice_both #(
.DataWidth( 4 ))
regslice_both_out_r_V_keep_V_U(
.ap_clk(ap_clk),
.ap_rst(ap_rst_n_inv),
.data_in(val_keep_reg_204_pp0_iter1_reg),
.vld_in(out_r_TVALID_int_regslice),
.ack_in(regslice_both_out_r_V_keep_V_U_ack_in_dummy),
.data_out(out_r_TKEEP),
.vld_out(regslice_both_out_r_V_keep_V_U_vld_out),
.ack_out(out_r_TREADY),
.apdone_blk(regslice_both_out_r_V_keep_V_U_apdone_blk)
);
test_square_axis2_regslice_both #(
.DataWidth( 4 ))
regslice_both_out_r_V_strb_V_U(
.ap_clk(ap_clk),
.ap_rst(ap_rst_n_inv),
.data_in(val_strb_reg_209_pp0_iter1_reg),
.vld_in(out_r_TVALID_int_regslice),
.ack_in(regslice_both_out_r_V_strb_V_U_ack_in_dummy),
.data_out(out_r_TSTRB),
.vld_out(regslice_both_out_r_V_strb_V_U_vld_out),
.ack_out(out_r_TREADY),
.apdone_blk(regslice_both_out_r_V_strb_V_U_apdone_blk)
);
test_square_axis2_regslice_both #(
.DataWidth( 1 ))
regslice_both_out_r_V_user_V_U(
.ap_clk(ap_clk),
.ap_rst(ap_rst_n_inv),
.data_in(val_user_reg_214_pp0_iter1_reg),
.vld_in(out_r_TVALID_int_regslice),
.ack_in(regslice_both_out_r_V_user_V_U_ack_in_dummy),
.data_out(out_r_TUSER),
.vld_out(regslice_both_out_r_V_user_V_U_vld_out),
.ack_out(out_r_TREADY),
.apdone_blk(regslice_both_out_r_V_user_V_U_apdone_blk)
);
test_square_axis2_regslice_both #(
.DataWidth( 1 ))
regslice_both_out_r_V_last_V_U(
.ap_clk(ap_clk),
.ap_rst(ap_rst_n_inv),
.data_in(val_last_reg_219_pp0_iter1_reg),
.vld_in(out_r_TVALID_int_regslice),
.ack_in(regslice_both_out_r_V_last_V_U_ack_in_dummy),
.data_out(out_r_TLAST),
.vld_out(regslice_both_out_r_V_last_V_U_vld_out),
.ack_out(out_r_TREADY),
.apdone_blk(regslice_both_out_r_V_last_V_U_apdone_blk)
);
test_square_axis2_regslice_both #(
.DataWidth( 1 ))
regslice_both_out_r_V_id_V_U(
.ap_clk(ap_clk),
.ap_rst(ap_rst_n_inv),
.data_in(val_id_reg_224_pp0_iter1_reg),
.vld_in(out_r_TVALID_int_regslice),
.ack_in(regslice_both_out_r_V_id_V_U_ack_in_dummy),
.data_out(out_r_TID),
.vld_out(regslice_both_out_r_V_id_V_U_vld_out),
.ack_out(out_r_TREADY),
.apdone_blk(regslice_both_out_r_V_id_V_U_apdone_blk)
);
test_square_axis2_regslice_both #(
.DataWidth( 1 ))
regslice_both_out_r_V_dest_V_U(
.ap_clk(ap_clk),
.ap_rst(ap_rst_n_inv),
.data_in(val_dest_reg_229_pp0_iter1_reg),
.vld_in(out_r_TVALID_int_regslice),
.ack_in(regslice_both_out_r_V_dest_V_U_ack_in_dummy),
.data_out(out_r_TDEST),
.vld_out(regslice_both_out_r_V_dest_V_U_vld_out),
.ack_out(out_r_TREADY),
.apdone_blk(regslice_both_out_r_V_dest_V_U_apdone_blk)
);
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_pp0_stage0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue_int == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if (((1'b0 == ap_block_pp0_stage0_subdone) & (ap_loop_exit_ready_pp0_iter2_reg == 1'b1))) begin
ap_done_reg <= 1'b1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
ap_enable_reg_pp0_iter1 <= 1'b0;
end else begin
if ((1'b1 == ap_condition_exit_pp0_iter0_stage0)) begin
ap_enable_reg_pp0_iter1 <= 1'b0;
end else if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
ap_enable_reg_pp0_iter1 <= ap_start_int;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
ap_enable_reg_pp0_iter2 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
ap_enable_reg_pp0_iter3 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
end
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_condition_192)) begin
if ((icmp_ln14_fu_142_p2 == 1'd0)) begin
i_fu_82 <= i_2_fu_148_p2;
end else if ((ap_loop_init == 1'b1)) begin
i_fu_82 <= 4'd0;
end
end
end
always @ (posedge ap_clk) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
ap_loop_exit_ready_pp0_iter1_reg <= ap_loop_exit_ready;
ap_loop_exit_ready_pp0_iter2_reg <= ap_loop_exit_ready_pp0_iter1_reg;
icmp_ln14_reg_194 <= icmp_ln14_fu_142_p2;
icmp_ln14_reg_194_pp0_iter1_reg <= icmp_ln14_reg_194;
val_dest_reg_229_pp0_iter1_reg <= val_dest_reg_229;
val_id_reg_224_pp0_iter1_reg <= val_id_reg_224;
val_keep_reg_204_pp0_iter1_reg <= val_keep_reg_204;
val_last_reg_219_pp0_iter1_reg <= val_last_reg_219;
val_strb_reg_209_pp0_iter1_reg <= val_strb_reg_209;
val_user_reg_214_pp0_iter1_reg <= val_user_reg_214;
end
end
always @ (posedge ap_clk) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln14_fu_142_p2 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
val_data_reg_198 <= in_r_TDATA_int_regslice;
val_dest_reg_229 <= in_r_TDEST_int_regslice;
val_id_reg_224 <= in_r_TID_int_regslice;
val_keep_reg_204 <= in_r_TKEEP_int_regslice;
val_last_reg_219 <= in_r_TLAST_int_regslice;
val_strb_reg_209 <= in_r_TSTRB_int_regslice;
val_user_reg_214 <= in_r_TUSER_int_regslice;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0_subdone) & (icmp_ln14_fu_142_p2 == 1'd1) & (ap_start_int == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
ap_condition_exit_pp0_iter0_stage0 = 1'b1;
end else begin
ap_condition_exit_pp0_iter0_stage0 = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0_subdone) & (ap_loop_exit_ready_pp0_iter2_reg == 1'b1))) begin
ap_done_int = 1'b1;
end else begin
ap_done_int = ap_done_reg;
end
end
always @ (*) begin
if (((ap_idle_pp0 == 1'b1) & (ap_start_int == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @ (*) begin
if (((ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin
ap_idle_pp0 = 1'b1;
end else begin
ap_idle_pp0 = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0_subdone) & (ap_start_int == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
ap_ready_int = 1'b1;
end else begin
ap_ready_int = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0) & (ap_start_int == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_loop_init == 1'b1))) begin
ap_sig_allocacmp_i_1 = 4'd0;
end else begin
ap_sig_allocacmp_i_1 = i_fu_82;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_129_ce = 1'b1;
end else begin
grp_fu_129_ce = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0) & (icmp_ln14_fu_142_p2 == 1'd0) & (ap_start_int == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
in_r_TDATA_blk_n = in_r_TVALID_int_regslice;
end else begin
in_r_TDATA_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln14_fu_142_p2 == 1'd0) & (ap_start_int == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
in_r_TREADY_int_regslice = 1'b1;
end else begin
in_r_TREADY_int_regslice = 1'b0;
end
end
always @ (*) begin
if ((((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter3 == 1'b1)) | ((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
out_r_TDATA_blk_n = out_r_TREADY_int_regslice;
end else begin
out_r_TDATA_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
out_r_TVALID_int_regslice = 1'b1;
end else begin
out_r_TVALID_int_regslice = 1'b0;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_fsm_pp0_stage0 : begin
ap_NS_fsm = ap_ST_fsm_pp0_stage0;
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd0];
assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage0_01001 = (((ap_loop_exit_ready_pp0_iter2_reg == 1'b1) & (regslice_both_out_r_V_data_V_U_apdone_blk == 1'b1)) | ((ap_enable_reg_pp0_iter2 == 1'b1) & ((regslice_both_out_r_V_data_V_U_apdone_blk == 1'b1) | (out_r_TREADY_int_regslice == 1'b0))) | ((icmp_ln14_fu_142_p2 == 1'd0) & (in_r_TVALID_int_regslice == 1'b0) & (ap_start_int == 1'b1)) | ((out_r_TREADY_int_regslice == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b1)));
end
always @ (*) begin
ap_block_pp0_stage0_11001 = (((ap_loop_exit_ready_pp0_iter2_reg == 1'b1) & (regslice_both_out_r_V_data_V_U_apdone_blk == 1'b1)) | ((ap_enable_reg_pp0_iter2 == 1'b1) & ((regslice_both_out_r_V_data_V_U_apdone_blk == 1'b1) | (out_r_TREADY_int_regslice == 1'b0))) | ((icmp_ln14_fu_142_p2 == 1'd0) & (in_r_TVALID_int_regslice == 1'b0) & (ap_start_int == 1'b1)) | ((out_r_TREADY_int_regslice == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b1)));
end
always @ (*) begin
ap_block_pp0_stage0_subdone = (((ap_loop_exit_ready_pp0_iter2_reg == 1'b1) & (regslice_both_out_r_V_data_V_U_apdone_blk == 1'b1)) | ((ap_enable_reg_pp0_iter2 == 1'b1) & ((regslice_both_out_r_V_data_V_U_apdone_blk == 1'b1) | (out_r_TREADY_int_regslice == 1'b0))) | ((icmp_ln14_fu_142_p2 == 1'd0) & (in_r_TVALID_int_regslice == 1'b0) & (ap_start_int == 1'b1)) | ((out_r_TREADY_int_regslice == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b1)));
end
always @ (*) begin
ap_block_state1_pp0_stage0_iter0 = ((icmp_ln14_fu_142_p2 == 1'd0) & (in_r_TVALID_int_regslice == 1'b0));
end
assign ap_block_state2_pp0_stage0_iter1 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state3_pp0_stage0_iter2 = ((regslice_both_out_r_V_data_V_U_apdone_blk == 1'b1) | (out_r_TREADY_int_regslice == 1'b0));
end
always @ (*) begin
ap_block_state4_pp0_stage0_iter3 = (out_r_TREADY_int_regslice == 1'b0);
end
always @ (*) begin
ap_condition_192 = ((1'b0 == ap_block_pp0_stage0_11001) & (ap_start_int == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0));
end
assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1);
assign ap_enable_reg_pp0_iter0 = ap_start_int;
assign ap_loop_exit_ready = ap_condition_exit_pp0_iter0_stage0;
always @ (*) begin
ap_rst_n_inv = ~ap_rst_n;
end
assign i_2_fu_148_p2 = (ap_sig_allocacmp_i_1 + 4'd1);
assign icmp_ln14_fu_142_p2 = ((ap_sig_allocacmp_i_1 == 4'd10) ? 1'b1 : 1'b0);
assign in_r_TREADY = regslice_both_in_r_V_data_V_U_ack_in;
assign out_r_TVALID = regslice_both_out_r_V_data_V_U_vld_out;
`ifdef COCOTB_SIM
initial begin
$dumpfile ("test_square_axis2.vcd");
$dumpvars (0, test_square_axis2);
#1;
end
`endif
endmodule //test_square_axis2
(base) masaaki@masaaki-H110M4-M01:/media/masaaki/Ubuntu_Disk/Cocotb/cocotbext-axi/tests/test_square_axis2$ make
rm -f results.xml
make -f Makefile results.xml
make[1]: ディレクトリ '/media/masaaki/Ubuntu_Disk/Cocotb/cocotbext-axi/tests/test_square_axis2' に入ります
rm -f results.xml
MODULE=test_square_axis2 TESTCASE= TOPLEVEL=test_square_axis2 TOPLEVEL_LANG=verilog \
/usr/bin/vvp -M /home/masaaki/anaconda3/lib/python3.8/site-packages/cocotb/libs -m libcocotbvpi_icarus sim_build/sim.vvp
-.--ns INFO gpi ..mbed/gpi_embed.cpp:76 in set_program_name_in_venv Did not detect Python virtual environment. Using system-wide Python interpreter
-.--ns INFO gpi ../gpi/GpiCommon.cpp:101 in gpi_print_registered_impl VPI registered
0.00ns INFO cocotb Running on Icarus Verilog version 10.1 (stable)
0.00ns INFO cocotb Running tests with cocotb v1.7.0 from /home/masaaki/anaconda3/lib/python3.8/site-packages/cocotb
0.00ns INFO cocotb Seeding Python random module with 1687373978
0.00ns INFO cocotb.regression Found test test_square_axis2.test_square_axis2
0.00ns INFO cocotb.regression running test_square_axis2 (1/1)
0.00ns INFO ...test_square_axis2.s_axi_control AXI lite master (write)
0.00ns INFO ...test_square_axis2.s_axi_control cocotbext-axi version 0.1.18
0.00ns INFO ...test_square_axis2.s_axi_control Copyright (c) 2020 Alex Forencich
0.00ns INFO ...test_square_axis2.s_axi_control https://github.com/alexforencich/cocotbext-axi
0.00ns INFO ...test_square_axis2.s_axi_control Reset de-asserted
0.00ns INFO ...test_square_axis2.s_axi_control Reset de-asserted
0.00ns INFO ...test_square_axis2.s_axi_control Reset de-asserted
0.00ns INFO ...test_square_axis2.s_axi_control AXI lite master configuration:
0.00ns INFO ...test_square_axis2.s_axi_control Address width: 5 bits
0.00ns INFO ...test_square_axis2.s_axi_control Byte size: 8 bits
0.00ns INFO ...test_square_axis2.s_axi_control Data width: 32 bits (4 bytes)
0.00ns INFO ...test_square_axis2.s_axi_control AXI lite master signals:
0.00ns INFO ...test_square_axis2.s_axi_control awaddr width: 5 bits
0.00ns INFO ...test_square_axis2.s_axi_control awprot: not present
0.00ns INFO ...test_square_axis2.s_axi_control awready width: 1 bits
0.00ns INFO ...test_square_axis2.s_axi_control awvalid width: 1 bits
0.00ns INFO ...test_square_axis2.s_axi_control wdata width: 32 bits
0.00ns INFO ...test_square_axis2.s_axi_control wready width: 1 bits
0.00ns INFO ...test_square_axis2.s_axi_control wstrb width: 4 bits
0.00ns INFO ...test_square_axis2.s_axi_control wvalid width: 1 bits
0.00ns INFO ...test_square_axis2.s_axi_control bready width: 1 bits
0.00ns INFO ...test_square_axis2.s_axi_control bresp: not present
0.00ns INFO ...test_square_axis2.s_axi_control bvalid width: 1 bits
0.00ns INFO ...test_square_axis2.s_axi_control Reset de-asserted
0.00ns INFO ...test_square_axis2.s_axi_control AXI lite master (read)
0.00ns INFO ...test_square_axis2.s_axi_control cocotbext-axi version 0.1.18
0.00ns INFO ...test_square_axis2.s_axi_control Copyright (c) 2020 Alex Forencich
0.00ns INFO ...test_square_axis2.s_axi_control https://github.com/alexforencich/cocotbext-axi
0.00ns INFO ...test_square_axis2.s_axi_control Reset de-asserted
0.00ns INFO ...test_square_axis2.s_axi_control Reset de-asserted
0.00ns INFO ...test_square_axis2.s_axi_control AXI lite master configuration:
0.00ns INFO ...test_square_axis2.s_axi_control Address width: 5 bits
0.00ns INFO ...test_square_axis2.s_axi_control Byte size: 8 bits
0.00ns INFO ...test_square_axis2.s_axi_control Data width: 32 bits (4 bytes)
0.00ns INFO ...test_square_axis2.s_axi_control AXI lite master signals:
0.00ns INFO ...test_square_axis2.s_axi_control araddr width: 5 bits
0.00ns INFO ...test_square_axis2.s_axi_control arprot: not present
0.00ns INFO ...test_square_axis2.s_axi_control arready width: 1 bits
0.00ns INFO ...test_square_axis2.s_axi_control arvalid width: 1 bits
0.00ns INFO ...test_square_axis2.s_axi_control rdata width: 32 bits
0.00ns INFO ...test_square_axis2.s_axi_control rready width: 1 bits
0.00ns INFO ...test_square_axis2.s_axi_control rresp: not present
0.00ns INFO ...test_square_axis2.s_axi_control rvalid width: 1 bits
0.00ns INFO ...test_square_axis2.s_axi_control Reset de-asserted
0.00ns INFO cocotb.test_square_axis2.in_r AXI stream source
0.00ns INFO cocotb.test_square_axis2.in_r cocotbext-axi version 0.1.18
0.00ns INFO cocotb.test_square_axis2.in_r Copyright (c) 2020 Alex Forencich
0.00ns INFO cocotb.test_square_axis2.in_r https://github.com/alexforencich/cocotbext-axi
0.00ns INFO cocotb.test_square_axis2.in_r AXI stream source configuration:
0.00ns INFO cocotb.test_square_axis2.in_r Byte size: 32 bits
0.00ns INFO cocotb.test_square_axis2.in_r Data width: 32 bits (1 bytes)
0.00ns INFO cocotb.test_square_axis2.in_r AXI stream source signals:
0.00ns INFO cocotb.test_square_axis2.in_r tdata width: 32 bits
0.00ns INFO cocotb.test_square_axis2.in_r tdest: not present
0.00ns INFO cocotb.test_square_axis2.in_r tid: not present
0.00ns INFO cocotb.test_square_axis2.in_r tkeep: not present
0.00ns INFO cocotb.test_square_axis2.in_r tlast: not present
0.00ns INFO cocotb.test_square_axis2.in_r tready width: 1 bits
0.00ns INFO cocotb.test_square_axis2.in_r tuser: not present
0.00ns INFO cocotb.test_square_axis2.in_r tvalid width: 1 bits
0.00ns INFO cocotb.test_square_axis2.in_r Reset de-asserted
0.00ns INFO cocotb.test_square_axis2.out_r AXI stream sink
0.00ns INFO cocotb.test_square_axis2.out_r cocotbext-axi version 0.1.18
0.00ns INFO cocotb.test_square_axis2.out_r Copyright (c) 2020 Alex Forencich
0.00ns INFO cocotb.test_square_axis2.out_r https://github.com/alexforencich/cocotbext-axi
0.00ns INFO cocotb.test_square_axis2.out_r AXI stream sink configuration:
0.00ns INFO cocotb.test_square_axis2.out_r Byte size: 32 bits
0.00ns INFO cocotb.test_square_axis2.out_r Data width: 32 bits (1 bytes)
0.00ns INFO cocotb.test_square_axis2.out_r AXI stream sink signals:
0.00ns INFO cocotb.test_square_axis2.out_r tdata width: 32 bits
0.00ns INFO cocotb.test_square_axis2.out_r tdest: not present
0.00ns INFO cocotb.test_square_axis2.out_r tid: not present
0.00ns INFO cocotb.test_square_axis2.out_r tkeep: not present
0.00ns INFO cocotb.test_square_axis2.out_r tlast: not present
0.00ns INFO cocotb.test_square_axis2.out_r tready width: 1 bits
0.00ns INFO cocotb.test_square_axis2.out_r tuser: not present
0.00ns INFO cocotb.test_square_axis2.out_r tvalid width: 1 bits
0.00ns INFO cocotb.test_square_axis2.out_r Reset de-asserted
VCD info: dumpfile test_square_axis2.vcd opened for output.
40.00ns INFO ...test_square_axis2.s_axi_control Write start addr: 0x00000000 prot: AxiProt.NONSECURE data: 01 00 00 00
70.00ns INFO ...test_square_axis2.s_axi_control Write complete addr: 0x00000000 prot: AxiProt.NONSECURE resp: AxiResp.OKAY length: 4
70.00ns INFO ...test_square_axis2.s_axi_control Read start addr: 0x00000000 prot: AxiProt.NONSECURE length: 1
80.00ns INFO cocotb.test_square_axis2.in_r TX frame: AxiStreamFrame(tdata=bytearray(b'\x00\x00\x00\x00'), tkeep=None, tid=None, tdest=None, tuser=1, sim_time_start=80000, sim_time_end=None)
100.00ns INFO ...test_square_axis2.s_axi_control Read complete addr: 0x00000000 prot: AxiProt.NONSECURE resp: AxiResp.OKAY data: 01
100.00ns INFO ...test_square_axis2.s_axi_control Read start addr: 0x00000000 prot: AxiProt.NONSECURE length: 1
120.00ns INFO cocotb.test_square_axis2.in_r TX frame: AxiStreamFrame(tdata=bytearray(b'\x01\x00\x00\x00'), tkeep=None, tid=None, tdest=None, tuser=0, sim_time_start=120000, sim_time_end=None)
130.00ns INFO cocotb.test_square_axis2.out_r RX frame: AxiStreamFrame(tdata=[0], tkeep=[], tid=[], tdest=[], tuser=[], sim_time_start=130000, sim_time_end=130000)
130.00ns INFO ...test_square_axis2.s_axi_control Read complete addr: 0x00000000 prot: AxiProt.NONSECURE resp: AxiResp.OKAY data: 01
130.00ns INFO ...test_square_axis2.s_axi_control Read start addr: 0x00000000 prot: AxiProt.NONSECURE length: 1
140.00ns INFO cocotb.test_square_axis2.out_r RX frame: AxiStreamFrame(tdata=[0], tkeep=[], tid=[], tdest=[], tuser=[], sim_time_start=140000, sim_time_end=140000)
150.00ns INFO cocotb.test_square_axis2.out_r RX frame: AxiStreamFrame(tdata=[0], tkeep=[], tid=[], tdest=[], tuser=[], sim_time_start=150000, sim_time_end=150000)
160.00ns INFO cocotb.test_square_axis2.in_r TX frame: AxiStreamFrame(tdata=bytearray(b'\x02\x00\x00\x00'), tkeep=None, tid=None, tdest=None, tuser=0, sim_time_start=160000, sim_time_end=None)
160.00ns INFO cocotb.test_square_axis2.out_r RX frame: AxiStreamFrame(tdata=[0], tkeep=[], tid=[], tdest=[], tuser=[], sim_time_start=160000, sim_time_end=160000)
160.00ns INFO ...test_square_axis2.s_axi_control Read complete addr: 0x00000000 prot: AxiProt.NONSECURE resp: AxiResp.OKAY data: 01
160.00ns INFO ...test_square_axis2.s_axi_control Read start addr: 0x00000000 prot: AxiProt.NONSECURE length: 1
170.00ns INFO cocotb.test_square_axis2.out_r RX frame: AxiStreamFrame(tdata=[1], tkeep=[], tid=[], tdest=[], tuser=[], sim_time_start=170000, sim_time_end=170000)
180.00ns INFO cocotb.test_square_axis2.out_r RX frame: AxiStreamFrame(tdata=[0], tkeep=[], tid=[], tdest=[], tuser=[], sim_time_start=180000, sim_time_end=180000)
190.00ns INFO cocotb.test_square_axis2.out_r RX frame: AxiStreamFrame(tdata=[0], tkeep=[], tid=[], tdest=[], tuser=[], sim_time_start=190000, sim_time_end=190000)
190.00ns INFO ...test_square_axis2.s_axi_control Read complete addr: 0x00000000 prot: AxiProt.NONSECURE resp: AxiResp.OKAY data: 01
190.00ns INFO ...test_square_axis2.s_axi_control Read start addr: 0x00000000 prot: AxiProt.NONSECURE length: 1
200.00ns INFO cocotb.test_square_axis2.in_r TX frame: AxiStreamFrame(tdata=bytearray(b'\x03\x00\x00\x00'), tkeep=None, tid=None, tdest=None, tuser=0, sim_time_start=200000, sim_time_end=None)
200.00ns INFO cocotb.test_square_axis2.out_r RX frame: AxiStreamFrame(tdata=[0], tkeep=[], tid=[], tdest=[], tuser=[], sim_time_start=200000, sim_time_end=200000)
210.00ns INFO cocotb.test_square_axis2.out_r RX frame: AxiStreamFrame(tdata=[4], tkeep=[], tid=[], tdest=[], tuser=[], sim_time_start=210000, sim_time_end=210000)
220.00ns INFO cocotb.test_square_axis2.out_r RX frame: AxiStreamFrame(tdata=[0], tkeep=[], tid=[], tdest=[], tuser=[], sim_time_start=220000, sim_time_end=220000)
220.00ns INFO ...test_square_axis2.s_axi_control Read complete addr: 0x00000000 prot: AxiProt.NONSECURE resp: AxiResp.OKAY data: 08
220.00ns INFO ...test_square_axis2.s_axi_control Read start addr: 0x00000000 prot: AxiProt.NONSECURE length: 1
250.00ns INFO ...test_square_axis2.s_axi_control Read complete addr: 0x00000000 prot: AxiProt.NONSECURE resp: AxiResp.OKAY data: 06
i = 0 tdata = 0
i = 1 tdata = 0
250.00ns INFO cocotb.regression test_square_axis2 failed
Traceback (most recent call last):
File "/media/masaaki/Ubuntu_Disk/Cocotb/cocotbext-axi/tests/test_square_axis2/test_square_axis2.py", line 66, in test_square_axis2
assert tdata == i * i
AssertionError: assert 0 == (1 * 1)
250.00ns INFO cocotb.regression *********************************************************************************************
** TEST STATUS SIM TIME (ns) REAL TIME (s) RATIO (ns/s) **
*********************************************************************************************
** test_square_axis2.test_square_axis2 FAIL 250.00 0.03 8539.34 **
*********************************************************************************************
** TESTS=1 PASS=0 FAIL=1 SKIP=0 250.00 0.26 977.73 **
*********************************************************************************************
make[1]: ディレクトリ '/media/masaaki/Ubuntu_Disk/Cocotb/cocotbext-axi/tests/test_square_axis2' から出ます
(base) masaaki@masaaki-H110M4-M01:/media/masaaki/Ubuntu_Disk/Cocotb/cocotbext-axi/tests/test_square_axis2$ make
rm -f results.xml
make -f Makefile results.xml
make[1]: ディレクトリ '/media/masaaki/Ubuntu_Disk/Cocotb/cocotbext-axi/tests/test_square_axis2' に入ります
rm -f results.xml
MODULE=test_square_axis2 TESTCASE= TOPLEVEL=test_square_axis2 TOPLEVEL_LANG=verilog \
/usr/bin/vvp -M /home/masaaki/anaconda3/lib/python3.8/site-packages/cocotb/libs -m libcocotbvpi_icarus sim_build/sim.vvp
-.--ns INFO gpi ..mbed/gpi_embed.cpp:76 in set_program_name_in_venv Did not detect Python virtual environment. Using system-wide Python interpreter
-.--ns INFO gpi ../gpi/GpiCommon.cpp:101 in gpi_print_registered_impl VPI registered
0.00ns INFO cocotb Running on Icarus Verilog version 10.1 (stable)
0.00ns INFO cocotb Running tests with cocotb v1.7.0 from /home/masaaki/anaconda3/lib/python3.8/site-packages/cocotb
0.00ns INFO cocotb Seeding Python random module with 1687374185
0.00ns INFO cocotb.regression Found test test_square_axis2.test_square_axis2
0.00ns INFO cocotb.regression running test_square_axis2 (1/1)
0.00ns INFO ...test_square_axis2.s_axi_control AXI lite master (write)
0.00ns INFO ...test_square_axis2.s_axi_control cocotbext-axi version 0.1.18
0.00ns INFO ...test_square_axis2.s_axi_control Copyright (c) 2020 Alex Forencich
0.00ns INFO ...test_square_axis2.s_axi_control https://github.com/alexforencich/cocotbext-axi
0.00ns INFO ...test_square_axis2.s_axi_control Reset de-asserted
0.00ns INFO ...test_square_axis2.s_axi_control Reset de-asserted
0.00ns INFO ...test_square_axis2.s_axi_control Reset de-asserted
0.00ns INFO ...test_square_axis2.s_axi_control AXI lite master configuration:
0.00ns INFO ...test_square_axis2.s_axi_control Address width: 5 bits
0.00ns INFO ...test_square_axis2.s_axi_control Byte size: 8 bits
0.00ns INFO ...test_square_axis2.s_axi_control Data width: 32 bits (4 bytes)
0.00ns INFO ...test_square_axis2.s_axi_control AXI lite master signals:
0.00ns INFO ...test_square_axis2.s_axi_control awaddr width: 5 bits
0.00ns INFO ...test_square_axis2.s_axi_control awprot: not present
0.00ns INFO ...test_square_axis2.s_axi_control awready width: 1 bits
0.00ns INFO ...test_square_axis2.s_axi_control awvalid width: 1 bits
0.00ns INFO ...test_square_axis2.s_axi_control wdata width: 32 bits
0.00ns INFO ...test_square_axis2.s_axi_control wready width: 1 bits
0.00ns INFO ...test_square_axis2.s_axi_control wstrb width: 4 bits
0.00ns INFO ...test_square_axis2.s_axi_control wvalid width: 1 bits
0.00ns INFO ...test_square_axis2.s_axi_control bready width: 1 bits
0.00ns INFO ...test_square_axis2.s_axi_control bresp: not present
0.00ns INFO ...test_square_axis2.s_axi_control bvalid width: 1 bits
0.00ns INFO ...test_square_axis2.s_axi_control Reset de-asserted
0.00ns INFO ...test_square_axis2.s_axi_control AXI lite master (read)
0.00ns INFO ...test_square_axis2.s_axi_control cocotbext-axi version 0.1.18
0.00ns INFO ...test_square_axis2.s_axi_control Copyright (c) 2020 Alex Forencich
0.00ns INFO ...test_square_axis2.s_axi_control https://github.com/alexforencich/cocotbext-axi
0.00ns INFO ...test_square_axis2.s_axi_control Reset de-asserted
0.00ns INFO ...test_square_axis2.s_axi_control Reset de-asserted
0.00ns INFO ...test_square_axis2.s_axi_control AXI lite master configuration:
0.00ns INFO ...test_square_axis2.s_axi_control Address width: 5 bits
0.00ns INFO ...test_square_axis2.s_axi_control Byte size: 8 bits
0.00ns INFO ...test_square_axis2.s_axi_control Data width: 32 bits (4 bytes)
0.00ns INFO ...test_square_axis2.s_axi_control AXI lite master signals:
0.00ns INFO ...test_square_axis2.s_axi_control araddr width: 5 bits
0.00ns INFO ...test_square_axis2.s_axi_control arprot: not present
0.00ns INFO ...test_square_axis2.s_axi_control arready width: 1 bits
0.00ns INFO ...test_square_axis2.s_axi_control arvalid width: 1 bits
0.00ns INFO ...test_square_axis2.s_axi_control rdata width: 32 bits
0.00ns INFO ...test_square_axis2.s_axi_control rready width: 1 bits
0.00ns INFO ...test_square_axis2.s_axi_control rresp: not present
0.00ns INFO ...test_square_axis2.s_axi_control rvalid width: 1 bits
0.00ns INFO ...test_square_axis2.s_axi_control Reset de-asserted
0.00ns INFO cocotb.test_square_axis2.in_r AXI stream source
0.00ns INFO cocotb.test_square_axis2.in_r cocotbext-axi version 0.1.18
0.00ns INFO cocotb.test_square_axis2.in_r Copyright (c) 2020 Alex Forencich
0.00ns INFO cocotb.test_square_axis2.in_r https://github.com/alexforencich/cocotbext-axi
0.00ns INFO cocotb.test_square_axis2.in_r AXI stream source configuration:
0.00ns INFO cocotb.test_square_axis2.in_r Byte size: 32 bits
0.00ns INFO cocotb.test_square_axis2.in_r Data width: 32 bits (1 bytes)
0.00ns INFO cocotb.test_square_axis2.in_r AXI stream source signals:
0.00ns INFO cocotb.test_square_axis2.in_r tdata width: 32 bits
0.00ns INFO cocotb.test_square_axis2.in_r tdest: not present
0.00ns INFO cocotb.test_square_axis2.in_r tid: not present
0.00ns INFO cocotb.test_square_axis2.in_r tkeep: not present
0.00ns INFO cocotb.test_square_axis2.in_r tlast: not present
0.00ns INFO cocotb.test_square_axis2.in_r tready width: 1 bits
0.00ns INFO cocotb.test_square_axis2.in_r tuser: not present
0.00ns INFO cocotb.test_square_axis2.in_r tvalid width: 1 bits
0.00ns INFO cocotb.test_square_axis2.in_r Reset de-asserted
0.00ns INFO cocotb.test_square_axis2.out_r AXI stream sink
0.00ns INFO cocotb.test_square_axis2.out_r cocotbext-axi version 0.1.18
0.00ns INFO cocotb.test_square_axis2.out_r Copyright (c) 2020 Alex Forencich
0.00ns INFO cocotb.test_square_axis2.out_r https://github.com/alexforencich/cocotbext-axi
0.00ns INFO cocotb.test_square_axis2.out_r AXI stream sink configuration:
0.00ns INFO cocotb.test_square_axis2.out_r Byte size: 32 bits
0.00ns INFO cocotb.test_square_axis2.out_r Data width: 32 bits (1 bytes)
0.00ns INFO cocotb.test_square_axis2.out_r AXI stream sink signals:
0.00ns INFO cocotb.test_square_axis2.out_r tdata width: 32 bits
0.00ns INFO cocotb.test_square_axis2.out_r tdest: not present
0.00ns INFO cocotb.test_square_axis2.out_r tid: not present
0.00ns INFO cocotb.test_square_axis2.out_r tkeep: not present
0.00ns INFO cocotb.test_square_axis2.out_r tlast: not present
0.00ns INFO cocotb.test_square_axis2.out_r tready width: 1 bits
0.00ns INFO cocotb.test_square_axis2.out_r tuser: not present
0.00ns INFO cocotb.test_square_axis2.out_r tvalid width: 1 bits
0.00ns INFO cocotb.test_square_axis2.out_r Reset de-asserted
VCD info: dumpfile test_square_axis2.vcd opened for output.
40.00ns INFO ...test_square_axis2.s_axi_control Write start addr: 0x00000000 prot: AxiProt.NONSECURE data: 01 00 00 00
70.00ns INFO ...test_square_axis2.s_axi_control Write complete addr: 0x00000000 prot: AxiProt.NONSECURE resp: AxiResp.OKAY length: 4
70.00ns INFO ...test_square_axis2.s_axi_control Read start addr: 0x00000000 prot: AxiProt.NONSECURE length: 1
80.00ns INFO cocotb.test_square_axis2.in_r TX frame: AxiStreamFrame(tdata=bytearray(b'\x00\x00\x00\x00'), tkeep=None, tid=None, tdest=None, tuser=1, sim_time_start=80000, sim_time_end=None)
100.00ns INFO ...test_square_axis2.s_axi_control Read complete addr: 0x00000000 prot: AxiProt.NONSECURE resp: AxiResp.OKAY data: 01
100.00ns INFO ...test_square_axis2.s_axi_control Read start addr: 0x00000000 prot: AxiProt.NONSECURE length: 1
120.00ns INFO cocotb.test_square_axis2.in_r TX frame: AxiStreamFrame(tdata=bytearray(b'\x01\x00\x00\x00'), tkeep=None, tid=None, tdest=None, tuser=0, sim_time_start=120000, sim_time_end=None)
130.00ns INFO cocotb.test_square_axis2.out_r RX frame: AxiStreamFrame(tdata=[0], tkeep=[], tid=[], tdest=[], tuser=[], sim_time_start=130000, sim_time_end=130000)
130.00ns INFO ...test_square_axis2.s_axi_control Read complete addr: 0x00000000 prot: AxiProt.NONSECURE resp: AxiResp.OKAY data: 01
130.00ns INFO ...test_square_axis2.s_axi_control Read start addr: 0x00000000 prot: AxiProt.NONSECURE length: 1
140.00ns INFO cocotb.test_square_axis2.out_r RX frame: AxiStreamFrame(tdata=[0], tkeep=[], tid=[], tdest=[], tuser=[], sim_time_start=140000, sim_time_end=140000)
150.00ns INFO cocotb.test_square_axis2.out_r RX frame: AxiStreamFrame(tdata=[0], tkeep=[], tid=[], tdest=[], tuser=[], sim_time_start=150000, sim_time_end=150000)
160.00ns INFO cocotb.test_square_axis2.in_r TX frame: AxiStreamFrame(tdata=bytearray(b'\x02\x00\x00\x00'), tkeep=None, tid=None, tdest=None, tuser=0, sim_time_start=160000, sim_time_end=None)
160.00ns INFO cocotb.test_square_axis2.out_r RX frame: AxiStreamFrame(tdata=[0], tkeep=[], tid=[], tdest=[], tuser=[], sim_time_start=160000, sim_time_end=160000)
160.00ns INFO ...test_square_axis2.s_axi_control Read complete addr: 0x00000000 prot: AxiProt.NONSECURE resp: AxiResp.OKAY data: 01
160.00ns INFO ...test_square_axis2.s_axi_control Read start addr: 0x00000000 prot: AxiProt.NONSECURE length: 1
170.00ns INFO cocotb.test_square_axis2.out_r RX frame: AxiStreamFrame(tdata=[1], tkeep=[], tid=[], tdest=[], tuser=[], sim_time_start=170000, sim_time_end=170000)
180.00ns INFO cocotb.test_square_axis2.out_r RX frame: AxiStreamFrame(tdata=[0], tkeep=[], tid=[], tdest=[], tuser=[], sim_time_start=180000, sim_time_end=180000)
190.00ns INFO cocotb.test_square_axis2.out_r RX frame: AxiStreamFrame(tdata=[0], tkeep=[], tid=[], tdest=[], tuser=[], sim_time_start=190000, sim_time_end=190000)
190.00ns INFO ...test_square_axis2.s_axi_control Read complete addr: 0x00000000 prot: AxiProt.NONSECURE resp: AxiResp.OKAY data: 01
190.00ns INFO ...test_square_axis2.s_axi_control Read start addr: 0x00000000 prot: AxiProt.NONSECURE length: 1
200.00ns INFO cocotb.test_square_axis2.in_r TX frame: AxiStreamFrame(tdata=bytearray(b'\x03\x00\x00\x00'), tkeep=None, tid=None, tdest=None, tuser=0, sim_time_start=200000, sim_time_end=None)
200.00ns INFO cocotb.test_square_axis2.out_r RX frame: AxiStreamFrame(tdata=[0], tkeep=[], tid=[], tdest=[], tuser=[], sim_time_start=200000, sim_time_end=200000)
210.00ns INFO cocotb.test_square_axis2.out_r RX frame: AxiStreamFrame(tdata=[4], tkeep=[], tid=[], tdest=[], tuser=[], sim_time_start=210000, sim_time_end=210000)
220.00ns INFO cocotb.test_square_axis2.out_r RX frame: AxiStreamFrame(tdata=[0], tkeep=[], tid=[], tdest=[], tuser=[], sim_time_start=220000, sim_time_end=220000)
220.00ns INFO ...test_square_axis2.s_axi_control Read complete addr: 0x00000000 prot: AxiProt.NONSECURE resp: AxiResp.OKAY data: 08
220.00ns INFO ...test_square_axis2.s_axi_control Read start addr: 0x00000000 prot: AxiProt.NONSECURE length: 1
250.00ns INFO ...test_square_axis2.s_axi_control Read complete addr: 0x00000000 prot: AxiProt.NONSECURE resp: AxiResp.OKAY data: 06
i = 0 tdata = 0
i = 1 tdata = 0
i = 2 tdata = 0
i = 3 tdata = 0
i = 4 tdata = 1
i = 5 tdata = 0
i = 6 tdata = 0
i = 7 tdata = 0
i = 8 tdata = 4
i = 9 tdata = 0
250.00ns INFO cocotb.regression test_square_axis2 failed
Traceback (most recent call last):
File "/media/masaaki/Ubuntu_Disk/Cocotb/cocotbext-axi/tests/test_square_axis2/test_square_axis2.py", line 68, in test_square_axis2
assert test.axis_source.empty()
AssertionError: assert False
+ where False = <bound method AxiStreamBase.empty of <cocotbext.axi.axis.AxiStreamSource object at 0x7fa7491f6430>>()
+ where <bound method AxiStreamBase.empty of <cocotbext.axi.axis.AxiStreamSource object at 0x7fa7491f6430>> = <cocotbext.axi.axis.AxiStreamSource object at 0x7fa7491f6430>.empty
+ where <cocotbext.axi.axis.AxiStreamSource object at 0x7fa7491f6430> = <test_square_axis2.TEST object at 0x7fa7492ce940>.axis_source
250.00ns INFO cocotb.regression *********************************************************************************************
** TEST STATUS SIM TIME (ns) REAL TIME (s) RATIO (ns/s) **
*********************************************************************************************
** test_square_axis2.test_square_axis2 FAIL 250.00 0.03 8429.17 **
*********************************************************************************************
** TESTS=1 PASS=0 FAIL=1 SKIP=0 250.00 0.26 962.41 **
*********************************************************************************************
make[1]: ディレクトリ '/media/masaaki/Ubuntu_Disk/Cocotb/cocotbext-axi/tests/test_square_axis2' から出ます
i = 0 tdata = 0
i = 1 tdata = 0
i = 2 tdata = 0
i = 3 tdata = 0
i = 4 tdata = 1
i = 5 tdata = 0
i = 6 tdata = 0
i = 7 tdata = 0
i = 8 tdata = 4
i = 9 tdata = 0
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