/*
* AvalonMM_Slave_Dyna7seg_0 configuration
*
*/
#define AVALONMM_SLAVE_DYNA7SEG_0_NAME "/dev/AvalonMM_Slave_Dyna7seg_0"
#define AVALONMM_SLAVE_DYNA7SEG_0_TYPE "AvalonMM_Slave_Dyna7seg"
#define AVALONMM_SLAVE_DYNA7SEG_0_BASE 0x00000020
#define AVALONMM_SLAVE_DYNA7SEG_0_SPAN 32
#define AVALONMM_SLAVE_DYNA7SEG_0_TERMINATED_PORTS ""
#define ALT_MODULE_CLASS_AvalonMM_Slave_Dyna7seg_0 AvalonMM_Slave_Dyna7seg
static void SevenSegCount( void )
{
alt_u32 count;
for (count = 0; count <= 0xff; count++)
{
IOWR_ALTERA_AVALON_PIO_DATA(AVALONMM_SLAVE_DYNA7SEG_0_BASE, count&0xf);
IOWR_ALTERA_AVALON_PIO_DATA(AVALONMM_SLAVE_DYNA7SEG_0_BASE+4, count>>4);
IOWR_ALTERA_AVALON_PIO_DATA(AVALONMM_SLAVE_DYNA7SEG_0_BASE+8, count&0xf);
IOWR_ALTERA_AVALON_PIO_DATA(AVALONMM_SLAVE_DYNA7SEG_0_BASE+12, count>>4);
IOWR_ALTERA_AVALON_PIO_DATA(AVALONMM_SLAVE_DYNA7SEG_0_BASE+16, count&0xf);
IOWR_ALTERA_AVALON_PIO_DATA(AVALONMM_SLAVE_DYNA7SEG_0_BASE+20, count>>4);
IOWR_ALTERA_AVALON_PIO_DATA(AVALONMM_SLAVE_DYNA7SEG_0_BASE+24, count&0xf);
IOWR_ALTERA_AVALON_PIO_DATA(AVALONMM_SLAVE_DYNA7SEG_0_BASE+28, count>>4);
usleep(500000);
}
}
static void SevenSegCount( void )
{
alt_u32 count;
for (count = 0; count <= 0xff; count++)
{
IOWR_ALTERA_AVALON_PIO_DATA(AVALONMM_SLAVE_DYNA7SEG_0_BASE, count&0xf);
IOWR_ALTERA_AVALON_PIO_DATA(AVALONMM_SLAVE_DYNA7SEG_0_BASE+4, count&0xf);
IOWR_ALTERA_AVALON_PIO_DATA(AVALONMM_SLAVE_DYNA7SEG_0_BASE+8, count&0xf);
IOWR_ALTERA_AVALON_PIO_DATA(AVALONMM_SLAVE_DYNA7SEG_0_BASE+12, count&0xf);
IOWR_ALTERA_AVALON_PIO_DATA(AVALONMM_SLAVE_DYNA7SEG_0_BASE+16, count&0xf);
IOWR_ALTERA_AVALON_PIO_DATA(AVALONMM_SLAVE_DYNA7SEG_0_BASE+20, count&0xf);
IOWR_ALTERA_AVALON_PIO_DATA(AVALONMM_SLAVE_DYNA7SEG_0_BASE+24, count&0xf);
IOWR_ALTERA_AVALON_PIO_DATA(AVALONMM_SLAVE_DYNA7SEG_0_BASE+28, count&0xf);
usleep(500000);
}
}
assign seven_seg_digit = drive_led;
nois_sdram nois_sdram_inst
(
.clk_0 (clk_0),
.out_port_from_the_led_pio (out_port_from_the_led_pio),
.reset_n (reset_n),
.seven_seg_a_from_the_AvalonMM_Slave_Dyna7seg_0 (seven_seg_a_from_the_AvalonMM_Slave_Dyna7seg_0),
.seven_seg_b_from_the_AvalonMM_Slave_Dyna7seg_0 (seven_seg_b_from_the_AvalonMM_Slave_Dyna7seg_0),
.seven_seg_c_from_the_AvalonMM_Slave_Dyna7seg_0 (seven_seg_c_from_the_AvalonMM_Slave_Dyna7seg_0),
.seven_seg_d_from_the_AvalonMM_Slave_Dyna7seg_0 (seven_seg_d_from_the_AvalonMM_Slave_Dyna7seg_0),
.seven_seg_digit_from_the_AvalonMM_Slave_Dyna7seg_0 (seven_seg_digit_from_the_AvalonMM_Slave_Dyna7seg_0),
.seven_seg_dp_from_the_AvalonMM_Slave_Dyna7seg_0 (seven_seg_dp_from_the_AvalonMM_Slave_Dyna7seg_0),
.seven_seg_e_from_the_AvalonMM_Slave_Dyna7seg_0 (seven_seg_e_from_the_AvalonMM_Slave_Dyna7seg_0),
.seven_seg_f_from_the_AvalonMM_Slave_Dyna7seg_0 (seven_seg_f_from_the_AvalonMM_Slave_Dyna7seg_0),
.seven_seg_g_from_the_AvalonMM_Slave_Dyna7seg_0 (seven_seg_g_from_the_AvalonMM_Slave_Dyna7seg_0),
.zs_addr_from_the_sdram (zs_addr_from_the_sdram),
.zs_ba_from_the_sdram (zs_ba_from_the_sdram),
.zs_cas_n_from_the_sdram (zs_cas_n_from_the_sdram),
.zs_cke_from_the_sdram (zs_cke_from_the_sdram),
.zs_cs_n_from_the_sdram (zs_cs_n_from_the_sdram),
.zs_dq_to_and_from_the_sdram (zs_dq_to_and_from_the_sdram),
.zs_dqm_from_the_sdram (zs_dqm_from_the_sdram),
.zs_ras_n_from_the_sdram (zs_ras_n_from_the_sdram),
.zs_we_n_from_the_sdram (zs_we_n_from_the_sdram)
);
// nois2_sdram_led
`default_nettype none
module nois2_sdram_led(
input wire clk,
input wire reset_n,
output wire [7:0] led_pio,
output wire sdram_clk,
output wire [11:0] SDRAM_A,
output wire [1:0] SDRAM_BA,
output wire SDRAM_nCAS,
output wire SDRAM_CKE,
output wire SDRAM_nCS,
inout wire [15:0] SDRAM_D,
output wire [1:0] SDRAM_DQM,
output wire SDRAM_nRAS,
output wire SDRAM_nWE,
output wire [7:0] seven_seg_digit,
output wire seven_seg_a,
output wire seven_seg_b,
output wire seven_seg_c,
output wire seven_seg_d,
output wire seven_seg_e,
output wire seven_seg_f,
output wire seven_seg_g,
output wire seven_seg_dp
);
wire clk_pll;
wire pll_locked;
reg [10:0] count;
wire reset_n_int_node, reset_n_int;
nois_sdram nois_sdram_inst
(
.clk_0 (clk_pll),
.out_port_from_the_led_pio (led_pio),
.reset_n (reset_n_int),
.seven_seg_a_from_the_AvalonMM_Slave_Dyna7seg_0 (seven_seg_a),
.seven_seg_b_from_the_AvalonMM_Slave_Dyna7seg_0 (seven_seg_b),
.seven_seg_c_from_the_AvalonMM_Slave_Dyna7seg_0 (seven_seg_c),
.seven_seg_d_from_the_AvalonMM_Slave_Dyna7seg_0 (seven_seg_d),
.seven_seg_digit_from_the_AvalonMM_Slave_Dyna7seg_0 (seven_seg_digit),
.seven_seg_dp_from_the_AvalonMM_Slave_Dyna7seg_0 (seven_seg_dp),
.seven_seg_e_from_the_AvalonMM_Slave_Dyna7seg_0 (seven_seg_e),
.seven_seg_f_from_the_AvalonMM_Slave_Dyna7seg_0 (seven_seg_f),
.seven_seg_g_from_the_AvalonMM_Slave_Dyna7seg_0 (seven_seg_g),
.zs_addr_from_the_sdram (SDRAM_A),
.zs_ba_from_the_sdram (SDRAM_BA),
.zs_cas_n_from_the_sdram (SDRAM_nCAS),
.zs_cke_from_the_sdram (SDRAM_CKE),
.zs_cs_n_from_the_sdram (SDRAM_nCS),
.zs_dq_to_and_from_the_sdram (SDRAM_D),
.zs_dqm_from_the_sdram (SDRAM_DQM),
.zs_ras_n_from_the_sdram (SDRAM_nRAS),
.zs_we_n_from_the_sdram (SDRAM_nWE)
);
altpllpll altpllpll_inst(
.inclk0 ( clk ),
.c0 ( clk_pll ),
.c1 ( sdram_clk ),
.locked ( pll_locked )
);
always @(posedge clk) begin
if (!reset_n)
count <= 11'd0;
else begin
if (count[10]==1'b0)
count <= count + 11'd1;
end
end
assign reset_n_int_node = count[10];
assign reset_n_int = reset_n_int_node & pll_locked;
endmodule
// Dynamic 7segment Display test
// avs_s1_address = 0 : seven_value0(下位5ビットのみ使用)
// avs_s1_address = 1 : seven_value1(下位5ビットのみ使用)
// avs_s1_address = 2 : seven_value2(下位5ビットのみ使用)
// avs_s1_address = 3 : seven_value3(下位5ビットのみ使用)
// avs_s1_address = 4 : seven_value4(下位5ビットのみ使用)
// avs_s1_address = 5 : seven_value5(下位5ビットのみ使用)
// avs_s1_address = 6 : seven_value6(下位5ビットのみ使用)
// avs_s1_address = 7 : seven_value7(下位5ビットのみ使用)
// +16をするとDPが点灯
`default_nettype none
module AvalonMM_Slave_Dyna7seg(
input wire csi_global_reset, // リセット
input wire csi_global_clk, // クロック
input wire[2:0] avs_s1_address, // アバロンバス
input wire avs_s1_read, // アバロンバス
output reg[31:0] avs_s1_readdata, // アバロンバス
input wire avs_s1_write, // アバロンバス
input wire[31:0] avs_s1_writedata, // アバロンバス
output wire[7:0] seven_seg_digit, // 外部出力、7セグメントLEDデジット
output reg seven_seg_a, // 外部出力、7セグメントLEDセグメント
output reg seven_seg_b, // 外部出力、7セグメントLEDセグメント
output reg seven_seg_c, // 外部出力、7セグメントLEDセグメント
output reg seven_seg_d, // 外部出力、7セグメントLEDセグメント
output reg seven_seg_e, // 外部出力、7セグメントLEDセグメント
output reg seven_seg_f, // 外部出力、7セグメントLEDセグメント
output reg seven_seg_g, // 外部出力、7セグメントLEDセグメント
output reg seven_seg_dp // 外部出力、7セグメントLEDセグメント
);
reg[7:0] seven_value [7:0]; // 7セグメントの表示
reg[31:0] avs_s1_readdata_node;
reg[7:0] drive_led; // 7セグLEDを指定するカウント
wire disp_ena;
reg[3:0] led_binary;
wire[6:0] segdecout;
// avalon bus write
always @(posedge csi_global_clk, posedge csi_global_reset) begin : SEVEN_VALUE_PROCESS
integer i; // ローカル変数iの宣言
if (csi_global_reset) begin
for (i=0; i<8 ; i=i+1) begin
seven_value[i] <= 8'd0;
end
end else begin
if (avs_s1_write) begin
case(avs_s1_address)
3'b000 :
seven_value[0] <= avs_s1_writedata[7:0];
3'b001 :
seven_value[1] <= avs_s1_writedata[7:0];
3'b010 :
seven_value[2] <= avs_s1_writedata[7:0];
3'b011 :
seven_value[3] <= avs_s1_writedata[7:0];
3'b100 :
seven_value[4] <= avs_s1_writedata[7:0];
3'b101 :
seven_value[5] <= avs_s1_writedata[7:0];
3'b110 :
seven_value[6] <= avs_s1_writedata[7:0];
3'b111 :
seven_value[7] <= avs_s1_writedata[7:0];
endcase
end
end
end
// avalon bus read
always @* begin
avs_s1_readdata[31:8] = 24'd0;
case (avs_s1_address)
3'b000 :
avs_s1_readdata[7:0] <= seven_value[0];
3'b001 :
avs_s1_readdata[7:0] <= seven_value[1];
3'b010 :
avs_s1_readdata[7:0] <= seven_value[2];
3'b011 :
avs_s1_readdata[7:0] <= seven_value[3];
3'b100 :
avs_s1_readdata[7:0] <= seven_value[4];
3'b101 :
avs_s1_readdata[7:0] <= seven_value[5];
3'b110 :
avs_s1_readdata[7:0] <= seven_value[6];
default : // 3'b111
avs_s1_readdata[7:0] <= seven_value[7];
endcase
end
// LED選択用シフトレジスタ
always @(posedge csi_global_clk) begin
if (csi_global_reset)
drive_led <= 8'b1111_1110;
else begin
if (disp_ena) begin
if (drive_led[7]==1'b0) // 最後の次はdrive_led[0]を0にする
drive_led <= 8'b1111_1110;
else
drive_led <= {drive_led[6:0], 1'b1}; // 0を1ビットシフト
end
end
end
assign seven_seg_digit = drive_led;
// LEDリフレッシュ周波数分周器
FreqDiv FreqDiv_inst(
.clk(csi_global_clk),
.reset(csi_global_reset),
.disp_ena(disp_ena)
);
// 7セグメント・デコーダ
B27segDec B27segDec_inst(
.binary(led_binary),
.enable(1'b1),
.segdecout(segdecout)
);
// 7セグメント・デコーダに入れるバイナリデータの選択と出力の選択
always @(posedge csi_global_clk) begin : SELECTED_BINAREY_DATA
integer i; // ローカル変数の宣言
if (csi_global_reset) begin
led_binary <= 4'd0;
{seven_seg_dp, seven_seg_a, seven_seg_b, seven_seg_c, seven_seg_d, seven_seg_e, seven_seg_f, seven_seg_g} <= -1;
end else begin
for(i=0; i<8; i=i+1) begin
if (drive_led[i]==1'b0) begin
led_binary <= seven_value[i];
{seven_seg_dp, seven_seg_a, seven_seg_b, seven_seg_c, seven_seg_d, seven_seg_e, seven_seg_f, seven_seg_g} <= {~seven_value[i][4], ~segdecout}; // 0で点灯なのでsegdecoutを反転する
end
end
end
end
endmodule
//入力クロックをダイナミック点灯時の周波数(1KHz)に分周する
// 1KHz clock
// マスタークロックを1KHzのdisp_enaに分周します。
// クロック周波数をclk_frequencyにKHz単位で設定してください。defaultで50MHzです。
// lcntが16ビットになっているので、clk_frequencyが65536以上の場合はビットを増やしてください。
// sync resetに変更
`default_nettype none
`timescale 1ns / 1ps
module FreqDiv(clk, reset, disp_ena);
input clk, reset;
output disp_ena;
wire clk, reset;
wire disp_ena;
reg [20:0] lcnt;
parameter clk_frequency = 50000;
always @(posedge clk) begin
if (reset)
lcnt <= 0;
else if (lcnt==clk_frequency)
lcnt <= 0;
else
lcnt <= lcnt + 1;
end
assign disp_ena = (lcnt==clk_frequency);
endmodule
// Frequncy Divider for Dynamic Lighting
// 1KHz clock
// マスタークロックを1KHzのdisp_enaに分周します。
// クロック周波数をclk_frequencyにKHz単位で設定してください。defaultで50MHzです。
// Binary to 7 segment LED Decoder
// バイナリデータを7セグメントLED用のデータに変換します。
// enableを0にすると消灯。
// 点灯するセグメントを1で表しているが、実際には0で点灯するので上のファイルで反転しています。
`default_nettype none
`timescale 1ns / 1ps
module B27segDec(binary, enable, segdecout);
input [3:0] binary;
input enable;
output [6:0] segdecout;
wire [3:0] binary;
wire enable;
reg [6:0] segdecout;
always @* begin
if (enable)
case (binary)
4'h0 :
segdecout = 7'b1111110;
4'h1 :
segdecout = 7'b0110000;
4'h2 :
segdecout = 7'b1101101;
4'h3 :
segdecout = 7'b1111001;
4'h4 :
segdecout = 7'b0110011;
4'h5 :
segdecout = 7'b1011011;
4'h6 :
segdecout = 7'b1011111;
4'h7 :
segdecout = 7'b1110000;
4'h8 :
segdecout = 7'b1111111;
4'h9 :
segdecout = 7'b1111011;
4'hA :
segdecout = 7'b1110111;
4'hB :
segdecout = 7'b0011111;
4'hC :
segdecout = 7'b1001110;
4'hD :
segdecout = 7'b0111101;
default : // F
segdecout = 7'b1000111;
endcase
else
segdecout = 7'b1111111;
end
endmodule
// AvalonMM_Slave_Dyna7seg_tb
`default_nettype none
`timescale 1ns / 1ps
module AvalonMM_Slave_Dyna7seg_tb;
reg csi_global_reset; // リセット
reg csi_global_clk; // クロック
reg[2:0] avs_s1_address; // アバロンバス
reg avs_s1_read; // アバロンバス
wire[31:0] avs_s1_readdata; // アバロンバス
reg avs_s1_write; // アバロンバス
reg[31:0] avs_s1_writedata; // アバロンバス
wire[7:0] seven_seg_digit; // 外部出力、7セグメントLEDデジット
wire seven_seg_a; // 外部出力、7セグメントLEDセグメント
wire seven_seg_b; // 外部出力、7セグメントLEDセグメント
wire seven_seg_c; // 外部出力、7セグメントLEDセグメント
wire seven_seg_d; // 外部出力、7セグメントLEDセグメント
wire seven_seg_e; // 外部出力、7セグメントLEDセグメント
wire seven_seg_f; // 外部出力、7セグメントLEDセグメント
wire seven_seg_g; // 外部出力、7セグメントLEDセグメント
wire seven_seg_dp; // 外部出力、7セグメントLEDセグメント
parameter CLK_PERIOD = 20;
defparam AvalonMM_Slave_Dyna7seg_inst.FreqDiv_inst.clk_frequency = 5; // シミュレーション用にカウント数を小さくする
AvalonMM_Slave_Dyna7seg AvalonMM_Slave_Dyna7seg_inst(
.csi_global_reset(csi_global_reset),
.csi_global_clk(csi_global_clk),
.avs_s1_address(avs_s1_address),
.avs_s1_read(avs_s1_read),
.avs_s1_readdata(avs_s1_readdata),
.avs_s1_write(avs_s1_write),
.avs_s1_writedata(avs_s1_writedata),
.seven_seg_digit(seven_seg_digit),
.seven_seg_a(seven_seg_a),
.seven_seg_b(seven_seg_b),
.seven_seg_c(seven_seg_c),
.seven_seg_d(seven_seg_d),
.seven_seg_e(seven_seg_e),
.seven_seg_f(seven_seg_f),
.seven_seg_g(seven_seg_g),
.seven_seg_dp(seven_seg_dp)
);
initial begin
csi_global_reset = 1'b1;
#100 csi_global_reset = 1'b0;
end
always begin
#(CLK_PERIOD/2) csi_global_clk = 1'b1 ;
#(CLK_PERIOD/2) csi_global_clk = 1'b0 ;
end
task AVALON_BUS_WRITE;
input[2:0] write_address;
input[31:0] write_data;
begin
@(posedge csi_global_clk); // 次のクロックの立ち上がり
#1;
avs_s1_write = 1'b1; // Write
avs_s1_address = write_address;
avs_s1_writedata = write_data;
@(posedge csi_global_clk); // 次のクロックの立ち上がり
#1;
avs_s1_write = 1'b0;
end
endtask
task AVALON_BUS_READ;
input[2:0] read_address;
begin
@(posedge csi_global_clk); // 次のクロックの立ち上がり
#1;
avs_s1_address = read_address;
@(posedge csi_global_clk); // 次のクロックの立ち上がり
#1;
end
endtask
initial begin
avs_s1_address = 3'd0;
avs_s1_read = 1'b0;
avs_s1_write = 1'b0;
avs_s1_writedata = 32'd0;
#100;
AVALON_BUS_WRITE(3'd0, 32'h0000_0001);
AVALON_BUS_WRITE(3'd1, 32'h0000_0002);
AVALON_BUS_WRITE(3'd2, 32'h0000_0003);
AVALON_BUS_WRITE(3'd3, 32'h0000_0004);
AVALON_BUS_WRITE(3'd4, 32'h0000_0005);
AVALON_BUS_WRITE(3'd5, 32'h0000_0006);
AVALON_BUS_WRITE(3'd6, 32'h0000_0007);
AVALON_BUS_WRITE(3'd7, 32'h0000_0008);
#100;
AVALON_BUS_READ(3'd0);
AVALON_BUS_READ(3'd1);
AVALON_BUS_READ(3'd2);
AVALON_BUS_READ(3'd3);
AVALON_BUS_READ(3'd4);
AVALON_BUS_READ(3'd5);
AVALON_BUS_READ(3'd6);
AVALON_BUS_READ(3'd7);
#500;
$stop;
end
endmodule
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.0 Build 184 04/29/2009 Service Pack 1 SJ Web Edition
# Date created = 19:20:23 July 31, 2009
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# nios2_sdram_led_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C5Q208C8
set_global_assignment -name TOP_LEVEL_ENTITY nois2_sdram_led
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:20:23 JULY 31, 2009"
set_global_assignment -name LAST_QUARTUS_VERSION "9.0 SP1"
set_global_assignment -name EDA_SIMULATION_TOOL ""
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
set_global_assignment -name DEVICE_FILTER_PACKAGE PQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 208
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name QIP_FILE nois_sdram.qip
set_global_assignment -name VERILOG_FILE nois2_sdram_led.v
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_location_assignment PIN_152 -to SDRAM_A[11]
set_location_assignment PIN_187 -to SDRAM_A[10]
set_location_assignment PIN_160 -to SDRAM_A[9]
set_location_assignment PIN_161 -to SDRAM_A[8]
set_location_assignment PIN_162 -to SDRAM_A[7]
set_location_assignment PIN_163 -to SDRAM_A[6]
set_location_assignment PIN_164 -to SDRAM_A[5]
set_location_assignment PIN_165 -to SDRAM_A[4]
set_location_assignment PIN_185 -to SDRAM_A[3]
set_location_assignment PIN_182 -to SDRAM_A[2]
set_location_assignment PIN_181 -to SDRAM_A[1]
set_location_assignment PIN_180 -to SDRAM_A[0]
set_location_assignment PIN_188 -to SDRAM_BA[1]
set_global_assignment -name MISC_FILE "H:/HDL/Altera/qdesigns/nisyo_board/nios2_sdram_led/nios2_sdram_led.dpf"
set_location_assignment PIN_189 -to SDRAM_BA[0]
//Example instantiation for system 'nois_sdram'
nois_sdram nois_sdram_inst
(
.clk_0 (clk_0),
.out_port_from_the_exboard_led_pio (out_port_from_the_exboard_led_pio),
.pll_0_c0_out (pll_0_c0_out),
.pll_0_c1_out (pll_0_c1_out),
.reset_n (reset_n),
.zs_addr_from_the_sdram_0 (zs_addr_from_the_sdram_0),
.zs_ba_from_the_sdram_0 (zs_ba_from_the_sdram_0),
.zs_cas_n_from_the_sdram_0 (zs_cas_n_from_the_sdram_0),
.zs_cke_from_the_sdram_0 (zs_cke_from_the_sdram_0),
.zs_cs_n_from_the_sdram_0 (zs_cs_n_from_the_sdram_0),
.zs_dq_to_and_from_the_sdram_0 (zs_dq_to_and_from_the_sdram_0),
.zs_dqm_from_the_sdram_0 (zs_dqm_from_the_sdram_0),
.zs_ras_n_from_the_sdram_0 (zs_ras_n_from_the_sdram_0),
.zs_we_n_from_the_sdram_0 (zs_we_n_from_the_sdram_0)
);
Error: Can't generate netlist output files because the file "H:/HDL/Altera/qdesigns/nisyo_board/nios2_sdram_led/incremental_db/compiled_partitions/nios2_sdram_led.root_partition.map.atm" is an OpenCore Plus time-limited file
// nois2_sdram_led
`default_nettype none
module nois2_sdram_led(clk, reset_n, exboard_led_pio, sdram_clk, SDRAM_A, SDRAM_BA, SDRAM_nCAS, SDRAM_CKE, SDRAM_nCS, SDRAM_D, SDRAM_DQM, SDRAM_nRAS, SDRAM_nWE);
input clk;
input reset_n;
output [7:0] exboard_led_pio;
output sdram_clk;
output [11:0] SDRAM_A;
output [1:0] SDRAM_BA;
output SDRAM_nCAS;
output SDRAM_CKE;
output SDRAM_nCS;
inout [15:0] SDRAM_D;
output [1:0] SDRAM_DQM;
output SDRAM_nRAS;
output SDRAM_nWE;
wire clk;
wire reset_n;
wire [7:0] exboard_led_pio;
wire sdram_clk;
wire [11:0] SDRAM_A;
wire [1:0] SDRAM_BA;
wire SDRAM_nCAS;
wire SDRAM_CKE;
wire SDRAM_nCS;
wire [15:0] SDRAM_D;
wire [1:0] SDRAM_DQM;
wire SDRAM_nRAS;
wire SDRAM_nWE;
nois_sdram nois_sdram_inst
(
.clk_0 (clk),
.out_port_from_the_exboard_led_pio (exboard_led_pio),
.pll_0_c0_out (),
.pll_0_c1_out (sdram_clk),
.reset_n (reset_n),
.zs_addr_from_the_sdram_0 (SDRAM_A),
.zs_ba_from_the_sdram_0 (SDRAM_BA),
.zs_cas_n_from_the_sdram_0 (SDRAM_nCAS),
.zs_cke_from_the_sdram_0 (SDRAM_CKE),
.zs_cs_n_from_the_sdram_0 (SDRAM_nCS),
.zs_dq_to_and_from_the_sdram_0 (SDRAM_D),
.zs_dqm_from_the_sdram_0 (SDRAM_DQM),
.zs_ras_n_from_the_sdram_0 (SDRAM_nRAS),
.zs_we_n_from_the_sdram_0 (SDRAM_nWE)
);
endmodule
// nois2_sdram_led
`default_nettype none
module nois2_sdram_led(
input wire clk,
input wire reset_n,
output wire [7:0] exboard_led_pio,
output wire sdram_clk,
output wire [11:0] SDRAM_A,
output wire [1:0] SDRAM_BA,
output wire SDRAM_nCAS,
output wire SDRAM_CKE,
output wire SDRAM_nCS,
output wire [15:0] SDRAM_D,
output wire [1:0] SDRAM_DQM,
output wire SDRAM_nRAS,
output wire SDRAM_nWE);
nois_sdram nois_sdram_inst
(
.clk_0 (clk),
.out_port_from_the_exboard_led_pio (exboard_led_pio),
.pll_0_c0_out (),
.pll_0_c1_out (sdram_clk),
.reset_n (reset_n),
.zs_addr_from_the_sdram_0 (SDRAM_A),
.zs_ba_from_the_sdram_0 (SDRAM_BA),
.zs_cas_n_from_the_sdram_0 (SDRAM_nCAS),
.zs_cke_from_the_sdram_0 (SDRAM_CKE),
.zs_cs_n_from_the_sdram_0 (SDRAM_nCS),
.zs_dq_to_and_from_the_sdram_0 (SDRAM_D),
.zs_dqm_from_the_sdram_0 (SDRAM_DQM),
.zs_ras_n_from_the_sdram_0 (SDRAM_nRAS),
.zs_we_n_from_the_sdram_0 (SDRAM_nWE)
);
endmodule
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