assign display_enable = display_on_d2;
// CharDispCtrlerTest_SP605.v
// CharDispCtrlerTest.vのSP605用のラッパー、CH7301Cを使用する
//
// 2012/07/26 : ODDR2 のDDR_ALIGNMENTとSRTYPEを修正
//
`default_nettype none
module CharDispCtrlerTest_SP605 (
input wire sysclk_p, sysclk_n,
input wire reset_sw,
output wire dvi_xclk_p, dvi_xclk_n,
output reg dvi_de, dvi_h, dvi_v,
output wire [11:0] dvi_d,
output wire dvi_reset_b,
output wire dvi_sda,
output wire dvi_scl
);
wire clk, clkb;
wire clk90, clk90b;
wire clkdv;
wire reset;
wire locked;
wire vga_red, vga_green, vga_blue;
wire vga_hsync, vga_vsync;
wire display_enable;
DCM_CLKGEN_S6 clk200_DCM (
.CLK_IN1_P (sysclk_p), // IN
.CLK_IN1_N (sysclk_n), // IN
// Clock out ports
.CLK_OUT1 (clk), // OUT
.CLK_OUT2 (clk90), // OUT
// Status and control signals
.RESET (reset_sw), // IN
.LOCKED (locked) // OUT
);
assign reset = !locked;
assign clkb = !clk;
assign clk90b = !clk90;
// assign dvi_reset_b = locked;
assign dvi_reset_b = 1'b1;
CharDispCtrlerTest CharDispCtrlerTest_inst (
.clk(clk),
.reset(reset),
.VGA_RED(vga_red),
.VGA_GREEN(vga_green),
.VGA_BLUE(vga_blue),
.VGA_HSYNC(vga_hsync),
.VGA_VSYNC(vga_vsync),
.display_enable(display_enable)
);
always @(posedge clk) begin
if (reset) begin
dvi_de <= 1'b0;
dvi_h <= 1'b1;
dvi_v <= 1'b1;
end else begin
dvi_de <= display_enable;
dvi_h <= vga_hsync;
dvi_v <= vga_vsync;
end
end
// dvi_xclk_p : clkbと同位相
ODDR2 #(
.DDR_ALIGNMENT("C0"), // Sets output alignment to "NONE", "C0" or "C1"
.INIT(1'b0), // Sets initial state of the Q output to 1’b0 or 1’b1
.SRTYPE("ASYNC") // Specifies "SYNC" or "ASYNC" set/reset
) ODDR2_xclk_p (
.Q(dvi_xclk_p), // 1-bit DDR output data
.C0(clk90), // 1-bit clock input
.C1(clk90b), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D0(1'b1), // 1-bit data input (associated with C0)
.D1(1'b0), // 1-bit data input (associated with C1)
.R(reset), // 1-bit reset input
.S(1'b0) // 1-bit set input
);
// dvi_xclk_n : clkと同位相
ODDR2 #(
.DDR_ALIGNMENT("C0"), // Sets output alignment to "NONE", "C0" or "C1"
.INIT(1'b1), // Sets initial state of the Q output to 1’b0 or 1’b1
.SRTYPE("ASYNC") // Specifies "SYNC" or "ASYNC" set/reset
) ODDR2_xclk_n (
.Q(dvi_xclk_n), // 1-bit DDR output data
.C0(clk90), // 1-bit clock input
.C1(clk90b), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D0(1'b0), // 1-bit data input (associated with C0)
.D1(1'b1), // 1-bit data input (associated with C1)
.R(reset), // 1-bit reset input
.S(1'b0) // 1-bit set input
);
// DVI_D// DVI_D[0]
ODDR2 #(
.DDR_ALIGNMENT("C0"), // Sets output alignment to "NONE", "C0" or "C1"
.INIT(1'b0), // Sets initial state of the Q output to 1’b0 or 1’b1
.SRTYPE("ASYNC") // Specifies "SYNC" or "ASYNC" set/reset
) ODDR2_D0 (
.Q(dvi_d[0]), // 1-bit DDR output data
.C0(clk), // 1-bit clock input
.C1(clkb), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D0(vga_blue), // B0[0], 1-bit data input (associated with C0)
.D1(vga_green), // G0[4], 1-bit data input (associated with C1)
.R(reset), // 1-bit reset input
.S(1'b0) // 1-bit set input
);
ODDR2 #( // DVI_D[1]
.DDR_ALIGNMENT("C0"), // Sets output alignment to "NONE", "C0" or "C1"
.INIT(1'b0), // Sets initial state of the Q output to 1’b0 or 1’b1
.SRTYPE("ASYNC") // Specifies "SYNC" or "ASYNC" set/reset
) ODDR2_D1 (
.Q(dvi_d[1]), // 1-bit DDR output data
.C0(clk), // 1-bit clock input
.C1(clkb), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D0(vga_blue), // B0[1], 1-bit data input (associated with C0)
.D1(vga_green), // G0[5], 1-bit data input (associated with C1)
.R(reset), // 1-bit reset input
.S(1'b0) // 1-bit set input
);
ODDR2 #( // DVI_D[2]
.DDR_ALIGNMENT("C0"), // Sets output alignment to "NONE", "C0" or "C1"
.INIT(1'b0), // Sets initial state of the Q output to 1’b0 or 1’b1
.SRTYPE("ASYNC") // Specifies "SYNC" or "ASYNC" set/reset
) ODDR2_D2 (
.Q(dvi_d[2]), // 1-bit DDR output data
.C0(clk), // 1-bit clock input
.C1(clkb), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D0(vga_blue), // B0[2], 1-bit data input (associated with C0)
.D1(vga_green), // G0[6], 1-bit data input (associated with C1)
.R(reset), // 1-bit reset input
.S(1'b0) // 1-bit set input
);
ODDR2 #( // DVI_D[3]
.DDR_ALIGNMENT("C0"), // Sets output alignment to "NONE", "C0" or "C1"
.INIT(1'b0), // Sets initial state of the Q output to 1’b0 or 1’b1
.SRTYPE("ASYNC") // Specifies "SYNC" or "ASYNC" set/reset
) ODDR2_D3 (
.Q(dvi_d[3]), // 1-bit DDR output data
.C0(clk), // 1-bit clock input
.C1(clkb), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D0(vga_blue), // B0[3], 1-bit data input (associated with C0)
.D1(vga_green), // G0[7], 1-bit data input (associated with C1)
.R(reset), // 1-bit reset input
.S(1'b0) // 1-bit set input
);
ODDR2 #( // DVI_D[4]
.DDR_ALIGNMENT("C0"), // Sets output alignment to "NONE", "C0" or "C1"
.INIT(1'b0), // Sets initial state of the Q output to 1’b0 or 1’b1
.SRTYPE("ASYNC") // Specifies "SYNC" or "ASYNC" set/reset
) ODDR2_D4 (
.Q(dvi_d[4]), // 1-bit DDR output data
.C0(clk), // 1-bit clock input
.C1(clkb), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D0(vga_blue), // B0[4], 1-bit data input (associated with C0)
.D1(vga_red), // R0[0], 1-bit data input (associated with C1)
.R(reset), // 1-bit reset input
.S(1'b0) // 1-bit set input
);
ODDR2 #( // DVI_D[5]
.DDR_ALIGNMENT("C0"), // Sets output alignment to "NONE", "C0" or "C1"
.INIT(1'b0), // Sets initial state of the Q output to 1’b0 or 1’b1
.SRTYPE("ASYNC") // Specifies "SYNC" or "ASYNC" set/reset
) ODDR2_D5 (
.Q(dvi_d[5]), // 1-bit DDR output data
.C0(clk), // 1-bit clock input
.C1(clkb), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D0(vga_blue), // B0[5], 1-bit data input (associated with C0)
.D1(vga_red), // R0[1], 1-bit data input (associated with C1)
.R(reset), // 1-bit reset input
.S(1'b0) // 1-bit set input
);
ODDR2 #( // DVI_D[6]
.DDR_ALIGNMENT("C0"), // Sets output alignment to "NONE", "C0" or "C1"
.INIT(1'b0), // Sets initial state of the Q output to 1’b0 or 1’b1
.SRTYPE("ASYNC") // Specifies "SYNC" or "ASYNC" set/reset
) ODDR2_D6 (
.Q(dvi_d[6]), // 1-bit DDR output data
.C0(clk), // 1-bit clock input
.C1(clkb), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D0(vga_blue), // B0[6], 1-bit data input (associated with C0)
.D1(vga_red), // R0[2], 1-bit data input (associated with C1)
.R(reset), // 1-bit reset input
.S(1'b0) // 1-bit set input
);
ODDR2 #( // DVI_D[7]
.DDR_ALIGNMENT("C0"), // Sets output alignment to "NONE", "C0" or "C1"
.INIT(1'b0), // Sets initial state of the Q output to 1’b0 or 1’b1
.SRTYPE("ASYNC") // Specifies "SYNC" or "ASYNC" set/reset
) ODDR2_D7 (
.Q(dvi_d[7]), // 1-bit DDR output data
.C0(clk), // 1-bit clock input
.C1(clkb), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D0(vga_blue), // B0[7], 1-bit data input (associated with C0)
.D1(vga_red), // R0[3], 1-bit data input (associated with C1)
.R(reset), // 1-bit reset input
.S(1'b0) // 1-bit set input
);
ODDR2 #( // DVI_D[8]
.DDR_ALIGNMENT("C0"), // Sets output alignment to "NONE", "C0" or "C1"
.INIT(1'b0), // Sets initial state of the Q output to 1’b0 or 1’b1
.SRTYPE("ASYNC") // Specifies "SYNC" or "ASYNC" set/reset
) ODDR2_D8 (
.Q(dvi_d[8]), // 1-bit DDR output data
.C0(clk), // 1-bit clock input
.C1(clkb), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D0(vga_green), // G0[0], 1-bit data input (associated with C0)
.D1(vga_red), // R0[4], 1-bit data input (associated with C1)
.R(reset), // 1-bit reset input
.S(1'b0) // 1-bit set input
);
ODDR2 #( // DVI_D[9]
.DDR_ALIGNMENT("C0"), // Sets output alignment to "NONE", "C0" or "C1"
.INIT(1'b0), // Sets initial state of the Q output to 1’b0 or 1’b1
.SRTYPE("ASYNC") // Specifies "SYNC" or "ASYNC" set/reset
) ODDR2_D9 (
.Q(dvi_d[9]), // 1-bit DDR output data
.C0(clk), // 1-bit clock input
.C1(clkb), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D0(vga_green), // G0[1], 1-bit data input (associated with C0)
.D1(vga_red), // R0[5], 1-bit data input (associated with C1)
.R(reset), // 1-bit reset input
.S(1'b0) // 1-bit set input
);
ODDR2 #( // DVI_D[10]
.DDR_ALIGNMENT("C0"), // Sets output alignment to "NONE", "C0" or "C1"
.INIT(1'b0), // Sets initial state of the Q output to 1’b0 or 1’b1
.SRTYPE("ASYNC") // Specifies "SYNC" or "ASYNC" set/reset
) ODDR2_D10 (
.Q(dvi_d[10]), // 1-bit DDR output data
.C0(clk), // 1-bit clock input
.C1(clkb), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D0(vga_green), // G0[2], 1-bit data input (associated with C0)
.D1(vga_red), // R0[6], 1-bit data input (associated with C1)
.R(reset), // 1-bit reset input
.S(1'b0) // 1-bit set input
);
ODDR2 #( // DVI_D[11]
.DDR_ALIGNMENT("C0"), // Sets output alignment to "NONE", "C0" or "C1"
.INIT(1'b0), // Sets initial state of the Q output to 1’b0 or 1’b1
.SRTYPE("ASYNC") // Specifies "SYNC" or "ASYNC" set/reset
) ODDR2_D11 (
.Q(dvi_d[11]), // 1-bit DDR output data
.C0(clk), // 1-bit clock input
.C1(clkb), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D0(vga_green), // G0[3], 1-bit data input (associated with C0)
.D1(vga_red), // R0[7], 1-bit data input (associated with C1)
.R(reset), // 1-bit reset input
.S(1'b0) // 1-bit set input
);
SCCB_Reg_Controller I2C_Setting_inst (
.clk(clk),
.reset(reset),
.SCL(dvi_scl),
.SDA(dvi_sda)
);
endmodule
assign dvi_reset_b = locked;
assign dvi_reset_b = 1'b1;
parameter ENABLE_COUNT = 23'd250000; // インプリメント
defparam uut.CharDispCtrlerTest_inst.ENABLE_COUNT = 23'd000004; // シミュレーション
IDF Description
0 12-bit multiplexed RGB input (24-bit color), (multiplex scheme 1)
1 12-bit multiplexed RGB2 input (24-bit color), (multiplex scheme 2)
2 8-bit multiplexed RGB input (16-bit color, 565)
3 8-bit multiplexed RGB input (15-bit color, 555)
4 8-bit multiplexed YCrCb input (24-bit color), (Y, Cr and Cb are multiplexed)
initial begin
if ($value$plusargs("TESTNAME=%s", testname))
$display("Running test {%0s}......", testname);
else
begin
testname = "sample_smoke_test0";
$display("Running default test {%0s}......", testname);
end
demo_tb.exe -gui -testplusarg TESTNAME=sample_smoke_test1
Simulator is doing circuit initialization process.
Running test {sample_smoke_test1}......
[ 0] : System Reset Asserted...
Finished circuit initialization process.
[ 399600000] : System Reset De-asserted...
[ 960680600] : Transaction Reset Is De-asserted...
board.EP.s6_pcie_v1_3_i.PCIE_A1.B_PCIE_A1_INST.SHIP.SHELL.BUT.pcie_pcie_inv.pcie_pcie.pcie_core.xil_pcie_sa_mod18.xil_pcie_sa_mod19.com.tlm.u_tlm_rx.xil_pcie_sa_mod75 checking
[ 1894626600] : Transaction Link Is Up...
[ 1895816600] : TSK_PARSE_FRAME on Transmit
[ 2233396600] : TSK_PARSE_FRAME on Receive
[ 2295792600] : Check Device/Vendor ID - PASSED
[ 2296992600] : TSK_PARSE_FRAME on Transmit
[ 2559776600] : TSK_PARSE_FRAME on Receive
[ 2696968600] : Check CMPS ID - PASSED
[ 2696968600] : SYSTEM CHECK PASSED
[ 2696968600] : Reading from PCI/PCI-Express Configuration Register 0x00
[ 2696968600] : Expected Device/Vendor ID = 000710ee
[ 2698168600] : TSK_PARSE_FRAME on Transmit
[ 2962954600] : TSK_PARSE_FRAME on Receive
[ 2962954600] : Received CPLD --- Tag 0x00
[ 2962954600] : TEST PASSED --- Finished transmission of PCI-Express TLPs
[ 2963354800] : Reading Cfg Addr [0x00000001]
[ 2966951800] : Writing Cfg Addr [0x00000001]
[ 2970552600] : Reading Cfg Addr [0x00000001]
Stopped at time : 29734527 ps : File "H:/HDL/FndtnISEWork/Spartan6/sp605_pcie_ISE121/s6_pcie_v1_3/simulation/tests/tests.v" Line 205
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