.............
wire ACLK;
wire hdmir_clk;
// clk_gen (ACLK)
clk_gen #(
.CLK_PERIOD(50), // 10nsec, 100MHz
.CLK_DUTY_CYCLE(0.5),
.CLK_OFFSET(0),
.START_STATE(1'b0)
) ACLKi (
.clk_out(ACLK)
);
// clk_gen (hdmir_clk)
clk_gen #(
.CLK_PERIOD(68), // 6.8nsec, 147.6MHz(HD 148.5MHz)
.CLK_DUTY_CYCLE(0.5),
.CLK_OFFSET(0),
.START_STATE(1'b0)
) WRITE_CLKi (
.clk_out(hdmir_clk)
);
endmodule
module clk_gen #(
parameter CLK_PERIOD = 100,
parameter real CLK_DUTY_CYCLE = 0.5,
parameter CLK_OFFSET = 0,
parameter START_STATE = 1'b0 )
(
output reg clk_out
);
begin
initial begin
#CLK_OFFSET;
forever
begin
clk_out = START_STATE;
#(CLK_PERIOD-(CLK_PERIOD*CLK_DUTY_CYCLE)) clk_out = ~START_STATE;
#(CLK_PERIOD*CLK_DUTY_CYCLE);
end
end
end
endmodule
.................
reg ACLK = 1'b0;
reg hdmir_clk = 1'b0;
always #(50)
ACLK = ~ACLK;
always #(34)
hdmir_clk = ~hdmir_clk;
ISimハードウェア協調シミュレーション1(キャラクタ・ディスプレイ・コントローラ)
ISimハードウェア協調シミュレーション2(FFTのシミュレーション1)
ISimハードウェア協調シミュレーション3(FFTのシミュレーション2)
ERROR:HDLCompiler:104 - "C:/HDL/Xilinx/14.5/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/dynshreg_f.vhd" Line 328: Cannot find
in library . Please ensure that the library was compiled, and that a library and a use clause are present in the VHDL file.
ERROR:HDLCompiler:854 - "C:/HDL/Xilinx/14.5/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/dynshreg_f.vhd" Line 158: Unitignored due to previous errors.
--------------------------------------------------------------------------------
ERROR:HWCoSim - Program 'xst' returned with a non-zero exit code 6. Please refer to log file 'D:\HDL\FndtnISEWork\Zynq-7000\ZedBoard\test\VDMA_test2\isim\hwcosim_tmp\jtag\synth_model\xst_system_top.srp' for further details.
HDL wrapper and bitstream generation process failed.
Other Compiler Options : -L accellera_ovl_vlog=C:\HDL\Xilinx\14.6\ISE_DS\ISE\verilog\hdp\nt64\accellera_ovl_vlog
Specify Search Directories for 'Include : D:\HDL\OVL\std_ovl_v2p7
Specify 'define Macro Name and Value : OVL_VERILOG,OVL_ASSERT_ON,OVL_FINISH_OFF
現在のOVL Ver. 2.7 の入手先は、”License and Statement of Use of Accellera System Initiative's Open Verification Library”です。そのWebページの”Accept agreement and proceed to download OVL.”をクリックするとダウンロード出来ます。
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_always.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_always_on_edge.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_arbiter.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_bits.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_change.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_code_distance.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_coverage.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_decrement.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_crc.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_cycle_sequence.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_delta.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_even_parity.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_fifo.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_fifo_index.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_frame.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_handshake.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_hold_value.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_implication.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_increment.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_memory_async.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_memory_sync.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_multiport_fifo.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_mutex.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_never.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_never_unknown.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_never_unknown_async.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_next.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_next_state.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_no_contention.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_no_overflow.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_no_transition.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_no_underflow.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_odd_parity.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_one_cold.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_one_hot.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_proposition.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_quiescent_state.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_range.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_reg_loaded.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_req_ack_unique.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_req_requires.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_stack.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_time.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_transition.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_unchange.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_valid_id.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_value.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_value_coverage.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_width.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_window.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_win_change.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_win_unchange.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_xproduct_bit_coverage.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_xproduct_value_coverage.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_zero_one_hot.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\std_ovl.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\std_ovl_procs.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\std_ovl_components_vlog.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\std_ovl_clock_gating.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\std_ovl_reset_gating.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_always.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_always_on_edge.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_change.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_cycle_sequence.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_decrement.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_delta.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_even_parity.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_fifo_index.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_frame.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_handshake.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_implication.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_increment.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_never.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_never_unknown.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_never_unknown_async.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_next.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_no_overflow.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_no_transition.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_no_underflow.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_odd_parity.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_one_cold.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_one_hot.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_proposition.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_quiescent_state.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_range.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_time.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_transition.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_unchange.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_width.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_win_change.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_win_unchange.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_window.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_zero_one_hot.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\vhdl93\ovl_always_rtl.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\vhdl93\ovl_cycle_sequence_rtl.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\vhdl93\ovl_implication_rtl.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\vhdl93\ovl_never_rtl.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\vhdl93\ovl_never_unknown_async_rtl.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\vhdl93\ovl_never_unknown_rtl.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\vhdl93\ovl_next_rtl.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\vhdl93\ovl_one_hot_rtl.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\vhdl93\ovl_range_rtl.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\vhdl93\ovl_zero_one_hot_rtl.vhd
accellera_ovl_vlog=$XILINX/verilog/hdp/nt64/accellera_ovl_vlog
accellera_ovl_vhdl=$XILINX/vhdl/hdp/nt64/accellera_ovl_vhdl
`timescale 1ns / 1ps
module fp_fft_core_top_tb;
// Inputs
reg clk;
reg start;
reg [15:0] xn_re;
reg [15:0] xn_im;
reg fwd_inv;
reg fwd_inv_we;
reg [13:0] scale_sch;
reg scale_sch_we;
// Outputs
wire rfd;
wire [13:0] xn_index;
wire busy;
wire edone;
wire done;
wire dv;
wire [13:0] xk_index;
wire [15:0] xk_re;
wire [15:0] xk_im;
// Instantiate the Unit Under Test (UUT)
fp_fft_core_top uut (
.clk(clk),
.start(start),
.xn_re(xn_re),
.xn_im(xn_im),
.fwd_inv(fwd_inv),
.fwd_inv_we(fwd_inv_we),
.scale_sch(scale_sch),
.scale_sch_we(scale_sch_we),
.rfd(rfd),
.xn_index(xn_index),
.busy(busy),
.edone(edone),
.done(done),
.dv(dv),
.xk_index(xk_index),
.xk_re(xk_re),
.xk_im(xk_im)
);
parameter PERIOD = 10;
parameter real DUTY_CYCLE = 0.5;
parameter OFFSET = 0;
initial // Clock process for clk
begin
clk = 1'b0;
#OFFSET;
forever begin
clk = 1'b0;
#(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1;
#(PERIOD*DUTY_CYCLE);
end
end
initial begin
// Initialize Inputs
start = 0;
fwd_inv = 0;
fwd_inv_we = 0;
scale_sch = 0;
scale_sch_we = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
start = 1;
end
initial begin
xn_re = 0;
#100;
forever begin
xn_re = 0;
#500 xn_re = 16;
#500;
end
end
initial begin // 位相を45度遅らせる
xn_im = 0;
#125;
forever begin
xn_im = 0;
#500 xn_im = 16;
#500;
end
end
endmodule
initial begin // 位相を45度遅らせる
xn_im = 0;
// #125;
#130;
forever begin
xn_im = 0;
#500 xn_im = 16;
#500;
end
end
module fp_fft_core_top(
clk,
start,
xn_re,
xn_im,
fwd_inv,
fwd_inv_we,
scale_sch,
scale_sch_we,
rfd,
xn_index,
busy,
edone,
done,
dv,
xk_index,
xk_re,
xk_im);
input wire clk;
input wire start;
input wire [15 : 0] xn_re;
input wire [15 : 0] xn_im;
input wire fwd_inv;
input wire fwd_inv_we;
input wire [13 : 0] scale_sch;
input wire scale_sch_we;
output wire rfd;
output wire [13 : 0] xn_index;
output wire busy;
output wire edone;
output wire done;
output wire dv;
output wire [13 : 0] xk_index;
output wire [15 : 0] xk_re;
output wire [15 : 0] xk_im;
fft_core2 fft_core2_inst (
.clk(clk), // input clk
.start(start), // input start
.xn_re(xn_re), // input [15 : 0] xn_re
.xn_im(xn_im), // input [15 : 0] xn_im
.fwd_inv(fwd_inv), // input fwd_inv
.fwd_inv_we(fwd_inv_we), // input fwd_inv_we
.scale_sch(scale_sch), // input [9 : 0] scale_sch
.scale_sch_we(scale_sch_we), // input scale_sch_we
.rfd(rfd), // ouput rfd
.xn_index(xn_index), // ouput [13 : 0] xn_index
.busy(busy), // ouput busy
.edone(edone), // ouput edone
.done(done), // ouput done
.dv(dv), // ouput dv
.xk_index(xk_index), // ouput [13 : 0] xk_index
.xk_re(xk_re), // ouput [15 : 0] xk_re
.xk_im(xk_im) // ouput [15 : 0] xk_im
);
endmodule
Release 13.2 Map O.61xd (nt)
Xilinx Mapping Report File for Design 'fp_fft_core_top'
Design Information
------------------
Command Line : map -intstyle ise -p xc6slx45t-fgg484-3 -w -logic_opt off -ol
high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off
-pr off -lc off -power off -o fp_fft_core_top_map.ncd fp_fft_core_top.ngd
fp_fft_core_top.pcf
Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : THU 14 JUL 18:58:14 2011
Interim Summary
---------------
Slice Logic Utilization:
Number of Slice Registers: 4,929 out of 54,576 9%
Number used as Flip Flops: 4,929
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 3,211 out of 27,288 11%
Number used as logic: 2,408 out of 27,288 8%
Number using O6 output only: 1,026
Number using O5 output only: 20
Number using O5 and O6: 1,362
Number used as ROM: 0
Number used as Memory: 795 out of 6,408 12%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 32
Number using O6 output only: 32
Number using O5 output only: 0
Number using O5 and O6: 0
Number used as Shift Register: 763
Number using O6 output only: 153
Number using O5 output only: 0
Number using O5 and O6: 610
Number used exclusively as route-thrus: 8
Number with same-slice register load: 0
Number with same-slice carry load: 8
Number with other load: 0
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 4,258
Number with an unused Flip Flop: 296 out of 4,258 6%
Number with an unused LUT: 1,047 out of 4,258 24%
Number of fully used LUT-FF pairs: 2,915 out of 4,258 68%
Number of unique control sets: 28
Number of slice register sites lost
to control set restrictions: 42 out of 54,576 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 95 out of 296 32%
Specific Feature Utilization:
Number of RAMB16BWERs: 62 out of 116 53%
Number of RAMB8BWERs: 9 out of 232 3%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 1 out of 16 6%
Number used as BUFGs: 1
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 8 0%
Number of ILOGIC2/ISERDES2s: 0 out of 376 0%
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 376 0%
Number of OLOGIC2/OSERDES2s: 0 out of 376 0%
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 256 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 24 out of 58 41%
Number of GTPA1_DUALs: 0 out of 2 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCIE_A1s: 0 out of 1 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 4 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
日 | 月 | 火 | 水 | 木 | 金 | 土 |
---|---|---|---|---|---|---|
- | - | - | - | 1 | 2 | 3 |
4 | 5 | 6 | 7 | 8 | 9 | 10 |
11 | 12 | 13 | 14 | 15 | 16 | 17 |
18 | 19 | 20 | 21 | 22 | 23 | 24 |
25 | 26 | 27 | 28 | 29 | 30 | - |