0x200 番地 ― Clock Configuration Register 0
Bit[25:16] = CLKFBOUT_FRAC Multiply = 0
Bit[15:8] = CLKFBOUT_MULT = 8
Bit[7:0] = DIVCLK_DIVIDE = 1
0x208 番地 - Clock Configuration Register 2
Bit[7:0] = CLKOUT0_DIVIDE = 0x49 (10進で 73)
Integer part of clkout0 divide value
For example, for 2.250, this value is 2 = 0x2
Bit[17:8] = CLKOUT0_FRAC Divide = 0
Fractional part of clkout0 divide value
For example, for 2.250, this value is 250 = 0xFA
XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr, 0x200, 0x0801);
XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr, 0x208, 0x50);
XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr, 0x200, 0x0801);
XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr, 0x208, 0x20);
XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr, 0x200, 0x0801);
XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr, 0x208, 0x28);
// Dynamic_Clocking.c
// 2023/05/18 by marsee
// Referred to "MicroZed Chronicles: Dynamic Clocking"
// https://www.adiuvoengineering.com/post/microzed-chronicles-dynamic-clocking
// 2023/05/27 : Modified by marsee
#include <stdio.h>
#include "xclk_wiz.h"
#include "xgpio.h"
#include "xparameters.h"
XClk_Wiz ClkWiz_Dynamic;
XClk_Wiz_Config *CfgPtr_Dynamic;
XGpio gpio_0, gpio_1;
#define XCLK_WIZARD_DEVICE_ID XPAR_CLK_WIZ_0_DEVICE_ID
#define XCLK_US_WIZ_RECONFIG_OFFSET 0x0000025C
#define CLK_LOCK 1
int main(){
u32 count, locked;
int Status;
CfgPtr_Dynamic = XClk_Wiz_LookupConfig(XCLK_WIZARD_DEVICE_ID);
XClk_Wiz_CfgInitialize(&ClkWiz_Dynamic, CfgPtr_Dynamic, CfgPtr_Dynamic->BaseAddr);
XGpio_Initialize(&gpio_0, XPAR_AXI_GPIO_0_DEVICE_ID);
XGpio_Initialize(&gpio_1, XPAR_AXI_GPIO_1_DEVICE_ID);
printf("freq = 40 MHz\n");
XGpio_DiscreteWrite(&gpio_1, 1, 1); // counter SCLR = 1, CE = 0
usleep(1000);
XGpio_DiscreteWrite(&gpio_1, 1, 2); // counter SCLR = 0, CE = 1
sleep(1);
XGpio_DiscreteWrite(&gpio_1, 1, 0); // counter SCLR = 0, CE = 0
count = XGpio_DiscreteRead(&gpio_0, 1);
locked = XGpio_DiscreteRead(&gpio_0, 2);
printf("count = %d, locked = %d\n\n", count, locked);
XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr, XCLK_WIZ_REG25_OFFSET, 0);
//XClk_Wiz_SetRate(&ClkWiz_Dynamic, 10);
XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr, 0x200, 0x0801);
XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr, 0x208, 0x50);
XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr,
XCLK_US_WIZ_RECONFIG_OFFSET,
(XCLK_WIZ_RECONFIG_LOAD | XCLK_WIZ_RECONFIG_SADDR));
Status = XClk_Wiz_WaitForLock(&ClkWiz_Dynamic);
printf("freq = 10 MHz, XClk_Wiz_SetRate\n");
XGpio_DiscreteWrite(&gpio_1, 1, 1); // counter SCLR = 1, CE = 0
usleep(1000);
XGpio_DiscreteWrite(&gpio_1, 1, 2); // counter SCLR = 0, CE = 1
sleep(1);
XGpio_DiscreteWrite(&gpio_1, 1, 0); // counter SCLR = 0, CE = 0
count = XGpio_DiscreteRead(&gpio_0, 1);
locked = XGpio_DiscreteRead(&gpio_0, 2);
printf("count = %d, locked = %d\n\n", count, locked);
XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr, XCLK_WIZ_REG25_OFFSET, 0);
//XClk_Wiz_SetRate(&ClkWiz_Dynamic, 25);
XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr, 0x200, 0x0801);
XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr, 0x208, 0x20);
XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr,
XCLK_US_WIZ_RECONFIG_OFFSET,
(XCLK_WIZ_RECONFIG_LOAD | XCLK_WIZ_RECONFIG_SADDR));
Status = XClk_Wiz_WaitForLock(&ClkWiz_Dynamic);
printf("freq = 25 MHz\n");
XGpio_DiscreteWrite(&gpio_1, 1, 1); // counter SCLR = 1, CE = 0
usleep(1000);
XGpio_DiscreteWrite(&gpio_1, 1, 2); // counter SCLR = 0, CE = 1
sleep(1);
XGpio_DiscreteWrite(&gpio_1, 1, 0); // counter SCLR = 0, CE = 0
count = XGpio_DiscreteRead(&gpio_0, 1);
locked = XGpio_DiscreteRead(&gpio_0, 2);
printf("count = %d, locked = %d\n\n", count, locked);
XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr, XCLK_WIZ_REG25_OFFSET, 0);
//XClk_Wiz_SetRateHz(&ClkWiz_Dynamic, 20000000);
XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr, 0x200, 0x0801);
XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr, 0x208, 0x28);
XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr,
XCLK_US_WIZ_RECONFIG_OFFSET,
(XCLK_WIZ_RECONFIG_LOAD | XCLK_WIZ_RECONFIG_SADDR));
Status = XClk_Wiz_WaitForLock(&ClkWiz_Dynamic);
printf("freq = 20 MHz, XClk_Wiz_SetRateHz(&ClkWiz_Dynamic, 20000000);\n");
XGpio_DiscreteWrite(&gpio_1, 1, 1); // counter SCLR = 1, CE = 0
usleep(1000);
XGpio_DiscreteWrite(&gpio_1, 1, 2); // counter SCLR = 0, CE = 1
sleep(1);
XGpio_DiscreteWrite(&gpio_1, 1, 0); // counter SCLR = 0, CE = 0
count = XGpio_DiscreteRead(&gpio_0, 1);
locked = XGpio_DiscreteRead(&gpio_0, 2);
printf("count = %d, locked = %d\n\n", count, locked);
return(0);
}
// Dynamic_Clocking.c
// 2023/05/18 by marsee
// Referred to "MicroZed Chronicles: Dynamic Clocking"
// https://www.adiuvoengineering.com/post/microzed-chronicles-dynamic-clocking
#include <stdio.h>
#include "xclk_wiz.h"
#include "xgpio.h"
#include "xparameters.h"
XClk_Wiz ClkWiz_Dynamic;
XClk_Wiz_Config *CfgPtr_Dynamic;
XGpio gpio_0, gpio_1;
#define XCLK_WIZARD_DEVICE_ID XPAR_CLK_WIZ_0_DEVICE_ID
#define XCLK_US_WIZ_RECONFIG_OFFSET 0x0000025C
#define CLK_LOCK 1
int main(){
u32 count, locked;
int Status;
CfgPtr_Dynamic = XClk_Wiz_LookupConfig(XCLK_WIZARD_DEVICE_ID);
XClk_Wiz_CfgInitialize(&ClkWiz_Dynamic, CfgPtr_Dynamic, CfgPtr_Dynamic->BaseAddr);
XGpio_Initialize(&gpio_0, XPAR_AXI_GPIO_0_DEVICE_ID);
XGpio_Initialize(&gpio_1, XPAR_AXI_GPIO_1_DEVICE_ID);
printf("freq = 40 MHz\n");
XGpio_DiscreteWrite(&gpio_1, 1, 1); // counter SCLR = 1, CE = 0
usleep(1000);
XGpio_DiscreteWrite(&gpio_1, 1, 2); // counter SCLR = 0, CE = 1
sleep(1);
XGpio_DiscreteWrite(&gpio_1, 1, 0); // counter SCLR = 0, CE = 0
count = XGpio_DiscreteRead(&gpio_0, 1);
locked = XGpio_DiscreteRead(&gpio_0, 2);
printf("count = %d, locked = %d\n\n", count, locked);
XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr, XCLK_WIZ_REG25_OFFSET, 0);
XClk_Wiz_SetRate(&ClkWiz_Dynamic, 10);
XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr,
XCLK_US_WIZ_RECONFIG_OFFSET,
(XCLK_WIZ_RECONFIG_LOAD | XCLK_WIZ_RECONFIG_SADDR));
Status = XClk_Wiz_WaitForLock(&ClkWiz_Dynamic);
printf("freq = 10 MHz, XClk_Wiz_SetRate\n");
XGpio_DiscreteWrite(&gpio_1, 1, 1); // counter SCLR = 1, CE = 0
usleep(1000);
XGpio_DiscreteWrite(&gpio_1, 1, 2); // counter SCLR = 0, CE = 1
sleep(1);
XGpio_DiscreteWrite(&gpio_1, 1, 0); // counter SCLR = 0, CE = 0
count = XGpio_DiscreteRead(&gpio_0, 1);
locked = XGpio_DiscreteRead(&gpio_0, 2);
printf("count = %d, locked = %d\n\n", count, locked);
XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr, XCLK_WIZ_REG25_OFFSET, 0);
XClk_Wiz_SetRate(&ClkWiz_Dynamic, 25);
XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr,
XCLK_US_WIZ_RECONFIG_OFFSET,
(XCLK_WIZ_RECONFIG_LOAD | XCLK_WIZ_RECONFIG_SADDR));
Status = XClk_Wiz_WaitForLock(&ClkWiz_Dynamic);
printf("freq = 25 MHz\n");
XGpio_DiscreteWrite(&gpio_1, 1, 1); // counter SCLR = 1, CE = 0
usleep(1000);
XGpio_DiscreteWrite(&gpio_1, 1, 2); // counter SCLR = 0, CE = 1
sleep(1);
XGpio_DiscreteWrite(&gpio_1, 1, 0); // counter SCLR = 0, CE = 0
count = XGpio_DiscreteRead(&gpio_0, 1);
locked = XGpio_DiscreteRead(&gpio_0, 2);
printf("count = %d, locked = %d\n\n", count, locked);
XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr, XCLK_WIZ_REG25_OFFSET, 0);
XClk_Wiz_SetRateHz(&ClkWiz_Dynamic, 20000000);
XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr,
XCLK_US_WIZ_RECONFIG_OFFSET,
(XCLK_WIZ_RECONFIG_LOAD | XCLK_WIZ_RECONFIG_SADDR));
Status = XClk_Wiz_WaitForLock(&ClkWiz_Dynamic);
printf("freq = 20 MHz, XClk_Wiz_SetRateHz(&ClkWiz_Dynamic, 20000000);\n");
XGpio_DiscreteWrite(&gpio_1, 1, 1); // counter SCLR = 1, CE = 0
usleep(1000);
XGpio_DiscreteWrite(&gpio_1, 1, 2); // counter SCLR = 0, CE = 1
sleep(1);
XGpio_DiscreteWrite(&gpio_1, 1, 0); // counter SCLR = 0, CE = 0
count = XGpio_DiscreteRead(&gpio_0, 1);
locked = XGpio_DiscreteRead(&gpio_0, 2);
printf("count = %d, locked = %d\n\n", count, locked);
return(0);
}
// timer_test.c
// 2023/02/08 by marsee
// Reference URL:https://github.com/ikwzm/ZYBO_UIO_IRQ_SAMPLE/blob/master/c-sample/sample1.c
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <fcntl.h>
#include <string.h>
#include <time.h>
#include <sys/time.h>
#include <poll.h>
#include <sys/types.h>
#include <sys/mman.h>
#define ENABLE_ALL_TIMERS (0x1<<10)
#define ENABLE_PULSE_WIDTH_MODULATION (0x1<<9)
#define TIMER_INTERRUPT (0x1<<8)
#define ENABLE_TIMER (0x1<<7)
#define ENABLE_INTERRUPT (0x1<<6)
#define LOAD_TIMER (0x1<<5)
#define AUTO_RELOAD_HOLD_TIMER (0x1<<4)
#define ENABLE_EXT_CAPTURE_TRIG (0x1<<3)
#define ENABLE_EXT_GENERATE_SIG (0x1<<2)
#define DOWN_UP_COUNT_TIMER (0x1<<1)
#define TIMER_MODE_CAP_GENE (0x1)
int uio_irq_on(int uio_fd)
{
unsigned int irq_on = 1;
write(uio_fd, &irq_on, sizeof(irq_on));
}
int uio_wait_irq(int uio_fd)
{
unsigned int count = 0;
return read(uio_fd, &count, sizeof(count));
}
void main()
{
int uio0_fd, uio1_fd;
uint32_t *axi_gpio, *axi_timer;
static uint32_t led_stat = 0;
if((uio0_fd = open("/dev/uio0", O_RDWR)) == -1) {
printf("Can not open /dev/uio0\n");
exit(1);
}
axi_gpio = (uint32_t*)mmap(NULL, 0x10000, PROT_READ|PROT_WRITE, MAP_SHARED, uio0_fd, 0);
if((uio1_fd = open("/dev/uio1", O_RDWR)) == -1) {
printf("Can not open /dev/uio1\n");
exit(1);
}
axi_timer = (uint32_t*)mmap(NULL, 0x10000, PROT_READ|PROT_WRITE, MAP_SHARED, uio1_fd, 0);
// axi_timer_0 -> Timer0
axi_timer[1] = 0x02FAF080; // TLR0, Decimal = 50,000,000, 100 MHz = 0.5sec
axi_timer[0] = LOAD_TIMER; // TCR0, ENALL and LOAD0 = 1
axi_timer[0] = TIMER_INTERRUPT | ENABLE_TIMER | ENABLE_INTERRUPT | AUTO_RELOAD_HOLD_TIMER | DOWN_UP_COUNT_TIMER; // timer interrupt clear
for(int i=0; i<100; i++){
if(uio_irq_on(uio1_fd) == -1){
fprintf(stderr, "uio_irq_on error\n");
break;
}
if(uio_wait_irq(uio1_fd) == -1){
fprintf(stderr, "uio_wait_irq error\n");
break;
}
axi_timer[0] = TIMER_INTERRUPT | ENABLE_TIMER | ENABLE_INTERRUPT | AUTO_RELOAD_HOLD_TIMER | DOWN_UP_COUNT_TIMER; // timer interrupt clear
led_stat ^= 0xf;
axi_gpio[0] = led_stat;
}
close(uio0_fd);
close(uio1_fd);
}
ダイレク ト レジスタ モード (シンプル DMA)
シンプル DMA モード (スキャ ッター/ギャザー エンジン無効) は MM2S および S2MM チャネル上でシンプルな DMA 転送を実行するためのコ ン フ ィ ギ ュ レーシ ョ ンで、 必要な FPGA リ ソース量を抑え る こ と ができ ます。 DMACR、 SA または DA、 LENGTH レ ジ ス タ に ア ク セ ス す る と 転送が開始 し ま す。 転送が完了す る と 、 そ のチ ャ ネルの DMASR.IOC_Irq がアサー ト され、 割 り 込みを有効に し ている場合は割 り 込み出力が生成されます。
MM2S チャネルの DMA 動作は、 次のシーケンスで設定および開始し ます。
1. RS ビッ トを 1 (MM2S_DMACR.RS = 1) にセッ ト して MM2S チャネルの動作を開始し ます。 MM2S チャネルが動作中は、 Halted ビッ ト (DMASR.Halted) がデ ィ アサー ト し ます。
2. 必要に応じ て、 MM2S_DMACR.IOC_IrqEn と MM2S_DMACR.Err_IrqEn に 1 を書き込み、 割 り 込みを有効にします。 AXI DMA をシンプル DMA モー ド に設定し てい る場合、 遅延割 り 込み、 遅延カ ウ ン ト 、 しきい値カ ウ ン トは使用し ません。
3. MM2S_SA レジス タに有効な ソース ア ド レ ス を書き込みます。 データ再ア ラ イ メ ン ト を有効に し ていない場合、有効なア ド レ ス を正し く ア ラ イ ン し ていない と未定義の結果 と な り ます。 ア ラ イ ン し てい るかど う かは、 ス トリーム データ幅で判定します。 AXI_DMA をマイ クロ DMA モー ド に設定し た場合、 正しいア ド レ ス を指定するよ う にユーザーが注意する必要があり ます。 マ イ ク ロ DMA モー ドでは、 4K 境界チェ ッ クは行われません。
たとえばメモ リ マ ッ プのデータ幅が 32 の場合、 データがワー ド オフセッ ト (32 ビッ ト オフセッ ト )、 すなわち 0x0、 0x4、 0x8、 0xC、 … に揃っていれば正し く ア ラ イ ン し ています。 DRE が有効でス ト リ ー ミ ング データ幅が128 よ り 小 さい場合、 ソース ア ド レ スは任意のバイ ト オフセ ッ ト とする こ と ができ ます。
4. 転送するバイ ト 数を MM2S_LENGTH レジ ス タに書き込みます。 値 0 を書き込んで も無視されます。
MM2S_LENGTH に 0 以外の値を指定する と、 その数のバイ ト が MM2S AXI4 イ ン ターフ ェ イ スで読み出され、MM2S AXI4-Stream イ ン ターフ ェ イ スか ら送信 されます。 MM2S_LENGTH レジ ス タは最後に書き込む必要があります。 それ以外の MM2S レ ジ ス タは任意の順番で書き込む こ と がで き ます。 マ イ ク ロ DMA モー ド の場合、MM2S_LENGTH に [ Burst_length * (メモリ マップ データ幅)/8] を超え る値は指定でき ません。
S2MM チャネルの DMA 動作は、 次のシーケン スで設定および開始し ます。
1. RS ビッ トを 1 (S2MM_DMACR.RS = 1) にセッ ト して S2MM チャネルの動作を開始し ます。 S2MM チャネルが動作中は、 Halted ビッ ト (DMASR.Halted) がデ ィ アサー ト し ます。
2. 必要に応じ て、 S2MM_DMACR.IOC_IrqEn と S2MM_DMACR.Err_IrqEn に 1 を書き込み、 割 り 込みを有効に します。 AXI DMA をシンプル DMA モー ド に設定し てい る場合、 遅延割 り 込み、 遅延カ ウ ン ト 、 し きい値カ ウ ン トは使用し ません。
3. S2MM_DA レジス タに有効なデステ ィ ネーシ ョ ン ア ド レ ス を書き込みます。データ再ア ラ イ メ ン ト を有効に していない場合、 有効なア ド レ ス を正し く ア ラ イ ン し ていない と未定義の結果 と な り ます。 ア ラ イ ン し ているかどうかは、 ス ト リ ーム データ幅で判定し ます。
たとえばメモ リ マ ッ プのデータ幅が 32 の場合、 データがワー ド オフセッ ト (32 ビッ ト オフセッ ト )、 すなわち 0x0、 0x4、 0x8、 0xC、 … に揃っていれば正し く ア ラ イ ン し ています。 DRE が有効でス ト リ ー ミ ング データ幅が 128 よ り 小 さい場合、 デステ ィ ネーシ ョ ン ア ド レ スは任意のバイ ト オフセ ッ ト とする こ と ができ ます。
4. 受信バ ッ フ ァーの長 さ を S2MM_LENGTH レジ ス タに書き込みます (単位 : バイ ト )。 値 0 を書き込んで も無視されます。 0 以外の値を指定する と、 S2MM AXI4-Stream イ ン ターフ ェ イ スで受信し たその数のバイ ト が S2MM AXI4 イ ン ターフ ェ イ スに書き込まれます。 S2MM_LENGTH には、 最大受信パケ ッ ト 以上の値を書き込む必要があ り ます。 受信バ ッ フ ァーの長 さに指定し た値を超え るバイ ト 数を受信する と 、 未定義の結果 と な り ます。 AXI DMA をマイ クロ DMA モー ド に設定し た場合、 この値は S2MM AXI4-Stream イ ン ターフ ェ イ スでの受信バイ ト数 と正確に一致し てい る必要があ り ます。 S2MM_LENGTH レジ ス タは最後に書き込む必要があ り ます。 それ以外の S2MM レジ ス タは任意の順番で書き込むこ と ができ ます。
1. 0x00 番地に 1 を書く。MM2S DMA 制御レジ ス タ(MM2S_DMACR)のビット 0 (Run/Stop ビット)を 1 (Run)に設定する
2. 0x18 番地に画像データの物理アドレスを書く。MM2S ソース アドレス(MM2S_SA)に画像データの物理アドレスを書く
3. 0x28 番地に画像データの長さを書く。MM2S 転送長 さ (バイ ト )(MM2S_LENGTH)に画像データの長さを書く。これで MM2S の DMA がスタートする。
4. MM2S の DMA 終了は、0x04 番地の MM2S DMA ステータ ス レジスタ(MM2S_DMASR)のビット 1 の Idle ビットが 1 に遷移するのを確認する
1. 0x30 番地に 1 を書く。S2MM DMA 制御レジ ス タ(S2MM_DMACR)のビット 0 (Run/Stop ビット)を 1 (Run)に設定する
2. 0x48 番地に画像データの物理アドレスを書く。S2MM ソース アドレス(S2MM_SA)に画像データの物理アドレスを書く
3. 0x58 番地に画像データの長さを書く。S2MM 転送長 さ (バイ ト )(S2MM_LENGTH)に画像データの長さを書く。これで MM2S の DMA がスタートする。
4. S2MM の DMA 終了は、0x34 番地の S2MM DMA ステータ ス レジスタ(S2MM_DMASR)のビット 1 の Idle ビットが 1 に遷移するのを確認する
にアクセスした。http://192.168.3.17:9090/tree/my_project/cam_disp2
# VTC enable
vtc.write(0x0, 0x04) # Generation Enable
を追加してある。vtc = cam_disp.v_tc_0
#!/usr/bin/env python
# coding: utf-8
# cam_disp2<br>
# 2022/09/06 by marsee
# In[1]:
from PIL import Image
import numpy as np
import matplotlib.pyplot as plt
get_ipython().run_line_magic('matplotlib', 'inline')
from pynq import allocate, Overlay
import time
import cv2
# In[2]:
# Download bitstream
cam_disp = Overlay("./cam_disp.bit")
# In[3]:
# Generate an instance for each IP
vflip_dmaw = cam_disp.vflip_dma_write_0
paracam_inf = cam_disp.paracam_inf_axis_0
vtc = cam_disp.v_tc_0
cam_iic = cam_disp.axi_iic_0
sobel0 = cam_disp.sobel_axis_RGB24_0
sobel1 = cam_disp.sobel_axis_RGB24_1
dma2axis30 = cam_disp.DMA2axis_3buf_0
dma2axis31 = cam_disp.DMA2axis_3buf_1
axis2dma = cam_disp.axis2DMA4dwc_0
# In[4]:
def cam_i2c_init(cam_iic):
cam_iic.write(0x100, 0x2) # reset tx fifo ,address is 0x100, i2c_control_reg
cam_iic.write(0x100, 0x1) # enable i2c
# In[5]:
def cam_i2x_write_sync():
time.sleep(0.001) # 1ms wait
# In[6]:
def cam_i2c_write(cam_iic, device_addr, write_addr, write_data):
cam_iic.write(0x108, 0x100 | (device_addr & 0xfe)) # Slave IIC Write Address, address is 0x108, i2c_tx_fifo
cam_iic.write(0x108, (write_addr >> 8) & 0xff) # address upper byte
cam_iic.write(0x108, write_addr & 0xff) # address lower byte
cam_iic.write(0x108, 0x200 | (write_data & 0xff)) # data
cam_i2x_write_sync()
# In[7]:
def cam_reg_set(cam_iic, device_addr):
cam_i2c_write(cam_iic, device_addr, 0x3103, 0x93)
cam_i2c_write(cam_iic, device_addr, 0x3008, 0x82)
cam_i2c_write(cam_iic, device_addr, 0x3017, 0x7f)
cam_i2c_write(cam_iic, device_addr, 0x3018, 0xfc)
cam_i2c_write(cam_iic, device_addr, 0x3810, 0xc2)
cam_i2c_write(cam_iic, device_addr, 0x3615, 0xf0)
cam_i2c_write(cam_iic, device_addr, 0x3000, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x3001, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x3002, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x3003, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x3000, 0xf8)
cam_i2c_write(cam_iic, device_addr, 0x3001, 0x48)
cam_i2c_write(cam_iic, device_addr, 0x3002, 0x5c)
cam_i2c_write(cam_iic, device_addr, 0x3003, 0x02)
cam_i2c_write(cam_iic, device_addr, 0x3004, 0x07)
cam_i2c_write(cam_iic, device_addr, 0x3005, 0xb7)
cam_i2c_write(cam_iic, device_addr, 0x3006, 0x43)
cam_i2c_write(cam_iic, device_addr, 0x3007, 0x37)
cam_i2c_write(cam_iic, device_addr, 0x3011, 0x08) # 0x08 - 15fps, 0x10 - 30fps
cam_i2c_write(cam_iic, device_addr, 0x3010, 0x10)
cam_i2c_write(cam_iic, device_addr, 0x460c, 0x22)
cam_i2c_write(cam_iic, device_addr, 0x3815, 0x04)
cam_i2c_write(cam_iic, device_addr, 0x370d, 0x06)
cam_i2c_write(cam_iic, device_addr, 0x370c, 0xa0)
cam_i2c_write(cam_iic, device_addr, 0x3602, 0xfc)
cam_i2c_write(cam_iic, device_addr, 0x3612, 0xff)
cam_i2c_write(cam_iic, device_addr, 0x3634, 0xc0)
cam_i2c_write(cam_iic, device_addr, 0x3613, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x3605, 0x7c)
cam_i2c_write(cam_iic, device_addr, 0x3621, 0x09)
cam_i2c_write(cam_iic, device_addr, 0x3622, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x3604, 0x40)
cam_i2c_write(cam_iic, device_addr, 0x3603, 0xa7)
cam_i2c_write(cam_iic, device_addr, 0x3603, 0x27)
cam_i2c_write(cam_iic, device_addr, 0x4000, 0x21)
cam_i2c_write(cam_iic, device_addr, 0x401d, 0x02)
cam_i2c_write(cam_iic, device_addr, 0x3600, 0x54)
cam_i2c_write(cam_iic, device_addr, 0x3605, 0x04)
cam_i2c_write(cam_iic, device_addr, 0x3606, 0x3f)
cam_i2c_write(cam_iic, device_addr, 0x3c01, 0x80)
cam_i2c_write(cam_iic, device_addr, 0x5000, 0x4f)
cam_i2c_write(cam_iic, device_addr, 0x5020, 0x04)
cam_i2c_write(cam_iic, device_addr, 0x5181, 0x79)
cam_i2c_write(cam_iic, device_addr, 0x5182, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5185, 0x22)
cam_i2c_write(cam_iic, device_addr, 0x5197, 0x01)
cam_i2c_write(cam_iic, device_addr, 0x5001, 0xff)
cam_i2c_write(cam_iic, device_addr, 0x5500, 0x0a)
cam_i2c_write(cam_iic, device_addr, 0x5504, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5505, 0x7f)
cam_i2c_write(cam_iic, device_addr, 0x5080, 0x08)
cam_i2c_write(cam_iic, device_addr, 0x300e, 0x18)
cam_i2c_write(cam_iic, device_addr, 0x4610, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x471d, 0x05)
cam_i2c_write(cam_iic, device_addr, 0x4708, 0x06)
cam_i2c_write(cam_iic, device_addr, 0x3710, 0x10)
cam_i2c_write(cam_iic, device_addr, 0x3632, 0x41)
cam_i2c_write(cam_iic, device_addr, 0x3702, 0x40)
cam_i2c_write(cam_iic, device_addr, 0x3620, 0x37)
cam_i2c_write(cam_iic, device_addr, 0x3631, 0x01)
cam_i2c_write(cam_iic, device_addr, 0x3808, 0x02)
cam_i2c_write(cam_iic, device_addr, 0x3809, 0x80)
cam_i2c_write(cam_iic, device_addr, 0x380a, 0x01)
cam_i2c_write(cam_iic, device_addr, 0x380b, 0xe0)
cam_i2c_write(cam_iic, device_addr, 0x380e, 0x07)
cam_i2c_write(cam_iic, device_addr, 0x380f, 0xd0)
cam_i2c_write(cam_iic, device_addr, 0x501f, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5000, 0x4f)
cam_i2c_write(cam_iic, device_addr, 0x4300, 0x61) # RGB565
cam_i2c_write(cam_iic, device_addr, 0x3503, 0x07)
cam_i2c_write(cam_iic, device_addr, 0x3501, 0x73)
cam_i2c_write(cam_iic, device_addr, 0x3502, 0x80)
cam_i2c_write(cam_iic, device_addr, 0x350b, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x3503, 0x07)
cam_i2c_write(cam_iic, device_addr, 0x3824, 0x11)
cam_i2c_write(cam_iic, device_addr, 0x3501, 0x1e)
cam_i2c_write(cam_iic, device_addr, 0x3502, 0x80)
cam_i2c_write(cam_iic, device_addr, 0x350b, 0x7f)
cam_i2c_write(cam_iic, device_addr, 0x380c, 0x0c)
cam_i2c_write(cam_iic, device_addr, 0x380d, 0x80)
cam_i2c_write(cam_iic, device_addr, 0x380e, 0x03)
cam_i2c_write(cam_iic, device_addr, 0x380f, 0xe8)
cam_i2c_write(cam_iic, device_addr, 0x3a0d, 0x04)
cam_i2c_write(cam_iic, device_addr, 0x3a0e, 0x03)
cam_i2c_write(cam_iic, device_addr, 0x3818, 0xc1)
cam_i2c_write(cam_iic, device_addr, 0x3705, 0xdb)
cam_i2c_write(cam_iic, device_addr, 0x370a, 0x81)
cam_i2c_write(cam_iic, device_addr, 0x3801, 0x80)
cam_i2c_write(cam_iic, device_addr, 0x3621, 0xc7)
cam_i2c_write(cam_iic, device_addr, 0x3801, 0x50)
cam_i2c_write(cam_iic, device_addr, 0x3803, 0x08)
cam_i2c_write(cam_iic, device_addr, 0x3827, 0x08)
cam_i2c_write(cam_iic, device_addr, 0x3810, 0xc0)
cam_i2c_write(cam_iic, device_addr, 0x3804, 0x05)
cam_i2c_write(cam_iic, device_addr, 0x3805, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5682, 0x05)
cam_i2c_write(cam_iic, device_addr, 0x5683, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x3806, 0x03)
cam_i2c_write(cam_iic, device_addr, 0x3807, 0xc0)
cam_i2c_write(cam_iic, device_addr, 0x5686, 0x03)
cam_i2c_write(cam_iic, device_addr, 0x5687, 0xc0)
cam_i2c_write(cam_iic, device_addr, 0x3a00, 0x78)
cam_i2c_write(cam_iic, device_addr, 0x3a1a, 0x04)
cam_i2c_write(cam_iic, device_addr, 0x3a13, 0x30)
cam_i2c_write(cam_iic, device_addr, 0x3a18, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x3a19, 0x7c)
cam_i2c_write(cam_iic, device_addr, 0x3a08, 0x12)
cam_i2c_write(cam_iic, device_addr, 0x3a09, 0xc0)
cam_i2c_write(cam_iic, device_addr, 0x3a0a, 0x0f)
cam_i2c_write(cam_iic, device_addr, 0x3a0b, 0xa0)
cam_i2c_write(cam_iic, device_addr, 0x3004, 0xff)
cam_i2c_write(cam_iic, device_addr, 0x350c, 0x07)
cam_i2c_write(cam_iic, device_addr, 0x350d, 0xd0)
cam_i2c_write(cam_iic, device_addr, 0x3500, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x3501, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x3502, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x350a, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x350b, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x3503, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x528a, 0x02)
cam_i2c_write(cam_iic, device_addr, 0x528b, 0x04)
cam_i2c_write(cam_iic, device_addr, 0x528c, 0x08)
cam_i2c_write(cam_iic, device_addr, 0x528d, 0x08)
cam_i2c_write(cam_iic, device_addr, 0x528e, 0x08)
cam_i2c_write(cam_iic, device_addr, 0x528f, 0x10)
cam_i2c_write(cam_iic, device_addr, 0x5290, 0x10)
cam_i2c_write(cam_iic, device_addr, 0x5292, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5293, 0x02)
cam_i2c_write(cam_iic, device_addr, 0x5294, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5295, 0x02)
cam_i2c_write(cam_iic, device_addr, 0x5296, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5297, 0x02)
cam_i2c_write(cam_iic, device_addr, 0x5298, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5299, 0x02)
cam_i2c_write(cam_iic, device_addr, 0x529a, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x529b, 0x02)
cam_i2c_write(cam_iic, device_addr, 0x529c, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x529d, 0x02)
cam_i2c_write(cam_iic, device_addr, 0x529e, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x529f, 0x02)
cam_i2c_write(cam_iic, device_addr, 0x3a0f, 0x3c)
cam_i2c_write(cam_iic, device_addr, 0x3a10, 0x30)
cam_i2c_write(cam_iic, device_addr, 0x3a1b, 0x3c)
cam_i2c_write(cam_iic, device_addr, 0x3a1e, 0x30)
cam_i2c_write(cam_iic, device_addr, 0x3a11, 0x70)
cam_i2c_write(cam_iic, device_addr, 0x3a1f, 0x10)
cam_i2c_write(cam_iic, device_addr, 0x3030, 0x0b)
cam_i2c_write(cam_iic, device_addr, 0x3a02, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x3a03, 0x7d)
cam_i2c_write(cam_iic, device_addr, 0x3a04, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x3a14, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x3a15, 0x7d)
cam_i2c_write(cam_iic, device_addr, 0x3a16, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x3a00, 0x78)
cam_i2c_write(cam_iic, device_addr, 0x3a08, 0x09)
cam_i2c_write(cam_iic, device_addr, 0x3a09, 0x60)
cam_i2c_write(cam_iic, device_addr, 0x3a0a, 0x07)
cam_i2c_write(cam_iic, device_addr, 0x3a0b, 0xd0)
cam_i2c_write(cam_iic, device_addr, 0x3a0d, 0x08)
cam_i2c_write(cam_iic, device_addr, 0x3a0e, 0x06)
cam_i2c_write(cam_iic, device_addr, 0x5193, 0x70)
cam_i2c_write(cam_iic, device_addr, 0x3620, 0x57)
cam_i2c_write(cam_iic, device_addr, 0x3703, 0x98)
cam_i2c_write(cam_iic, device_addr, 0x3704, 0x1c)
cam_i2c_write(cam_iic, device_addr, 0x589b, 0x04)
cam_i2c_write(cam_iic, device_addr, 0x589a, 0xc5)
cam_i2c_write(cam_iic, device_addr, 0x528a, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x528b, 0x02)
cam_i2c_write(cam_iic, device_addr, 0x528c, 0x08)
cam_i2c_write(cam_iic, device_addr, 0x528d, 0x10)
cam_i2c_write(cam_iic, device_addr, 0x528e, 0x20)
cam_i2c_write(cam_iic, device_addr, 0x528f, 0x28)
cam_i2c_write(cam_iic, device_addr, 0x5290, 0x30)
cam_i2c_write(cam_iic, device_addr, 0x5292, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5293, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5294, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5295, 0x02)
cam_i2c_write(cam_iic, device_addr, 0x5296, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5297, 0x08)
cam_i2c_write(cam_iic, device_addr, 0x5298, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5299, 0x10)
cam_i2c_write(cam_iic, device_addr, 0x529a, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x529b, 0x20)
cam_i2c_write(cam_iic, device_addr, 0x529c, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x529d, 0x28)
cam_i2c_write(cam_iic, device_addr, 0x529e, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x529f, 0x30)
cam_i2c_write(cam_iic, device_addr, 0x5282, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5300, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5301, 0x20)
cam_i2c_write(cam_iic, device_addr, 0x5302, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5303, 0x7c)
cam_i2c_write(cam_iic, device_addr, 0x530c, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x530d, 0x0c)
cam_i2c_write(cam_iic, device_addr, 0x530e, 0x20)
cam_i2c_write(cam_iic, device_addr, 0x530f, 0x80)
cam_i2c_write(cam_iic, device_addr, 0x5310, 0x20)
cam_i2c_write(cam_iic, device_addr, 0x5311, 0x80)
cam_i2c_write(cam_iic, device_addr, 0x5308, 0x20)
cam_i2c_write(cam_iic, device_addr, 0x5309, 0x40)
cam_i2c_write(cam_iic, device_addr, 0x5304, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5305, 0x30)
cam_i2c_write(cam_iic, device_addr, 0x5306, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5307, 0x80)
cam_i2c_write(cam_iic, device_addr, 0x5314, 0x08)
cam_i2c_write(cam_iic, device_addr, 0x5315, 0x20)
cam_i2c_write(cam_iic, device_addr, 0x5319, 0x30)
cam_i2c_write(cam_iic, device_addr, 0x5316, 0x10)
cam_i2c_write(cam_iic, device_addr, 0x5317, 0x08)
cam_i2c_write(cam_iic, device_addr, 0x5318, 0x02)
cam_i2c_write(cam_iic, device_addr, 0x5380, 0x01)
cam_i2c_write(cam_iic, device_addr, 0x5381, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5382, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5383, 0x4e)
cam_i2c_write(cam_iic, device_addr, 0x5384, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5385, 0x0f)
cam_i2c_write(cam_iic, device_addr, 0x5386, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5387, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5388, 0x01)
cam_i2c_write(cam_iic, device_addr, 0x5389, 0x15)
cam_i2c_write(cam_iic, device_addr, 0x538a, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x538b, 0x31)
cam_i2c_write(cam_iic, device_addr, 0x538c, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x538d, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x538e, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x538f, 0x0f)
cam_i2c_write(cam_iic, device_addr, 0x5390, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5391, 0xab)
cam_i2c_write(cam_iic, device_addr, 0x5392, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5393, 0xa2)
cam_i2c_write(cam_iic, device_addr, 0x5394, 0x08)
cam_i2c_write(cam_iic, device_addr, 0x5480, 0x14)
cam_i2c_write(cam_iic, device_addr, 0x5481, 0x21)
cam_i2c_write(cam_iic, device_addr, 0x5482, 0x36)
cam_i2c_write(cam_iic, device_addr, 0x5483, 0x57)
cam_i2c_write(cam_iic, device_addr, 0x5484, 0x65)
cam_i2c_write(cam_iic, device_addr, 0x5485, 0x71)
cam_i2c_write(cam_iic, device_addr, 0x5486, 0x7d)
cam_i2c_write(cam_iic, device_addr, 0x5487, 0x87)
cam_i2c_write(cam_iic, device_addr, 0x5488, 0x91)
cam_i2c_write(cam_iic, device_addr, 0x5489, 0x9a)
cam_i2c_write(cam_iic, device_addr, 0x548a, 0xaa)
cam_i2c_write(cam_iic, device_addr, 0x548b, 0xb8)
cam_i2c_write(cam_iic, device_addr, 0x548c, 0xcd)
cam_i2c_write(cam_iic, device_addr, 0x548d, 0xdd)
cam_i2c_write(cam_iic, device_addr, 0x548e, 0xea)
cam_i2c_write(cam_iic, device_addr, 0x548f, 0x10)
cam_i2c_write(cam_iic, device_addr, 0x5490, 0x05)
cam_i2c_write(cam_iic, device_addr, 0x5491, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5492, 0x04)
cam_i2c_write(cam_iic, device_addr, 0x5493, 0x20)
cam_i2c_write(cam_iic, device_addr, 0x5494, 0x03)
cam_i2c_write(cam_iic, device_addr, 0x5495, 0x60)
cam_i2c_write(cam_iic, device_addr, 0x5496, 0x02)
cam_i2c_write(cam_iic, device_addr, 0x5497, 0xb8)
cam_i2c_write(cam_iic, device_addr, 0x5498, 0x02)
cam_i2c_write(cam_iic, device_addr, 0x5499, 0x86)
cam_i2c_write(cam_iic, device_addr, 0x549a, 0x02)
cam_i2c_write(cam_iic, device_addr, 0x549b, 0x5b)
cam_i2c_write(cam_iic, device_addr, 0x549c, 0x02)
cam_i2c_write(cam_iic, device_addr, 0x549d, 0x3b)
cam_i2c_write(cam_iic, device_addr, 0x549e, 0x02)
cam_i2c_write(cam_iic, device_addr, 0x549f, 0x1c)
cam_i2c_write(cam_iic, device_addr, 0x54a0, 0x02)
cam_i2c_write(cam_iic, device_addr, 0x54a1, 0x04)
cam_i2c_write(cam_iic, device_addr, 0x54a2, 0x01)
cam_i2c_write(cam_iic, device_addr, 0x54a3, 0xed)
cam_i2c_write(cam_iic, device_addr, 0x54a4, 0x01)
cam_i2c_write(cam_iic, device_addr, 0x54a5, 0xc5)
cam_i2c_write(cam_iic, device_addr, 0x54a6, 0x01)
cam_i2c_write(cam_iic, device_addr, 0x54a7, 0xa5)
cam_i2c_write(cam_iic, device_addr, 0x54a8, 0x01)
cam_i2c_write(cam_iic, device_addr, 0x54a9, 0x6c)
cam_i2c_write(cam_iic, device_addr, 0x54aa, 0x01)
cam_i2c_write(cam_iic, device_addr, 0x54ab, 0x41)
cam_i2c_write(cam_iic, device_addr, 0x54ac, 0x01)
cam_i2c_write(cam_iic, device_addr, 0x54ad, 0x20)
cam_i2c_write(cam_iic, device_addr, 0x54ae, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x54af, 0x16)
cam_i2c_write(cam_iic, device_addr, 0x3406, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5192, 0x04) # 0x04
cam_i2c_write(cam_iic, device_addr, 0x5191, 0xf8) # 0xf8
cam_i2c_write(cam_iic, device_addr, 0x5193, 0x70)
cam_i2c_write(cam_iic, device_addr, 0x5194, 0xf0)
cam_i2c_write(cam_iic, device_addr, 0x5195, 0xf0)
cam_i2c_write(cam_iic, device_addr, 0x518d, 0x3d)
cam_i2c_write(cam_iic, device_addr, 0x518f, 0x54)
cam_i2c_write(cam_iic, device_addr, 0x518e, 0x3d)
cam_i2c_write(cam_iic, device_addr, 0x5190, 0x54)
cam_i2c_write(cam_iic, device_addr, 0x518b, 0xc0)
cam_i2c_write(cam_iic, device_addr, 0x518c, 0xbd)
cam_i2c_write(cam_iic, device_addr, 0x5187, 0x18)
cam_i2c_write(cam_iic, device_addr, 0x5188, 0x18)
cam_i2c_write(cam_iic, device_addr, 0x5189, 0x6e)
cam_i2c_write(cam_iic, device_addr, 0x518a, 0x68)
cam_i2c_write(cam_iic, device_addr, 0x5186, 0x1c)
cam_i2c_write(cam_iic, device_addr, 0x5181, 0x50)
cam_i2c_write(cam_iic, device_addr, 0x5184, 0x25)
cam_i2c_write(cam_iic, device_addr, 0x5182, 0x11)
cam_i2c_write(cam_iic, device_addr, 0x5183, 0x14)
cam_i2c_write(cam_iic, device_addr, 0x5184, 0x25)
cam_i2c_write(cam_iic, device_addr, 0x5185, 0x24)
cam_i2c_write(cam_iic, device_addr, 0x5025, 0x82)
cam_i2c_write(cam_iic, device_addr, 0x5583, 0x40)
cam_i2c_write(cam_iic, device_addr, 0x5584, 0x40)
cam_i2c_write(cam_iic, device_addr, 0x5580, 0x02) # 0x02
cam_i2c_write(cam_iic, device_addr, 0x3633, 0x07)
cam_i2c_write(cam_iic, device_addr, 0x3702, 0x10)
cam_i2c_write(cam_iic, device_addr, 0x3703, 0xb2)
cam_i2c_write(cam_iic, device_addr, 0x3704, 0x18)
cam_i2c_write(cam_iic, device_addr, 0x370b, 0x40)
cam_i2c_write(cam_iic, device_addr, 0x370d, 0x02)
cam_i2c_write(cam_iic, device_addr, 0x3620, 0x52)
cam_i2c_write(cam_iic, device_addr, 0x3c00, 0x04)
cam_i2c_write(cam_iic, device_addr, 0x5001, 0xFF)
cam_i2c_write(cam_iic, device_addr, 0x5282, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5300, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5301, 0x20)
cam_i2c_write(cam_iic, device_addr, 0x5302, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5303, 0x7c)
cam_i2c_write(cam_iic, device_addr, 0x530c, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x530d, 0x10)
cam_i2c_write(cam_iic, device_addr, 0x530e, 0x20)
cam_i2c_write(cam_iic, device_addr, 0x530f, 0x80)
cam_i2c_write(cam_iic, device_addr, 0x5310, 0x20)
cam_i2c_write(cam_iic, device_addr, 0x5311, 0x80)
cam_i2c_write(cam_iic, device_addr, 0x5308, 0x20)
cam_i2c_write(cam_iic, device_addr, 0x5309, 0x40)
cam_i2c_write(cam_iic, device_addr, 0x5304, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5305, 0x30)
cam_i2c_write(cam_iic, device_addr, 0x5306, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5307, 0x80)
cam_i2c_write(cam_iic, device_addr, 0x5314, 0x08)
cam_i2c_write(cam_iic, device_addr, 0x5315, 0x20)
cam_i2c_write(cam_iic, device_addr, 0x5319, 0x30)
cam_i2c_write(cam_iic, device_addr, 0x5316, 0x10)
cam_i2c_write(cam_iic, device_addr, 0x5317, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5318, 0x02)
cam_i2c_write(cam_iic, device_addr, 0x5500, 0x10)
cam_i2c_write(cam_iic, device_addr, 0x5502, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5503, 0x06)
cam_i2c_write(cam_iic, device_addr, 0x5504, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5505, 0x7f)
cam_i2c_write(cam_iic, device_addr, 0x5025, 0x80)
cam_i2c_write(cam_iic, device_addr, 0x5300, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5301, 0x20)
cam_i2c_write(cam_iic, device_addr, 0x5302, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5303, 0x7c)
cam_i2c_write(cam_iic, device_addr, 0x530c, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x530d, 0x0c)
cam_i2c_write(cam_iic, device_addr, 0x530e, 0x20)
cam_i2c_write(cam_iic, device_addr, 0x530f, 0x80)
cam_i2c_write(cam_iic, device_addr, 0x5310, 0x20)
cam_i2c_write(cam_iic, device_addr, 0x5311, 0x80)
cam_i2c_write(cam_iic, device_addr, 0x5308, 0x20)
cam_i2c_write(cam_iic, device_addr, 0x5309, 0x40)
cam_i2c_write(cam_iic, device_addr, 0x5304, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5305, 0x30)
cam_i2c_write(cam_iic, device_addr, 0x5306, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5307, 0x80)
cam_i2c_write(cam_iic, device_addr, 0x5314, 0x08)
cam_i2c_write(cam_iic, device_addr, 0x5315, 0x20)
cam_i2c_write(cam_iic, device_addr, 0x5319, 0x30)
cam_i2c_write(cam_iic, device_addr, 0x5316, 0x10)
cam_i2c_write(cam_iic, device_addr, 0x5317, 0x08)
cam_i2c_write(cam_iic, device_addr, 0x5318, 0x02)
cam_i2c_write(cam_iic, device_addr, 0x5380, 0x01)
cam_i2c_write(cam_iic, device_addr, 0x5381, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5382, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5383, 0x1f)
cam_i2c_write(cam_iic, device_addr, 0x5384, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5385, 0x06)
cam_i2c_write(cam_iic, device_addr, 0x5386, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5387, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5388, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5389, 0xE1)
cam_i2c_write(cam_iic, device_addr, 0x538A, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x538B, 0x2B)
cam_i2c_write(cam_iic, device_addr, 0x538C, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x538D, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x538E, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x538F, 0x10)
cam_i2c_write(cam_iic, device_addr, 0x5390, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5391, 0xB3)
cam_i2c_write(cam_iic, device_addr, 0x5392, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5393, 0xA6)
cam_i2c_write(cam_iic, device_addr, 0x5394, 0x08)
cam_i2c_write(cam_iic, device_addr, 0x5480, 0xd)
cam_i2c_write(cam_iic, device_addr, 0x5481, 0x18)
cam_i2c_write(cam_iic, device_addr, 0x5482, 0x2a)
cam_i2c_write(cam_iic, device_addr, 0x5483, 0x49)
cam_i2c_write(cam_iic, device_addr, 0x5484, 0x56)
cam_i2c_write(cam_iic, device_addr, 0x5485, 0x62)
cam_i2c_write(cam_iic, device_addr, 0x5486, 0x6c)
cam_i2c_write(cam_iic, device_addr, 0x5487, 0x76)
cam_i2c_write(cam_iic, device_addr, 0x5488, 0x80)
cam_i2c_write(cam_iic, device_addr, 0x5489, 0x88)
cam_i2c_write(cam_iic, device_addr, 0x548a, 0x96)
cam_i2c_write(cam_iic, device_addr, 0x548b, 0xa2)
cam_i2c_write(cam_iic, device_addr, 0x548c, 0xb8)
cam_i2c_write(cam_iic, device_addr, 0x548d, 0xcc)
cam_i2c_write(cam_iic, device_addr, 0x548e, 0xe0)
cam_i2c_write(cam_iic, device_addr, 0x548f, 0x10)
cam_i2c_write(cam_iic, device_addr, 0x5490, 0x3)
cam_i2c_write(cam_iic, device_addr, 0x5491, 0x40)
cam_i2c_write(cam_iic, device_addr, 0x5492, 0x3)
cam_i2c_write(cam_iic, device_addr, 0x5493, 0x0)
cam_i2c_write(cam_iic, device_addr, 0x5494, 0x2)
cam_i2c_write(cam_iic, device_addr, 0x5495, 0xa0)
cam_i2c_write(cam_iic, device_addr, 0x5496, 0x2)
cam_i2c_write(cam_iic, device_addr, 0x5497, 0x48)
cam_i2c_write(cam_iic, device_addr, 0x5498, 0x2)
cam_i2c_write(cam_iic, device_addr, 0x5499, 0x26)
cam_i2c_write(cam_iic, device_addr, 0x549a, 0x2)
cam_i2c_write(cam_iic, device_addr, 0x549b, 0xb)
cam_i2c_write(cam_iic, device_addr, 0x549c, 0x1)
cam_i2c_write(cam_iic, device_addr, 0x549d, 0xee)
cam_i2c_write(cam_iic, device_addr, 0x549e, 0x1)
cam_i2c_write(cam_iic, device_addr, 0x549f, 0xd8)
cam_i2c_write(cam_iic, device_addr, 0x54a0, 0x1)
cam_i2c_write(cam_iic, device_addr, 0x54a1, 0xc7)
cam_i2c_write(cam_iic, device_addr, 0x54a2, 0x1)
cam_i2c_write(cam_iic, device_addr, 0x54a3, 0xb3)
cam_i2c_write(cam_iic, device_addr, 0x54a4, 0x1)
cam_i2c_write(cam_iic, device_addr, 0x54a5, 0x90)
cam_i2c_write(cam_iic, device_addr, 0x54a6, 0x1)
cam_i2c_write(cam_iic, device_addr, 0x54a7, 0x62)
cam_i2c_write(cam_iic, device_addr, 0x54a8, 0x1)
cam_i2c_write(cam_iic, device_addr, 0x54a9, 0x27)
cam_i2c_write(cam_iic, device_addr, 0x54aa, 0x01)
cam_i2c_write(cam_iic, device_addr, 0x54ab, 0x09)
cam_i2c_write(cam_iic, device_addr, 0x54ac, 0x01)
cam_i2c_write(cam_iic, device_addr, 0x54ad, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x54ae, 0x0)
cam_i2c_write(cam_iic, device_addr, 0x54af, 0x40)
cam_i2c_write(cam_iic, device_addr, 0x54b0, 0x1)
cam_i2c_write(cam_iic, device_addr, 0x54b1, 0x20)
cam_i2c_write(cam_iic, device_addr, 0x54b2, 0x1)
cam_i2c_write(cam_iic, device_addr, 0x54b3, 0x40)
cam_i2c_write(cam_iic, device_addr, 0x54b4, 0x0)
cam_i2c_write(cam_iic, device_addr, 0x54b5, 0xf0)
cam_i2c_write(cam_iic, device_addr, 0x54b6, 0x1)
cam_i2c_write(cam_iic, device_addr, 0x54b7, 0xdf)
cam_i2c_write(cam_iic, device_addr, 0x5583, 0x5d)
cam_i2c_write(cam_iic, device_addr, 0x5584, 0x5d)
cam_i2c_write(cam_iic, device_addr, 0x5580, 0x06)
cam_i2c_write(cam_iic, device_addr, 0x5587, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5588, 0x20)
cam_i2c_write(cam_iic, device_addr, 0x558a, 0x09)
cam_i2c_write(cam_iic, device_addr, 0x5589, 0x10)
cam_i2c_write(cam_iic, device_addr, 0x5000, 0xcf)
cam_i2c_write(cam_iic, device_addr, 0x5800, 0x48)
cam_i2c_write(cam_iic, device_addr, 0x5801, 0x31)
cam_i2c_write(cam_iic, device_addr, 0x5802, 0x21)
cam_i2c_write(cam_iic, device_addr, 0x5803, 0x1b)
cam_i2c_write(cam_iic, device_addr, 0x5804, 0x1a)
cam_i2c_write(cam_iic, device_addr, 0x5805, 0x1e)
cam_i2c_write(cam_iic, device_addr, 0x5806, 0x29)
cam_i2c_write(cam_iic, device_addr, 0x5807, 0x38)
cam_i2c_write(cam_iic, device_addr, 0x5808, 0x26)
cam_i2c_write(cam_iic, device_addr, 0x5809, 0x17)
cam_i2c_write(cam_iic, device_addr, 0x580a, 0x11)
cam_i2c_write(cam_iic, device_addr, 0x580b, 0xe)
cam_i2c_write(cam_iic, device_addr, 0x580c, 0xd)
cam_i2c_write(cam_iic, device_addr, 0x580d, 0xe)
cam_i2c_write(cam_iic, device_addr, 0x580e, 0x13)
cam_i2c_write(cam_iic, device_addr, 0x580f, 0x1a)
cam_i2c_write(cam_iic, device_addr, 0x5810, 0x15)
cam_i2c_write(cam_iic, device_addr, 0x5811, 0xd)
cam_i2c_write(cam_iic, device_addr, 0x5812, 0x8)
cam_i2c_write(cam_iic, device_addr, 0x5813, 0x5)
cam_i2c_write(cam_iic, device_addr, 0x5814, 0x4)
cam_i2c_write(cam_iic, device_addr, 0x5815, 0x5)
cam_i2c_write(cam_iic, device_addr, 0x5816, 0x9)
cam_i2c_write(cam_iic, device_addr, 0x5817, 0xd)
cam_i2c_write(cam_iic, device_addr, 0x5818, 0x11)
cam_i2c_write(cam_iic, device_addr, 0x5819, 0xa)
cam_i2c_write(cam_iic, device_addr, 0x581a, 0x4)
cam_i2c_write(cam_iic, device_addr, 0x581b, 0x0)
cam_i2c_write(cam_iic, device_addr, 0x581c, 0x0)
cam_i2c_write(cam_iic, device_addr, 0x581d, 0x1)
cam_i2c_write(cam_iic, device_addr, 0x581e, 0x6)
cam_i2c_write(cam_iic, device_addr, 0x581f, 0x9)
cam_i2c_write(cam_iic, device_addr, 0x5820, 0x12)
cam_i2c_write(cam_iic, device_addr, 0x5821, 0xb)
cam_i2c_write(cam_iic, device_addr, 0x5822, 0x4)
cam_i2c_write(cam_iic, device_addr, 0x5823, 0x0)
cam_i2c_write(cam_iic, device_addr, 0x5824, 0x0)
cam_i2c_write(cam_iic, device_addr, 0x5825, 0x1)
cam_i2c_write(cam_iic, device_addr, 0x5826, 0x6)
cam_i2c_write(cam_iic, device_addr, 0x5827, 0xa)
cam_i2c_write(cam_iic, device_addr, 0x5828, 0x17)
cam_i2c_write(cam_iic, device_addr, 0x5829, 0xf)
cam_i2c_write(cam_iic, device_addr, 0x582a, 0x9)
cam_i2c_write(cam_iic, device_addr, 0x582b, 0x6)
cam_i2c_write(cam_iic, device_addr, 0x582c, 0x5)
cam_i2c_write(cam_iic, device_addr, 0x582d, 0x6)
cam_i2c_write(cam_iic, device_addr, 0x582e, 0xa)
cam_i2c_write(cam_iic, device_addr, 0x582f, 0xe)
cam_i2c_write(cam_iic, device_addr, 0x5830, 0x28)
cam_i2c_write(cam_iic, device_addr, 0x5831, 0x1a)
cam_i2c_write(cam_iic, device_addr, 0x5832, 0x11)
cam_i2c_write(cam_iic, device_addr, 0x5833, 0xe)
cam_i2c_write(cam_iic, device_addr, 0x5834, 0xe)
cam_i2c_write(cam_iic, device_addr, 0x5835, 0xf)
cam_i2c_write(cam_iic, device_addr, 0x5836, 0x15)
cam_i2c_write(cam_iic, device_addr, 0x5837, 0x1d)
cam_i2c_write(cam_iic, device_addr, 0x5838, 0x6e)
cam_i2c_write(cam_iic, device_addr, 0x5839, 0x39)
cam_i2c_write(cam_iic, device_addr, 0x583a, 0x27)
cam_i2c_write(cam_iic, device_addr, 0x583b, 0x1f)
cam_i2c_write(cam_iic, device_addr, 0x583c, 0x1e)
cam_i2c_write(cam_iic, device_addr, 0x583d, 0x23)
cam_i2c_write(cam_iic, device_addr, 0x583e, 0x2f)
cam_i2c_write(cam_iic, device_addr, 0x583f, 0x41)
cam_i2c_write(cam_iic, device_addr, 0x5840, 0xe)
cam_i2c_write(cam_iic, device_addr, 0x5841, 0xc)
cam_i2c_write(cam_iic, device_addr, 0x5842, 0xd)
cam_i2c_write(cam_iic, device_addr, 0x5843, 0xc)
cam_i2c_write(cam_iic, device_addr, 0x5844, 0xc)
cam_i2c_write(cam_iic, device_addr, 0x5845, 0xc)
cam_i2c_write(cam_iic, device_addr, 0x5846, 0xc)
cam_i2c_write(cam_iic, device_addr, 0x5847, 0xc)
cam_i2c_write(cam_iic, device_addr, 0x5848, 0xd)
cam_i2c_write(cam_iic, device_addr, 0x5849, 0xe)
cam_i2c_write(cam_iic, device_addr, 0x584a, 0xe)
cam_i2c_write(cam_iic, device_addr, 0x584b, 0xa)
cam_i2c_write(cam_iic, device_addr, 0x584c, 0xe)
cam_i2c_write(cam_iic, device_addr, 0x584d, 0xe)
cam_i2c_write(cam_iic, device_addr, 0x584e, 0x10)
cam_i2c_write(cam_iic, device_addr, 0x584f, 0x10)
cam_i2c_write(cam_iic, device_addr, 0x5850, 0x11)
cam_i2c_write(cam_iic, device_addr, 0x5851, 0xa)
cam_i2c_write(cam_iic, device_addr, 0x5852, 0xf)
cam_i2c_write(cam_iic, device_addr, 0x5853, 0xe)
cam_i2c_write(cam_iic, device_addr, 0x5854, 0x10)
cam_i2c_write(cam_iic, device_addr, 0x5855, 0x10)
cam_i2c_write(cam_iic, device_addr, 0x5856, 0x10)
cam_i2c_write(cam_iic, device_addr, 0x5857, 0xa)
cam_i2c_write(cam_iic, device_addr, 0x5858, 0xe)
cam_i2c_write(cam_iic, device_addr, 0x5859, 0xe)
cam_i2c_write(cam_iic, device_addr, 0x585a, 0xf)
cam_i2c_write(cam_iic, device_addr, 0x585b, 0xf)
cam_i2c_write(cam_iic, device_addr, 0x585c, 0xf)
cam_i2c_write(cam_iic, device_addr, 0x585d, 0xa)
cam_i2c_write(cam_iic, device_addr, 0x585e, 0x9)
cam_i2c_write(cam_iic, device_addr, 0x585f, 0xd)
cam_i2c_write(cam_iic, device_addr, 0x5860, 0xc)
cam_i2c_write(cam_iic, device_addr, 0x5861, 0xb)
cam_i2c_write(cam_iic, device_addr, 0x5862, 0xd)
cam_i2c_write(cam_iic, device_addr, 0x5863, 0x7)
cam_i2c_write(cam_iic, device_addr, 0x5864, 0x17)
cam_i2c_write(cam_iic, device_addr, 0x5865, 0x14)
cam_i2c_write(cam_iic, device_addr, 0x5866, 0x18)
cam_i2c_write(cam_iic, device_addr, 0x5867, 0x18)
cam_i2c_write(cam_iic, device_addr, 0x5868, 0x16)
cam_i2c_write(cam_iic, device_addr, 0x5869, 0x12)
cam_i2c_write(cam_iic, device_addr, 0x586a, 0x1b)
cam_i2c_write(cam_iic, device_addr, 0x586b, 0x1a)
cam_i2c_write(cam_iic, device_addr, 0x586c, 0x16)
cam_i2c_write(cam_iic, device_addr, 0x586d, 0x16)
cam_i2c_write(cam_iic, device_addr, 0x586e, 0x18)
cam_i2c_write(cam_iic, device_addr, 0x586f, 0x1f)
cam_i2c_write(cam_iic, device_addr, 0x5870, 0x1c)
cam_i2c_write(cam_iic, device_addr, 0x5871, 0x16)
cam_i2c_write(cam_iic, device_addr, 0x5872, 0x10)
cam_i2c_write(cam_iic, device_addr, 0x5873, 0xf)
cam_i2c_write(cam_iic, device_addr, 0x5874, 0x13)
cam_i2c_write(cam_iic, device_addr, 0x5875, 0x1c)
cam_i2c_write(cam_iic, device_addr, 0x5876, 0x1e)
cam_i2c_write(cam_iic, device_addr, 0x5877, 0x17)
cam_i2c_write(cam_iic, device_addr, 0x5878, 0x11)
cam_i2c_write(cam_iic, device_addr, 0x5879, 0x11)
cam_i2c_write(cam_iic, device_addr, 0x587a, 0x14)
cam_i2c_write(cam_iic, device_addr, 0x587b, 0x1e)
cam_i2c_write(cam_iic, device_addr, 0x587c, 0x1c)
cam_i2c_write(cam_iic, device_addr, 0x587d, 0x1c)
cam_i2c_write(cam_iic, device_addr, 0x587e, 0x1a)
cam_i2c_write(cam_iic, device_addr, 0x587f, 0x1a)
cam_i2c_write(cam_iic, device_addr, 0x5880, 0x1b)
cam_i2c_write(cam_iic, device_addr, 0x5881, 0x1f)
cam_i2c_write(cam_iic, device_addr, 0x5882, 0x14)
cam_i2c_write(cam_iic, device_addr, 0x5883, 0x1a)
cam_i2c_write(cam_iic, device_addr, 0x5884, 0x1d)
cam_i2c_write(cam_iic, device_addr, 0x5885, 0x1e)
cam_i2c_write(cam_iic, device_addr, 0x5886, 0x1a)
cam_i2c_write(cam_iic, device_addr, 0x5887, 0x1a)
cam_i2c_write(cam_iic, device_addr, 0x528a, 0x02)
cam_i2c_write(cam_iic, device_addr, 0x528b, 0x06)
cam_i2c_write(cam_iic, device_addr, 0x528c, 0x20)
cam_i2c_write(cam_iic, device_addr, 0x528d, 0x30)
cam_i2c_write(cam_iic, device_addr, 0x528e, 0x40)
cam_i2c_write(cam_iic, device_addr, 0x528f, 0x50)
cam_i2c_write(cam_iic, device_addr, 0x5290, 0x60)
cam_i2c_write(cam_iic, device_addr, 0x5292, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5293, 0x02)
cam_i2c_write(cam_iic, device_addr, 0x5294, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5295, 0x04)
cam_i2c_write(cam_iic, device_addr, 0x5296, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5297, 0x08)
cam_i2c_write(cam_iic, device_addr, 0x5298, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5299, 0x10)
cam_i2c_write(cam_iic, device_addr, 0x529a, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x529b, 0x20)
cam_i2c_write(cam_iic, device_addr, 0x529c, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x529d, 0x28)
cam_i2c_write(cam_iic, device_addr, 0x529e, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x529f, 0x30)
cam_i2c_write(cam_iic, device_addr, 0x5282, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5680, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5681, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5682, 0x05)
cam_i2c_write(cam_iic, device_addr, 0x5683, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5684, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5685, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x5686, 0x03)
cam_i2c_write(cam_iic, device_addr, 0x5687, 0xc0)
cam_i2c_write(cam_iic, device_addr, 0x5180, 0xff)
cam_i2c_write(cam_iic, device_addr, 0x5181, 0x52)
cam_i2c_write(cam_iic, device_addr, 0x5182, 0x11)
cam_i2c_write(cam_iic, device_addr, 0x5183, 0x14)
cam_i2c_write(cam_iic, device_addr, 0x5184, 0x25)
cam_i2c_write(cam_iic, device_addr, 0x5185, 0x24)
cam_i2c_write(cam_iic, device_addr, 0x5186, 0x14)
cam_i2c_write(cam_iic, device_addr, 0x5187, 0x14)
cam_i2c_write(cam_iic, device_addr, 0x5188, 0x14)
cam_i2c_write(cam_iic, device_addr, 0x5189, 0x80)
cam_i2c_write(cam_iic, device_addr, 0x518a, 0x60)
cam_i2c_write(cam_iic, device_addr, 0x518b, 0xa2)
cam_i2c_write(cam_iic, device_addr, 0x518c, 0x9c)
cam_i2c_write(cam_iic, device_addr, 0x518d, 0x36)
cam_i2c_write(cam_iic, device_addr, 0x518e, 0x34)
cam_i2c_write(cam_iic, device_addr, 0x518f, 0x54)
cam_i2c_write(cam_iic, device_addr, 0x5190, 0x4c)
cam_i2c_write(cam_iic, device_addr, 0x5191, 0xf8)
cam_i2c_write(cam_iic, device_addr, 0x5192, 0x04)
cam_i2c_write(cam_iic, device_addr, 0x5193, 0x70)
cam_i2c_write(cam_iic, device_addr, 0x5194, 0xf0)
cam_i2c_write(cam_iic, device_addr, 0x5195, 0xf0)
cam_i2c_write(cam_iic, device_addr, 0x5196, 0x03)
cam_i2c_write(cam_iic, device_addr, 0x5197, 0x01)
cam_i2c_write(cam_iic, device_addr, 0x5198, 0x05)
cam_i2c_write(cam_iic, device_addr, 0x5199, 0x2f)
cam_i2c_write(cam_iic, device_addr, 0x519a, 0x04)
cam_i2c_write(cam_iic, device_addr, 0x519b, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x519c, 0x06)
cam_i2c_write(cam_iic, device_addr, 0x519d, 0xa0)
cam_i2c_write(cam_iic, device_addr, 0x519e, 0xa0)
cam_i2c_write(cam_iic, device_addr, 0x3a0f, 0x3c)
cam_i2c_write(cam_iic, device_addr, 0x3a10, 0x30)
cam_i2c_write(cam_iic, device_addr, 0x3a1b, 0x3c)
cam_i2c_write(cam_iic, device_addr, 0x3a1e, 0x30)
cam_i2c_write(cam_iic, device_addr, 0x3a11, 0x70)
cam_i2c_write(cam_iic, device_addr, 0x3a1f, 0x10)
cam_i2c_write(cam_iic, device_addr, 0x3800, 0x1)
cam_i2c_write(cam_iic, device_addr, 0x3801, 0x50)
cam_i2c_write(cam_iic, device_addr, 0x3802, 0x0)
cam_i2c_write(cam_iic, device_addr, 0x3803, 0x8)
cam_i2c_write(cam_iic, device_addr, 0x3804, 0x5)
cam_i2c_write(cam_iic, device_addr, 0x3805, 0x0)
cam_i2c_write(cam_iic, device_addr, 0x3806, 0x3)
cam_i2c_write(cam_iic, device_addr, 0x3807, 0xc0)
cam_i2c_write(cam_iic, device_addr, 0x3808, 0x3)
cam_i2c_write(cam_iic, device_addr, 0x3809, 0x20)
cam_i2c_write(cam_iic, device_addr, 0x380a, 0x2)
cam_i2c_write(cam_iic, device_addr, 0x380b, 0x58)
cam_i2c_write(cam_iic, device_addr, 0x380c, 0xc)
cam_i2c_write(cam_iic, device_addr, 0x380d, 0x80)
cam_i2c_write(cam_iic, device_addr, 0x380e, 0x3)
cam_i2c_write(cam_iic, device_addr, 0x380f, 0xe8)
cam_i2c_write(cam_iic, device_addr, 0x5001, 0x7f)
cam_i2c_write(cam_iic, device_addr, 0x5680, 0x0)
cam_i2c_write(cam_iic, device_addr, 0x5681, 0x0)
cam_i2c_write(cam_iic, device_addr, 0x5682, 0x5)
cam_i2c_write(cam_iic, device_addr, 0x5683, 0x0)
cam_i2c_write(cam_iic, device_addr, 0x5684, 0x0)
cam_i2c_write(cam_iic, device_addr, 0x5685, 0x0)
cam_i2c_write(cam_iic, device_addr, 0x5686, 0x3)
cam_i2c_write(cam_iic, device_addr, 0x5687, 0xc0)
cam_i2c_write(cam_iic, device_addr, 0x5687, 0xc0)
cam_i2c_write(cam_iic, device_addr, 0x3815, 0x02)
cam_i2c_write(cam_iic, device_addr, 0x3503, 0x00)
cam_i2c_write(cam_iic, device_addr, 0x3818, 0x81) # No Mirror
cam_i2c_write(cam_iic, device_addr, 0x3621, 0xa7)
cam_i2c_write(cam_iic, device_addr, 0x4740, 0x21)
cam_i2c_write(cam_iic, device_addr, 0x501e, 0x2a)
cam_i2c_write(cam_iic, device_addr, 0x5002, 0x78)
cam_i2c_write(cam_iic, device_addr, 0x501f, 0x01)
cam_i2c_write(cam_iic, device_addr, 0x4300, 0x61)
# In[8]:
# frame buffer alocate
height = 600
width = 800
buffer0 = allocate(shape=(height, width, 1), dtype=np.uint32, cacheable=1)
buffer1 = allocate(shape=(height, width, 1), dtype=np.uint32, cacheable=1)
buffer2 = allocate(shape=(height, width, 1), dtype=np.uint32, cacheable=1)
buffer3 = allocate(shape=(height, width, 3), dtype=np.uint8, cacheable=1)
# In[9]:
# frame buffer resister set
vflip_dmaw.register_map.fb0_1 = buffer0.physical_address
vflip_dmaw.register_map.fb0_2 = 0
vflip_dmaw.register_map.fb1_1 = buffer1.physical_address
vflip_dmaw.register_map.fb1_2 = 0
vflip_dmaw.register_map.fb2_1 = buffer2.physical_address
vflip_dmaw.register_map.fb2_2 = 0
# In[10]:
dma2axis30.register_map.fb0 = buffer0.physical_address
dma2axis30.register_map.fb1 = buffer1.physical_address
dma2axis30.register_map.fb2 = buffer2.physical_address
dma2axis30.register_map.mode = 0 # DMA_WRITE_MODE
# In[11]:
dma2axis31.register_map.fb0 = buffer0.physical_address
dma2axis31.register_map.fb1 = buffer1.physical_address
dma2axis31.register_map.fb2 = buffer2.physical_address
dma2axis31.register_map.mode = 0 # DMA_WRITE_MODE
# In[12]:
sobel0.register_map.row_size = height
sobel0.register_map.col_size = width
sobel0.register_map.function_r = 0 # ORG_IMGwAxiVdma
# In[13]:
sobel1.register_map.row_size = height
sobel1.register_map.col_size = width
sobel1.register_map.function_r = 0 # ORG_IMGwAxiVdma
# In[14]:
axis2dma.register_map.out_r = buffer3.physical_address
axis2dma.register_map.row_size = height
axis2dma.register_map.col_size = width
# In[15]:
# vflip_dma_write start and auto repeat
vflip_dmaw.register_map.CTRL = 0x81
# In[16]:
# Camera Initialization
cam_i2c_init(cam_iic)
cam_reg_set(cam_iic, 0x78)
# In[17]:
# paracam_inf_axi start
paracam_inf.write(0x0, 0x0)
paracam_inf.write(0x4, 0x0)
# In[18]:
# VTC enable
vtc.write(0x0, 0x04) # Generation Enable
# In[19]:
# sobel_axis_RGB24 start
sobel0.register_map.CTRL = 0x81
# In[20]:
# dma2axis_3buf start and auto repeat
dma2axis30.register_map.CTRL = 0x81
# In[21]:
# image capture
axis2dma.register_map.CTRL = 0x1
# In[22]:
print(axis2dma.register_map.CTRL)
# In[23]:
sobel1.register_map.CTRL = 0x1
# In[24]:
print(sobel1.register_map.CTRL)
# In[25]:
dma2axis31.register_map.CTRL = 0x1
# In[26]:
print(dma2axis31.register_map.CTRL)
# In[27]:
print(axis2dma.register_map.CTRL)
print(sobel1.register_map.CTRL)
print(dma2axis31.register_map.CTRL)
# In[28]:
cam_image = Image.fromarray(buffer3)
# In[29]:
print("Image size: {}x{} pixels.".format(width, height))
plt.figure(figsize=(12, 10));
_ = plt.imshow(cam_image)
# In[30]:
cam_image.save('temp.jpg')
# In[31]:
#sobel filter on for camera image
sobel0.register_map.function_r = 1 # SOBELwAxiVdma
# In[32]:
# sobel filter off for camera image
sobel0.register_map.function_r = 0 # ORG_IMGwAxiVdma
# In[27]:
#sobel fliter on for image capture
sobel1.register_map.function_r = 1 # SOBELwAxiVdma
#axis2dma.register_map.CTRL = 0x1
#sobel1.register_map.CTRL = 0x1
#dma2axis31.register_map.CTRL = 0x1
# In[ ]:
#sobel fliter off for image capture
sobel1.register_map.function_r = 0 # ORG_IMGwAxiVdma
#axis2dma.register_map.CTRL = 0x1
#sobel1.register_map.CTRL = 0x1
#dma2axis31.register_map.CTRL = 0x1
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