#image_path = "./test2.jpg"
image_path = "./blue.bmp"
#image_path = "./green.bmp"
#image_path = "./red.bmp"
original_image = Image.open(image_path)
gaussian.register_map.row_size = height
gaussian.register_map.col_size = width
gaussian.register_map.function_r = 2 # ORG_IMGwAxiDma
#gaussian.register_map.function_r = 3 # GAUSSIANwAxiDma
median.register_map.row_size = height
median.register_map.col_size = width
median.register_map.function_r = 2 # ORG_IMGwAxiDma
#median.register_map.function_r = 3 # MEDIANwAxiDma
sobel.register_map.row_size = height
sobel.register_map.col_size = width
sobel.register_map.function_r = 2 # ORG_IMGwAxiDma
#sobel.register_map.function_r = 3 # SOBELwAxiDma
#image_path = "./test2.jpg"
image_path = "./blue.png"
#image_path = "./green.png"
#image_path = "./red.png"
original_image = Image.open(image_path)
gaussian.register_map.row_size = height
gaussian.register_map.col_size = width
gaussian.register_map.function_r = 2 # ORG_IMGwAxiDma
#gaussian.register_map.function_r = 3 # GAUSSIANwAxiDma
median.register_map.row_size = height
median.register_map.col_size = width
median.register_map.function_r = 2 # ORG_IMGwAxiDma
#median.register_map.function_r = 3 # MEDIANwAxiDma
sobel.register_map.row_size = height
sobel.register_map.col_size = width
sobel.register_map.function_r = 2 # ORG_IMGwAxiDma
#sobel.register_map.function_r = 3 # SOBELwAxiDma
0x200 番地 ― Clock Configuration Register 0
Bit[25:16] = CLKFBOUT_FRAC Multiply = 0
Bit[15:8] = CLKFBOUT_MULT = 8
Bit[7:0] = DIVCLK_DIVIDE = 1
0x208 番地 - Clock Configuration Register 2
Bit[7:0] = CLKOUT0_DIVIDE = 0x49 (10進で 73)
Integer part of clkout0 divide value
For example, for 2.250, this value is 2 = 0x2
Bit[17:8] = CLKOUT0_FRAC Divide = 0
Fractional part of clkout0 divide value
For example, for 2.250, this value is 250 = 0xFA
XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr, 0x200, 0x0801);
XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr, 0x208, 0x50);
XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr, 0x200, 0x0801);
XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr, 0x208, 0x20);
XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr, 0x200, 0x0801);
XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr, 0x208, 0x28);
// Dynamic_Clocking.c
// 2023/05/18 by marsee
// Referred to "MicroZed Chronicles: Dynamic Clocking"
// https://www.adiuvoengineering.com/post/microzed-chronicles-dynamic-clocking
// 2023/05/27 : Modified by marsee
#include <stdio.h>
#include "xclk_wiz.h"
#include "xgpio.h"
#include "xparameters.h"
XClk_Wiz ClkWiz_Dynamic;
XClk_Wiz_Config *CfgPtr_Dynamic;
XGpio gpio_0, gpio_1;
#define XCLK_WIZARD_DEVICE_ID XPAR_CLK_WIZ_0_DEVICE_ID
#define XCLK_US_WIZ_RECONFIG_OFFSET 0x0000025C
#define CLK_LOCK 1
int main(){
u32 count, locked;
int Status;
CfgPtr_Dynamic = XClk_Wiz_LookupConfig(XCLK_WIZARD_DEVICE_ID);
XClk_Wiz_CfgInitialize(&ClkWiz_Dynamic, CfgPtr_Dynamic, CfgPtr_Dynamic->BaseAddr);
XGpio_Initialize(&gpio_0, XPAR_AXI_GPIO_0_DEVICE_ID);
XGpio_Initialize(&gpio_1, XPAR_AXI_GPIO_1_DEVICE_ID);
printf("freq = 40 MHz\n");
XGpio_DiscreteWrite(&gpio_1, 1, 1); // counter SCLR = 1, CE = 0
usleep(1000);
XGpio_DiscreteWrite(&gpio_1, 1, 2); // counter SCLR = 0, CE = 1
sleep(1);
XGpio_DiscreteWrite(&gpio_1, 1, 0); // counter SCLR = 0, CE = 0
count = XGpio_DiscreteRead(&gpio_0, 1);
locked = XGpio_DiscreteRead(&gpio_0, 2);
printf("count = %d, locked = %d\n\n", count, locked);
XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr, XCLK_WIZ_REG25_OFFSET, 0);
//XClk_Wiz_SetRate(&ClkWiz_Dynamic, 10);
XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr, 0x200, 0x0801);
XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr, 0x208, 0x50);
XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr,
XCLK_US_WIZ_RECONFIG_OFFSET,
(XCLK_WIZ_RECONFIG_LOAD | XCLK_WIZ_RECONFIG_SADDR));
Status = XClk_Wiz_WaitForLock(&ClkWiz_Dynamic);
printf("freq = 10 MHz, XClk_Wiz_SetRate\n");
XGpio_DiscreteWrite(&gpio_1, 1, 1); // counter SCLR = 1, CE = 0
usleep(1000);
XGpio_DiscreteWrite(&gpio_1, 1, 2); // counter SCLR = 0, CE = 1
sleep(1);
XGpio_DiscreteWrite(&gpio_1, 1, 0); // counter SCLR = 0, CE = 0
count = XGpio_DiscreteRead(&gpio_0, 1);
locked = XGpio_DiscreteRead(&gpio_0, 2);
printf("count = %d, locked = %d\n\n", count, locked);
XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr, XCLK_WIZ_REG25_OFFSET, 0);
//XClk_Wiz_SetRate(&ClkWiz_Dynamic, 25);
XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr, 0x200, 0x0801);
XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr, 0x208, 0x20);
XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr,
XCLK_US_WIZ_RECONFIG_OFFSET,
(XCLK_WIZ_RECONFIG_LOAD | XCLK_WIZ_RECONFIG_SADDR));
Status = XClk_Wiz_WaitForLock(&ClkWiz_Dynamic);
printf("freq = 25 MHz\n");
XGpio_DiscreteWrite(&gpio_1, 1, 1); // counter SCLR = 1, CE = 0
usleep(1000);
XGpio_DiscreteWrite(&gpio_1, 1, 2); // counter SCLR = 0, CE = 1
sleep(1);
XGpio_DiscreteWrite(&gpio_1, 1, 0); // counter SCLR = 0, CE = 0
count = XGpio_DiscreteRead(&gpio_0, 1);
locked = XGpio_DiscreteRead(&gpio_0, 2);
printf("count = %d, locked = %d\n\n", count, locked);
XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr, XCLK_WIZ_REG25_OFFSET, 0);
//XClk_Wiz_SetRateHz(&ClkWiz_Dynamic, 20000000);
XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr, 0x200, 0x0801);
XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr, 0x208, 0x28);
XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr,
XCLK_US_WIZ_RECONFIG_OFFSET,
(XCLK_WIZ_RECONFIG_LOAD | XCLK_WIZ_RECONFIG_SADDR));
Status = XClk_Wiz_WaitForLock(&ClkWiz_Dynamic);
printf("freq = 20 MHz, XClk_Wiz_SetRateHz(&ClkWiz_Dynamic, 20000000);\n");
XGpio_DiscreteWrite(&gpio_1, 1, 1); // counter SCLR = 1, CE = 0
usleep(1000);
XGpio_DiscreteWrite(&gpio_1, 1, 2); // counter SCLR = 0, CE = 1
sleep(1);
XGpio_DiscreteWrite(&gpio_1, 1, 0); // counter SCLR = 0, CE = 0
count = XGpio_DiscreteRead(&gpio_0, 1);
locked = XGpio_DiscreteRead(&gpio_0, 2);
printf("count = %d, locked = %d\n\n", count, locked);
return(0);
}
// Dynamic_Clocking.c
// 2023/05/18 by marsee
// Referred to "MicroZed Chronicles: Dynamic Clocking"
// https://www.adiuvoengineering.com/post/microzed-chronicles-dynamic-clocking
#include <stdio.h>
#include "xclk_wiz.h"
#include "xgpio.h"
#include "xparameters.h"
XClk_Wiz ClkWiz_Dynamic;
XClk_Wiz_Config *CfgPtr_Dynamic;
XGpio gpio_0, gpio_1;
#define XCLK_WIZARD_DEVICE_ID XPAR_CLK_WIZ_0_DEVICE_ID
#define XCLK_US_WIZ_RECONFIG_OFFSET 0x0000025C
#define CLK_LOCK 1
int main(){
u32 count, locked;
int Status;
CfgPtr_Dynamic = XClk_Wiz_LookupConfig(XCLK_WIZARD_DEVICE_ID);
XClk_Wiz_CfgInitialize(&ClkWiz_Dynamic, CfgPtr_Dynamic, CfgPtr_Dynamic->BaseAddr);
XGpio_Initialize(&gpio_0, XPAR_AXI_GPIO_0_DEVICE_ID);
XGpio_Initialize(&gpio_1, XPAR_AXI_GPIO_1_DEVICE_ID);
printf("freq = 40 MHz\n");
XGpio_DiscreteWrite(&gpio_1, 1, 1); // counter SCLR = 1, CE = 0
usleep(1000);
XGpio_DiscreteWrite(&gpio_1, 1, 2); // counter SCLR = 0, CE = 1
sleep(1);
XGpio_DiscreteWrite(&gpio_1, 1, 0); // counter SCLR = 0, CE = 0
count = XGpio_DiscreteRead(&gpio_0, 1);
locked = XGpio_DiscreteRead(&gpio_0, 2);
printf("count = %d, locked = %d\n\n", count, locked);
XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr, XCLK_WIZ_REG25_OFFSET, 0);
XClk_Wiz_SetRate(&ClkWiz_Dynamic, 10);
XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr,
XCLK_US_WIZ_RECONFIG_OFFSET,
(XCLK_WIZ_RECONFIG_LOAD | XCLK_WIZ_RECONFIG_SADDR));
Status = XClk_Wiz_WaitForLock(&ClkWiz_Dynamic);
printf("freq = 10 MHz, XClk_Wiz_SetRate\n");
XGpio_DiscreteWrite(&gpio_1, 1, 1); // counter SCLR = 1, CE = 0
usleep(1000);
XGpio_DiscreteWrite(&gpio_1, 1, 2); // counter SCLR = 0, CE = 1
sleep(1);
XGpio_DiscreteWrite(&gpio_1, 1, 0); // counter SCLR = 0, CE = 0
count = XGpio_DiscreteRead(&gpio_0, 1);
locked = XGpio_DiscreteRead(&gpio_0, 2);
printf("count = %d, locked = %d\n\n", count, locked);
XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr, XCLK_WIZ_REG25_OFFSET, 0);
XClk_Wiz_SetRate(&ClkWiz_Dynamic, 25);
XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr,
XCLK_US_WIZ_RECONFIG_OFFSET,
(XCLK_WIZ_RECONFIG_LOAD | XCLK_WIZ_RECONFIG_SADDR));
Status = XClk_Wiz_WaitForLock(&ClkWiz_Dynamic);
printf("freq = 25 MHz\n");
XGpio_DiscreteWrite(&gpio_1, 1, 1); // counter SCLR = 1, CE = 0
usleep(1000);
XGpio_DiscreteWrite(&gpio_1, 1, 2); // counter SCLR = 0, CE = 1
sleep(1);
XGpio_DiscreteWrite(&gpio_1, 1, 0); // counter SCLR = 0, CE = 0
count = XGpio_DiscreteRead(&gpio_0, 1);
locked = XGpio_DiscreteRead(&gpio_0, 2);
printf("count = %d, locked = %d\n\n", count, locked);
XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr, XCLK_WIZ_REG25_OFFSET, 0);
XClk_Wiz_SetRateHz(&ClkWiz_Dynamic, 20000000);
XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr,
XCLK_US_WIZ_RECONFIG_OFFSET,
(XCLK_WIZ_RECONFIG_LOAD | XCLK_WIZ_RECONFIG_SADDR));
Status = XClk_Wiz_WaitForLock(&ClkWiz_Dynamic);
printf("freq = 20 MHz, XClk_Wiz_SetRateHz(&ClkWiz_Dynamic, 20000000);\n");
XGpio_DiscreteWrite(&gpio_1, 1, 1); // counter SCLR = 1, CE = 0
usleep(1000);
XGpio_DiscreteWrite(&gpio_1, 1, 2); // counter SCLR = 0, CE = 1
sleep(1);
XGpio_DiscreteWrite(&gpio_1, 1, 0); // counter SCLR = 0, CE = 0
count = XGpio_DiscreteRead(&gpio_0, 1);
locked = XGpio_DiscreteRead(&gpio_0, 2);
printf("count = %d, locked = %d\n\n", count, locked);
return(0);
}
// timer_test.c
// 2023/02/08 by marsee
// Reference URL:https://github.com/ikwzm/ZYBO_UIO_IRQ_SAMPLE/blob/master/c-sample/sample1.c
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <fcntl.h>
#include <string.h>
#include <time.h>
#include <sys/time.h>
#include <poll.h>
#include <sys/types.h>
#include <sys/mman.h>
#define ENABLE_ALL_TIMERS (0x1<<10)
#define ENABLE_PULSE_WIDTH_MODULATION (0x1<<9)
#define TIMER_INTERRUPT (0x1<<8)
#define ENABLE_TIMER (0x1<<7)
#define ENABLE_INTERRUPT (0x1<<6)
#define LOAD_TIMER (0x1<<5)
#define AUTO_RELOAD_HOLD_TIMER (0x1<<4)
#define ENABLE_EXT_CAPTURE_TRIG (0x1<<3)
#define ENABLE_EXT_GENERATE_SIG (0x1<<2)
#define DOWN_UP_COUNT_TIMER (0x1<<1)
#define TIMER_MODE_CAP_GENE (0x1)
int uio_irq_on(int uio_fd)
{
unsigned int irq_on = 1;
write(uio_fd, &irq_on, sizeof(irq_on));
}
int uio_wait_irq(int uio_fd)
{
unsigned int count = 0;
return read(uio_fd, &count, sizeof(count));
}
void main()
{
int uio0_fd, uio1_fd;
uint32_t *axi_gpio, *axi_timer;
static uint32_t led_stat = 0;
if((uio0_fd = open("/dev/uio0", O_RDWR)) == -1) {
printf("Can not open /dev/uio0\n");
exit(1);
}
axi_gpio = (uint32_t*)mmap(NULL, 0x10000, PROT_READ|PROT_WRITE, MAP_SHARED, uio0_fd, 0);
if((uio1_fd = open("/dev/uio1", O_RDWR)) == -1) {
printf("Can not open /dev/uio1\n");
exit(1);
}
axi_timer = (uint32_t*)mmap(NULL, 0x10000, PROT_READ|PROT_WRITE, MAP_SHARED, uio1_fd, 0);
// axi_timer_0 -> Timer0
axi_timer[1] = 0x02FAF080; // TLR0, Decimal = 50,000,000, 100 MHz = 0.5sec
axi_timer[0] = LOAD_TIMER; // TCR0, ENALL and LOAD0 = 1
axi_timer[0] = TIMER_INTERRUPT | ENABLE_TIMER | ENABLE_INTERRUPT | AUTO_RELOAD_HOLD_TIMER | DOWN_UP_COUNT_TIMER; // timer interrupt clear
for(int i=0; i<100; i++){
if(uio_irq_on(uio1_fd) == -1){
fprintf(stderr, "uio_irq_on error\n");
break;
}
if(uio_wait_irq(uio1_fd) == -1){
fprintf(stderr, "uio_wait_irq error\n");
break;
}
axi_timer[0] = TIMER_INTERRUPT | ENABLE_TIMER | ENABLE_INTERRUPT | AUTO_RELOAD_HOLD_TIMER | DOWN_UP_COUNT_TIMER; // timer interrupt clear
led_stat ^= 0xf;
axi_gpio[0] = led_stat;
}
close(uio0_fd);
close(uio1_fd);
}
日 | 月 | 火 | 水 | 木 | 金 | 土 |
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- | - | - | - | - | 1 | 2 |
3 | 4 | 5 | 6 | 7 | 8 | 9 |
10 | 11 | 12 | 13 | 14 | 15 | 16 |
17 | 18 | 19 | 20 | 21 | 22 | 23 |
24 | 25 | 26 | 27 | 28 | 29 | 30 |
31 | - | - | - | - | - | - |