-- SLC, SDA を遅延させる
process(clk) begin
if clk'event and clk='1' then
if reset='1' then
SDA_Delay <= (others => '1');
SDA_ena_Delay <= (others => '1');
SCL_Delay <= '1';
else
SDA_Delay(2) <= SDA_shift_reg(8);
SDA_Delay(1) <= SDA_Delay(2);
SDA_Delay(0) <= SDA_Delay(1);
SDA_ena_Delay(1) <= SDA_enable;
SDA_ena_Delay(0) <= SDA_ena_Delay(1);
SCL_Delay <= SCL_shift_reg(17);
end if;
end if;
end process;
SRL16E_SDA : SRL16E generic map(
INIT => X"0000")
port map(
Q => SDA_Delay_SRL16,
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
CE => '1',
CLK => clk,
D => SDA_Delay(0)
);
SRL16E_SDA_ena : SRL16E generic map(
INIT => X"0000")
port map(
Q => SDA_ena_Delay_SR16,
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
CE => '1',
CLK => clk,
D => SDA_ena_Delay(0)
);
SDA <= SDA_Delay_SRL16 when SDA_ena_Delay_SR16='0' else 'Z';
SCL <= SCL_Delay;
NET "dvi_d[0]" IOSTANDARD = LVDCI_33;
NET "dvi_d[1]" IOSTANDARD = LVDCI_33;
NET "dvi_d[2]" IOSTANDARD = LVDCI_33;
NET "dvi_d[3]" IOSTANDARD = LVDCI_33;
NET "dvi_d[4]" IOSTANDARD = LVDCI_33;
NET "dvi_d[5]" IOSTANDARD = LVDCI_33;
NET "dvi_d[6]" IOSTANDARD = LVDCI_33;
NET "dvi_d[7]" IOSTANDARD = LVDCI_33;
NET "dvi_d[8]" IOSTANDARD = LVDCI_33;
NET "dvi_d[9]" IOSTANDARD = LVDCI_33;
NET "dvi_d[10]" IOSTANDARD = LVDCI_33;
NET "dvi_d[11]" IOSTANDARD = LVDCI_33;
NET "dvi_de" IOSTANDARD = LVCMOS33;
NET "dvi_hsync" IOSTANDARD = LVDCI_33;
NET "dvi_reset_b" IOSTANDARD = LVCMOS33;
NET "dvi_vsync" IOSTANDARD = LVDCI_33;
NET "dvi_xclk_n" IOSTANDARD = LVCMOS33;
NET "dvi_xclk_p" IOSTANDARD = LVCMOS33;
NET "dvi_xclk_n" DRIVE = 24;
NET "dvi_xclk_p" DRIVE = 24;
NET "dvi_xclk_n" SLEW = FAST;
NET "dvi_xclk_p" SLEW = FAST;
NET "reset_sw" IOSTANDARD = LVCMOS33;
NET "dvi_scl" LOC = U27;
NET "dvi_sda" LOC = T29;
NET "dvi_scl" IOSTANDARD = LVCMOS18;
NET "dvi_sda" IOSTANDARD = LVCMOS18;
NET "dvi_scl" SLEW = FAST;
NET "dvi_sda" SLEW = FAST;
NET "dvi_scl" DRIVE = 24;
NET "dvi_sda" DRIVE = 24;
NET "dvi_scl" TIG;
NET "dvi_sda" TIG;
NET "dvi_scl" PULLUP;
NET "dvi_sda" PULLUP;
INST "dvi_de" IOB = FORCE;
INST "dvi_hsync" IOB = FORCE;
INST "dvi_vsync" IOB = FORCE;
sim_tb_top.\gen_cs[0].gen[0].u_mem0 .cmd_task: at time 20718860.0 ps ERROR: Activate Failure. Initialization sequence is not complete.
1. 9129.485 ns All banks PRECHARGE
2. 10111.985 ns LOAD MODE
BA=2, EMR2 値は0000、1X refresh rate
3. 11094.485 ns LOAD MODE
BA=3, EMR3 値は0000
4. 12076.985 ns LOAD MODE
BA=1, EMR1 値は0004、Outputs Enable, RDQS Disable, DQS# Enable, OCD exit, Rtt=75Ω, Posted CAS# = 0, Output Drive Strength Full, DLL Enable
5. 13059.485 ns LOAD MODE
BA=0, MR 値は0742、Fast exit, Write Recovery = 4, DLL Reast = Yes, CAS Latency = 4, Sequential, Burst Length = 4
6. 14821.985 ns All banks PRECHARGE
7. 15804.485 ns REFRESH
8. 16786.985 ns REFRESH
9. 17769.485 ns LOAD MODE
BA=0, MR 値は0642、Fast exit, Write Recovery = 4, DLL Reast = No, CAS Latency = 4, Sequential, Burst Length = 4
10. 18751.985 ns LOAD MODE
BA=1, EMR1 値は0384、Outputs Enable, RDQS Disable, DQS# Enable, Enable OCD defaults, Rtt=75Ω, Posted CAS# = 0, Output Drive Strength Full, DLL Enable
11. 19734.485 ns LOAD MODE
BA=1, EMR1 値は0004、Outputs Enable, RDQS Disable, DQS# Enable, OCD exit, Rtt=75Ω, Posted CAS# = 0, Output Drive Strength Full, DLL Enable
12. 20716.985 ns Activate ここでエラーになる。ERROR: Activate Failure. Initialization sequence is not complete.
BA=0, address=0000
13. 21691.985 ns Write 当然、ここでもエラー。ERROR: Write Failure. Initialization sequence is not complete.
BA=0, address=0000、データはFFFFFFFFFFFFFFFFと0000000000000000の繰り返し
14. 21699.485 ns Write 当然、ここでもエラー。ERROR: Write Failure. Initialization sequence is not complete.
BA=0, address=0004、データはFFFFFFFFFFFFFFFFと0000000000000000の繰り返し
vlog +incdir+. +define+x512Mb +define+sg37E +define+x16 ddr2_model.v
`define x512Mb
`define sg37E
`define x16
・ このMIGデザインは、SMAコネクタのクロック入力J10とJ11から200MHzの差動クロックを入力している。SMAコネクタから入力された差動クロックは、回路図の2ページ右上のH14(SMA_DIFF_CLKIN_P), H15(SMA_DIFF_CLKIN_N)に入力されている。
・ クロックが出力されるのはJ12とJ13で、これは、ICS843001-21から出力された差動クロックだ。回路図9ページ。
・ SW6が設定スイッチとして割り当てられている。SW6が01001010と設定されていると、N0-0, N1-1, N2-0, M0-0, M1-1, M2-0, SEL1-1, SEL0-0 となる。
・ SEL1, SEL0で入力を選択していて、この値の時はTEST_CLK入力となる。TEST_CLKには、25MHzの水晶発振器がつながっている。
・ ICS843001-21は上記の設定だと、25MHz入力、M分周比=24, N分周比=3となって、出力周波数は200MHzとなる。(TABLE 3A. COMMON CONFIGURATIONS TABLE 参照)
NET "sys_clk_p" LOC = "K18" ; #Bank 3
NET "sys_clk_n" LOC = "J19" ; #Bank 3
-- 表示タイミングの定義
library ieee;
use ieee.std_logic_1164.all;
package disp_timing_pack is
constant H_ACTIVE_VIDEO : integer := 640;
constant H_FRONT_PORCH : integer := 16;
constant H_SYNC_PULSE : integer := 96;
constant H_BACK_PORCH : integer := 48;
constant H_SUM : integer := H_ACTIVE_VIDEO + H_FRONT_PORCH + H_SYNC_PULSE + H_BACK_PORCH;
constant V_ACTIVE_VIDEO : integer := 480;
constant V_FRONT_PORCH : integer := 11;
constant V_SYNC_PULSE : integer := 2;
constant V_BACK_PORCH : integer := 31;
constant V_SUM : integer := V_ACTIVE_VIDEO + V_FRONT_PORCH + V_SYNC_PULSE + V_BACK_PORCH;
constant H_DISPLAY_SIZE : integer := H_ACTIVE_VIDEO/8; -- 横80桁
constant V_DISPLAY_SIZE : integer := V_ACTIVE_VIDEO/8; -- 縦60行
end disp_timing_pack;
-- CharDispCtrlerTest.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
entity CharDispCtrlerTest is
port(
clk : in std_logic;
reset : in std_logic;
-- dvi_reset : in std_logic;
dvi_xclk_p : out std_logic;
dvi_xclk_n : out std_logic;
dvi_reset_b : out std_logic;
dvi_hsync : out std_logic;
dvi_vsync : out std_logic;
dvi_de : out std_logic;
dvi_d : out std_logic_vector(11 downto 0);
dvi_sda : out std_logic;
dvi_scl : out std_logic
);
end CharDispCtrlerTest;
architecture RTL of CharDispCtrlerTest is
...
-- CH7301C へ出力する
dvi_reset_b <= '1';
ODDR_dvi_xclk_p : ODDR generic map(
DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
INIT => '0', -- Initial value for Q port (’1’ or ’0’)
SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
port map(
Q => dvi_xclk_p,
C => clk90,
CE => '1',
D1 => '1',
D2 => '0',
R => reset_node,
S => '0'
);
ODDR_dvi_xclk_n : ODDR generic map(
DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
INIT => '1', -- Initial value for Q port (’1’ or ’0’)
SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
port map(
Q => dvi_xclk_n,
C => clk90,
CE => '1',
D1 => '0',
D2 => '1',
R => reset_node,
S => '0'
);
ODDR_dvi_d0 : ODDR generic map(
DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
INIT => '0', -- Initial value for Q port (’1’ or ’0’)
SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
port map(
Q => dvi_d(0),
C => clk0,
CE => '1',
D1 => VGA_BLUE, -- B[0]
D2 => VGA_GREEN, -- G[4]
R => reset_node,
S => '0'
);
ODDR_dvi_d1 : ODDR generic map(
DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
INIT => '0', -- Initial value for Q port (’1’ or ’0’)
SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
port map(
Q => dvi_d(1),
C => clk0,
CE => '1',
D1 => VGA_BLUE, -- B[1]
D2 =>VGA_GREEN, -- G[5]
R => reset_node,
S => '0'
);
ODDR_dvi_d2 : ODDR generic map(
DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
INIT => '0', -- Initial value for Q port (’1’ or ’0’)
SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
port map(
Q => dvi_d(2),
C => clk0,
CE => '1',
D1 => VGA_BLUE, -- B[2]
D2 => VGA_GREEN, -- G[6]
R => reset_node,
S => '0'
);
ODDR_dvi_d3 : ODDR generic map(
DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
INIT => '0', -- Initial value for Q port (’1’ or ’0’)
SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
port map(
Q => dvi_d(3),
C => clk0,
CE => '1',
D1 => VGA_BLUE, -- B[3]
D2 => VGA_GREEN, -- G[7]
R => reset_node,
S => '0'
);
ODDR_dvi_d4 : ODDR generic map(
DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
INIT => '0', -- Initial value for Q port (’1’ or ’0’)
SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
port map(
Q => dvi_d(4),
C => clk0,
CE => '1',
D1 => VGA_BLUE, -- B[4]
D2 => VGA_RED, -- R[0]
R => reset_node,
S => '0'
);
ODDR_dvi_d5 : ODDR generic map(
DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
INIT => '0', -- Initial value for Q port (’1’ or ’0’)
SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
port map(
Q => dvi_d(5),
C => clk0,
CE => '1',
D1 => VGA_BLUE, -- B[5]
D2 => VGA_RED, -- R[1]
R => reset_node,
S => '0'
);
ODDR_dvi_d6 : ODDR generic map(
DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
INIT => '0', -- Initial value for Q port (’1’ or ’0’)
SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
port map(
Q => dvi_d(6),
C => clk0,
CE => '1',
D1 => VGA_BLUE, -- B[6]
D2 => VGA_RED, -- R[2]
R => reset_node,
S => '0'
);
ODDR_dvi_d7 : ODDR generic map(
DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
INIT => '0', -- Initial value for Q port (’1’ or ’0’)
SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
port map(
Q => dvi_d(7),
C => clk0,
CE => '1',
D1 => VGA_BLUE, -- B[7]
D2 => VGA_RED, -- R[3]
R => reset_node,
S => '0'
);
ODDR_dvi_d8 : ODDR generic map(
DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
INIT => '0', -- Initial value for Q port (’1’ or ’0’)
SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
port map(
Q => dvi_d(8),
C => clk0,
CE => '1',
D1 => VGA_GREEN, -- G[0]
D2 => VGA_RED, -- R[4]
R => reset_node,
S => '0'
);
ODDR_dvi_d9 : ODDR generic map(
DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
INIT => '0', -- Initial value for Q port (’1’ or ’0’)
SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
port map(
Q => dvi_d(9),
C => clk0,
CE => '1',
D1 => VGA_GREEN, -- G[1]
D2 => VGA_RED, -- R[5]
R => reset_node,
S => '0'
);
ODDR_dvi_d10 : ODDR generic map(
DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
INIT => '0', -- Initial value for Q port (’1’ or ’0’)
SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
port map(
Q => dvi_d(10),
C => clk0,
CE => '1',
D1 => VGA_GREEN, -- G[2]
D2 => VGA_RED, -- R[6]
R => reset_node,
S => '0'
);
ODDR_dvi_d11 : ODDR generic map(
DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
INIT => '0', -- Initial value for Q port (’1’ or ’0’)
SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
port map(
Q => dvi_d(11),
C => clk0,
CE => '1',
D1 => VGA_GREEN, -- G[3]
D2 => VGA_RED, -- R[7]
R => reset_node,
S => '0'
);
-- I2C 設定レジスタ設定回路
I2C_setting_inst : SCCB_Reg_Controller port map(
clk => clk0,
reset => reset_node,
SCL => dvi_scl,
SDA => dvi_sda
);
end RTL;
INST "dvi_de" IOB = FORCE;
INST "dvi_hsync" IOB = FORCE;
INST "dvi_vsync" IOB = FORCE;
日 | 月 | 火 | 水 | 木 | 金 | 土 |
---|---|---|---|---|---|---|
- | - | - | - | 1 | 2 | 3 |
4 | 5 | 6 | 7 | 8 | 9 | 10 |
11 | 12 | 13 | 14 | 15 | 16 | 17 |
18 | 19 | 20 | 21 | 22 | 23 | 24 |
25 | 26 | 27 | 28 | 29 | 30 | - |