app_af_cmd[2:0]:(入力) 3ビットのコマンド。000がWriteコマンド、001がReadコマンド。それ以外は不正値。
app_af_addr[30:0]:(入力) 31ビットのアドレス。今回は25ビット幅、26ビット目はChip Select。アドレスの割当はBank + Row + Column address。
app_af_wren:(入力) User Address FIFOへのWrite enable。これが1の時は、app_af_cmdとapp_af_addrが有効。
aff_wdf_data[2*DQ_WIDTH-1:0]:(入力) User Input Data。DDR2 SDRAMのデータ幅の2倍のデータ幅がある。クロックの立ち上がりのデータが下位、クロックの立ち下がりのデータが上位。128ビット幅。
app_wdf_mask_data[2*DM_WIDTH–1:0]:(入力) User Data Mask。DDR2 SDRAMのマスク幅の2倍の幅がある。 クロックの立ち上がりのマスクが下位、クロックの立ち下がりのマスクが上位。16ビット幅。
app_wdf_wren:(入力) User Write FIFOのWrite enable。これが1の時は、aff_wdf_dataとapp_wdf_mask_dataが有効。
app_af_afull:(出力) Address FIFOのAlmost Full。残り12以下の時に1になる。
app_wdf_afull:(出力) User Write FIFOのAlmost Full。残り12以下の時に1になる。
rd_data_valid:(出力) rd_data_fifo_outのデータが有効であることを示す。
rd_data_fifo_out[2*DQ_WIDTH–1:0]:(出力) メモリからReadしたデータ。128ビット幅。
phy_init_done:(出力) DDR2 SDRAMコントローラの初期化とキャリブレーションが終了した。
clk0_tb:(出力) ユーザー回路へのclk0出力
268252100.0 ps INFO: Precharge All
268372100.0 ps INFO: Load Mode 2
268372100.0 ps INFO: Load Mode 2 High Temperature Self Refresh rate = 1X (0C-85C)
268492100.0 ps INFO: Load Mode 3
268612100.0 ps INFO: Load Mode 1
268612100.0 ps INFO: Load Mode 1 DLL Enable = Enabled
268612100.0 ps INFO: Load Mode 1 Output Drive Strength = Full
268612100.0 ps INFO: Load Mode 1 ODT Rtt = Disabled
268612100.0 ps INFO: Load Mode 1 Additive Latency = 0
268612100.0 ps INFO: Load Mode 1 OCD Program = OCD Exit
268612100.0 ps INFO: Load Mode 1 DQS_N Enable = Enabled
268612100.0 ps INFO: Load Mode 1 RDQS Enable = Disabled
268612100.0 ps INFO: Load Mode 1 Output Enable = Enabled
268732100.0 ps INFO: Load Mode 0
268732100.0 ps INFO: Load Mode 0 Burst Length = 4
268732100.0 ps INFO: Load Mode 0 Burst Order = Sequential
268732100.0 ps INFO: Load Mode 0 CAS Latency = 3
268732100.0 ps INFO: Load Mode 0 Test Mode = Normal
268732100.0 ps INFO: Load Mode 0 DLL Reset = Reset DLL
268732100.0 ps INFO: Load Mode 0 Write Recovery = 3
268732100.0 ps INFO: Load Mode 0 Power Down Mode = Fast Exit
268852100.0 ps INFO: Precharge All
268972100.0 ps INFO: Refresh
269092100.0 ps INFO: Refresh
269212100.0 ps INFO: Load Mode 0
269212100.0 ps INFO: Load Mode 0 Burst Length = 4
269212100.0 ps INFO: Load Mode 0 Burst Order = Sequential
269212100.0 ps INFO: Load Mode 0 CAS Latency = 3
269212100.0 ps INFO: Load Mode 0 Test Mode = Normal
269212100.0 ps INFO: Load Mode 0 DLL Reset = Normal
269212100.0 ps INFO: Load Mode 0 Write Recovery = 3
269212100.0 ps INFO: Load Mode 0 Power Down Mode = Fast Exit
269332100.0 ps INFO: Load Mode 1
269332100.0 ps INFO: Load Mode 1 DLL Enable = Enabled
269332100.0 ps INFO: Load Mode 1 Output Drive Strength = Full
269332100.0 ps INFO: Load Mode 1 ODT Rtt = Disabled
269332100.0 ps INFO: Load Mode 1 Additive Latency = 0
269332100.0 ps INFO: Load Mode 1 OCD Program = OCD Default
269332100.0 ps INFO: Load Mode 1 DQS_N Enable = Enabled
269332100.0 ps INFO: Load Mode 1 RDQS Enable = Disabled
269332100.0 ps INFO: Load Mode 1 Output Enable = Enabled
269452100.0 ps INFO: Load Mode 1
269452100.0 ps INFO: Load Mode 1 DLL Enable = Enabled
269452100.0 ps INFO: Load Mode 1 Output Drive Strength = Full
269452100.0 ps INFO: Load Mode 1 ODT Rtt = Disabled
269452100.0 ps INFO: Load Mode 1 Additive Latency = 0
269452100.0 ps INFO: Load Mode 1 OCD Program = OCD Exit
269452100.0 ps INFO: Load Mode 1 DQS_N Enable = Enabled
269452100.0 ps INFO: Load Mode 1 RDQS Enable = Disabled
269452100.0 ps INFO: Load Mode 1 Output Enable = Enabled
269452100.0 ps INFO: Initialization Sequence is complete
clk0:位相0度のクロック
clk90:位相90度のクロック
user_command_register:Write Request(100) やRead Request(110)、NOP(000) などのコマンド。Initialize memory(010)。(clk0の立ち下がりに同期)
user_cmd_ack:MIGからコマンドをうけとれるという返事。リフレッシュなどの用事があってコマンドを受け取れない場合はアサートされない。(clk0の立ち下がりに同期)
user_input_address:アドレス入力。使いにくいことにROW+COLUMN+BANKの順番になっているので、まともに使用するためには、COLUMNとBANKのアドレスを入れ替える必要がありそう。(clk0の立ち下がりに同期)
burst_done:バーストの終了時に4バーストモードは2クロック間、8バーストモードは4クロック間アサートする。(clk0の立ち下がりに同期)
user_input_data:clk90に同期してデータを出力する(Writeのみ)。(clk90の立ち上がりに同期)
user_data_valid:user_output_dataが有効。(Readのみ)(clk90の立ち上がりに同期)
user_output_data:Readしたデータ。(Readのみ)(clk90の立ち上がりに同期)
1.clk0の立ち下がりに同期して、ユーザー回路はWriteコマンドを発行し始める。
2.最低1クロック後にMIGは、clk0の立ち下がりに同期してuser_cmd_ackをアサートし、Writeコマンドを受け付けたことをユーザー回路に知らせる。ただし、リフレッシュ動作中でuser_cmd_ackのアサートが遅れることもある。
3.user_cmd_ackがアサートされた後のclk90の立ち上がりに同期して、ユーザー回路はuser_input_dataにWriteするデータを入力する。user_input_dataはDDR2 SDRAMのデータ幅の2倍幅となっている。4バーストモードならば、2つのデータを入力する必要がある。
4.ユーザー回路が入力するアドレス(row+column+bank address)は、user_cmd_ackがアサートされた後の3クロック間維持する。その後のバーストアドレスは2クロック維持する。(clk0の立ち下がりに同期)
5.write burstを終了させるときに、ユーザー回路はburst_doneをアサートしてMIGに知らせる。4バーストモードの時は2クロック間アサートする。
6.burst_doneのアサート後にWriteコマンドをデアサートする。(NOPコマンドに変更)
7.プリチャージをした後に、MIGはuser_cmd_ackをデアサートする。user_cmd_ackをデアサートされたら、ユーザー回路は次のコマンドを入力することができる。
1.clk0の立ち下がりに同期して、ユーザー回路はReadコマンドを発行し始める。
2.最低1クロック後にMIGは、clk0の立ち下がりに同期してuser_cmd_ackをアサートし、Readコマンドを受け付けたことをユーザー回路に知らせる。ただし、リフレッシュ動作中でuser_cmd_ackのアサートが遅れることもある。
3.ユーザー回路が入力するアドレス(row+column+bank address)は、user_cmd_ackがアサートされた後の3クロック間維持する。その後のバーストアドレスは2クロック維持する。(clk0の立ち下がりに同期)
4.user_output_dataが有効なのは、user_data_validがアサートされた時である。
5.DDR2 SDRAMのReadしたデータがuser_output_dataに出力される。user_output_dataはDDR2 SDRAMのバス幅の2倍の幅がある。DDR2 SDRAMは1クロックで2つのデータを読み書きするが、その2つのデータがuser_output_dataにSDR1クロックで出力される。4バーストモードでは、2つのデータがclk90の立ち上がりに同期して出力される。
6.read burstを終了させるときに、ユーザー回路はburst_doneをアサートしてMIGに知らせる。4バーストモードの時は2クロック間アサートする。
7.burst_doneのアサート後にReadコマンドをデアサートする。(NOPコマンドに変更)
8.プリチャージをした後に、MIGはuser_cmd_ackをデアサートする。user_cmd_ackをデアサートされたら、ユーザー回路は次のコマンドを入力することができる。大体、Readコマンドを発行してからデータが来るまで17クロックかかるようだ。
`define x512Mb
`define sg3
`define x16
restart; run 300us
ODDR2 #(
.DDR_ALIGNMENT("NONE"),
.SRTYPE("ASYNC")
) ODDR2_TRI(
.Q(tri_out),
.C0(clk270),
.C1(clk90),
.CE(tri_ddr_ce_to_io),
.D0(tri_ddr_d0_to_io),
.D1(tri_ddr_d1_to_io),
.R(1'b0),
.S(reset)
);
ODDR2 #(
.DDR_ALIGNMENT("NONE"),
.SRTYPE("SYNC")
) ODDR2_DATA(
.Q(to_io_pad),
.C0(clk270),
.C1(clk90),
.CE(data_ddr_ce_to_io),
.D0(data_ddr_d0_to_io),
.D1(data_ddr_d1_to_io),
.R(1'b0),
.S(reset)
);
IOBUF IOBUF_DQ(
.O(dq_data_from_io),
.IO(io_pad),
.I(to_io_pad),
.T(tri_out)
);
driver - comp.pin "cntrl0_ddr2_dq[0].I", site.pin "AA1.I"
0.464ns - comp.pin "main_00/top0/data_path0/data_read0/fifo_1_data_out[0].BY", site.pin "SLICE_X0Y3.BY"
0.464ns - comp.pin "main_00/top0/data_path0/data_read0/fifo_0_data_out[0].BY", site.pin "SLICE_X0Y2.BY"
driver - comp.pin "ddr2_dq<0>.I", site.pin "H1.I"
0.411ns - comp.pin "ddr2_sdram_cont_inst/read_write_io_inst/dout<16>.BY", site.pin "SLICE_X2Y63.BY"
0.411ns - comp.pin "ddr2_sdram_cont_inst/read_write_io_inst/dout<0>.BY", site.pin "SLICE_X2Y62.BY"
NET "cntrl0_ddr2_ck[0]" LOC = "M1" ; #bank 3
NET "cntrl0_ddr2_ck_n[0]" LOC = "M2" ; #bank 3
NET "cntrl0_ddr2_dm[0]" LOC = "J3" ; #bank 3
NET "cntrl0_ddr2_dm[1]" LOC = "E3" ; #bank 3
NET "cntrl0_ddr2_a[12]" LOC = "Y2" ; #bank 3
NET "cntrl0_ddr2_a[11]" LOC = "V1" ; #bank 3
NET "cntrl0_ddr2_a[10]" LOC = "T3" ; #bank 3
NET "cntrl0_ddr2_a[9]" LOC = "W2" ; #bank 3
NET "cntrl0_ddr2_a[8]" LOC = "W1" ; #bank 3
NET "cntrl0_ddr2_a[7]" LOC = "Y1" ; #bank 3
NET "cntrl0_ddr2_a[6]" LOC = "U1" ; #bank 3
NET "cntrl0_ddr2_a[5]" LOC = "U4" ; #bank 3
NET "cntrl0_ddr2_a[4]" LOC = "U2" ; #bank 3
NET "cntrl0_ddr2_a[3]" LOC = "U3" ; #bank 3
NET "cntrl0_ddr2_a[2]" LOC = "R1" ; #bank 3
NET "cntrl0_ddr2_a[1]" LOC = "T4" ; #bank 3
NET "cntrl0_ddr2_a[0]" LOC = "R2" ; #bank 3
NET "cntrl0_ddr2_ba[1]" LOC = "R3" ; #bank 3
NET "cntrl0_ddr2_ba[0]" LOC = "P3" ; #bank 3
NET "cntrl0_ddr2_cke" LOC = "N3" ; #bank 3
NET "cntrl0_ddr2_cs_n" LOC = "M5" ; #bank 3
NET "cntrl0_ddr2_ras_n" LOC = "M3" ; #bank 3
NET "cntrl0_ddr2_cas_n" LOC = "M4" ; #bank 3
NET "cntrl0_ddr2_we_n" LOC = "N4" ; #bank 3
NET "cntrl0_ddr2_odt" LOC = "P1" ; #bank 3
NET "cntrl0_ddr2_dq[15]" LOC = "F3"; #bank 3
NET "cntrl0_ddr2_dq[14]" LOC = "G3"; #bank 3
NET "cntrl0_ddr2_dq[13]" LOC = "F1"; #bank 3
NET "cntrl0_ddr2_dq[12]" LOC = "H5"; #bank 3
NET "cntrl0_ddr2_dq[11]" LOC = "H6"; #bank 3
NET "cntrl0_ddr2_dq[10]" LOC = "G1"; #bank 3
NET "cntrl0_ddr2_dq[9]" LOC = "G4"; #bank 3
NET "cntrl0_ddr2_dq[8]" LOC = "F2"; #bank 3
NET "cntrl0_ddr2_dq[7]" LOC = "H2"; #bank 3
NET "cntrl0_ddr2_dq[6]" LOC = "K4"; #bank 3
NET "cntrl0_ddr2_dq[5]" LOC = "L1"; #bank 3
NET "cntrl0_ddr2_dq[4]" LOC = "L5"; #bank 3
NET "cntrl0_ddr2_dq[3]" LOC = "L3"; #bank 3
NET "cntrl0_ddr2_dq[2]" LOC = "K1"; #bank 3
NET "cntrl0_ddr2_dq[1]" LOC = "K5"; #bank 3
NET "cntrl0_ddr2_dq[0]" LOC = "H1"; #bank 3
NET "cntrl0_ddr2_dqs[1]" LOC = "K6"; #bank 3
NET "cntrl0_ddr2_dqs_n[1]" LOC = "J5"; #bank 3
NET "cntrl0_ddr2_dqs[0]" LOC = "K3"; #bank 3
NET "cntrl0_ddr2_dqs_n[0]" LOC = "K2"; #bank 3
NET "cntrl0_rst_dqs_div_in" LOC = "H4"; #bank 3
NET "cntrl0_rst_dqs_div_out" LOC = "H3"; #bank 3
NET "reset_in_n" LOC = "T15" ; #bank 3
Verification Report
Generated by MIG Version 3.6.1 on 金 5 13 05:35:49 2011
Reading design libraries of xc3s700a-fg484... successful !
/*******************************************************/
/* Controller 0
/*******************************************************/
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/five-slice_x3y27" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/four-slice_x2y26" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/one-slice_x2y27" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/six-slice_x3y26" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/three-slice_x2y26" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/two-slice_x2y27" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/five-slice_x1y27" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/four-slice_x0y26" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/one-slice_x0y27" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/six-slice_x1y26" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/three-slice_x0y26" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/two-slice_x0y27" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/five-g" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/four-f" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/one-f" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/six-g" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/three-g" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/two-g" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/five-g" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/four-f" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/one-f" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/six-g" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/three-g" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/two-g" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_0_wr_addr_inst/bit0-slice_x1y22" for Fifo write address or write enable of dqs[1] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_0_wr_addr_inst/bit1-slice_x1y22" for Fifo write address or write enable of dqs[1] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_0_wr_addr_inst/bit2-slice_x1y23" for Fifo write address or write enable of dqs[1] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_0_wr_addr_inst/bit3-slice_x1y23" for Fifo write address or write enable of dqs[1] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_1_wr_addr_inst/bit0-slice_x3y22" for Fifo write address or write enable of dqs[1] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_1_wr_addr_inst/bit1-slice_x3y22" for Fifo write address or write enable of dqs[1] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_1_wr_addr_inst/bit2-slice_x3y23" for Fifo write address or write enable of dqs[1] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_1_wr_addr_inst/bit3-slice_x3y23" for Fifo write address or write enable of dqs[1] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_en[1].fifo_0_wr_en_inst-slice_x1y25" for Fifo write address or write enable of dqs[1] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_en[1].fifo_1_wr_en_inst-slice_x3y25" for Fifo write address or write enable of dqs[1] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit7-slice_x2y30" allocated for dq[15] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit7-slice_x2y31" allocated for dq[15] is invalid.
ERROR: Trying to allocate dq[15] to a wrong PAD in an IO tile in the bank 3. All the even dq
signals (e.g. dq[0],dq[2]) should be allocated to the top pad and odd dq signals to
the bottom pad in an IO tile in the bank 3 for the selected Spartan device. Use FPGA
editor to know the PAD info of any pin.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit6-slice_x0y30" allocated for dq[14] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit6-slice_x0y31" allocated for dq[14] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit5-slice_x2y28" allocated for dq[13] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit5-slice_x2y29" allocated for dq[13] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit4-slice_x0y28" allocated for dq[12] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit4-slice_x0y29" allocated for dq[12] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit3-slice_x2y22" allocated for dq[11] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit3-slice_x2y23" allocated for dq[11] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit2-slice_x0y20" allocated for dq[10] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit2-slice_x0y21" allocated for dq[10] is invalid.
ERROR: Trying to allocate dq[10] to a wrong PAD in an IO tile in the bank 3. All the even dq
signals (e.g. dq[0],dq[2]) should be allocated to the top pad and odd dq signals to
the bottom pad in an IO tile in the bank 3 for the selected Spartan device. Use FPGA
editor to know the PAD info of any pin.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit1-slice_x2y20" allocated for dq[9] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit1-slice_x2y21" allocated for dq[9] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit0-slice_x0y18" allocated for dq[8] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit0-slice_x0y19" allocated for dq[8] is invalid.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/five-slice_x3y7" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/four-slice_x2y6" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/one-slice_x2y7" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/six-slice_x3y6" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/three-slice_x2y6" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/two-slice_x2y7" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/five-slice_x1y7" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/four-slice_x0y6" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/one-slice_x0y7" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/six-slice_x1y6" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/three-slice_x0y6" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/two-slice_x0y7" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/five-g" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/four-f" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/one-f" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/six-g" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/three-g" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/two-g" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/five-g" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/four-f" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/one-f" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/six-g" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/three-g" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/two-g" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_0_wr_addr_inst/bit0-slice_x1y2" for Fifo write address or write enable of dqs[0] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_0_wr_addr_inst/bit1-slice_x1y2" for Fifo write address or write enable of dqs[0] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_0_wr_addr_inst/bit2-slice_x1y3" for Fifo write address or write enable of dqs[0] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_0_wr_addr_inst/bit3-slice_x1y3" for Fifo write address or write enable of dqs[0] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_1_wr_addr_inst/bit0-slice_x3y2" for Fifo write address or write enable of dqs[0] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_1_wr_addr_inst/bit1-slice_x3y2" for Fifo write address or write enable of dqs[0] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_1_wr_addr_inst/bit2-slice_x3y3" for Fifo write address or write enable of dqs[0] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_1_wr_addr_inst/bit3-slice_x3y3" for Fifo write address or write enable of dqs[0] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_en[0].fifo_0_wr_en_inst-slice_x1y5" for Fifo write address or write enable of dqs[0] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_en[0].fifo_1_wr_en_inst-slice_x3y5" for Fifo write address or write enable of dqs[0] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit7-slice_x2y12" allocated for dq[7] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit7-slice_x2y13" allocated for dq[7] is invalid.
ERROR: Trying to allocate dq[7] to a wrong PAD in an IO tile in the bank 3. All the even dq
signals (e.g. dq[0],dq[2]) should be allocated to the top pad and odd dq signals to
the bottom pad in an IO tile in the bank 3 for the selected Spartan device. Use FPGA
editor to know the PAD info of any pin.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit6-slice_x0y12" allocated for dq[6] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit6-slice_x0y13" allocated for dq[6] is invalid.
ERROR: Trying to allocate dq[6] to a wrong PAD in an IO tile in the bank 3. All the even dq
signals (e.g. dq[0],dq[2]) should be allocated to the top pad and odd dq signals to
the bottom pad in an IO tile in the bank 3 for the selected Spartan device. Use FPGA
editor to know the PAD info of any pin.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit5-slice_x2y10" allocated for dq[5] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit5-slice_x2y11" allocated for dq[5] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit4-slice_x0y10" allocated for dq[4] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit4-slice_x0y11" allocated for dq[4] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit3-slice_x2y4" allocated for dq[3] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit3-slice_x2y5" allocated for dq[3] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit2-slice_x0y4" allocated for dq[2] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit2-slice_x0y5" allocated for dq[2] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit1-slice_x2y2" allocated for dq[1] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit1-slice_x2y3" allocated for dq[1] is invalid.
ERROR: Trying to allocate dq[1] to a wrong PAD in an IO tile in the bank 3. All the even dq
signals (e.g. dq[0],dq[2]) should be allocated to the top pad and odd dq signals to
the bottom pad in an IO tile in the bank 3 for the selected Spartan device. Use FPGA
editor to know the PAD info of any pin.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit0-slice_x0y2" allocated for dq[0] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit0-slice_x0y3" allocated for dq[0] is invalid.
ERROR: Trying to allocate dq[0] to a wrong PAD in an IO tile in the bank 3. All the even dq
signals (e.g. dq[0],dq[2]) should be allocated to the top pad and odd dq signals to
the bottom pad in an IO tile in the bank 3 for the selected Spartan device. Use FPGA
editor to know the PAD info of any pin.
WARNING: The signal reset_in_n is missing or allocated to invalid I/O.
WARNING:
Slice location constraint for delayed rst_dqs_div_out signal is not correct.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/five-slice_x1y14" for delayed rst_dqs_div_in signal is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/four-slice_x1y14" for delayed rst_dqs_div_in signal is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/one-slice_x0y15" for delayed rst_dqs_div_in signal is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/six-slice_x1y15" for delayed rst_dqs_div_in signal is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/three-slice_x0y15" for delayed rst_dqs_div_in signal is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/two-slice_x0y14" for delayed rst_dqs_div_in signal is invalid.
Verification completed. Found the following warnings.
Number of warnings in the input UCF = 108.
Verification completed. Found the following errors.
Number of errors in the input UCF = 6.
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4 | 5 | 6 | 7 | 8 | 9 | 10 |
11 | 12 | 13 | 14 | 15 | 16 | 17 |
18 | 19 | 20 | 21 | 22 | 23 | 24 |
25 | 26 | 27 | 28 | 29 | 30 | - |