ERROR:Place:1413 - The following IOBs have an IO Standard that requires VCCAUX =
3.300v. This is incompatible with the device's current setting of VCCAUX =
2.500v. By default, VCCAUX = 2.5v but it can be specified to a different
value in your user constraints file (UCF). Please refer to the Spartan6 FPGA
SelectIO Resources User's Guide for more information on VCCAUX and the
requirements of each IO Standard.
IO Standard: TMDS_33
List of IOB's:
TMDS_RX_0_N
TMDS_RX_0_P
TMDS_RX_1_N
TMDS_RX_1_P
TMDS_RX_2_N
TMDS_RX_2_P
TMDS_RX_CLK_N
TMDS_RX_CLK_P
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.
NET "TMDS_RX_0_P" IOSTANDARD = TMDS_33;
NET "TMDS_RX_1_P" IOSTANDARD = TMDS_33;
NET "TMDS_RX_2_P" IOSTANDARD = TMDS_33;
NET "TMDS_RX_SCL" IOSTANDARD = LVCMOS33;
NET "TMDS_RX_SDA" IOSTANDARD = LVCMOS33;
NET "TMDS_TX_0_P" IOSTANDARD = TML_33;
NET "TMDS_TX_1_P" IOSTANDARD = TML_33;
NET "TMDS_TX_2_P" IOSTANDARD = TML_33;
NET "TMDS_TX_CLK_P" IOSTANDARD = TML_33;
NET "CLK100M" IOSTANDARD = LVCMOS33;
NET "RESET" IOSTANDARD = LVCMOS33;
NET "TMDS_RX_CLK_P" IOSTANDARD = TMDS_33;
CONFIG VCCAUX = 3.3;
Command Line: elfcheck -hw
H:/HDL/FndtnISEWork/Spartan6/Atlys/Atlys_XPS_CamDisp/SDK/SDK_Export/Atlys_XPS_Ca
mDisp_hw_platform/system.xml -mode bootload -mem BRAM -pe microblaze_0
H:/HDL/FndtnISEWork/Spartan6/Atlys/Atlys_XPS_CamDisp/SDK/SDK_Export/axi_timer_te
st/Debug/axi_timer_test.elf
ELF file :
H:/HDL/FndtnISEWork/Spartan6/Atlys/Atlys_XPS_CamDisp/SDK/SDK_Export/axi_timer_te
st/Debug/axi_timer_test.elf
ERROR:EDK:3165 - elfcheck failed!
The following sections did not fit into Processor BRAM memory:
Section .jcr (0xC0000944 - 0xC0000947)
Section .eh_frame (0xC0000940 - 0xC0000943)
Section .data (0xC0000818 - 0xC000093F)
Section .rodata (0xC000080C - 0xC0000811)
Section .dtors (0xC0000804 - 0xC000080B)
Section .ctors (0xC00007FC - 0xC0000803)
Section .fini (0xC00007E0 - 0xC00007FB)
Section .init (0xC00007A4 - 0xC00007DF)
Section .text (0xC0000000 - 0xC00007A3)
Try using the linker script generation tools to generate an ELF that maps
correctly to your hardware design.
Programming the FPGA failed due to errors from elfcheck
Process STDIO not connected to console.
If you'd like to see UART output in this console, please modify STDIO settings in the Run/Debug configuration.
/* * axi_timer_test.c * * Created on: 2012/01/02 * Author: Masaaki */
#include "xbasic_types.h"
#include "xio.h"
#include "mb_interface.h"
#include "xparameters.h"
// MICROBLAZE_INTC define
#define MICROBLAZE_0_INTC_ISR XPAR_MICROBLAZE_0_INTC_BASEADDR // Interrupt Status Register
#define MICROBLAZE_0_INTC_IPR XPAR_MICROBLAZE_0_INTC_BASEADDR+0x4 // Interrupt Pending Register
#define MICROBLAZE_0_INTC_IER XPAR_MICROBLAZE_0_INTC_BASEADDR+0x8 // Interrupt Enable Register
#define MICROBLAZE_0_INTC_IAR XPAR_MICROBLAZE_0_INTC_BASEADDR+0xC // Interrupt Acknowledge Register
#define MICROBLAZE_0_INTC_SIE XPAR_MICROBLAZE_0_INTC_BASEADDR+0x10 // Set Interrupt Enable Bits
#define MICROBLAZE_0_INTC_CIE XPAR_MICROBLAZE_0_INTC_BASEADDR+0x14 // Clear Interrupt Enable Bits
#define MICROBLAZE_0_INTC_IVR XPAR_MICROBLAZE_0_INTC_BASEADDR+0x18 // Interrupt Vector Register
#define MICROBLAZE_0_INTC_MER XPAR_MICROBLAZE_0_INTC_BASEADDR+0x1C // Master Enable Register
// LED 8bits
#define XPAR_LEDS_8BITS_DATA XPAR_LEDS_8BITS_BASEADDR
#define XPAR_LEDS_8BITS_TRI XPAR_LEDS_8BITS_BASEADDR+0x4
// AXI_TIMER define
#define AXI_TIMER_0_TCSR0 XPAR_AXI_TIMER_0_BASEADDR // Control/Status Register 0
#define AXI_TIMER_0_TLR0 XPAR_AXI_TIMER_0_BASEADDR+0x4 // Load Register 0
#define AXI_TIMER_0_TCR0 XPAR_AXI_TIMER_0_BASEADDR+0x8 // Timer/Counter Register 0
#define AXI_TIMER_0_TCSR1 XPAR_AXI_TIMER_0_BASEADDR+0x10 // Control/Status Register 1
#define AXI_TIMER_0_TLR1 XPAR_AXI_TIMER_0_BASEADDR+0x14 // Load Register 1
#define AXI_TIMER_0_TCR1 XPAR_AXI_TIMER_0_BASEADDR+0x18 // Timer/Counter Register 1
#define ENABLE_ALL_TIMERS (0x1<<10)
#define ENABLE_PULSE_WIDTH_MODULATION (0x1<<9)
#define TIMER_INTERRUPT (0x1<<8)
#define ENABLE_TIMER (0x1<<7)
#define ENABLE_INTERRUPT (0x1<<6)
#define LOAD_TIMER (0x1<<5)
#define AUTO_RELOAD_HOLD_TIMER (0x1<<4)
#define ENABLE_EXT_CAPTURE_TRIG (0x1<<3)
#define ENABLE_EXT_GENERATE_SIG (0x1<<2)
#define DOWN_UP_COUNT_TIMER (0x1<<1)
#define TIMER_MODE_CAP_GENE (0x1)
int interrupt = 0;
void axi_intc_init() {
*(volatile unsigned int *)(MICROBLAZE_0_INTC_IER) = 0x1; // int0 enable
*(volatile unsigned int *)(MICROBLAZE_0_INTC_MER) = 0x3; // IRQ Enable
}
void axi_timer_init(){
*(volatile unsigned int *)(AXI_TIMER_0_TLR0) = 100000000; // 100MHzで1秒
*(volatile unsigned int *)(AXI_TIMER_0_TCSR0) = ENABLE_ALL_TIMERS | LOAD_TIMER; // TLR0へロード
*(volatile unsigned int *)(AXI_TIMER_0_TCSR0) = ENABLE_ALL_TIMERS | ENABLE_TIMER | ENABLE_INTERRUPT | DOWN_UP_COUNT_TIMER; // GenerateモードでDWONカウント、割り込みあり
}
void timer_int_handler(void * arg) {
interrupt = 1;
}
int main()
{
unsigned int data;
*(volatile unsigned int *)(XPAR_LEDS_8BITS_TRI) = 0; // 出力設定
*(volatile unsigned int *)(XPAR_LEDS_8BITS_DATA) = 1;
axi_timer_init(); // axi_timerの初期化
axi_intc_init(); // axi_intcの初期化
// 割り込みハンドラ登録、割り込み許可
microblaze_register_handler(timer_int_handler, (void *) 0);
microblaze_enable_interrupts();
for(data=0; data>=0; data++){
*(volatile unsigned int *)(XPAR_LEDS_8BITS_DATA) = data;
// axi_timter割り込み待ち
interrupt = 0;
while(interrupt==0);
*(volatile unsigned int *)(AXI_TIMER_0_TCSR0) = ENABLE_ALL_TIMERS | ENABLE_TIMER | ENABLE_INTERRUPT | DOWN_UP_COUNT_TIMER | TIMER_INTERRUPT; // 割り込みクリア
*(volatile unsigned int *)(MICROBLAZE_0_INTC_IAR) = 0x1; // int0 clear
*(volatile unsigned int *)(AXI_TIMER_0_TLR0) = 100000000; // 1秒 1000,000,000ns/10ns = 100,000,000
*(volatile unsigned int *)(AXI_TIMER_0_TCSR0) = ENABLE_ALL_TIMERS | LOAD_TIMER; // TLR0へロード、割り込みクリア
*(volatile unsigned int *)(AXI_TIMER_0_TCSR0) = ENABLE_ALL_TIMERS | ENABLE_TIMER | ENABLE_INTERRUPT | DOWN_UP_COUNT_TIMER; // GenerateモードでDWONカウント、割り込みあり
}
return 0;
}
XMD% mwr 0xC0000000 0x56789ABC
XMD% mrd 0xC0000000
C0000000: 56789ABC
XMD% mwr 0xC0000008 0x55667788
XMD% mrd 0xC0000008
C0000008: 55667788
Release 13.3 Map O.76xd (nt)
Xilinx Mapping Report File for Design 'system'
Design Information
------------------
Command Line : map -o system_map.ncd -w -pr b -ol high -timing -detail
system.ngd system.pcf
Target Device : xc6slx45
Target Package : csg324
Target Speed : -2
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : SAT 31 DEC 18:42:38 2011
Design Summary
--------------
Number of errors: 0
Number of warnings: 28
Slice Logic Utilization:
Number of Slice Registers: 3,484 out of 54,576 6%
Number used as Flip Flops: 3,475
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 9
Number of Slice LUTs: 4,149 out of 27,288 15%
Number used as logic: 3,837 out of 27,288 14%
Number using O6 output only: 2,903
Number using O5 output only: 104
Number using O5 and O6: 830
Number used as ROM: 0
Number used as Memory: 236 out of 6,408 3%
Number used as Dual Port RAM: 96
Number using O6 output only: 4
Number using O5 output only: 1
Number using O5 and O6: 91
Number used as Single Port RAM: 4
Number using O6 output only: 4
Number using O5 output only: 0
Number using O5 and O6: 0
Number used as Shift Register: 136
Number using O6 output only: 43
Number using O5 output only: 1
Number using O5 and O6: 92
Number used exclusively as route-thrus: 76
Number with same-slice register load: 58
Number with same-slice carry load: 12
Number with other load: 6
Slice Logic Distribution:
Number of occupied Slices: 1,800 out of 6,822 26%
Nummber of MUXCYs used: 652 out of 13,644 4%
Number of LUT Flip Flop pairs used: 5,065
Number with an unused Flip Flop: 1,860 out of 5,065 36%
Number with an unused LUT: 916 out of 5,065 18%
Number of fully used LUT-FF pairs: 2,289 out of 5,065 45%
Number of unique control sets: 278
Number of slice register sites lost
to control set restrictions: 1,082 out of 54,576 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 89 out of 218 40%
Number of LOCed IOBs: 89 out of 89 100%
IOB Flip Flops: 20
Specific Feature Utilization:
Number of RAMB16BWERs: 20 out of 116 17%
Number of RAMB8BWERs: 0 out of 232 0%
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
Number used as BUFIO2s: 1
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 2 out of 16 12%
Number used as BUFGs: 2
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 8 0%
Number of ILOGIC2/ISERDES2s: 12 out of 376 3%
Number used as ILOGIC2s: 12
Number used as ISERDES2s: 0
Number of IODELAY2/IODRP2/IODRP2_MCBs: 24 out of 376 6%
Number used as IODELAY2s: 0
Number used as IODRP2s: 2
Number used as IODRP2_MCBs: 22
Number of OLOGIC2/OSERDES2s: 52 out of 376 13%
Number used as OLOGIC2s: 7
Number used as OSERDES2s: 45
Number of BSCANs: 1 out of 4 25%
Number of BUFHs: 0 out of 256 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 1 out of 4 25%
Number of DSP48A1s: 3 out of 58 5%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 1 out of 2 50%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 1 out of 4 25%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.95
| 日 | 月 | 火 | 水 | 木 | 金 | 土 |
|---|---|---|---|---|---|---|
| - | - | - | - | 1 | 2 | 3 |
| 4 | 5 | 6 | 7 | 8 | 9 | 10 |
| 11 | 12 | 13 | 14 | 15 | 16 | 17 |
| 18 | 19 | 20 | 21 | 22 | 23 | 24 |
| 25 | 26 | 27 | 28 | 29 | 30 | - |