type STATE is (idle, active, holdoff);
type STATE2 is (idle2, active2);
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity block_check is
Port ( reset : in STD_LOGIC;
clk : in STD_LOGIC;
in_sig1 : in STD_LOGIC;
in_sig2 : in STD_LOGIC;
pulse : out STD_LOGIC;
active_sig : out STD_LOGIC);
end block_check;
architecture RTL of block_check is
begin
STATE_MACHINE1 : block
type STATE is (idle, active, holdoff);
signal c_state, n_state : STATE;
begin
process(reset, clk) begin
if reset='1' then
c_state <= idle;
elsif clk'event and clk='1' then
c_state <= n_state;
end if;
end process;
process(c_state, in_sig1) begin
case c_state is
when idle =>
pulse <= '0';
if in_sig1='1' then
n_state <= active;
else
n_state <= idle;
end if;
when active =>
pulse <= '1';
n_state <= holdoff;
when holdoff =>
pulse <= '0';
if in_sig1='0' then
n_state <= idle;
else
n_state <= holdoff;
end if;
end case;
end process;
end block STATE_MACHINE1;
STATE_MACHINE2 : block
type STATE is (idle, active);
signal c_state, n_state : STATE;
begin
process(reset, clk) begin
if reset='1' then
c_state <= idle;
elsif clk'event and clk='1' then
c_state <= n_state;
end if;
end process;
process(c_state, in_sig2) begin
case c_state is
when idle =>
active_sig <= '0';
if in_sig2='1' then
n_state <= active;
else
n_state <= idle;
end if;
when active =>
active_sig <= '1';
if in_sig2='1' then
n_state <= idle;
else
n_state <= active;
end if;
end case;
end process;
end block STATE_MACHINE2;
end RTL;
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