do setup_sim.do
# h:/altera/91/quartus//sopc_builder
# h:/altera/91/quartus//bin/perl
# Sopc_Builder Directory: h:/altera/91/quartus//sopc_builder
# @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
# @@
# @@ setup_sim.do
# @@
# @@ Defined aliases:
# @@
# @@ s -- Load all design (HDL) files.
# @@ re-vlog/re-vcom and re-vsim the design.
# @@
# @@ c -- Re-compile memory contents.
# @@ Builds C- and assembly-language programs
# @@ (and associated simulation data-files
# @@ such as UART simulation strings) for
# @@ refreshing memory contents.
# @@ Does NOT re-generate hardware (HDL) files
# @@ ONLY WORKS WITH LEGACY SDK (Not the Nios IDE)
# @@
# @@ w -- Sets-up waveforms for this design
# @@ Each SOPC-Builder component may have
# @@ signals 'marked' for display during
# @@ simulation. This command opens a wave-
# @@ window containing all such signals.
# @@
# @@ l -- Sets-up list waveforms for this design
# @@ Each SOPC-Builder component may have
# @@ signals 'marked' for listing during
# @@ simulation. This command opens a list-
# @@ window containing all such signals.
# @@
# @@ h -- print this message
# @@
# @@
s
# Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
# -- Compiling module burstcount_fifo_for_avalon_bfm_burst_0_upstream_module
# -- Compiling module rdv_fifo_for_mm_master_bfm_0_m0_to_avalon_bfm_burst_0_upstream_module
# -- Compiling module avalon_bfm_burst_0_upstream_arbitrator
# -- Compiling module avalon_bfm_burst_0_downstream_arbitrator
# -- Compiling module mm_master_bfm_0_m0_arbitrator
# -- Compiling module onchip_memory2_0_s1_arbitrator
# -- Compiling module avalon_bfm_reset_clk_0_domain_synch_module
# -- Compiling module avalon_bfm
# -- Compiling module lcell
# -- Compiling module ALTERA_MF_MEMORY_INITIALIZATION
# -- Compiling module ALTERA_MF_HINT_EVALUATION
# -- Compiling module ALTERA_DEVICE_FAMILIES
# -- Compiling module dffp
# -- Compiling module pll_iobuf
# -- Compiling module stx_m_cntr
# -- Compiling module stx_n_cntr
# -- Compiling module stx_scale_cntr
# -- Compiling module MF_pll_reg
# -- Compiling module MF_stratix_pll
# -- Compiling module arm_m_cntr
# -- Compiling module arm_n_cntr
# -- Compiling module arm_scale_cntr
# -- Compiling module MF_stratixii_pll
# -- Compiling module ttn_m_cntr
# -- Compiling module ttn_n_cntr
# -- Compiling module ttn_scale_cntr
# -- Compiling module MF_stratixiii_pll
# -- Compiling module cda_m_cntr
# -- Compiling module cda_n_cntr
# -- Compiling module cda_scale_cntr
# -- Compiling module MF_cycloneiii_pll
# -- Compiling module MF_cycloneiiigl_m_cntr
# -- Compiling module MF_cycloneiiigl_n_cntr
# -- Compiling module MF_cycloneiiigl_scale_cntr
# -- Compiling module cycloneiiigl_post_divider
# -- Compiling module MF_cycloneiiigl_pll
# -- Compiling module altpll
# -- Compiling module altlvds_rx
# -- Compiling module stratix_lvds_rx
# -- Compiling module stratixgx_dpa_lvds_rx
# -- Compiling module stratixii_lvds_rx
# -- Compiling module flexible_lvds_rx
# -- Compiling module stratixiii_lvds_rx
# -- Compiling module stratixiii_lvds_rx_channel
# -- Compiling module stratixiii_lvds_rx_dpa
# -- Compiling module altlvds_tx
# -- Compiling module stratix_tx_outclk
# -- Compiling module stratixii_tx_outclk
# -- Compiling module flexible_lvds_tx
# -- Compiling module dcfifo_dffpipe
# -- Compiling module dcfifo_fefifo
# -- Compiling module dcfifo_async
# -- Compiling module dcfifo_sync
# -- Compiling module dcfifo_low_latency
# -- Compiling module dcfifo_mixed_widths
# -- Compiling module dcfifo
# -- Compiling module altaccumulate
# -- Compiling module altmult_accum
# -- Compiling module altmult_add
# -- Compiling module altfp_mult
# -- Compiling module altsqrt
# -- Compiling module altclklock
# -- Compiling module altddio_in
# -- Compiling module altddio_out
# -- Compiling module altddio_bidir
# -- Compiling module altdpram
# -- Compiling module altsyncram
# -- Compiling module alt3pram
# -- Compiling module parallel_add
# -- Compiling module scfifo
# -- Compiling module altshift_taps
# -- Compiling module a_graycounter
# -- Compiling module altsquare
# -- Compiling module altera_std_synchronizer
# -- Compiling module altera_std_synchronizer_bundle
# -- Compiling module alt_cal
# -- Compiling module alt_aeq_s4
# -- Compiling module alt_eyemon
# -- Compiling module alt_dfe
# -- Compiling module signal_gen
# -- Compiling module jtag_tap_controller
# -- Compiling module dummy_hub
# -- Compiling module sld_virtual_jtag
# -- Compiling module sld_signaltap
# -- Compiling module altstratixii_oct
# -- Compiling module altparallel_flash_loader
# -- Compiling module altserial_flash_loader
# -- Compiling module altsource_probe
# -- Compiling module LPM_MEMORY_INITIALIZATION
# -- Compiling module LPM_HINT_EVALUATION
# -- Compiling module LPM_DEVICE_FAMILIES
# -- Compiling module lpm_constant
# -- Compiling module lpm_inv
# -- Compiling module lpm_and
# -- Compiling module lpm_or
# -- Compiling module lpm_xor
# -- Compiling module lpm_bustri
# -- Compiling module lpm_mux
# -- Compiling module lpm_decode
# -- Compiling module lpm_clshift
# -- Compiling module lpm_add_sub
# -- Compiling module lpm_compare
# -- Compiling module lpm_mult
# -- Compiling module lpm_divide
# -- Compiling module lpm_abs
# -- Compiling module lpm_counter
# -- Compiling module lpm_latch
# -- Compiling module lpm_ff
# -- Compiling module lpm_shiftreg
# -- Compiling module lpm_ram_dq
# -- Compiling module lpm_ram_dp
# -- Compiling module lpm_ram_io
# -- Compiling module lpm_rom
# -- Compiling module lpm_fifo
# -- Compiling module lpm_fifo_dc_dffpipe
# -- Compiling module lpm_fifo_dc_fefifo
# -- Compiling module lpm_fifo_dc_async
# -- Compiling module lpm_fifo_dc
# -- Compiling module lpm_inpad
# -- Compiling module lpm_outpad
# -- Compiling module lpm_bipad
# -- Compiling module oper_add
# -- Compiling module oper_addsub
# -- Compiling module mux21
# -- Compiling module io_buf_tri
# -- Compiling module io_buf_opdrn
# -- Compiling module oper_mult
# -- Compiling module tri_bus
# -- Compiling module oper_div
# -- Compiling module oper_mod
# -- Compiling module oper_left_shift
# -- Compiling module oper_right_shift
# -- Compiling module oper_rotate_left
# -- Compiling module oper_rotate_right
# -- Compiling module oper_less_than
# -- Compiling module oper_mux
# -- Compiling module oper_selector
# -- Compiling module oper_decoder
# -- Compiling module oper_bus_mux
# -- Compiling module oper_latch
# -- Compiling package verbosity_pkg
# -- Compiling package avalon_mm_pkg
# -- Importing package verbosity_pkg
# -- Compiling module altera_avalon_mm_master_bfm
# -- Importing package verbosity_pkg
# -- Importing package avalon_mm_pkg
# -- Compiling module mm_master_bfm_0
# -- Compiling module avalon_bfm_burst_0
# -- Compiling module onchip_memory2_0
# -- Compiling module test_bench
# -- Compiling module tb_prog
# -- Importing package avalon_mm_pkg
# -- Importing package verbosity_pkg
#
# Top level modules:
# lcell
# altpll
# altlvds_rx
# altlvds_tx
# dcfifo
# altaccumulate
# altmult_accum
# altmult_add
# altfp_mult
# altsqrt
# altclklock
# altddio_bidir
# altdpram
# alt3pram
# parallel_add
# scfifo
# altshift_taps
# a_graycounter
# altsquare
# altera_std_synchronizer_bundle
# alt_cal
# alt_aeq_s4
# alt_eyemon
# alt_dfe
# sld_virtual_jtag
# sld_signaltap
# altstratixii_oct
# altparallel_flash_loader
# altserial_flash_loader
# altsource_probe
# lpm_constant
# lpm_inv
# lpm_and
# lpm_or
# lpm_xor
# lpm_bustri
# lpm_compare
# lpm_abs
# lpm_counter
# lpm_latch
# lpm_ff
# lpm_shiftreg
# lpm_ram_dq
# lpm_ram_dp
# lpm_ram_io
# lpm_rom
# lpm_fifo
# lpm_fifo_dc
# lpm_inpad
# lpm_outpad
# lpm_bipad
# oper_add
# oper_addsub
# mux21
# io_buf_tri
# io_buf_opdrn
# oper_mult
# tri_bus
# oper_div
# oper_mod
# oper_left_shift
# oper_right_shift
# oper_rotate_left
# oper_rotate_right
# oper_less_than
# oper_mux
# oper_selector
# oper_decoder
# oper_bus_mux
# oper_latch
# test_bench
# tb_prog
# vsim +nowarnTFMPC -L lpm_ver -L sgate_ver -L altera_mf_ver -L altgxb_ver -L stratixiigx_hssi_ver -L stratixgx_ver -L stratixgx_gxb_ver -L stratixiigx -L altera_ver -L stratixiii_ver -L stratixii_ver -L cycloneii_ver -L cycloneiii_ver -L stratixiv_hssi_ver -L arriaii_ver -L arriaii_pcie_hip_ver -L arriaii_hssi_ver -L stratixiv_pcie_hip_ver -L cycloneiv_pcie_hip_ver -L cycloneiv_hssi_ver -L hardcopyiv_pcie_hip_ver -L hardcopyiv_hssi_ver -t ps -sv_root prog -sv_lib dpi_main test_bench tb_prog
# (vsim-3763) SystemVerilog DPI cannot access file 'prog\dpi_main.dll'
# No such file or directory. (errno = ENOENT)
# Use the -help option for complete vsim usage.
# Error loading design
vsim -c -dpiexportobj prog/exportobj.obj test_bench tb_prog
gcc -c dpi_main.c
gcc -shared -o dpi_main.dll dpi_main.o exportobj.obj /c/altera/91/modelsim_ase/win32aloem/mtipli.dll
import "DPI-C" context task dpi_main();
export "DPI-C" task bfm_write32;
export "DPI-C" task bfm_read32;
export "DPI-C" task bfm_write16;
export "DPI-C" task bfm_read16;
export "DPI-C" task bfm_write8;
export "DPI-C" task bfm_read8;
export "DPI-C" task bfm_nop;
tar xvf vim-7.2-1-msys-1.0.11-bin.tar.lzma.tar
lzma -d vim-7.2-1-msys-1.0.11-bin.tar.lzma
tar xvf vim-7.2-1-msys-1.0.11-bin.tar
tar zxvf libiconv-1.11-1-i386-mingw32.tar.gz
INST "ddr2_sdram_cont_i/dcm_module_inst/DCM_INST1/DCM_SP" LOC = DCM_X0Y2;
INST "ddr2_sdram_cont_i/dcm_module_inst/DCM_INST1/DCM_SP" LOC = DCM_X0Y1;
INST "dcm_DDR2_VGA_clk_i/dcm_VGA_clk_dcm/DCM_SP" LOC = DCM_X0Y2;
INST "dcm_DDR2_VGA_clk_i/dcm_DDR2_clk_dcm/DCM_SP" LOC = "DCM_X2Y3";
NET "sd_loop_in_IBUF"
ROUTE="{3;1;3s700afg484;df4ab136!-1;-70632;33392;S!0;-159;0!1;1612;-912!"
"1;1596;1056!1;1680;-1720!1;-1464;-3608!1;-1618;10040!1;-225;1797!1;-1632;"
"-10456!2;-3069;-3647!3;450;5392!3;4355;1359!4;4;-12032!4;4255;-597!5;"
"3927;-4329!5;0;-7000!6;-474;9200!6;178;6576!6;184;13320!7;-1185;4651!7;"
"-1867;-629!8;4111;-10997!8;192;-13688!9;0;-6876!9;3952;222!10;3905;-657!"
"11;2808;3082!11;2917;-5975!11;1152;657;L!11;1152;313;L!12;2123;3408;L!13;"
"-511;-4883!13;1168;-1715;L!13;1168;-1371;L!14;13605;-139!14;-447;-2703!"
"15;24;-6784!16;1099;79!17;-17;-7547!17;-652;-752!18;-658;-744!19;3905;"
"-657!20;1099;-97!21;2976;-3486!22;3935;-4073!22;-652;-752!23;3952;98!24;"
"1152;313;L!24;1152;657;L!25;1152;313;L!25;1152;657;L!26;-2848;-1044!27;"
"-2957;1261!31;-2953;1265!34;-8965;428;L!34;-8965;772;L!35;3935;-4073!36;"
"3935;-4073!37;6944;-24!38;3952;98!39;1099;79!40;1099;79!41;1152;313;L!41;"
"1152;657;L!42;6912;0!43;-2968;104!44;12173;-119!45;1099;79!46;1152;657;L!"
"46;1152;313;L!51;1352;-701;L!51;-2104;-1045;L!52;1352;-701;L!53;1176;"
"-1377;L!56;1152;657;L!56;1152;313;L!57;1152;657;L!57;1152;313;L!58;-2304;"
"313;L!58;1152;313;L!58;1152;657;L!58;-2304;657;L!59;1152;657;L!59;1152;"
"313;L!60;6944;-24!61;6944;-24!64;-2112;-1039;L!65;1160;651;L!65;1160;307;"
"L!66;-7565;776;L!66;-7565;432;L!67;15333;-139!84;1152;657;L!84;1152;313;L"
"!85;-2304;313;L!85;-2304;657;L!91;-7237;772;L!91;-7237;428;L!}";
// 02/20 @ 12:48:23
NET "ddr2_sdram_cont_i/read_write_io_inst/ddr2_cont_iob_inst/dqs_clk_node<0>"
ROUTE="{3;1;3s700afg484;c20d0b8b!-1;-70632;12888;S!0;-159;0!1;-161;-887!"
"2;-1291;-2737!3;-29;-8091!4;259;-695!5;-1703;-139!6;108;53;L!}";
// 02/20 @ 12:51:22
NET "ddr2_sdram_cont_i/read_write_io_inst/dq_data<0>"
ROUTE="{3;1;3s700afg484;a5bd1784!-1;-70632;26072;S!0;-159;0!1;2447;-605!"
"2;4489;301!2;4489;645!3;167;0;L!4;167;0;L!}";
NET "ddr2_sdram_cont_i/read_write_io_inst/dq_data<1>"
ROUTE="{3;1;3s700afg484;751a0e0!-1;-70632;19640;S!0;-159;0!1;1696;1720!2;"
"1784;1376!2;1784;1032!3;167;0;L!4;167;0;L!}";
NET "ddr2_sdram_cont_i/read_write_io_inst/dq_data<2>"
ROUTE="{3;1;3s700afg484;89ffb99b!-1;-70632;6136;S!0;-159;0!1;1696;1720!2;"
"1784;1376!2;1784;1032!3;167;0;L!4;167;0;L!}";
NET "ddr2_sdram_cont_i/read_write_io_inst/dq_data<3>"
ROUTE="{3;1;3s700afg484;61a7f9cb!-1;-70632;9192;S!0;-159;0!1;2447;-605!2;"
"4489;645!2;4489;301!3;167;0;L!4;167;0;L!}";
NET "ddr2_sdram_cont_i/read_write_io_inst/dq_data<4>"
ROUTE="{3;1;3s700afg484;5a9ec78e!-1;-70632;9512;S!0;-159;0!1;1696;1720!2;"
"1784;1376!2;1784;1032!3;167;0;L!4;167;0;L!}";
NET "ddr2_sdram_cont_i/read_write_io_inst/dq_data<5>"
ROUTE="{3;1;3s700afg484;c3906147!-1;-70632;5816;S!0;-159;0!1;2447;-605!2;"
"4489;645!2;4489;301!3;167;0;L!4;167;0;L!}";
NET "ddr2_sdram_cont_i/read_write_io_inst/dq_data<6>"
ROUTE="{3;1;3s700afg484;3cdde0e5!-1;-70632;19320;S!0;-159;0!1;2447;-605!"
"2;4489;645!2;4489;301!3;167;0;L!4;167;0;L!}";
NET "ddr2_sdram_cont_i/read_write_io_inst/dq_data<7>"
ROUTE="{3;1;3s700afg484;48045bde!-1;-70632;26392;S!0;-159;0!1;1696;1968!"
"2;1784;1032!2;1784;1376!3;167;0;L!4;167;0;L!}";
NET "ddr2_sdram_cont_i/read_write_io_inst/dq_data<8>"
ROUTE="{3;1;3s700afg484;8152c779!-1;-70632;40144;S!0;-159;0!1;1696;1720!"
"2;1784;1376!2;1784;1032!3;167;0;L!4;167;0;L!}";
NET "ddr2_sdram_cont_i/read_write_io_inst/dq_data<9>"
ROUTE="{3;1;3s700afg484;bfa7b4d9!-1;-70632;53328;S!0;-159;0!1;1696;2040!"
"2;1784;1376!2;1784;1032!3;167;0;L!4;167;0;L!}";
NET "ddr2_sdram_cont_i/read_write_io_inst/dq_data<10>"
ROUTE="{3;1;3s700afg484;ace04032!-1;-70632;36448;S!0;-159;0!1;2447;-605!"
"2;4489;645!2;4489;301!3;167;0;L!4;167;0;L!}";
NET "ddr2_sdram_cont_i/read_write_io_inst/dq_data<11>"
ROUTE="{3;1;3s700afg484;fc333603!-1;-70632;49952;S!0;-159;0!1;2447;-605!"
"2;4489;645!2;4489;301!3;167;0;L!4;167;0;L!}";
NET "ddr2_sdram_cont_i/read_write_io_inst/dq_data<12>"
ROUTE="{3;1;3s700afg484;4ce19306!-1;-70632;50272;S!0;-159;0!1;1696;1720!"
"2;1784;1032!2;1784;1376!3;167;0;L!4;167;0;L!}";
NET "ddr2_sdram_cont_i/read_write_io_inst/dq_data<13>"
ROUTE="{3;1;3s700afg484;7f7f4c8c!-1;-70632;39824;S!0;-159;0!1;2447;-605!"
"2;4489;301!2;4489;645!3;167;0;L!4;167;0;L!}";
NET "ddr2_sdram_cont_i/read_write_io_inst/dq_data<14>"
ROUTE="{3;1;3s700afg484;10d3a509!-1;-70632;36768;S!0;-159;0!1;1696;1720!"
"2;1784;1032!2;1784;1376!3;167;0;L!4;167;0;L!}";
NET "ddr2_sdram_cont_i/read_write_io_inst/dq_data<15>"
ROUTE="{3;1;3s700afg484;473a4c3d!-1;-70632;53648;S!0;-159;0!1;2479;-949!"
"2;4457;661!3;0;8!3;0;-336!4;167;0;L!5;167;0;L!}";
INST "ddr2_sdram_cont_i/dcm_module_inst/DCM_INST1/DCM_SP" LOC = DCM_X0Y1;
INST "dcm_DDR2_VGA_clk_i/dcm_VGA_clk_dcm/DCM_SP" LOC = DCM_X0Y2;
INST "dcm_DDR2_VGA_clk_i/dcm_DDR2_clk_dcm/DCM_SP" LOC = "DCM_X2Y3";
NET "ddr2_dq[0]" IBUF_DELAY_VALUE = 1;
NET "ddr2_dq[1]" IBUF_DELAY_VALUE = 1;
NET "ddr2_dq[2]" IBUF_DELAY_VALUE = 1;
NET "ddr2_dq[3]" IBUF_DELAY_VALUE = 1;
NET "ddr2_dq[4]" IBUF_DELAY_VALUE = 1;
NET "ddr2_dq[5]" IBUF_DELAY_VALUE = 1;
NET "ddr2_dq[6]" IBUF_DELAY_VALUE = 1;
NET "ddr2_dq[7]" IBUF_DELAY_VALUE = 1;
NET "ddr2_dq[8]" IBUF_DELAY_VALUE = 1;
NET "ddr2_dq[9]" IBUF_DELAY_VALUE = 1;
NET "ddr2_dq[10]" IBUF_DELAY_VALUE = 1;
NET "ddr2_dq[11]" IBUF_DELAY_VALUE = 1;
NET "ddr2_dq[12]" IBUF_DELAY_VALUE = 1;
NET "ddr2_dq[13]" IBUF_DELAY_VALUE = 1;
NET "ddr2_dq[14]" IBUF_DELAY_VALUE = 1;
NET "ddr2_dq[15]" IBUF_DELAY_VALUE = 1;
#
NET "ddr2_dqs[0]" IBUF_DELAY_VALUE = 1;
# NET "sd_loop_in" IBUF_DELAY_VALUE = 1;
# sd_loop_in // 02/21 @ 20:52:31
NET "sd_loop_in_IBUF"
ROUTE="{3;1;3s700afg484;df4ab136!-1;-70632;33392;S!0;-159;0!1;1612;-912!"
"1;1596;1056!1;1680;-1720!1;-1464;-3608!1;-1618;10040!1;-225;1797!1;-1632;"
"-10456!2;-3069;-3647!3;450;5392!3;4355;1359!4;4;-12032!4;4255;-597!5;"
"3927;-4329!5;0;-7000!6;-474;9200!6;178;6576!6;184;13320!7;-1185;4651!7;"
"-1867;-629!8;4111;-10997!8;192;-13688!9;0;-6876!9;3952;222!10;3905;-657!"
"11;2808;3082!11;2917;-5975!11;1152;657;L!11;1152;313;L!12;2123;3408;L!13;"
"-511;-4883!13;1168;-1715;L!13;1168;-1371;L!14;13605;-139!14;-447;-2703!"
"15;24;-6784!16;1099;79!17;-17;-7547!17;-652;-752!18;-658;-744!19;3905;"
"-657!20;1099;-97!21;2976;-3486!22;3935;-4073!22;-652;-752!23;3952;98!24;"
"1152;313;L!24;1152;657;L!25;1152;313;L!25;1152;657;L!26;-2848;-1044!27;"
"-2957;1261!31;-2953;1265!34;-8965;428;L!34;-8965;772;L!35;3935;-4073!36;"
"3935;-4073!37;6944;-24!38;3952;98!39;1099;79!40;1099;79!41;1152;313;L!41;"
"1152;657;L!42;6912;0!43;-2968;104!44;12173;-119!45;1099;79!46;1152;657;L!"
"46;1152;313;L!51;1352;-701;L!51;-2104;-1045;L!52;1352;-701;L!53;1176;"
"-1377;L!56;1152;657;L!56;1152;313;L!57;1152;657;L!57;1152;313;L!58;-2304;"
"313;L!58;1152;313;L!58;1152;657;L!58;-2304;657;L!59;1152;657;L!59;1152;"
"313;L!60;6944;-24!61;6944;-24!64;-2112;-1039;L!65;1160;651;L!65;1160;307;"
"L!66;-7565;776;L!66;-7565;432;L!67;15333;-139!84;1152;657;L!84;1152;313;L"
"!85;-2304;313;L!85;-2304;657;L!91;-7237;772;L!91;-7237;428;L!}";
// 02/20 @ 12:51:22
NET "ddr2_sdram_cont_i/read_write_io_inst/dq_data<0>"
ROUTE="{3;1;3s700afg484;a5bd1784!-1;-70632;26072;S!0;-159;0!1;2447;-605!"
"2;4489;301!2;4489;645!3;167;0;L!4;167;0;L!}";
NET "ddr2_sdram_cont_i/read_write_io_inst/dq_data<1>"
ROUTE="{3;1;3s700afg484;751a0e0!-1;-70632;19640;S!0;-159;0!1;1696;1720!2;"
"1784;1376!2;1784;1032!3;167;0;L!4;167;0;L!}";
NET "ddr2_sdram_cont_i/read_write_io_inst/dq_data<2>"
ROUTE="{3;1;3s700afg484;89ffb99b!-1;-70632;6136;S!0;-159;0!1;1696;1720!2;"
"1784;1376!2;1784;1032!3;167;0;L!4;167;0;L!}";
NET "ddr2_sdram_cont_i/read_write_io_inst/dq_data<3>"
ROUTE="{3;1;3s700afg484;61a7f9cb!-1;-70632;9192;S!0;-159;0!1;2447;-605!2;"
"4489;645!2;4489;301!3;167;0;L!4;167;0;L!}";
NET "ddr2_sdram_cont_i/read_write_io_inst/dq_data<4>"
ROUTE="{3;1;3s700afg484;5a9ec78e!-1;-70632;9512;S!0;-159;0!1;1696;1720!2;"
"1784;1376!2;1784;1032!3;167;0;L!4;167;0;L!}";
NET "ddr2_sdram_cont_i/read_write_io_inst/dq_data<5>"
ROUTE="{3;1;3s700afg484;c3906147!-1;-70632;5816;S!0;-159;0!1;2447;-605!2;"
"4489;645!2;4489;301!3;167;0;L!4;167;0;L!}";
NET "ddr2_sdram_cont_i/read_write_io_inst/dq_data<6>"
ROUTE="{3;1;3s700afg484;3cdde0e5!-1;-70632;19320;S!0;-159;0!1;2447;-605!"
"2;4489;645!2;4489;301!3;167;0;L!4;167;0;L!}";
NET "ddr2_sdram_cont_i/read_write_io_inst/dq_data<7>"
ROUTE="{3;1;3s700afg484;48045bde!-1;-70632;26392;S!0;-159;0!1;1696;1968!"
"2;1784;1032!2;1784;1376!3;167;0;L!4;167;0;L!}";
NET "ddr2_sdram_cont_i/read_write_io_inst/dq_data<8>"
ROUTE="{3;1;3s700afg484;8152c779!-1;-70632;40144;S!0;-159;0!1;1696;1720!"
"2;1784;1376!2;1784;1032!3;167;0;L!4;167;0;L!}";
NET "ddr2_sdram_cont_i/read_write_io_inst/dq_data<9>"
ROUTE="{3;1;3s700afg484;bfa7b4d9!-1;-70632;53328;S!0;-159;0!1;1696;2040!"
"2;1784;1376!2;1784;1032!3;167;0;L!4;167;0;L!}";
NET "ddr2_sdram_cont_i/read_write_io_inst/dq_data<10>"
ROUTE="{3;1;3s700afg484;ace04032!-1;-70632;36448;S!0;-159;0!1;2447;-605!"
"2;4489;645!2;4489;301!3;167;0;L!4;167;0;L!}";
NET "ddr2_sdram_cont_i/read_write_io_inst/dq_data<11>"
ROUTE="{3;1;3s700afg484;fc333603!-1;-70632;49952;S!0;-159;0!1;2447;-605!"
"2;4489;645!2;4489;301!3;167;0;L!4;167;0;L!}";
NET "ddr2_sdram_cont_i/read_write_io_inst/dq_data<12>"
ROUTE="{3;1;3s700afg484;4ce19306!-1;-70632;50272;S!0;-159;0!1;1696;1720!"
"2;1784;1032!2;1784;1376!3;167;0;L!4;167;0;L!}";
NET "ddr2_sdram_cont_i/read_write_io_inst/dq_data<13>"
ROUTE="{3;1;3s700afg484;7f7f4c8c!-1;-70632;39824;S!0;-159;0!1;2447;-605!"
"2;4489;301!2;4489;645!3;167;0;L!4;167;0;L!}";
NET "ddr2_sdram_cont_i/read_write_io_inst/dq_data<14>"
ROUTE="{3;1;3s700afg484;10d3a509!-1;-70632;36768;S!0;-159;0!1;1696;1720!"
"2;1784;1032!2;1784;1376!3;167;0;L!4;167;0;L!}";
NET "ddr2_sdram_cont_i/read_write_io_inst/dq_data<15>"
ROUTE="{3;1;3s700afg484;473a4c3d!-1;-70632;53648;S!0;-159;0!1;2479;-949!"
"2;4457;661!3;0;8!3;0;-336!4;167;0;L!5;167;0;L!}";
// 02/20 @ 12:48:23
NET "ddr2_sdram_cont_i/read_write_io_inst/ddr2_cont_iob_inst/dqs_clk_node<0>"
ROUTE="{3;1;3s700afg484;c20d0b8b!-1;-70632;12888;S!0;-159;0!1;-161;-887!"
"2;-1291;-2737!3;-29;-8091!4;259;-695!5;-1703;-139!6;108;53;L!}";
INST "ddr2_sdram_cont_i/read_write_io_inst/ddr2_cont_iob_inst/BUFG_inst" LOC = BUFGMUX_X0Y5;
PIN "dcm_DDR2_VGA_clk_i/dcm_DDR2_clk_dcm/DCM_SP.CLKFX" CLOCK_DEDICATED_ROUTE = FALSE;
// テスト回路
always @(posedge clk_vga) begin
if (reset_vga)
start_vram_data <= 16'd0;
else begin
if (h_count==1 && v_count==0 && pixel_afifo_rd_en)
start_vram_data <= vram_data_out;
end
end
always @(posedge clk_vga) begin
if (reset_vga)
diff_start_data <= 1'b0;
else begin
if (h_count==1 && v_count==0 && pixel_afifo_rd_en) begin
if (start_vram_data==vram_data_out)
diff_start_data <= 1'b1;
else
diff_start_data <= 1'b0;
end
end
end
assign start_vram_data_out = start_vram_data[6:0];
// Bitmap_VGA_Controller_top.v
// Bitmap_VGA_Controllerをテストするトップファイル
module Bitmap_VGA_Controller_top(SYS_CLK, SYS_RST, red_out, green_out, blue_out, hsyncx, vsyncx);
`include "Address_Map_Define.vh"
input wire SYS_CLK;
input wire SYS_RST;
output wire [3:0] red_out;
output wire [3:0] green_out;
output wire [3:0] blue_out;
output wire hsyncx;
output wire vsyncx;
wire clk_vga; // 65MHz クロック入力(VGA用)
wire clk_ddr2; // 150MHz クロック入力(DDR2へのインターフェース用)
wire reset_vga; // clk_vga用リセット
wire reset_ddr2; // clk_ddr2リセット
wire [31:0] vram_start_addr; // バイトアドレス
wire vram_request; // VRAMへのRead要求。アービタへ
wire vram_grant; // VRAMへのRead許可。アービタから
wire [31:0] vram_address; // バイトアドレス
wire read_write;
wire vram_req_we; // VRAM へのRead要求のWrite Enable
wire vram_addr_fifo_full; // VRAMのRead要求用FIFOのFULL
wire [31:0] vram_data_in;
reg vram_data_valid;
wire afifo_overflow; // 非同期FIFO のオーバーフロー・エラー
wire afifo_underflow; // 非同期FIFO
wire clk_ddr2_locked, clk_vga_locked;
reg [15:0] vram_data_in1, vram_data_in2;
reg vram_req_we_1d;
dcm_DDR2_VGA_clk dcm_DDR2_VGA_clk_i(
.sysclk(SYS_CLK),
.reset(SYS_RST),
.clk_ddr2(clk_ddr2),
.dcm_ddr2_locked(clk_ddr2_locked),
.clk_vga(clk_vga),
.dcm_vga_locked(clk_vga_locked)
);
assign reset_vga = SYS_RST | ~clk_vga_locked;
assign reset_ddr2 = SYS_RST | ~ clk_ddr2_locked;
Bitmap_VGA_Controller Bitmap_VGA_Cntrler_i(
.clk_vga(clk_vga),
.clk_ddr2(clk_ddr2),
.reset_vga(reset_vga),
.reset_ddr2(reset_ddr2),
.vram_start_addr(VRAM_START_ADDRESS),
.vram_request(vram_request),
.vram_grant(vram_grant),
.vram_address(vram_address),
.read_write(read_write),
.vram_req_we(vram_req_we),
.vram_addr_fifo_full(vram_addr_fifo_full),
.vram_data_in(vram_data_in),
.vram_data_valid(vram_data_valid),
.red_out(red_out),
.green_out(green_out),
.blue_out(blue_out),
.hsyncx(hsyncx),
.vsyncx(vsyncx),
.afifo_overflow(afifo_overflow),
.afifo_underflow(afifo_underflow)
);
assign vram_addr_fifo_full = 1'b0;
assign vram_grant = 1'b1;
always @(posedge clk_ddr2) begin // vram_req_weを1クロック遅延する
if (reset_ddr2)
vram_req_we_1d <= 1'b0;
else
vram_req_we_1d <= vram_req_we;
end
always @(posedge clk_ddr2) begin
if (reset_ddr2) begin
vram_data_in1 <= 16'h0000;
vram_data_in2 <= 16'h0fff;
end else begin
if (vram_req_we || vram_req_we_1d) begin // 1リクエストで2つデータを出力する
if (vram_address==VRAM_START_ADDRESS) begin
vram_data_in1 <= 16'h0000;
vram_data_in2 <= 16'h0000;
end else begin
vram_data_in1 <= vram_data_in1 + 16'd1;
vram_data_in2 <= vram_data_in2 + 16'd1;
end
end
end
end
assign vram_data_in = {vram_data_in1, vram_data_in2};
always @(posedge clk_ddr2) begin
if (reset_ddr2)
vram_data_valid <= 1'b0;
else begin
if (vram_req_we || vram_req_we_1d) // 1リクエストで2つデータを出力する
vram_data_valid <= 1'b1;
else
vram_data_valid <= 1'b0;
end
end
endmodule
`default_nettype wire
PIN "dcm_DDR2_VGA_clk_i/dcm_VGA_clk_dcm.CLKFX" TNM = VGA_CLK_OUTPUT;
PIN "dcm_DDR2_VGA_clk_i/dcm_DDR2_clk_dcm.CLKFX" TNM = DDR2_CLK_OUTPUT;
TIMESPEC TS_VGA2DDR2_CLK_TIG = FROM "VGA_CLK_OUTPUT" TO "DDR2_CLK_OUTPUT" TIG;
TIMESPEC TS_DDR22VGA_CLK_TIG = FROM "DDR2_CLK_OUTPUT" TO "VGA_CLK_OUTPUT" TIG;
parameter V_ACTIVE_VIDEO = 2;
parameter V_FRONT_PORCH = 0;
parameter V_SYNC_PULSE = 1;
parameter V_BACK_PORCH = 0;
// parameter V_ACTIVE_VIDEO = 768;
// parameter V_FRONT_PORCH = 3;
// parameter V_SYNC_PULSE = 6;
// parameter V_BACK_PORCH = 29;
INST "ddr2_sdram_cont_i/read_write_io_inst/rddata_afifo_inst/DQS2intclk_FIFO_FALL/DPRAM_GEN[15].RAM16X1D_inst" LOC = SLICE_X2Y79;
INST "ddr2_sdram_cont_i/read_write_io_inst/rddata_afifo_inst/DQS2intclk_FIFO_FALL/DPRAM_GEN[14].RAM16X1D_inst" LOC = SLICE_X0Y71;
PIN "dcm_DDR2_VGA_clk_i/dcm_VGA_clk_dcm.CLKFX" TNM = VGA_CLK_OUTPUT;
PIN "ddr2_sdram_cont_i/dcm_module_inst/DCM_INST1.CLK0" TNM = DDR2_CLK_OUTPUT;
TIMESPEC TS_VGA2DDR2_CLK_TIG = FROM "VGA_CLK_OUTPUT" TO "DDR2_CLK_OUTPUT" TIG;
TIMESPEC TS_DDR22VGA_CLK_TIG = FROM "DDR2_CLK_OUTPUT" TO "VGA_CLK_OUTPUT" TIG;
関連する資料
Spartan3A Starter KitのビットマップVGAコントローラの仕様1
Spartan3A Starter KitのビットマップVGAコントローラの仕様2
キャラクタ生成コントローラの仕様
キャラクタ生成コントローラの仕様2
parameter [1:0] vram_req_we_low= 2'b01,
vram_req_we_high= 2'b01; // active
parameter [1:0] vram_req_we_low= 2'b01,
vram_req_we_high= 2'b10; // active
parameter wait_cmd_fifo_not_empty =4'b0001;
parameter vram_addr_counter_load =4'b0010;
parameter next_char_code_load =4'b0100;
parameter char_generation_state =4'b1000;
parameter [3:0] wait_cmd_fifo_not_empty = 4'b0001,
vram_addr_counter_load = 4'b0010,
next_char_code_load = 4'b0100,
char_generation_state = 4'b1000;
parameter DECODE_ADDRESS_LENGTH = 4; // デーコードするアドレス長、上のビットから何ビットデーコードするか。
parameter CHAR_GEN_CONTROLLER_ADDR = DECODE_ADDRESS_LENGTH'hF; // キャラクタ生成コントローラのアドレスマップ
parameter DDR2_SDRAM_ADDR = DECODE_ADDRESS_LENGTH'h0;cpu_address <= {CHAR_GEN_CONTROLLER_ADDR, (DECODE_ADDRESS_LENGTH-8)'d4, 4'd0};
cpu_address <= {CHAR_GEN_CONTROLLER_ADDR, (32-(DECODE_ADDRESS_LENGTH+4))'d4, 4'd0};
`define DCODE_ADDRESS_LENGTH 4 // デーコードするアドレス長、上のビットから何ビットデーコードするか。
parameter CHAR_GEN_CONTROLLER_ADDR = `DECODE_ADDRESS_LENGTH'hF; // キャラクタ生成コントローラのアドレスマップ
parameter DDR2_SDRAM_ADDR = `DECODE_ADDRESS_LENGTH'h0;cpu_address <= {CHAR_GEN_CONTROLLER_ADDR, (32-(`DECODE_ADDRESS_LENGTH+4))'d4, 4'd0};
parameter DECODE_ADDRESS_LENGTH = 4; // デーコードするアドレス長、上のビットから何ビットデーコードするか。
parameter CHAR_GEN_CONTROLLER_ADDR = 4'hF; // キャラクタ生成コントローラのアドレスマップ
parameter DDR2_SDRAM_ADDR = 4'h0;
cpu_address[31:31-(DECODE_ADDRESS_LENGTH-1)] <= CHAR_GEN_CONTROLLER_ADDR;
cpu_address[31-(DECODE_ADDRESS_LENGTH):4] <= 4;
cpu_address[3:0] <= 4'd0;
// Address_Map_Define.vh
// アドレスマップを定義する
parameter DECODE_ADDRESS_LENGTH = 4; // デーコードするアドレス長、上のビットから何ビットデーコードするか。
parameter CHAR_GEN_CONTROLLER_ADDR = 4'hF; // キャラクタ生成コントローラのアドレスマップ
parameter DDR2_SDRAM_ADDR = 4'h0;
// Command_Status_Define.vh
// Command Registers
// 0番地の割り当て
parameter CHAR_CODE_UPPER_HIGH = 31; // キャラクタ・コードの上位バイト
parameter CHAR_CODE_UPPER_LOW = 24;
parameter CHAR_CODE_LOWER_HIGH = 23; // キャラクタ・コードの下位バイト
parameter CHAR_CODE_LOWER_LOW = 16;
parameter NOT_PAINTED_BACKGROUND = 15; // 0 - 文字の背景を塗りつぶす, 1 - 文字の背景を塗りつぶさない
parameter DRAW_IMMEDIATELY = 14; // 0 - 8番地の書き込みを待つ, 1 - 0番地の書き込みだけで描画
parameter RED_FEILD_HIGH = 11;
parameter RED_FEILD_LOW = 8;
parameter GREEN_FEILD_HIGH = 7;
parameter GREEN_FEILD_LOW = 4;
parameter BLUE_FEILD_HIGH = 3;
parameter BLUE_FEILD_LOW = 0;
// 4番地の割り当て
parameter MAGNIFICATION_HIGH = 15; // 拡大倍率
parameter MAGNIFICATION_LOW = 11;
// Red, Green, Blue の割り当ては0番地と同じ
// 8番地の割り当て
parameter VRAM_START_ADDRESS_HIGH = 31;
parameter VRAM_START_ADDRESS_LOW = 0;
// Status Register
parameter FIFO_COUNT_HIGH = 4;
parameter FIFO_COUNT_LOW = 0;
// 各領域のビット幅
`define CHAR_CODE_UPPER_WIDTH 8
`define CHAR_CODE_LOWER_WIDTH 8
`define RED_FEILD_WIDTH 4
parameter RED_FEILD_WIDTH = 4;
`define GREEN_FEILD_WIDTH 4
parameter GREEN_FEILD_WIDTH = 4;
`define BLUE_FEILD_WIDTH 4
parameter BLUE_FEILD_WIDTH = 4;
`define MAGNIFICATION_WIDTH 5
`define VRAM_START_ADDRESS_WIDTH 32
`define FIFO_COUNT_WIDTH 5
// テスト用キャラクタ描画モジュール
// Char_Draw_for_Test.v
//
// グラフィックメモリの先頭からキャラクタを描画する。0~9まで、A~Zまで描画したら元に戻る。背景色は黒とする
// Char_Gen_Controller.v のCPUのインターフェースを操作する。
// DDR2 SDRAMは64Mbytes, よって先頭を0x0とすると0x3FF_FFFFまで。
// グラフィックメモリは1024X768X2bytes = 1,572,864 bytes = 0x18_0000
// グラフィックメモリは0x300_0000からとする
// キャラクタは128X96文字 = 12,288文字を1画面に描画できる
`default_nettype none
module Char_Draw_for_Test (clk_vga, reset_vga, cpu_address, cpu_write_data, cpu_read_data, cpu_data_we);
input wire clk_vga; // VGAのクロック、65MHzの予定
input wire reset_vga; // clk_vga用リセット
output reg [31:0] cpu_address; // CPUのアドレス
output wire [31:0] cpu_write_data; // CPUのWrite データ
input wire [31:0] cpu_read_data; // CPUのRead データ
output reg cpu_data_we; // CPUのデータ入力のWrite Enable
`include "Address_Map_Define.vh"
`include "Command_Status_Define.vh"
parameter idle_char = 6'b000001;
parameter CGC_first_cmd0_set = 6'b000010;
parameter CGC_cmd4_set = 6'b000100;
parameter CGC_cmd8_set = 6'b001000;
parameter Wait_CGC_cmd0 = 6'b010000;
parameter CGC_cmd0_loop = 6'b100000;
reg [5:0] cs_char;
reg [7:0] char_code_count; // キャラクタのカウンタ
reg [RED_FEILD_HIGH:RED_FEILD_LOW] red_count;
reg [GREEN_FEILD_HIGH:GREEN_FEILD_LOW] green_count;
reg [BLUE_FEILD_HIGH:BLUE_FEILD_LOW] blue_count;
wire op_ena;
reg [13:0] vram_disp_count;
reg [31:0] cmd_data;
// 周波数分周
freqdiv #(.DIVISOR(3250000)) // 65MHzを20Hzにする
freqdiv_inst (
.clk(clk_vga),
.reset(reset_vga),
.op_ena(op_ena)
);
// キャラクタを書きまくるステートマシン
always @(posedge clk_vga) begin
if (reset_vga)
cs_char <= idle_char;
else begin
case (cs_char)
idle_char :
cs_char <= CGC_first_cmd0_set;
CGC_first_cmd0_set : // キャラクタ生成コントローラの0番地に最初のキャラクタと色をセット
cs_char <= CGC_cmd4_set;
CGC_cmd4_set : // キャラクタ生成コントローラの4番地背景色、倍率をセット
cs_char <= CGC_cmd8_set;
CGC_cmd8_set : // キャラクタ生成コントローラの8番地アドレスをセットして1キャラクタ描画
cs_char <= Wait_CGC_cmd0;
Wait_CGC_cmd0 : // 次のキャラクタを書くまでのWait
if ((cpu_read_data[FIFO_COUNT_HIGH:FIFO_COUNT_LOW]<5'h01110) && op_ena)
cs_char <= CGC_cmd0_loop;
CGC_cmd0_loop : // ループしながらキャラクタと色を+1しながら
if (vram_disp_count>14'd12287) // 1画面描画済み
cs_char <= CGC_first_cmd0_set;
else
cs_char <= Wait_CGC_cmd0;
endcase
end
end
// キャラクタ生成コントローラのコマンドデータの用意
always @(posedge clk_vga) begin
if (reset_vga) begin
cpu_address <= 32'd0;
cmd_data <= 32'd0;
cpu_data_we <= 1'b0;
end else begin
case (cs_char)
idle_char :begin
cpu_address <= 32'd0;
cmd_data <= 32'd0;
cpu_data_we <= 1'b0;
end
CGC_first_cmd0_set : begin
cpu_address[31:31-(DECODE_ADDRESS_LENGTH-1)] <= CHAR_GEN_CONTROLLER_ADDR;
cpu_address[31-(DECODE_ADDRESS_LENGTH):4] <= 0;
cpu_address[3:0] <= 4'd0;
cmd_data[CHAR_CODE_UPPER_HIGH:CHAR_CODE_UPPER_LOW] <= 0;
cmd_data[CHAR_CODE_LOWER_HIGH:CHAR_CODE_LOWER_LOW] <= `CHAR_CODE_LOWER_WIDTH'h30; // 0x30
cmd_data[NOT_PAINTED_BACKGROUND] <= 1'b0; // 背景を塗りつぶす
cmd_data[DRAW_IMMEDIATELY] <= 1'b0; // アドレスの書き込みを待つ
cmd_data[DRAW_IMMEDIATELY-1 : RED_FEILD_HIGH+1] <= 0;
cmd_data[RED_FEILD_HIGH:RED_FEILD_LOW] <= red_count;
cmd_data[GREEN_FEILD_HIGH:GREEN_FEILD_LOW] <= green_count;
cmd_data[BLUE_FEILD_HIGH:BLUE_FEILD_LOW] <= blue_count;
cpu_data_we <= 1'b1;
end
CGC_cmd4_set : begin
cpu_address[31:31-(DECODE_ADDRESS_LENGTH-1)] <= CHAR_GEN_CONTROLLER_ADDR;
cpu_address[31-(DECODE_ADDRESS_LENGTH):4] <= 0;
cpu_address[3:0] <= 4'd4;
cmd_data[31:MAGNIFICATION_HIGH+1] <= 0;
cmd_data[MAGNIFICATION_HIGH:MAGNIFICATION_LOW] <= 0; // 倍率1倍
cmd_data[RED_FEILD_HIGH:RED_FEILD_LOW] <= `RED_FEILD_WIDTH'd0;
cmd_data[GREEN_FEILD_HIGH:GREEN_FEILD_LOW] <= `GREEN_FEILD_WIDTH'd0;
cmd_data[BLUE_FEILD_HIGH:BLUE_FEILD_LOW] <= `BLUE_FEILD_WIDTH'd0;
cpu_data_we <= 1'b1;
end
CGC_cmd8_set : begin
cpu_address[31:31-(DECODE_ADDRESS_LENGTH-1)] <= CHAR_GEN_CONTROLLER_ADDR;
cpu_address[31-(DECODE_ADDRESS_LENGTH):4] <= 0;
cpu_address[3:0] <= 4'd8;
cmd_data <= VRAM_START_ADDRESS;
cpu_data_we <= 1'b1;
end
Wait_CGC_cmd0 : begin
cpu_address[31:31-(DECODE_ADDRESS_LENGTH-1)] <= CHAR_GEN_CONTROLLER_ADDR;
cpu_address[31-(DECODE_ADDRESS_LENGTH):4] <= 0;
cpu_address[3:0] <= 4'd0;
cmd_data[CHAR_CODE_UPPER_HIGH:CHAR_CODE_UPPER_LOW] <= 0;
cmd_data[CHAR_CODE_LOWER_HIGH:CHAR_CODE_LOWER_LOW] <= char_code_count;
cmd_data[NOT_PAINTED_BACKGROUND] <= 1'b0; // 背景を塗りつぶす
cmd_data[DRAW_IMMEDIATELY] <= 1'b1; // アドレスの書き込みを待つ
cmd_data[DRAW_IMMEDIATELY-1 : RED_FEILD_HIGH+1] <= 0;
cmd_data[RED_FEILD_HIGH:RED_FEILD_LOW] <= red_count;
cmd_data[GREEN_FEILD_HIGH:GREEN_FEILD_LOW] <= green_count;
cmd_data[BLUE_FEILD_HIGH:BLUE_FEILD_LOW] <= blue_count;
cpu_data_we <= 1'b0;
end
CGC_cmd0_loop : begin
cpu_address[31:31-(DECODE_ADDRESS_LENGTH-1)] <= CHAR_GEN_CONTROLLER_ADDR;
cpu_address[31-(DECODE_ADDRESS_LENGTH):4] <= 0;
cpu_address[3:0] <= 4'd0;
cmd_data[CHAR_CODE_UPPER_HIGH:CHAR_CODE_UPPER_LOW] <= 0;
cmd_data[CHAR_CODE_LOWER_HIGH:CHAR_CODE_LOWER_LOW] <= char_code_count;
cmd_data[NOT_PAINTED_BACKGROUND] <= 1'b0; // 背景を塗りつぶす
cmd_data[DRAW_IMMEDIATELY] <= 1'b1; // アドレスの書き込みを待つ
cmd_data[DRAW_IMMEDIATELY-1 : RED_FEILD_HIGH+1] <= 0;
cmd_data[RED_FEILD_HIGH:RED_FEILD_LOW] <= red_count;
cmd_data[GREEN_FEILD_HIGH:GREEN_FEILD_LOW] <= green_count;
cmd_data[BLUE_FEILD_HIGH:BLUE_FEILD_LOW] <= blue_count;
cpu_data_we <= 1'b1;
end
endcase
end
end
assign cpu_write_data = cmd_data;
// vram_disp_count の処理
always @(posedge clk_vga) begin
if (reset_vga)
vram_disp_count <= 14'd0;
else
if (cs_char==CGC_cmd8_set || cs_char==CGC_cmd0_loop) begin
if (vram_disp_count>14'd12287)
vram_disp_count <= 14'd0;
else
vram_disp_count <= vram_disp_count + 14'd0;
end
end
// キャラクタのカウンタ
always @(posedge clk_vga) begin
if (reset_vga)
char_code_count <= 8'h30;
else begin
if (cs_char==CGC_cmd8_set || cs_char==CGC_cmd0_loop) begin
if (char_code_count==8'h39) // 9
char_code_count <= 8'h41; // A
else if (char_code_count==8'h5A) // Z
char_code_count <= 8'h61; // a
else if (char_code_count==8'h7A) // z
char_code_count <= 8'h30; // 0
else
char_code_count <= char_code_count + 8'd1;
end
end
end
// Red のカウント
always @(posedge clk_vga) begin
if (reset_vga)
red_count <= {RED_FEILD_WIDTH{1'b1}};
else
if (cs_char==CGC_cmd8_set || cs_char==CGC_cmd0_loop)
red_count <= red_count - `RED_FEILD_WIDTH'd1;
end
// Green のカウント
always @(posedge clk_vga) begin
if (reset_vga)
green_count <= {GREEN_FEILD_WIDTH{1'b1}};
else
if ((cs_char==CGC_cmd8_set || cs_char==CGC_cmd0_loop) && red_count==`RED_FEILD_WIDTH'd0) // Redが0の時に-1
green_count <= green_count - `GREEN_FEILD_WIDTH'd1;
end
// Blue のカウント
always @(posedge clk_vga) begin
if (reset_vga)
blue_count <= {BLUE_FEILD_WIDTH{1'b1}};
else
if ((cs_char==CGC_cmd8_set || cs_char==CGC_cmd0_loop) && green_count==`GREEN_FEILD_WIDTH'd0) // Greenが0の時に-1
blue_count <= blue_count - `BLUE_FEILD_WIDTH'd1;
end
endmodule
// 各領域のビット幅
`define CHAR_CODE_UPPER_WIDTH 8
`define CHAR_CODE_LOWER_WIDTH 8
`define RED_FEILD_WIDTH 4
`define GREEN_FEILD_WIDTH 4
`define BLUE_FEILD_WIDTH 4
`define MAGNIFICATION_WIDTH 5
`define VRAM_START_ADDRESS_WIDTH 32
`define FIFO_COUNT_WIDTH 5
parameter RED_FEILD_WIDTH = `RED_FEILD_WIDTH;
parameter GREEN_FEILD_WIDTH = `GREEN_FEILD_WIDTH;
parameter BLUE_FEILD_WIDTH = `BLUE_FEILD_WIDTH;
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