.p0_rd_clk (c3_clk0),
.p0_rd_en (c3_p0_rd_en),
.p0_rd_data (c3_p0_rd_data),
.p0_rd_full (c3_p0_rd_full),
.p0_rd_empty (c3_p0_rd_empty),
.p0_rd_count (c3_p0_rd_count),
.p0_rd_overflow (c3_p0_rd_overflow),
.p0_rd_error (c3_p0_rd_error),
.p0_cmd_clk (c3_clk0),
.p0_cmd_en (c3_p0_cmd_en),
.p0_cmd_instr (c3_p0_cmd_instr),
.p0_cmd_bl (c3_p0_cmd_bl),
.p0_cmd_byte_addr (c3_p0_cmd_byte_addr),
.p0_cmd_empty (c3_p0_cmd_empty),
.p0_cmd_full (c3_p0_cmd_full),
.p0_wr_clk (c3_clk0),
.p0_wr_en (c3_p0_wr_en),
.p0_wr_mask (c3_p0_wr_mask),
.p0_wr_data (c3_p0_wr_data),
.p0_wr_full (c3_p0_wr_full),
.p0_wr_empty (c3_p0_wr_empty),
.p0_wr_count (c3_p0_wr_count),
.p0_wr_underrun (c3_p0_wr_underrun),
.p0_wr_error (c3_p0_wr_error),
sim_tb_top.\MEM_INST3.u_mem_c3 .cmd_task: at time 9622501.0 ps INFO: Activate bank 0 row 0000
sim_tb_top.\MEM_INST3.u_mem_c3 .cmd_task: at time 9637501.0 ps INFO: Write bank 0 col 200, auto precharge 0
sim_tb_top.\MEM_INST3.u_mem_c3 .main: at time 9645001.0 ps INFO: Sync On Die Termination Rtt_NOM = 60 Ohm
sim_tb_top.\MEM_INST3.u_mem_c3 .cmd_task: at time 9647501.0 ps INFO: Write bank 0 col 208, auto precharge 0
sim_tb_top.\MEM_INST3.u_mem_c3 .data_task: at time 9651251.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000200 data = 0400
sim_tb_top.\MEM_INST3.u_mem_c3 .data_task: at time 9652501.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000201 data = 0000
sim_tb_top.\MEM_INST3.u_mem_c3 .data_task: at time 9653751.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000202 data = 0400
sim_tb_top.\MEM_INST3.u_mem_c3 .data_task: at time 9655001.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000203 data = 0000
sim_tb_top.\MEM_INST3.u_mem_c3 .data_task: at time 9656251.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000204 data = 0400
sim_tb_top.\MEM_INST3.u_mem_c3 .data_task: at time 9657501.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000205 data = 0000
sim_tb_top.\MEM_INST3.u_mem_c3 .cmd_task: at time 9657501.0 ps INFO: Write bank 0 col 210, auto precharge 0
sim_tb_top.\MEM_INST3.u_mem_c3 .data_task: at time 9658751.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000206 data = 0400
sim_tb_top.\MEM_INST3.u_mem_c3 .data_task: at time 9660001.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000207 data = 0000
sim_tb_top.\MEM_INST3.u_mem_c3 .data_task: at time 9661251.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000208 data = 0410
sim_tb_top.\MEM_INST3.u_mem_c3 .data_task: at time 9662501.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000209 data = 0000
sim_tb_top.\MEM_INST3.u_mem_c3 .data_task: at time 9663751.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000020a data = 0410
sim_tb_top.\MEM_INST3.u_mem_c3 .data_task: at time 9665001.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000020b data = 0000
sim_tb_top.\MEM_INST3.u_mem_c3 .data_task: at time 9666251.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000020c data = 0410
sim_tb_top.\MEM_INST3.u_mem_c3 .data_task: at time 9667501.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000020d data = 0000
sim_tb_top.\MEM_INST3.u_mem_c3 .main: at time 13102501.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm
sim_tb_top.\MEM_INST3.u_mem_c3 .cmd_task: at time 13105001.0 ps INFO: Read bank 0 col 200, auto precharge 0
sim_tb_top.\MEM_INST3.u_mem_c3 .cmd_task: at time 13115001.0 ps INFO: Read bank 0 col 208, auto precharge 0
sim_tb_top.\MEM_INST3.u_mem_c3 .data_task: at time 13118751.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000200 data = 0400
sim_tb_top.\MEM_INST3.u_mem_c3 .data_task: at time 13120001.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000201 data = 0000
sim_tb_top.\MEM_INST3.u_mem_c3 .data_task: at time 13121251.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000202 data = 0400
sim_tb_top.\MEM_INST3.u_mem_c3 .data_task: at time 13122501.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000203 data = 0000
sim_tb_top.\MEM_INST3.u_mem_c3 .data_task: at time 13123751.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000204 data = 0400
sim_tb_top.\MEM_INST3.u_mem_c3 .data_task: at time 13125001.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000205 data = 0000
sim_tb_top.\MEM_INST3.u_mem_c3 .cmd_task: at time 13125001.0 ps INFO: Read bank 0 col 210, auto precharge 0
sim_tb_top.\MEM_INST3.u_mem_c3 .data_task: at time 13126251.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000206 data = 0400
sim_tb_top.\MEM_INST3.u_mem_c3 .data_task: at time 13127501.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000207 data = 0000
sim_tb_top.\MEM_INST3.u_mem_c3 .data_task: at time 13128751.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000208 data = 0410
sim_tb_top.\MEM_INST3.u_mem_c3 .data_task: at time 13130001.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000209 data = 0000
sim_tb_top.\MEM_INST3.u_mem_c3 .data_task: at time 13131251.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000020a data = 0410
sim_tb_top.\MEM_INST3.u_mem_c3 .data_task: at time 13132501.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000020b data = 0000
sim_tb_top.\MEM_INST3.u_mem_c3 .data_task: at time 13133751.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000020c data = 0410
sim_tb_top.\MEM_INST3.u_mem_c3 .data_task: at time 13135001.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000020d data = 0000
sim_tb_top.\MEM_INST3.u_mem_c3 .reset at time 5471251.0 ps WARNING: 200 us is required before RST_N goes inactive.
sim_tb_top.\MEM_INST3.u_mem_c3 .cmd_task at time 5622501.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
sim_tb_top.\MEM_INST3.u_mem_c3 .cmd_task: at time 5755001.0 ps INFO: Load Mode 2
sim_tb_top.\MEM_INST3.u_mem_c3 .cmd_task: at time 5755001.0 ps INFO: Load Mode 2 CAS Write Latency = 5
sim_tb_top.\MEM_INST3.u_mem_c3 .cmd_task: at time 5755001.0 ps INFO: Load Mode 2 Auto Self Refresh = Enabled
sim_tb_top.\MEM_INST3.u_mem_c3 .cmd_task: at time 5755001.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
sim_tb_top.\MEM_INST3.u_mem_c3 .cmd_task: at time 5755001.0 ps INFO: Load Mode 2 Self Refresh Temperature = Normal
sim_tb_top.\MEM_INST3.u_mem_c3 .cmd_task: at time 5755001.0 ps INFO: Load Mode 2 Dynamic ODT = Disabled
sim_tb_top.\MEM_INST3.u_mem_c3 .cmd_task: at time 5765001.0 ps INFO: Load Mode 3
sim_tb_top.\MEM_INST3.u_mem_c3 .cmd_task: at time 5765001.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern
sim_tb_top.\MEM_INST3.u_mem_c3 .cmd_task: at time 5765001.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Disabled
sim_tb_top.\MEM_INST3.u_mem_c3 .cmd_task: at time 5775001.0 ps INFO: Load Mode 1
sim_tb_top.\MEM_INST3.u_mem_c3 .cmd_task: at time 5775001.0 ps INFO: Load Mode 1 DLL Enable = Enabled
sim_tb_top.\MEM_INST3.u_mem_c3 .cmd_task: at time 5775001.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm
sim_tb_top.\MEM_INST3.u_mem_c3 .cmd_task: at time 5775001.0 ps INFO: Load Mode 1 ODT Rtt = 60 Ohm
sim_tb_top.\MEM_INST3.u_mem_c3 .cmd_task: at time 5775001.0 ps INFO: Load Mode 1 Additive Latency = 0
sim_tb_top.\MEM_INST3.u_mem_c3 .cmd_task: at time 5775001.0 ps INFO: Load Mode 1 Write Levelization = Disabled
sim_tb_top.\MEM_INST3.u_mem_c3 .cmd_task: at time 5775001.0 ps INFO: Load Mode 1 TDQS Enable = Disabled
sim_tb_top.\MEM_INST3.u_mem_c3 .cmd_task: at time 5775001.0 ps INFO: Load Mode 1 Qoff = Enabled
sim_tb_top.\MEM_INST3.u_mem_c3 .cmd_task: at time 5785001.0 ps INFO: Load Mode 0
sim_tb_top.\MEM_INST3.u_mem_c3 .cmd_task: at time 5785001.0 ps INFO: Load Mode 0 Burst Length = 8
sim_tb_top.\MEM_INST3.u_mem_c3 .cmd_task: at time 5785001.0 ps INFO: Load Mode 0 Burst Order = Sequential
sim_tb_top.\MEM_INST3.u_mem_c3 .cmd_task: at time 5785001.0 ps INFO: Load Mode 0 CAS Latency = 6
sim_tb_top.\MEM_INST3.u_mem_c3 .cmd_task: at time 5785001.0 ps INFO: Load Mode 0 DLL Reset = Reset DLL
sim_tb_top.\MEM_INST3.u_mem_c3 .cmd_task: at time 5785001.0 ps INFO: Load Mode 0 Write Recovery = 6
sim_tb_top.\MEM_INST3.u_mem_c3 .cmd_task: at time 5785001.0 ps INFO: Load Mode 0 Power Down Mode = DLL off
sim_tb_top.\MEM_INST3.u_mem_c3 .cmd_task: at time 5817501.0 ps INFO: ZQ long = 1
sim_tb_top.\MEM_INST3.u_mem_c3 .cmd_task: at time 5817501.0 ps INFO: Initialization Sequence is complete
1. DDR, DDR2, DDR3, and LPDDR (Mobile DDR)サポート
2. 800Mbps(400MHz DDR)までサポート
3. パッケージに最大４つのMCBが入っている。それぞれのMCBコアは以下の特徴がある。
・4、8、16ビット長の1つのメモリを制御する。
・メモリのサイズとしては4Gbitまで。
・最大12.8Gbit/secの性能。（800MHz X 16bit = 12,800Mbit/sec = 12.8Gbit/sec)
4. MCBはユーザーロジックからマルチポートのメモリ・コントローラとして使うことができる。
・1ポートから6ポートまで設定できる。
・データポートを32、64、128ビットのバス幅に設定できる。
・2つの両方向ポートと4つの片方向ポートがある。
5. 8個までのバンクを同時に開くことが出来る。（これは凄い、私の作ったコントローラは1つのバンクしか開かない、でもプリチャージは自分で管理するのかな？）
6. ハードマクロでコントローラ、PHYが内蔵されている。
7. それぞれのMCBで使用するピン配置は決定されている。（これも性能を取ったらそうなるだろう？）
8. メモリデバイスのパラメータは設定可能。
・ドライバのドライブ強度
・On-Die Termination(ODT)
・CAS Latency
・Self refresh
・リフレッシュ間隔
・Write recovery time
9. Readの時のDQSとDQの自動遅延キャリブレーション
10. FPGAon-chip input terminationのオプションの自動キャリブレーション
11. COER Generator とEDKでサポート
・MIGでサポート
・EDKからはマルチポートのメモリ・コントローラ(MPMC)IPとしてサポート
component MCB
generic (
ARB_NUM_TIME_SLOTS : integer := 12;
ARB_TIME_SLOT_0 : bit_vector := "111111111111111111";
ARB_TIME_SLOT_1 : bit_vector := "111111111111111111";
ARB_TIME_SLOT_10 : bit_vector := "111111111111111111";
ARB_TIME_SLOT_11 : bit_vector := "111111111111111111";
ARB_TIME_SLOT_2 : bit_vector := "111111111111111111";
ARB_TIME_SLOT_3 : bit_vector := "111111111111111111";
ARB_TIME_SLOT_4 : bit_vector := "111111111111111111";
ARB_TIME_SLOT_5 : bit_vector := "111111111111111111";
ARB_TIME_SLOT_6 : bit_vector := "111111111111111111";
ARB_TIME_SLOT_7 : bit_vector := "111111111111111111";
ARB_TIME_SLOT_8 : bit_vector := "111111111111111111";
ARB_TIME_SLOT_9 : bit_vector := "111111111111111111";
CAL_BA : bit_vector := X"0";
CAL_BYPASS : string := "YES";
CAL_CA : bit_vector := X"000";
CAL_CALIBRATION_MODE : string := "NOCALIBRATION";
CAL_CLK_DIV : integer := 1;
CAL_DELAY : string := "QUARTER";
CAL_RA : bit_vector := X"0000";
MEM_ADDR_ORDER : string := "BANK_ROW_COLUMN";
MEM_BA_SIZE : integer := 3;
MEM_BURST_LEN : integer := 8;
MEM_CAS_LATENCY : integer := 4;
MEM_CA_SIZE : integer := 11;
MEM_DDR1_2_ODS : string := "FULL";
MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
MEM_DDR2_3_PA_SR : string := "FULL";
MEM_DDR2_ADD_LATENCY : integer := 0;
MEM_DDR2_DIFF_DQS_EN : string := "YES";
MEM_DDR2_RTT : string := "50OHMS";
MEM_DDR2_WRT_RECOVERY : integer := 4;
MEM_DDR3_ADD_LATENCY : string := "OFF";
MEM_DDR3_AUTO_SR : string := "ENABLED";
MEM_DDR3_CAS_LATENCY : integer := 7;
MEM_DDR3_CAS_WR_LATENCY : integer := 5;
MEM_DDR3_DYN_WRT_ODT : string := "OFF";
MEM_DDR3_ODS : string := "DIV7";
MEM_DDR3_RTT : string := "DIV2";
MEM_DDR3_WRT_RECOVERY : integer := 7;
MEM_MDDR_ODS : string := "FULL";
MEM_MOBILE_PA_SR : string := "FULL";
MEM_MOBILE_TC_SR : integer := 0;
MEM_RAS_VAL : integer := 0;
MEM_RA_SIZE : integer := 13;
MEM_RCD_VAL : integer := 1;
MEM_REFI_VAL : integer := 0;
MEM_RFC_VAL : integer := 0;
MEM_RP_VAL : integer := 0;
MEM_RTP_VAL : integer := 0;
MEM_TYPE : string := "DDR3";
MEM_WIDTH : integer := 4;
MEM_WR_VAL : integer := 0;
MEM_WTR_VAL : integer := 3;
PORT_CONFIG : string := "B32_B32_B32_B32"
);
port (
ADDR : out std_logic_vector(14 downto 0);
BA : out std_logic_vector(2 downto 0);
CAS : out std_ulogic;
CKE : out std_ulogic;
DQIOWEN0 : out std_ulogic;
DQON : out std_logic_vector(15 downto 0);
DQOP : out std_logic_vector(15 downto 0);
DQSIOWEN90N : out std_ulogic;
DQSIOWEN90P : out std_ulogic;
IOIDRPADD : out std_ulogic;
IOIDRPADDR : out std_logic_vector(4 downto 0);
IOIDRPBROADCAST : out std_ulogic;
IOIDRPCLK : out std_ulogic;
IOIDRPCS : out std_ulogic;
IOIDRPSDO : out std_ulogic;
IOIDRPTRAIN : out std_ulogic;
IOIDRPUPDATE : out std_ulogic;
LDMN : out std_ulogic;
LDMP : out std_ulogic;
ODT : out std_ulogic;
P0CMDEMPTY : out std_ulogic;
P0CMDFULL : out std_ulogic;
P0RDCOUNT : out std_logic_vector(6 downto 0);
P0RDDATA : out std_logic_vector(31 downto 0);
P0RDEMPTY : out std_ulogic;
P0RDERROR : out std_ulogic;
P0RDFULL : out std_ulogic;
P0RDOVERFLOW : out std_ulogic;
P0WRCOUNT : out std_logic_vector(6 downto 0);
P0WREMPTY : out std_ulogic;
P0WRERROR : out std_ulogic;
P0WRFULL : out std_ulogic;
P0WRUNDERRUN : out std_ulogic;
P1CMDEMPTY : out std_ulogic;
P1CMDFULL : out std_ulogic;
P1RDCOUNT : out std_logic_vector(6 downto 0);
P1RDDATA : out std_logic_vector(31 downto 0);
P1RDEMPTY : out std_ulogic;
P1RDERROR : out std_ulogic;
P1RDFULL : out std_ulogic;
P1RDOVERFLOW : out std_ulogic;
P1WRCOUNT : out std_logic_vector(6 downto 0);
P1WREMPTY : out std_ulogic;
P1WRERROR : out std_ulogic;
P1WRFULL : out std_ulogic;
P1WRUNDERRUN : out std_ulogic;
P2CMDEMPTY : out std_ulogic;
P2CMDFULL : out std_ulogic;
P2COUNT : out std_logic_vector(6 downto 0);
P2EMPTY : out std_ulogic;
P2ERROR : out std_ulogic;
P2FULL : out std_ulogic;
P2RDDATA : out std_logic_vector(31 downto 0);
P2RDOVERFLOW : out std_ulogic;
P2WRUNDERRUN : out std_ulogic;
P3CMDEMPTY : out std_ulogic;
P3CMDFULL : out std_ulogic;
P3COUNT : out std_logic_vector(6 downto 0);
P3EMPTY : out std_ulogic;
P3ERROR : out std_ulogic;
P3FULL : out std_ulogic;
P3RDDATA : out std_logic_vector(31 downto 0);
P3RDOVERFLOW : out std_ulogic;
P3WRUNDERRUN : out std_ulogic;
P4CMDEMPTY : out std_ulogic;
P4CMDFULL : out std_ulogic;
P4COUNT : out std_logic_vector(6 downto 0);
P4EMPTY : out std_ulogic;
P4ERROR : out std_ulogic;
P4FULL : out std_ulogic;
P4RDDATA : out std_logic_vector(31 downto 0);
P4RDOVERFLOW : out std_ulogic;
P4WRUNDERRUN : out std_ulogic;
P5CMDEMPTY : out std_ulogic;
P5CMDFULL : out std_ulogic;
P5COUNT : out std_logic_vector(6 downto 0);
P5EMPTY : out std_ulogic;
P5ERROR : out std_ulogic;
P5FULL : out std_ulogic;
P5RDDATA : out std_logic_vector(31 downto 0);
P5RDOVERFLOW : out std_ulogic;
P5WRUNDERRUN : out std_ulogic;
RAS : out std_ulogic;
RST : out std_ulogic;
SELFREFRESHMODE : out std_ulogic;
STATUS : out std_logic_vector(31 downto 0);
UDMN : out std_ulogic;
UDMP : out std_ulogic;
UOCALSTART : out std_ulogic;
UOCMDREADYIN : out std_ulogic;
UODATA : out std_logic_vector(7 downto 0);
UODATAVALID : out std_ulogic;
UODONECAL : out std_ulogic;
UOREFRSHFLAG : out std_ulogic;
UOSDO : out std_ulogic;
WE : out std_ulogic;
DQI : in std_logic_vector(15 downto 0);
DQSIOIN : in std_ulogic;
DQSIOIP : in std_ulogic;
IOIDRPSDI : in std_ulogic;
P0ARBEN : in std_ulogic;
P0CMDBA : in std_logic_vector(2 downto 0);
P0CMDBL : in std_logic_vector(5 downto 0);
P0CMDCA : in std_logic_vector(11 downto 0);
P0CMDCLK : in std_ulogic;
P0CMDEN : in std_ulogic;
P0CMDINSTR : in std_logic_vector(2 downto 0);
P0CMDRA : in std_logic_vector(14 downto 0);
P0RDCLK : in std_ulogic;
P0RDEN : in std_ulogic;
P0RWRMASK : in std_logic_vector(3 downto 0);
P0WRCLK : in std_ulogic;
P0WRDATA : in std_logic_vector(31 downto 0);
P0WREN : in std_ulogic;
P1ARBEN : in std_ulogic;
P1CMDBA : in std_logic_vector(2 downto 0);
P1CMDBL : in std_logic_vector(5 downto 0);
P1CMDCA : in std_logic_vector(11 downto 0);
P1CMDCLK : in std_ulogic;
P1CMDEN : in std_ulogic;
P1CMDINSTR : in std_logic_vector(2 downto 0);
P1CMDRA : in std_logic_vector(14 downto 0);
P1RDCLK : in std_ulogic;
P1RDEN : in std_ulogic;
P1RWRMASK : in std_logic_vector(3 downto 0);
P1WRCLK : in std_ulogic;
P1WRDATA : in std_logic_vector(31 downto 0);
P1WREN : in std_ulogic;
P2ARBEN : in std_ulogic;
P2CLK : in std_ulogic;
P2CMDBA : in std_logic_vector(2 downto 0);
P2CMDBL : in std_logic_vector(5 downto 0);
P2CMDCA : in std_logic_vector(11 downto 0);
P2CMDCLK : in std_ulogic;
P2CMDEN : in std_ulogic;
P2CMDINSTR : in std_logic_vector(2 downto 0);
P2CMDRA : in std_logic_vector(14 downto 0);
P2EN : in std_ulogic;
P2WRDATA : in std_logic_vector(31 downto 0);
P2WRMASK : in std_logic_vector(3 downto 0);
P3ARBEN : in std_ulogic;
P3CLK : in std_ulogic;
P3CMDBA : in std_logic_vector(2 downto 0);
P3CMDBL : in std_logic_vector(5 downto 0);
P3CMDCA : in std_logic_vector(11 downto 0);
P3CMDCLK : in std_ulogic;
P3CMDEN : in std_ulogic;
P3CMDINSTR : in std_logic_vector(2 downto 0);
P3CMDRA : in std_logic_vector(14 downto 0);
P3EN : in std_ulogic;
P3WRDATA : in std_logic_vector(31 downto 0);
P3WRMASK : in std_logic_vector(3 downto 0);
P4ARBEN : in std_ulogic;
P4CLK : in std_ulogic;
P4CMDBA : in std_logic_vector(2 downto 0);
P4CMDBL : in std_logic_vector(5 downto 0);
P4CMDCA : in std_logic_vector(11 downto 0);
P4CMDCLK : in std_ulogic;
P4CMDEN : in std_ulogic;
P4CMDINSTR : in std_logic_vector(2 downto 0);
P4CMDRA : in std_logic_vector(14 downto 0);
P4EN : in std_ulogic;
P4WRDATA : in std_logic_vector(31 downto 0);
P4WRMASK : in std_logic_vector(3 downto 0);
P5ARBEN : in std_ulogic;
P5CLK : in std_ulogic;
P5CMDBA : in std_logic_vector(2 downto 0);
P5CMDBL : in std_logic_vector(5 downto 0);
P5CMDCA : in std_logic_vector(11 downto 0);
P5CMDCLK : in std_ulogic;
P5CMDEN : in std_ulogic;
P5CMDINSTR : in std_logic_vector(2 downto 0);
P5CMDRA : in std_logic_vector(14 downto 0);
P5EN : in std_ulogic;
P5WRDATA : in std_logic_vector(31 downto 0);
P5WRMASK : in std_logic_vector(3 downto 0);
PLLCE : in std_logic_vector(1 downto 0);
PLLCLK : in std_logic_vector(1 downto 0);
PLLLOCK : in std_ulogic;
RECAL : in std_ulogic;
SELFREFRESHENTER : in std_ulogic;
SYSRST : in std_ulogic;
UDQSIOIN : in std_ulogic;
UDQSIOIP : in std_ulogic;
UIADD : in std_ulogic;
UIADDR : in std_logic_vector(4 downto 0);
UIBROADCAST : in std_ulogic;
UICLK : in std_ulogic;
UICMD : in std_ulogic;
UICMDEN : in std_ulogic;
UICMDIN : in std_ulogic;
UICS : in std_ulogic;
UIDONECAL : in std_ulogic;
UIDQCOUNT : in std_logic_vector(3 downto 0);
UIDQLOWERDEC : in std_ulogic;
UIDQLOWERINC : in std_ulogic;
UIDQUPPERDEC : in std_ulogic;
UIDQUPPERINC : in std_ulogic;
UIDRPUPDATE : in std_ulogic;
UILDQSDEC : in std_ulogic;
UILDQSINC : in std_ulogic;
UIREAD : in std_ulogic;
UISDI : in std_ulogic;
UIUDQSDEC : in std_ulogic;
UIUDQSINC : in std_ulogic
);
end component;
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_always.v
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_always_on_edge.v
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_arbiter.v
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_bits.v
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_change.v
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_code_distance.v
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_cycle_sequence.v
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_decrement.v
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_delta.v
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_even_parity.v
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_fifo.v
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_fifo_index.v
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_frame.v
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_handshake.v
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_hold_value.v
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_implication.v
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_increment.v
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_memory_async.v
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_memory_sync.v
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_multiport_fifo.v
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_mutex.v
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_never.v
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_never_unknown.v
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_never_unknown_async.v
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_next.v
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_next_state.v
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_no_contention.v
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_no_overflow.v
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_no_transition.v
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_no_underflow.v
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_odd_parity.v
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_one_cold.v
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_one_hot.v
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_proposition.v
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_quiescent_state.v
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_range.v
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_reg_loaded.v
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_req_ack_unique.v
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_req_requires.v
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_stack.v
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_time.v
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_transition.v
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_unchange.v
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_valid_id.v
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_value.v
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_width.v
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_window.v
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_win_change.v
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_win_unchange.v
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_zero_one_hot.v
vhpcomp -work accellera_ovl_vhdl H:\HDL\OVL\std_ovl\std_ovl.vhd
vhpcomp -work accellera_ovl_vhdl H:\HDL\OVL\std_ovl\std_ovl_procs.vhd
vhpcomp -work accellera_ovl_vhdl H:\HDL\OVL\std_ovl\std_ovl_components_vlog.vhd
vhpcomp -work accellera_ovl_vhdl H:\HDL\OVL\std_ovl\std_ovl_clock_gating.vhd
vhpcomp -work accellera_ovl_vhdl H:\HDL\OVL\std_ovl\std_ovl_reset_gating.vhd
vhpcomp -work accellera_ovl_vhdl H:\HDL\OVL\std_ovl\ovl_always.vhd
vhpcomp -work accellera_ovl_vhdl H:\HDL\OVL\std_ovl\ovl_cycle_sequence.vhd
vhpcomp -work accellera_ovl_vhdl H:\HDL\OVL\std_ovl\ovl_implication.vhd
vhpcomp -work accellera_ovl_vhdl H:\HDL\OVL\std_ovl\ovl_never.vhd
vhpcomp -work accellera_ovl_vhdl H:\HDL\OVL\std_ovl\ovl_never_unknown.vhd
vhpcomp -work accellera_ovl_vhdl H:\HDL\OVL\std_ovl\ovl_never_unknown_async.vhd
vhpcomp -work accellera_ovl_vhdl H:\HDL\OVL\std_ovl\ovl_next.vhd
vhpcomp -work accellera_ovl_vhdl H:\HDL\OVL\std_ovl\ovl_one_hot.vhd
vhpcomp -work accellera_ovl_vhdl H:\HDL\OVL\std_ovl\ovl_range.vhd
vhpcomp -work accellera_ovl_vhdl H:\HDL\OVL\std_ovl\ovl_zero_one_hot.vhd
vhpcomp -work accellera_ovl_vhdl H:\HDL\OVL\vhdl93\ovl_always_rtl.vhd
vhpcomp -work accellera_ovl_vhdl H:\HDL\OVL\vhdl93\ovl_cycle_sequence_rtl.vhd
vhpcomp -work accellera_ovl_vhdl H:\HDL\OVL\vhdl93\ovl_implication_rtl.vhd
vhpcomp -work accellera_ovl_vhdl H:\HDL\OVL\vhdl93\ovl_never_rtl.vhd
vhpcomp -work accellera_ovl_vhdl H:\HDL\OVL\vhdl93\ovl_never_unknown_async_rtl.vhd
vhpcomp -work accellera_ovl_vhdl H:\HDL\OVL\vhdl93\ovl_never_unknown_rtl.vhd
vhpcomp -work accellera_ovl_vhdl H:\HDL\OVL\vhdl93\ovl_next_rtl.vhd
vhpcomp -work accellera_ovl_vhdl H:\HDL\OVL\vhdl93\ovl_one_hot_rtl.vhd
vhpcomp -work accellera_ovl_vhdl H:\HDL\OVL\vhdl93\ovl_range_rtl.vhd
vhpcomp -work accellera_ovl_vhdl H:\HDL\OVL\vhdl93\ovl_zero_one_hot_rtl.vhd
accellera_ovl_vlog=$XILINX/verilog/hdp/nt/accellera_ovl_vlog
accellera_ovl_vhdl=$XILINX/vhdl/hdp/nt/accellera_ovl_vhdl
1. ファイル名だけをNotepad++にコピーして、.vhdファイルを除いた。
2. 最初にOVL_Verilog_Lib_Comp.do を作って、vlogcompコマンドを1つのVerilogファイル毎に1行とした。vlogcomp -f OVL_Verilog_Lib_Comp.doでファイルを読んで実行させたが、エラー。どうも複数行あるとダメらしい。
3. 次に、ISim Helpに、vlogcomp suba.v subb.vの例があったので、同様に51個のVerilogファイル名をつないで実行させたら、途中でエラーになった。
4. それではと、2. で作ったOVL_Verilog_Lib_Comp.doをOVL_Verilog_Lib_Comp.batと名前を変えて、バッチファイルとして実行したら、うまく行った。
vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i H:\HDL\OVL\std_ovl -work accellera_ovl_vlog H:\HDL\OVL\std_ovl\ovl_always.v
1. LVDSなどで使用される差動信号の100Ω終端抵抗がFPGA内に内蔵されたそうだ。UCFの構文は、
NET ＜I/O_NAME＞ DIFF_TERM = "＜TRUE/FALSE＞";
2. DDRシリーズのSDRAMにインターフェース用の終端抵抗が内蔵された。(Virtexシリーズでは以前から機能があった）
3. IOパッドの出力ドライバの出力インピーダンスも変更可能。
1. IDDR2とODDR2は特に目立った変更はないようだ。
2. I/O遅延はリングオシレータとカウンタを使ったユニークな方式。1クロックサイクル未満の遅延となる。遅延タップの平均値は 80ps
3. 1つのISERDES2、OSEDES2では1:1～1：4まで、2つ使うと1:8までのSERDES（シリアルーパラレル変換）が可能。
4. 2つのISERDES2を使用して、位相検出器を構成することができるようだ。これは、差動信号のみとなる。
5. OSERDES2にはトレーニング機能があって、これをONにすると、指定のトレーニングパターンを送出するそうだ。DDR? メモリのトレーニングパターン送出時に都合がよい。
// DCM module
`default_nettype none
`timescale 1ns / 1ps
module dcm_inst(clkin, reset, clkout, clkfx, clkdv, locked);
input clkin;
input reset;
output clkout;
output clkfx;
output clkdv;
output locked;
wire clkin;
wire reset;
wire clkout;
wire clkfx;
wire clkdv;
wire locked;
wire clkout_node;
DCM_CLKGEN_I DCM_CLKGEN_I_inst
(// Clock in ports
.CLK_IN1 (clkin), // IN
.CLK_OUT1 (clkout_node), // OUT
.RESET (reset), // IN
.LOCKED (locked)); // OUT
assign clkout = clkout_node;
assign clkfx = clkout_node;
assign clkdv = clkout_node;
endmodule
Maximum Clock Path at Slow Process Corner: clk to CharDispCtrler_inst/blue_node
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
AB12.I Tiopi 0.904 clk
clk
dcm_inst_0/DCM_CLKGEN_I_inst/clkin1_buf
ProtoComp48.IMUX
DCM_X0Y1.CLKIN net (fanout=1) 2.930 dcm_inst_0/DCM_CLKGEN_I_inst/clkin1
DCM_X0Y1.CLKFX Tdmcko_CLKFX 0.350 dcm_inst_0/DCM_CLKGEN_I_inst/dcm_clkgen_inst
dcm_inst_0/DCM_CLKGEN_I_inst/dcm_clkgen_inst
BUFGMUX_X2Y3.I0 net (fanout=1) 0.941 dcm_inst_0/DCM_CLKGEN_I_inst/clkfx
BUFGMUX_X2Y3.O Tgi0o 0.209 dcm_inst_0/DCM_CLKGEN_I_inst/clkout1_buf
dcm_inst_0/DCM_CLKGEN_I_inst/clkout1_buf
SLICE_X17Y14.CLK net (fanout=55) 1.383 clkdv
------------------------------------------------- ---------------------------
Total 6.717ns (1.463ns logic, 5.254ns route)
(21.8% logic, 78.2% route)
// DCM module
`default_nettype none
`timescale 1ns / 1ps
module dcm_inst(clkin, reset, clkout, clkfx, clkdv, locked);
input clkin;
input reset;
output clkout;
output clkfx;
output clkdv;
output locked;
wire clkin;
wire reset;
wire clkout;
wire clkfx;
wire clkdv;
wire locked;
wire clk_ibuf;
wire clkfb, clkfx_node;
wire gnd, clk_node;
wire clkdv_node, clkdv_bufg;
assign gnd = 1'b0;
IBUFG IBUFG_inst (
.I(clkin),
.O(clk_ibuf)
);
DCM DCM_INST1 (
.CLKIN(clk_ibuf),
.CLKFB(clkfb),
.DSSEN(gnd),
.PSINCDEC(gnd),
.PSEN(gnd),
.PSCLK(gnd),
.RST(gnd), // リセットごとにDCMのロックが外れないようにgndにしておく
.CLK0(clk_node),
.CLK90(),
.CLK180(),
.CLK270(),
.CLK2X(),
.CLK2X180(),
.CLKDV(clkdv_node),
.CLKFX(clkfx_node),
.CLKFX180(),
.LOCKED(locked),
.PSDONE(),
.STATUS()
);
defparam DCM_INST1.CLKIN_PERIOD = 20.0;
defparam DCM_INST1.DLL_FREQUENCY_MODE = "LOW";
defparam DCM_INST1.DUTY_CYCLE_CORRECTION = "TRUE";
defparam DCM_INST1.CLKDV_DIVIDE = 2.0;
defparam DCM_INST1.PHASE_SHIFT = 0;
defparam DCM_INST1.CLKOUT_PHASE_SHIFT = "NONE";
defparam DCM_INST1.STARTUP_WAIT = "FALSE";
defparam DCM_INST1.FACTORY_JF = 16'hFFFF;
BUFG BUFG_inst(
.I(clk_node),
.O(clkfb)
);
BUFG BUFG_clkfx(
.I(clkfx_node),
.O(clkfx)
);
BUFG BUFG_clkdv(
.I(clkdv_node),
.O(clkdv_bufg)
);
assign clkout = clkdv_bufg;
assign clkdv = clkdv_bufg;
endmodule
NET "clk" TNM_NET = "clk";
TIMESPEC "TS_clk" = PERIOD "clk" 20 ns HIGH 50 %;
NET "VGA_BLUE" OFFSET = OUT 20 ns AFTER "clk";
Maximum Clock Path at Slow Process Corner: clk to CharDispCtrler_inst/blue_node
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
N4.I Tiopi 0.904 clk
clk
dcm_inst_0/IBUFG_inst
ProtoComp52.IMUX
BUFIO2_X1Y15.I net (fanout=1) 2.177 dcm_inst_0/clk_ibuf
BUFIO2_X1Y15.DIVCLK Tbufcko_DIVCLK 0.170 SP6_BUFIO_INSERT_ML_BUFIO2_0
SP6_BUFIO_INSERT_ML_BUFIO2_0
DCM_X0Y1.CLKIN net (fanout=1) 0.843 dcm_inst_0/DCM_INST1_ML_NEW_DIVCLK
DCM_X0Y1.CLKDV Tdmcko_CLKDV -5.680 dcm_inst_0/DCM_INST1
dcm_inst_0/DCM_INST1
BUFGMUX_X2Y3.I0 net (fanout=1) 0.941 dcm_inst_0/clkdv_node
BUFGMUX_X2Y3.O Tgi0o 0.209 dcm_inst_0/BUFG_clkdv
dcm_inst_0/BUFG_clkdv
SLICE_X18Y12.CLK net (fanout=54) 1.382 clkdv
------------------------------------------------- ---------------------------
Total 0.946ns (-4.397ns logic, 5.343ns route)
// assign clkdv = clkdv_bufg;
assign clkdv = clkfb;
Maximum Clock Path at Slow Process Corner: clk to CharDispCtrler_inst/blue_node
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
N4.I Tiopi 0.904 clk
clk
dcm_inst_0/IBUFG_inst
ProtoComp48.IMUX
BUFIO2_X1Y15.I net (fanout=1) 2.177 dcm_inst_0/clk_ibuf
BUFIO2_X1Y15.DIVCLK Tbufcko_DIVCLK 0.170 SP6_BUFIO_INSERT_ML_BUFIO2_0
SP6_BUFIO_INSERT_ML_BUFIO2_0
DCM_X0Y1.CLKIN net (fanout=1) 0.843 dcm_inst_0/DCM_INST1_ML_NEW_DIVCLK
DCM_X0Y1.CLK0 Tdmcko_CLK -5.694 dcm_inst_0/DCM_INST1
dcm_inst_0/DCM_INST1
BUFGMUX_X2Y3.I0 net (fanout=1) 0.941 dcm_inst_0/clk_node
BUFGMUX_X2Y3.O Tgi0o 0.209 dcm_inst_0/BUFG_inst
dcm_inst_0/BUFG_inst
SLICE_X17Y14.CLK net (fanout=56) 1.383 clkdv
------------------------------------------------- ---------------------------
Total 0.933ns (-4.411ns logic, 5.344ns route)
• CLKFX および CLKFX180で低出力ジッタ
• CLKIN でのジッタ許容を改善
• M および D 値をダイナミック プログラミング。
CLKFX_MULTIPLY および CLKFX_DIVIDE 属性を上書き し ます。
• 固定 CLKFX_MULTIPLY および CLKFX_DIVIDE 属性よ り 幅広い範囲から M および D 値を指定
• CLKFXDV で CLKFX 出力を追加逓倍
• 入力クロック 損失の場合のフリーランニング オシレータ
• スペクトラム拡散クロック生成
1. 超高速のロースキューI/Oリージョナル クロック リソースが40個ある。
2. BUFGMUXで駆動されるグローバル・クロックネットワークとI/Oクロック・バッファ(BUFIO2)、PLLクロックバッファ(BUFPLL)で駆動されるI/Oクロック・ネットワークがある。
3. BUFPLL及びBUFIO2は、ISEDESとOSERDESを駆動する。
4. BUFIO2はDDRバスのILOGIC及びOLOGICを駆動することができる。グローバル・クロック、DCMのGTPクロック、PLLクロック入力へ配線することができる。
| 日 | 月 | 火 | 水 | 木 | 金 | 土 |
|---|---|---|---|---|---|---|
| - | - | - | - | 1 | 2 | 3 |
| 4 | 5 | 6 | 7 | 8 | 9 | 10 |
| 11 | 12 | 13 | 14 | 15 | 16 | 17 |
| 18 | 19 | 20 | 21 | 22 | 23 | 24 |
| 25 | 26 | 27 | 28 | 29 | 30 | - |