// Instantiate the Unit Under Test (UUT) fifo32_16 uut ( .rst(rst), .wr_clk(wr_clk), .rd_clk(rd_clk), .din(din), .wr_en(wr_en), .rd_en(rd_en), .dout(dout), .full(full), .overflow(overflow), .empty(empty), .underflow(underflow), .wr_data_count(wr_data_count) );
// wr_clk always begin #(WR_CLK_PERIOD/2) wr_clk = 1'b1 ; #(WR_CLK_PERIOD/2) wr_clk = 1'b0 ; end
// rd_clk always begin #(RD_CLK_PERIOD/2) rd_clk = 1'b1 ; #(RD_CLK_PERIOD/2) rd_clk = 1'b0 ; end
always @(posedge wr_clk, posedge rst) begin if (rst) din <= 32'd0; else din <= din + 32'd1; end
WARNING: Behavioral models for independent clock FIFO configurations are not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
always @(posedge clk) begin if (reset) begin dvi_de <= 1'b0; dvi_h <= 1'b1; dvi_v <= 1'b1; end else begin dvi_de <= display_enable; dvi_h <= vga_hsync; dvi_v <= vga_vsync; end end
// dvi_xclk_p : clkbと同位相 ODDR2 #( .DDR_ALIGNMENT("C0"), // Sets output alignment to "NONE", "C0" or "C1" .INIT(1'b0), // Sets initial state of the Q output to 1’b0 or 1’b1 .SRTYPE("ASYNC") // Specifies "SYNC" or "ASYNC" set/reset ) ODDR2_xclk_p ( .Q(dvi_xclk_p), // 1-bit DDR output data .C0(clk90), // 1-bit clock input .C1(clk90b), // 1-bit clock input .CE(1'b1), // 1-bit clock enable input .D0(1'b1), // 1-bit data input (associated with C0) .D1(1'b0), // 1-bit data input (associated with C1) .R(reset), // 1-bit reset input .S(1'b0) // 1-bit set input );
// dvi_xclk_n : clkと同位相 ODDR2 #( .DDR_ALIGNMENT("C0"), // Sets output alignment to "NONE", "C0" or "C1" .INIT(1'b1), // Sets initial state of the Q output to 1’b0 or 1’b1 .SRTYPE("ASYNC") // Specifies "SYNC" or "ASYNC" set/reset ) ODDR2_xclk_n ( .Q(dvi_xclk_n), // 1-bit DDR output data .C0(clk90), // 1-bit clock input .C1(clk90b), // 1-bit clock input .CE(1'b1), // 1-bit clock enable input .D0(1'b0), // 1-bit data input (associated with C0) .D1(1'b1), // 1-bit data input (associated with C1) .R(reset), // 1-bit reset input .S(1'b0) // 1-bit set input );
// DVI_D// DVI_D[0] ODDR2 #( .DDR_ALIGNMENT("C0"), // Sets output alignment to "NONE", "C0" or "C1" .INIT(1'b0), // Sets initial state of the Q output to 1’b0 or 1’b1 .SRTYPE("ASYNC") // Specifies "SYNC" or "ASYNC" set/reset ) ODDR2_D0 ( .Q(dvi_d[0]), // 1-bit DDR output data .C0(clk), // 1-bit clock input .C1(clkb), // 1-bit clock input .CE(1'b1), // 1-bit clock enable input .D0(vga_blue), // B0[0], 1-bit data input (associated with C0) .D1(vga_green), // G0[4], 1-bit data input (associated with C1) .R(reset), // 1-bit reset input .S(1'b0) // 1-bit set input );
ODDR2 #( // DVI_D[1] .DDR_ALIGNMENT("C0"), // Sets output alignment to "NONE", "C0" or "C1" .INIT(1'b0), // Sets initial state of the Q output to 1’b0 or 1’b1 .SRTYPE("ASYNC") // Specifies "SYNC" or "ASYNC" set/reset ) ODDR2_D1 ( .Q(dvi_d[1]), // 1-bit DDR output data .C0(clk), // 1-bit clock input .C1(clkb), // 1-bit clock input .CE(1'b1), // 1-bit clock enable input .D0(vga_blue), // B0[1], 1-bit data input (associated with C0) .D1(vga_green), // G0[5], 1-bit data input (associated with C1) .R(reset), // 1-bit reset input .S(1'b0) // 1-bit set input );
ODDR2 #( // DVI_D[2] .DDR_ALIGNMENT("C0"), // Sets output alignment to "NONE", "C0" or "C1" .INIT(1'b0), // Sets initial state of the Q output to 1’b0 or 1’b1 .SRTYPE("ASYNC") // Specifies "SYNC" or "ASYNC" set/reset ) ODDR2_D2 ( .Q(dvi_d[2]), // 1-bit DDR output data .C0(clk), // 1-bit clock input .C1(clkb), // 1-bit clock input .CE(1'b1), // 1-bit clock enable input .D0(vga_blue), // B0[2], 1-bit data input (associated with C0) .D1(vga_green), // G0[6], 1-bit data input (associated with C1) .R(reset), // 1-bit reset input .S(1'b0) // 1-bit set input );
ODDR2 #( // DVI_D[3] .DDR_ALIGNMENT("C0"), // Sets output alignment to "NONE", "C0" or "C1" .INIT(1'b0), // Sets initial state of the Q output to 1’b0 or 1’b1 .SRTYPE("ASYNC") // Specifies "SYNC" or "ASYNC" set/reset ) ODDR2_D3 ( .Q(dvi_d[3]), // 1-bit DDR output data .C0(clk), // 1-bit clock input .C1(clkb), // 1-bit clock input .CE(1'b1), // 1-bit clock enable input .D0(vga_blue), // B0[3], 1-bit data input (associated with C0) .D1(vga_green), // G0[7], 1-bit data input (associated with C1) .R(reset), // 1-bit reset input .S(1'b0) // 1-bit set input );
ODDR2 #( // DVI_D[4] .DDR_ALIGNMENT("C0"), // Sets output alignment to "NONE", "C0" or "C1" .INIT(1'b0), // Sets initial state of the Q output to 1’b0 or 1’b1 .SRTYPE("ASYNC") // Specifies "SYNC" or "ASYNC" set/reset ) ODDR2_D4 ( .Q(dvi_d[4]), // 1-bit DDR output data .C0(clk), // 1-bit clock input .C1(clkb), // 1-bit clock input .CE(1'b1), // 1-bit clock enable input .D0(vga_blue), // B0[4], 1-bit data input (associated with C0) .D1(vga_red), // R0[0], 1-bit data input (associated with C1) .R(reset), // 1-bit reset input .S(1'b0) // 1-bit set input );
ODDR2 #( // DVI_D[5] .DDR_ALIGNMENT("C0"), // Sets output alignment to "NONE", "C0" or "C1" .INIT(1'b0), // Sets initial state of the Q output to 1’b0 or 1’b1 .SRTYPE("ASYNC") // Specifies "SYNC" or "ASYNC" set/reset ) ODDR2_D5 ( .Q(dvi_d[5]), // 1-bit DDR output data .C0(clk), // 1-bit clock input .C1(clkb), // 1-bit clock input .CE(1'b1), // 1-bit clock enable input .D0(vga_blue), // B0[5], 1-bit data input (associated with C0) .D1(vga_red), // R0[1], 1-bit data input (associated with C1) .R(reset), // 1-bit reset input .S(1'b0) // 1-bit set input );
ODDR2 #( // DVI_D[6] .DDR_ALIGNMENT("C0"), // Sets output alignment to "NONE", "C0" or "C1" .INIT(1'b0), // Sets initial state of the Q output to 1’b0 or 1’b1 .SRTYPE("ASYNC") // Specifies "SYNC" or "ASYNC" set/reset ) ODDR2_D6 ( .Q(dvi_d[6]), // 1-bit DDR output data .C0(clk), // 1-bit clock input .C1(clkb), // 1-bit clock input .CE(1'b1), // 1-bit clock enable input .D0(vga_blue), // B0[6], 1-bit data input (associated with C0) .D1(vga_red), // R0[2], 1-bit data input (associated with C1) .R(reset), // 1-bit reset input .S(1'b0) // 1-bit set input );
ODDR2 #( // DVI_D[7] .DDR_ALIGNMENT("C0"), // Sets output alignment to "NONE", "C0" or "C1" .INIT(1'b0), // Sets initial state of the Q output to 1’b0 or 1’b1 .SRTYPE("ASYNC") // Specifies "SYNC" or "ASYNC" set/reset ) ODDR2_D7 ( .Q(dvi_d[7]), // 1-bit DDR output data .C0(clk), // 1-bit clock input .C1(clkb), // 1-bit clock input .CE(1'b1), // 1-bit clock enable input .D0(vga_blue), // B0[7], 1-bit data input (associated with C0) .D1(vga_red), // R0[3], 1-bit data input (associated with C1) .R(reset), // 1-bit reset input .S(1'b0) // 1-bit set input );
ODDR2 #( // DVI_D[8] .DDR_ALIGNMENT("C0"), // Sets output alignment to "NONE", "C0" or "C1" .INIT(1'b0), // Sets initial state of the Q output to 1’b0 or 1’b1 .SRTYPE("ASYNC") // Specifies "SYNC" or "ASYNC" set/reset ) ODDR2_D8 ( .Q(dvi_d[8]), // 1-bit DDR output data .C0(clk), // 1-bit clock input .C1(clkb), // 1-bit clock input .CE(1'b1), // 1-bit clock enable input .D0(vga_green), // G0[0], 1-bit data input (associated with C0) .D1(vga_red), // R0[4], 1-bit data input (associated with C1) .R(reset), // 1-bit reset input .S(1'b0) // 1-bit set input );
ODDR2 #( // DVI_D[9] .DDR_ALIGNMENT("C0"), // Sets output alignment to "NONE", "C0" or "C1" .INIT(1'b0), // Sets initial state of the Q output to 1’b0 or 1’b1 .SRTYPE("ASYNC") // Specifies "SYNC" or "ASYNC" set/reset ) ODDR2_D9 ( .Q(dvi_d[9]), // 1-bit DDR output data .C0(clk), // 1-bit clock input .C1(clkb), // 1-bit clock input .CE(1'b1), // 1-bit clock enable input .D0(vga_green), // G0[1], 1-bit data input (associated with C0) .D1(vga_red), // R0[5], 1-bit data input (associated with C1) .R(reset), // 1-bit reset input .S(1'b0) // 1-bit set input );
ODDR2 #( // DVI_D[10] .DDR_ALIGNMENT("C0"), // Sets output alignment to "NONE", "C0" or "C1" .INIT(1'b0), // Sets initial state of the Q output to 1’b0 or 1’b1 .SRTYPE("ASYNC") // Specifies "SYNC" or "ASYNC" set/reset ) ODDR2_D10 ( .Q(dvi_d[10]), // 1-bit DDR output data .C0(clk), // 1-bit clock input .C1(clkb), // 1-bit clock input .CE(1'b1), // 1-bit clock enable input .D0(vga_green), // G0[2], 1-bit data input (associated with C0) .D1(vga_red), // R0[6], 1-bit data input (associated with C1) .R(reset), // 1-bit reset input .S(1'b0) // 1-bit set input );
ODDR2 #( // DVI_D[11] .DDR_ALIGNMENT("C0"), // Sets output alignment to "NONE", "C0" or "C1" .INIT(1'b0), // Sets initial state of the Q output to 1’b0 or 1’b1 .SRTYPE("ASYNC") // Specifies "SYNC" or "ASYNC" set/reset ) ODDR2_D11 ( .Q(dvi_d[11]), // 1-bit DDR output data .C0(clk), // 1-bit clock input .C1(clkb), // 1-bit clock input .CE(1'b1), // 1-bit clock enable input .D0(vga_green), // G0[3], 1-bit data input (associated with C0) .D1(vga_red), // R0[7], 1-bit data input (associated with C1) .R(reset), // 1-bit reset input .S(1'b0) // 1-bit set input );
ChipScope Pro (以下ChipScope)から、sp605_ibert.bitをコンフィギュレーションして、sp650_ibert.cpjのプロジェクトをロードする。 20ページで、GTPA1_DUAL_X0Y0_0とGTPA1_DUAL_X1Y0_1に近端PMAループバックを設定したつもりだったが、プロジェクトのデフォルト設定のままにしたら、近端PCSループバックだった。それで出たのが下の画像だ。
GTPA1_DUAL_X1Y0_0がNo Linkになっている。どうやらここが、SPFコネクタ/ケージのGTPトランシーバのようだ。GTPA1_DUAL_X0Y0_1がSMAケーブルで接続したGTPトランシーバらしいが、安いケーブルでも無事に2.5Gbpsでエラーなしに通信ができている。 あれ、やっているときは気がつかなかったが、両端の2つのGTPトランシーバは近端PCSループバックになっている。近端PMAループバックにするのを忘れてしまった。でも両端ともエラーはない。 さて、GTPA1_DUAL_X1Y0_0を近端PCSループバックにしてみた。だが、他のGTPトランシーバに比べて、RX Bit ErrorRatioが悪く、RX Received Bit Countもかなり出ている。(下図)どうしてだろうか?
process(clk) begin if clk'event and clk='1' then if reset='1' then a_sig_node0 <= (others => '0'); a_sig_node1 <= (others => '0'); a_sig_node2 <= (others => '0'); a_sig_node3 <= (others => '0'); else if cam_vsync_2d_fpulse='1' then -- cam_vsync_2d の立ち下がりなので、クリア a_sig_node0 <= (others => '0'); a_sig_node1 <= (others => '0'); a_sig_node2 <= (others => '0'); a_sig_node3 <= (others => '0'); elsif vd_read_line_write_2d='1' and current_line_is_even='0' and sub_count(1 downto 0)="11" then -- 奇数ライン if (select_sig(5 downto 0) & "00")=a_data_th then a_sig_node0 <= a_sig_node0 + 1; end if; if (select_sig(5 downto 0) & "01")=a_data_th then a_sig_node1 <= a_sig_node1 + 1; end if; if (select_sig(5 downto 0) & "10")=a_data_th then a_sig_node2 <= a_sig_node2 + 1; end if; if (select_sig(5 downto 0) & "11")=a_data_th then a_sig_node3 <= a_sig_node3 + 1; end if; end if; end if; end if; end process;