// SFIFO_test_tb.v
`default_nettype none
`timescale 1ns / 1ps
module SFIFO_test_tb;
reg clk;
reg [16:0] data;
reg rdreq;
reg wrreq;
wire empty;
wire full;
wire [16:0] q;
wire [3:0] usedw;
integer i;
parameter CLK_PERIOD = 40;
parameter DELAY_TIME = 10;
SFIFO_test SFIFO_test_inst (
.clock(clk),
.data(data),
.rdreq(rdreq),
.wrreq(wrreq),
.empty(empty),
.full(full),
.q(q),
.usedw(usedw)
);
always begin
#(CLK_PERIOD/2) clk = 1'b1 ;
#(CLK_PERIOD/2) clk = 1'b0 ;
end
initial begin
data = 17'd0;
rdreq = 1'b0;
wrreq = 1'b0;
#(DELAY_TIME*2);
@(posedge clk);
#DELAY_TIME;
for (i=0; i<9; i=i+1) begin
@(posedge clk);
#DELAY_TIME;
data = data + 17'd1;
wrreq = 1'b1;
end
@(posedge clk);
#DELAY_TIME;
wrreq = 1'b0;
@(posedge clk);
#DELAY_TIME;
for (i=0; i<9; i=i+1) begin
@(posedge clk);
#DELAY_TIME;
rdreq = 1'b1;
end
@(posedge clk);
#DELAY_TIME;
rdreq = 1'b0;
@(posedge clk);
#DELAY_TIME;
@(posedge clk);
#DELAY_TIME;
$stop;
end
endmodule
module SFIFO_module (
clock,
data,
rdreq,
wrreq,
empty,
full,
q,
usedw);
input clock;
input [16:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [16:0] q;
output [3:0] usedw;
endmodule
SFIFO_module SFIFO_module_inst (
.clock ( clock_sig ),
.data ( data_sig ),
.rdreq ( rdreq_sig ),
.wrreq ( wrreq_sig ),
.empty ( empty_sig ),
.full ( full_sig ),
.q ( q_sig ),
.usedw ( usedw_sig )
);
// SFIFO_test.v
`default_nettype none
module SFIFO_test(
input wire clock,
input wire [16:0] data,
input wire rdreq,
input wire wrreq,
output wire empty,
output wire full,
output wire [16:0] q,
output wire [3:0] usedw
);
SFIFO_module SFIFO_module_inst (
.clock ( clock ),
.data ( data ),
.rdreq ( rdreq ),
.wrreq ( wrreq ),
.empty ( empty ),
.full ( full ),
.q ( q ),
.usedw ( usedw )
);
endmodule
// SCCB_reg_valuse_ROM.v
// ROM生成、初期化データロード
`default_nettype none
module SCCB_reg_values_ROM (
input wire clk,
input wire [7:0] address,
output reg [15:0] dout
);
reg [15:0] ram [0:255];
initial begin
$readmemh("SCCB_reg_values.data", ram, 0, 255);
end
always @(posedge clk) begin
dout <= ram[address];
end
endmodule
`default_nettype wire
例7–35. Verilog-2001 例:ram_init_file 属性を適用
(* ram_init_file = "my_init_file.mif" *) reg [7:0] mem[0:255];
1713
1801
32B6
1902
1A7A
030A
73F0
7A20
7B10
7C1E
-- begin_signature
-- SCCB_reg_values_ROM
-- end_signature
WIDTH=16;
DEPTH=256;
ADDRESS_RADIX=UNS;
DATA_RADIX=BIN;
CONTENT BEGIN
..... 省略 ......
10 : 0111110100110101;
9 : 0111110000011110;
8 : 0111101100010000;
7 : 0111101000100000;
6 : 0111001111110000;
5 : 0000001100001010;
4 : 0001101001111010;
3 : 0001100100000010;
2 : 0011001010110110;
1 : 0001100000000001;
0 : 0001011100010011;
END;
for (j=0; j<4; j++){
r_int = (Y[j]<<8) + V[j]*359 - 45952;
g_int = (Y[j]<<8) - V[j]*183 - U[j]*88 + 34688;
b_int = (Y[j]<<8) + U[j]*454 - 58112;
if (r_int <0)
red = 0;
else if (((r_int)>>8)>=256)
red = 0xff;
else
red = (r_int)>>8;
if (g_int<0)
green = 0;
else if (((g_int)>>8)>=256)
green = 0xff;
else
green = (g_int)>>8;
if (b_int<0)
blue = 0;
else if (((b_int)>>8)>=256)
blue = 0xff;
else
blue = (b_int)>>8;
cam_red[(int)(i/640)][(int)((i%640)+j)] = red;
cam_green[(int)(i/640)][(int)((i%640)+j)] = green;
cam_blue[(int)(i/640)][(int)((i%640)+j)] = blue;
}
”AN 307: Xilinx ユーザー向けのアルテラのデザイン・フロー”に載っているデザイン例を後でやってみたい。( * keep = 1 *) wire my_wire;
製品概要
■ Platform Cable USBの互換品
■USBインタフェース、USB1.1 とUSB2.0両方サポートする。
Hot plug and playをサポートする。
Full-SpeedとHi-Speedをサポートする
■USBで給電、外部電源要らない
■ターゲットボードによって自動認識して1.5V~5Vの電源を提供する
(5V (TTL), 3.3V(LVCMOS), 2.5V, 1.8V and 1.5V)
■iMPACT とChipScopeをサポートする
■JTAG Boundary Scan、Slave Serial、
Serial Peripheral Interface SPIモードをサポートする
■JサポートするOS
――Microsoft Windows XP Professional
――Microsoft Windows Vista
――Windows 2000
――Red Hat Enterprise Linux
――SUSE Linux Enterprise
■USB-IF認証、CEとFCC規格を満たす
verilog work ../../../DDR2_SDRAM_cont_266/Sources/ddr2_sdram_cont/addr_fifo.v
verilog work ../../../DDR2_SDRAM_cont_266/Sources/ddr2_sdram_cont/async_fifo_fall.v
verilog work ../../../DDR2_SDRAM_cont_266/Sources/ddr2_sdram_cont/async_fifo_rise.v
verilog work ../../../DDR2_SDRAM_cont_266/Sources/ddr2_sdram_cont/controller.v
verilog work ../../../DDR2_SDRAM_cont_266/Sources/ddr2_sdram_cont/dcm_module.v
verilog work ../../../DDR2_SDRAM_cont_266/Sources/ddr2_sdram_cont/ddr2_cont_iob.v
verilog work ../../../DDR2_SDRAM_cont_266/Sources/ddr2_sdram_cont/dm_io_pad.v
verilog work ../../../DDR2_SDRAM_cont_266/Sources/ddr2_sdram_cont/dq_io_pad.v
verilog work ../../../DDR2_SDRAM_cont_266/Sources/ddr2_sdram_cont/dqs_io_pad.v
verilog work ../../../DDR2_SDRAM_cont_266/Sources/ddr2_sdram_cont/dqsb_io_pad.v
verilog work ../../../DDR2_SDRAM_cont_266/Sources/ddr2_sdram_cont/rddata_afifo.v
verilog work ../../../DDR2_SDRAM_cont_266/Sources/ddr2_sdram_cont/read_write_io.v
verilog work ../../../DDR2_SDRAM_cont_266/Sources/ddr2_sdram_cont/REFREQSM.v
verilog work ../../../DDR2_SDRAM_cont_266/Sources/ddr2_sdram_cont/wrdata_fifo.v
verilog work ../../../DDR2_SDRAM_cont_266/Sources/ddr2_sdram_cont/ddr2_sdram_cont.v
verilog work "../../Synth122/ipcore_dir/cam_cont_afifo.v"
verilog work "../../Synth122/ipcore_dir/cam_data_afifo.v"
verilog work ../../Sources/SWDiv.v
verilog work ../../Sources/SW_Controller.v
verilog work ../../Sources/VGA_Display_Controller.v
verilog work ../../Sources/Arbiter.v
verilog work ../../Sources/Camera_Controller.v
verilog work ../../Sources/dcm_CAM_DDR2_clk.v
verilog work ../../Sources/synchronizer.v
vhdl work ../../Sources/freqdiv.vhd
vhdl work ../../Sources/One_Transaction_SCCB.vhd
vhdl work ../../Sources/SCCB_Reg_Controller.vhd
vhdl work ../../Sources/SCCB_reg_values_ROM.vhd
verilog work ../../Sources/CamDisp_Cntrler_DDR2.v
verilog work ../OV7670_Model.v
verilog work H:\HDL\FndtnISEWork\Spartan3A_starter_kit\DDR2_SDRAM_cont_266\Simulation\256Mb_ddr2\ddr2.v
verilog work ../CamDispCntrler_DDR2_tb.v
verilog work H:\HDL\Xilinx\12.2\ISE_DS\ISE\verilog\src\glbl.v
H:\HDL\Xilinx\12.2\ISE_DS\ISE\bin\nt\fuse work.CamDispCntrler_DDR2_tb work.glbl -incremental -d OVL_VERLOG -i ..\ -i H:\HDL\OVL\std_ovl -d OVL_ASSERT_ON -d OVL_FINISH_OFF -L unisims_ver=H:\HDL\Xilinx\12.2\ISE_DS\ISE\verilog\hdp\nt\unisims_ver -L unimacro_ver=H:\HDL\Xilinx\12.2\ISE_DS\ISE\verilog\hdp\nt\unimacro_ver -L XilinxCoreLib_ver=H:\HDL\Xilinx\12.2\ISE_DS\ISE\verilog\hdp\nt\xilinxcorelib_ver -L accellera_ovl_vlog=H:\HDL\Xilinx\12.2\ISE_DS\ISE\verilog\hdp\nt\accellera_ovl_vlog -o CamDispCntrler_DDR2_tb.exe -prj CamDispCntrler_DDR2_Capt_SCCB_tb.prj
CamDispCntrler_DDR2_tb.exe -gui
Running: H:\HDL\Xilinx\12.2\ISE_DS\ISE\bin\nt\unwrapped\fuse.exe work.CamDispCnt
rler_DDR2_tb work.glbl -incremental -d OVL_VERLOG -i ..\ -i H:\HDL\OVL\std_ovl -
d OVL_ASSERT_ON -d OVL_FINISH_OFF -L unisims_ver=H:\HDL\Xilinx\12.2\ISE_DS\ISE\v
erilog\hdp\nt\unisims_ver -L unimacro_ver=H:\HDL\Xilinx\12.2\ISE_DS\ISE\verilog\
hdp\nt\unimacro_ver -L XilinxCoreLib_ver=H:\HDL\Xilinx\12.2\ISE_DS\ISE\verilog\h
dp\nt\xilinxcorelib_ver -L accellera_ovl_vlog=H:\HDL\Xilinx\12.2\ISE_DS\ISE\veri
log\hdp\nt\accellera_ovl_vlog -o CamDispCntrler_DDR2_tb.exe -prj CamDispCntrler_
DDR2_Capt_SCCB_tb.prj
ISim M.63c (signature 0xb869381d)
Number of CPUs detected in this system: 2
Turning on mult-threading, number of parallel sub-compilation jobs: 4
Determining compilation order of HDL files
WARNING:Simulator:1010 - One or more environment variables have been detected wh
ich affect the operation of the C compiler. These are typically not set in stand
ard installations and are not tested by Xilinx, however they may be appropriate
for your system, so the flow will attempt to continue. If errors occur, try run
ning fuse with the "-mt off -v 1" switches to see more information from the C co
mpiler. The following environment variables have been detected:
C_INCLUDE_PATH
LIBRARY_PATH
Analyzing Verilog file \"../../../DDR2_SDRAM_cont_266/Sources/ddr2_sdram_cont/ad
dr_fifo.v\" into library work
Analyzing Verilog file \"../../../DDR2_SDRAM_cont_266/Sources/ddr2_sdram_cont/as
ync_fifo_fall.v\" into library work
Analyzing Verilog file \"../../../DDR2_SDRAM_cont_266/Sources/ddr2_sdram_cont/as
ync_fifo_rise.v\" into library work
Analyzing Verilog file \"../../../DDR2_SDRAM_cont_266/Sources/ddr2_sdram_cont/co
ntroller.v\" into library work
Analyzing Verilog file \"../../../DDR2_SDRAM_cont_266/Sources/ddr2_sdram_cont/dc
m_module.v\" into library work
Analyzing Verilog file \"../../../DDR2_SDRAM_cont_266/Sources/ddr2_sdram_cont/dd
r2_cont_iob.v\" into library work
Analyzing Verilog file \"../../../DDR2_SDRAM_cont_266/Sources/ddr2_sdram_cont/dm
_io_pad.v\" into library work
Analyzing Verilog file \"../../../DDR2_SDRAM_cont_266/Sources/ddr2_sdram_cont/dq
_io_pad.v\" into library work
Analyzing Verilog file \"../../../DDR2_SDRAM_cont_266/Sources/ddr2_sdram_cont/dq
s_io_pad.v\" into library work
Analyzing Verilog file \"../../../DDR2_SDRAM_cont_266/Sources/ddr2_sdram_cont/dq
sb_io_pad.v\" into library work
Analyzing Verilog file \"../../../DDR2_SDRAM_cont_266/Sources/ddr2_sdram_cont/rd
data_afifo.v\" into library work
Analyzing Verilog file \"../../../DDR2_SDRAM_cont_266/Sources/ddr2_sdram_cont/re
ad_write_io.v\" into library work
Analyzing Verilog file \"../../../DDR2_SDRAM_cont_266/Sources/ddr2_sdram_cont/RE
FREQSM.v\" into library work
Analyzing Verilog file \"../../../DDR2_SDRAM_cont_266/Sources/ddr2_sdram_cont/wr
data_fifo.v\" into library work
Analyzing Verilog file \"../../../DDR2_SDRAM_cont_266/Sources/ddr2_sdram_cont/dd
r2_sdram_cont.v\" into library work
Analyzing Verilog file \"../../Synth122/ipcore_dir/cam_cont_afifo.v\" into libra
ry work
Analyzing Verilog file \"../../Synth122/ipcore_dir/cam_data_afifo.v\" into libra
ry work
Analyzing Verilog file \"../../Sources/SWDiv.v\" into library work
Analyzing Verilog file \"../../Sources/SW_Controller.v\" into library work
Analyzing Verilog file \"../../Sources/VGA_Display_Controller.v\" into library w
ork
Analyzing Verilog file \"../../Sources/Arbiter.v\" into library work
Analyzing Verilog file \"../../Sources/Camera_Controller.v\" into library work
Analyzing Verilog file \"../../Sources/dcm_CAM_DDR2_clk.v\" into library work
Analyzing Verilog file \"../../Sources/synchronizer.v\" into library work
Analyzing Verilog file \"../../Sources/CamDisp_Cntrler_DDR2.v\" into library wor
k
Analyzing Verilog file \"../OV7670_Model.v\" into library work
Analyzing Verilog file \"H:\HDL\FndtnISEWork\Spartan3A_starter_kit\DDR2_SDRAM_co
nt_266\Simulation\256Mb_ddr2\ddr2.v\" into library work
Analyzing Verilog file \"../CamDispCntrler_DDR2_tb.v\" into library work
Analyzing Verilog file \"H:\HDL\Xilinx\12.2\ISE_DS\ISE\verilog\src\glbl.v\" into
library work
Parsing VHDL file "../../Sources/freqdiv.vhd" into library work
Parsing VHDL file "../../Sources/One_Transaction_SCCB.vhd" into library work
Parsing VHDL file "../../Sources/SCCB_Reg_Controller.vhd" into library work
Parsing VHDL file "../../Sources/SCCB_reg_values_ROM.vhd" into library work
Starting static elaboration
WARNING:HDLCompiler:1016 - "../CamDispCntrler_DDR2_tb.v" Line 65: Port addr_is_z
ero is not connected to this instance
Completed static elaboration
Fuse Memory Usage: 69056 KB
Fuse CPU Usage: 530 ms
Using precompiled package standard from library std
Using precompiled package std_logic_1164 from library ieee
Using precompiled package std_logic_arith from library ieee
Using precompiled package std_logic_unsigned from library ieee
Using precompiled package textio from library std
Using precompiled package std_logic_textio from library ieee
Compiling module dcm_clock_divide_by_2
Compiling module dcm_maximum_period_check(clock_n...
Compiling module dcm_maximum_period_check(clock_n...
Compiling module dcm_clock_lost
Compiling module DCM(CLKDV_DIVIDE=2.0,CLKFX_DIVID...
Compiling module BUFG
Compiling module dcm_CAM_DDR2_clk_default
Compiling module ODDR2_default
Compiling module DCM(CLKDV_DIVIDE=16.0,CLKIN_PERI...
Compiling module dcm_module_default
Compiling module refreqsm
Compiling module controller_default
Compiling module ODDR2(SRTYPE="ASYNC")
Compiling module IOBUF
Compiling module dq_io_pad
Compiling module dqs_io_pad
Compiling module dqsb_io_pad
Compiling module OBUF
Compiling module dm_io_pad
Compiling module ddr2_cont_iob_default
Compiling module RAM16X1D
Compiling module async_fifo_rise
Compiling module async_fifo_fall
Compiling module rddata_afifo_default
Compiling module read_write_io_default
Compiling module addr_fifo_default
Compiling module wrdata_fifo_default
Compiling module ddr2_sdram_cont_default
Compiling module fifo_generator_v6_1_bhv_ver_as(C...
Compiling module fifo_generator_v6_1_bhv_ver_prel...
Compiling module FIFO_GENERATOR_V6_1(C_DATA_COUNT...
Compiling module cam_cont_afifo
Compiling module Camera_Controller
Compiling module fifo_generator_v6_1_bhv_ver_as(C...
Compiling module fifo_generator_v6_1_bhv_ver_prel...
Compiling module FIFO_GENERATOR_V6_1(C_DATA_COUNT...
Compiling module cam_data_afifo
Compiling module VGA_Display_Controller(VGA_CON_S...
Compiling module Arbiter_default
Compiling module synchronizer
Compiling module SWDiv(clk_frequency=25000)
Compiling module SW_Controller
Compiling module CamDisp_Cntrler_DDR2_default
Compiling module ddr2_default
Compiling module OV7670_Model(H_ACTIVE_VIDEO=20,H...
Compiling module CamDispCntrler_DDR2_tb
Compiling module glbl
Compiling package vcomponents
Compiling architecture rtl of entity freqdiv [\FreqDiv(125)\]
Compiling architecture rtl of entity sccb_reg_values_rom [sccb_reg_values_rom_de
fault]
Compiling architecture rtl of entity one_transaction_sccb [one_transaction_sccb_
default]
Compiling architecture rtl of entity sccb_reg_controller [sccb_reg_controller_de
fault]
Time Resolution for simulation is 1ps.
Waiting for 1 sub-compilation(s) to finish...
Compiled 15 VHDL Units
Compiled 48 Verilog Units
Built simulation executable CamDispCntrler_DDR2_tb.exe
Fuse Memory Usage: 87812 KB
Fuse CPU Usage: 1734 ms
// アサーション
// synthesis translate_off
always @ (posedge clk_ddr2) begin
if (reset_ddr2) begin
camc_addr_1d <= 0;
vgadc_addr_1d <= 0;
addr_assertion_valid <= 1'b0;
end else begin
if (ddr2_addr_we) begin
camc_addr_1d <= camc_addr;
end
if (vgadc_addr_we) begin
vgadc_addr_1d <= vgadc_addr;
end
if (ddr2_addr_we || vgadc_addr_we) begin
addr_assertion_valid <= 1'b1;
end
end
end
// Camera_Controller が有効の時にVGA_Display_Controller がライトしないことをチェックするOVLアサーション
ovl_never #(`OVL_ERROR, `OVL_ASSERT, "ERROR : Camera_Controller が有効の時にVGA_Display_Controller がライトした", `OVL_COVER_DEFAULT, `OVL_POSEDGE, `OVL_ACTIVE_HIGH, `OVL_GATE_CLOCK) camc_vga_we_assertion (clk_ddr2, reset_ddr2, 1'b1, (cs_abt==CAMC_Grant || cs_abt==VGADC_Wait) && vgadc_addr_we, fire_camc_vgac);
// 現在のCamera_Controller からのWrite Addressが以前のWrite Addressの+4かどうかをチェックするOVLアサーション
ovl_always #(`OVL_ERROR, `OVL_ASSERT, "ERROR : 以前のcamc_addr から+4されていない", `OVL_COVER_ALL, `OVL_POSEDGE, `OVL_ACTIVE_HIGH, `OVL_GATE_CLOCK) camc_addr_assertion (clk_ddr2, reset_ddr2, camc_addr>=4 && (cs_abt==CAMC_Grant || cs_abt==VGADC_Wait) && ddr2_addr_we , camc_addr_1d+4==camc_addr, fire_camc_addr);
// VGA_Display_Controller が有効の時にCamera_Controller がライトしないことをチェックするOVLアサーション
ovl_never #(`OVL_ERROR, `OVL_ASSERT, "ERROR : VGA_Display_Controller が有効の時に、camc_addr_ena, camc_data_ena が1になった", `OVL_COVER_DEFAULT, `OVL_POSEDGE, `OVL_ACTIVE_HIGH, `OVL_GATE_CLOCK) vgac_camc_we_assertion (clk_ddr2, reset_ddr2, 1'b1, (cs_abt==VGADC_Grant || cs_abt==CAMC_Wait) && (ddr2_addr_we || ddr2_addr_we), fire_vgac_camc);
// 現在のVGA_Display_Controller からのRead Addressが以前のRead Addressの+4かどうかをチェックするOVLアサーション
ovl_always #(`OVL_ERROR, `OVL_ASSERT, "ERROR : 以前のvgadc_addr から+4されていない", `OVL_COVER_ALL, `OVL_POSEDGE, `OVL_ACTIVE_HIGH, `OVL_GATE_CLOCK) vgadc_addr_assertion (clk_ddr2, reset_ddr2, vgadc_addr>=4 && (cs_abt==CAMC_Grant || cs_abt==VGADC_Wait) && ddr2_addr_we , vgadc_addr_1d+4==vgadc_addr, fire_vgac_addr);
// Camera_Controller がFIFOがフルの時に書き込んでいるか?をチェックするアサーション
ovl_never #(`OVL_ERROR, `OVL_ASSERT, "ERROR : アドレスFIFOがフルの時にCamera_Controller が書き込んだ", `OVL_COVER_DEFAULT, `OVL_POSEDGE, `OVL_ACTIVE_HIGH, `OVL_GATE_CLOCK) camc_addr_full_we_assertion (clk_ddr2, reset_ddr2, 1'b1, ddr2_addr_we && ddr2_addr_fifo_full, fire_camc_addr_overflow);
ovl_never #(`OVL_ERROR, `OVL_ASSERT, "ERROR : データFIFOがフルの時にCamera_Controller が書き込んだ", `OVL_COVER_DEFAULT, `OVL_POSEDGE, `OVL_ACTIVE_HIGH, `OVL_GATE_CLOCK) camc_data_full_we_assertion (clk_ddr2, reset_ddr2, 1'b1, ddr2_data_we && ddr2_wrdata_fifo_full, fire_camc_data_overflow);
// VGA_Display_Controller がFIFOがフルの時に書き込んでいるか?をチェックするアサーション
ovl_never #(`OVL_ERROR, `OVL_ASSERT, "ERROR : アドレスFIFOがフルの時にVGA_Display_Controller が書き込んだ", `OVL_COVER_DEFAULT, `OVL_POSEDGE, `OVL_ACTIVE_HIGH, `OVL_GATE_CLOCK) vgadc_data_full_we_assertion (clk_ddr2, reset_ddr2, 1'b1, vgadc_addr_we && ddr2_addr_fifo_full, fire_vgadc_addr_overflow);
// synthesis translate_on
red = (char)((int)(((Y[j]<<8) + V[j]*359 - 45952)>>8)&0xff);
green = (char)(((int)((Y[j]<<8) - V[j]*183 - U[j]*88 + 34688)>>8)&0xff);
blue = (char)((int)(((Y[j]<<8) + U[j]*454 - 58112)>>8)&0xff);
// Camera_Capture.cpp : コンソール アプリケーションのエントリ ポイントを定義します。
//
#pragma warning(disable:4996)
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <iostream>
#include <cstring>
#include "stdafx.h"
int _tmain(int argc, _TCHAR* argv[])
{
char cam_file[100];
char **cam_red, **cam_green, **cam_blue; // 640*480ピクセル
BITMAPFILEHEADER bmpfh; // BMPファイルのファイルヘッダ
BITMAPINFOHEADER bmpih; // BMPファイルのINFOヘッダ
BMP24FORMAT **bmp_data; // 24ビットのBMPファイルのデータ 640*480
FILE *fcam, *fbmp;
int i, j, k;
char temp_buf[100], temp_buf2[100];
int U[4], V[4], Y[4];
char *str;
unsigned int UVY[8];
char red, green, blue;
// 引数の処理
if (argc == 1) { // 引数なし
strcpy_s(cam_file, "camera_capture_data.txt");
} else if (argc == 2){ //
strcpy_s(cam_file, (const char *)argv[1]);
} else {
fprintf(stderr, "Camera2BMP <camera_capture_data.txt>\n");
exit(1);
}
// メモリをアロケートする
if ((cam_red =(char **)malloc(sizeof(char *) * 480)) == NULL){
fprintf(stderr, "cam_redの1次元目480のメモリを確保できません\n");
exit(1);
}
if ((cam_green =(char **)malloc(sizeof(char *) * 480)) == NULL){
fprintf(stderr, "cam_greenの1次元目480のメモリを確保できません\n");
exit(1);
}
if ((cam_blue =(char **)malloc(sizeof(char *) * 480)) == NULL){
fprintf(stderr, "cam_blueの1次元目480のメモリを確保できません\n");
exit(1);
}
for (i=0; i<480; i++){
if ((cam_red[i]=(char *)malloc(sizeof(char) * 640)) == NULL){
fprintf(stderr, "cam_redの2次元目の%d番目のメモリが確保できません\n", i);
exit(1);
}
}
for (i=0; i<480; i++){
if ((cam_green[i]=(char *)malloc(sizeof(char) * 640)) == NULL){
fprintf(stderr, "cam_greenの2次元目の%d番目のメモリが確保できません\n", i);
exit(1);
}
}
for (i=0; i<480; i++){
if ((cam_blue[i]=(char *)malloc(sizeof(char) * 640)) == NULL){
fprintf(stderr, "cam_blueの2次元目の%d番目のメモリが確保できません\n", i);
exit(1);
}
}
if ((bmp_data=(BMP24FORMAT **)malloc(sizeof(BMP24FORMAT *)*480)) == NULL){
fprintf(stderr, "bmp_dataの1次元目の480のメモリを確保できません\n");
exit(1);
}
for (i=0; i<480; i++){
if ((bmp_data[i]=(BMP24FORMAT *)malloc(sizeof(BMP24FORMAT) * 640)) == NULL){
fprintf(stderr, "bmp_dataの2次元目の%d番目のメモリが確保できません\n", i);
exit(1);
}
}
// cam_fileをtext readモードでオープン
if ((fcam = fopen(cam_file, "rt")) == NULL) {
fprintf(stderr, "Can't Open %s\n", cam_file);
exit(1);
}
// cam_fileの読み込み
for (i=0; i<307200; i=i+4){
if ((k=fscanf(fcam,"%s\n", temp_buf)) == EOF){
fprintf(stderr, "%s のデータが足りない。%d\n", cam_file, i);
exit(1);
} else if (k == 0){
fprintf(stderr, "%s のデータフォーマットがエラー\n", cam_file);
exit(1);
}
for (str=temp_buf, j=0; j<8; str+=2, j++){
strncpy(temp_buf2, str, 2); // 2文字コピー
temp_buf2[2] = '\n';
sscanf(temp_buf2, "%x\n", &UVY[j]);
}
U[0]=UVY[0];
Y[0]=UVY[1];
V[0]=UVY[2];
Y[1]=UVY[3];
U[2]=UVY[4];
Y[2]=UVY[5];
V[2]=UVY[6];
Y[3]=UVY[7];
U[1] = U[0]; V[1] = V[0];
U[3] = U[2]; V[3] = V[2];
for (j=0; j<4; j++){
red = (char)((int)(((Y[j]<<8) + V[j]*359 - 45952)>>8)&0xff);
green = (char)(((int)((Y[j]<<8) - V[j]*183 - U[j]*88 + 34688)>>8)&0xff);
blue = (char)((int)(((Y[j]<<8) + U[j]*454 - 58112)>>8)&0xff);
cam_red[(int)(i/640)][(int)((i%640)+j)] = red;
cam_green[(int)(i/640)][(int)((i%640)+j)] = green;
cam_blue[(int)(i/640)][(int)((i%640)+j)] = blue;
}
}
// cam_dataに読み込んだカメラのカラーデータをbmp_dataにをコピー(その際にBMPのデータは左下から始まる)
for (i=0; i<480; i++){
for (j=0; j<640; j++){
bmp_data[479-i][j].red = cam_red[i][j];
bmp_data[479-i][j].green = cam_green[i][j];
bmp_data[479-i][j].blue = cam_blue[i][j];
}
}
fclose(fcam);
// BMPファイルのファイルヘッダに値を代入
bmpfh.bfType = 0x4d42;
bmpfh.bfSize = 640*480*3+54;
bmpfh.bfReserved1 = 0;
bmpfh.bfReserved2 = 0;
bmpfh.bfOffBits = 0x36;
// BMPファイルのINFOヘッダに値を代入
bmpih.biSize = 0x28;
bmpih.biWidth = 640;
bmpih.biHeight = 480;
bmpih.biPlanes = 0x1;
bmpih.biBitCount = 24;
bmpih.biCompression = 0;
bmpih.biSizeImage = 0;
bmpih.biXPixPerMeter = 3779;
bmpih.biYPixPerMeter = 3779;
bmpih.biClrUsed = 0;
bmpih.biClrImporant = 0;
// bmpファイルに書き出す
if ((fbmp=fopen("cam_bmp_file.bmp", "wb")) == NULL){
fprintf(stderr, "cam_bmp_file.bmpがバイナリライトモードで開けません\n");
exit(1);
}
// BMPファイルヘッダの書き込み
fwrite(&bmpfh.bfType, sizeof(char), 2, fbmp);
fwrite(&bmpfh.bfSize, sizeof(long), 1, fbmp);
fwrite(&bmpfh.bfReserved1, sizeof(short), 1, fbmp);
fwrite(&bmpfh.bfReserved2, sizeof(short), 1, fbmp);
fwrite(&bmpfh.bfOffBits, sizeof(long), 1, fbmp);
// BMPファイルのINFOヘッダの書き込み
fwrite(&bmpih, sizeof(BITMAPINFOHEADER), 1, fbmp);
// bmp_dataの書き込み
for (i=0; i<480; i++) {
for (j=0; j<640; j++) {
fputc((int)bmp_data[i][j].blue, fbmp);
fputc((int)bmp_data[i][j].green, fbmp);
fputc((int)bmp_data[i][j].red, fbmp);
}
}
fclose(fbmp);
for(i=0; i<480; i++){
free(cam_red[i]);
free(cam_green[i]);
free(cam_blue[i]);
free(bmp_data[i]);
}
free(cam_red);
free(cam_green);
free(cam_blue);
free(bmp_data);
return 0;
}
// stdafx.h : 標準のシステム インクルード ファイルのインクルード ファイル、または
// 参照回数が多く、かつあまり変更されない、プロジェクト専用のインクルード ファイル
// を記述します。
//
#pragma once
#include "targetver.h"
#include <stdio.h>
#include <tchar.h>
// TODO: プログラムに必要な追加ヘッダーをここで参照してください。
// BITMAPFILEHEADER 14bytes
typedef struct tagBITMAPFILEHEADER {
unsigned short bfType;
unsigned long bfSize;
unsigned short bfReserved1;
unsigned short bfReserved2;
unsigned long bfOffBits;
} BITMAPFILEHEADER;
// BITMAPINFOHEADER 40bytes
typedef struct tagBITMAPINFOHEADER{
unsigned long biSize;
long biWidth;
long biHeight;
unsigned short biPlanes;
unsigned short biBitCount;
unsigned long biCompression;
unsigned long biSizeImage;
long biXPixPerMeter;
long biYPixPerMeter;
unsigned long biClrUsed;
unsigned long biClrImporant;
} BITMAPINFOHEADER;
typedef struct BMP24bitsFORMAT {
unsigned char blue;
unsigned char green;
unsigned char red;
} BMP24FORMAT;
SW_Controller #(
.frequency_KHz(25000))
SW_CONT_inst(
.clk(clk_cam),
.reset(reset_cam),
.sw0(sw0),
.sw1(sw1),
.sw0_out(capture_ena),
.sw1_out(vio_on)
);
CamCaptICON CamCaptICON_inst (
.CONTROL0(control0) // INOUT BUS [35:0]
);
CamCaptVIO CamCaptVIO_inst (
.CONTROL(control0), // INOUT BUS [35:0]
.CLK(clk_ddr2), // IN
.SYNC_IN(sync_in), // IN BUS [63:0]
.SYNC_OUT(sync_out) // OUT BUS [24:0]
);
// sync_outの変化を検知してvio_addr_we を出力する
always @(posedge clk_ddr2) begin
if (reset_ddr2) begin
sync_out_reg1 <= 25'd0;
sync_out_reg2 <= 25'd0;
end else begin
sync_out_reg1 <= sync_out;
sync_out_reg2 <= sync_out_reg1;
end
end
always @* begin
if (sync_out_reg1 != sync_out_reg2) // 以前の値と異なるとき
vio_addr_we <= 1'b1;
else
vio_addr_we <= 1'b0;
end
// first_dword VIOの最初の32ビット
always @(posedge clk_ddr2) begin
if (reset_ddr2)
first_dword <= 1'b1;
else begin
if (vio_on && ddr2_rddata_valid)
first_dword <= 1'b0;
else
first_dword <= 1'b1;
end
end
// sync_in 処理
always @(posedge clk_ddr2) begin
if (reset_ddr2)
sync_in <= 64'd0;
else begin
if (vio_on & first_dword && ddr2_rddata_valid) begin
sync_in[63:32] <= ddr2_output_data;
end
if (vio_on & ~first_dword && ddr2_rddata_valid) begin
sync_in[31:0] <= ddr2_output_data;
end
end
end
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