module bin2bcd (clk, bin, bcd);
input clk;
input [ 9:0] bin;
output [15:0] bcd;
wire [13:0] k3;
reg [13:0] k3b;
reg [ 3:0] d32;
reg [ 3:0] d31;
reg [ 3:0] d30;
wire [13:0] k2;
reg [13:0] k2b;
reg [ 3:0] d21;
reg [ 3:0] d20;
wire [13:0] k1;
reg [ 3:0] d10;
reg [ 3:0] d00;
assign k3 = bin + bin[9:6] + bin[9:7] + bin[9] + 1'b1;
always @(posedge clk) d32 <= k3[13:10];
always @(posedge clk) k3b <= bin - (k3[13:10] * 1000);
assign k2 = k3b * 10 + k3b[13:2];
always @(posedge clk) d21 <= k2[13:10];
always @(posedge clk) k2b <= k3b - (k2[13:10] * 100);
always @(posedge clk) d31 <= d32;
assign k1 = k2b * 102 + k2b[13:1];
always @(posedge clk) d00 <= k2b - (k1[13:10] * 10);
always @(posedge clk) d10 <= k1[13:10];
always @(posedge clk) d20 <= d21;
always @(posedge clk) d30 <= d31;
assign bcd = {d30,d20,d10,d00};
endmodule
`timescale 1ns / 1ps
module bin2bcd_tb;
// Inputs
reg clk;
reg [9:0] bin;
// Outputs
wire [15:0] bcd;
parameter CLK_PERIOD = 10;
integer i, j;
// Instantiate the Unit Under Test (UUT)
bin2bcd uut (
.clk(clk),
.bin(bin),
.bcd(bcd)
);
always begin // clk
#(CLK_PERIOD/2) clk = 1'b1 ;
#(CLK_PERIOD/2) clk = 1'b0 ;
end
initial begin
// Initialize Inputs
bin = 0;
// Add stimulus here
for (i=0; i<=1000; i=i+1) begin
@(posedge clk);
#1;
bin = i;
for (j=0; j<=3; j=j+1) begin
@(posedge clk);
#1;
end
end
#50;
$stop;
end
endmodule
-- bin2bcd.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bin2bcd is
port(
clk : in std_logic;
reset : in std_logic;
din : in std_logic_vector(9 downto 0);
load : in std_logic;
bcd_out : out std_logic_vector(11 downto 0);
done : out std_logic
);
end bin2bcd;
architecture RTL of bin2bcd is
component BcdDigit
Port ( Clk : in STD_LOGIC;
Init : in STD_LOGIC;
DoneIn: in STD_LOGIC;
ModIn : in STD_LOGIC;
ModOut : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR (3 downto 0));
end component;
signal shift_reg : std_logic_vector(9 downto 0);
signal count : std_logic_vector(3 downto 0);
signal done_node : std_logic;
signal modout0, modout1 : std_logic;
begin
-- 3つのBcdDigit をインスタンス
BcdDigit0 : BcdDigit port map(
Clk => clk,
Init => reset,
DoneIn => done_node,
ModIn => shift_reg(9),
ModOut => modout0,
Q => bcd_out(3 downto 0)
);
BcdDigit1 : BcdDigit port map(
Clk => clk,
Init => reset,
DoneIn => done_node,
ModIn => modout0,
ModOut => modout1,
Q => bcd_out(7 downto 4)
);
BcdDigit2 : BcdDigit port map(
Clk => clk,
Init => reset,
DoneIn => done_node,
ModIn => modout1,
ModOut => open,
Q => bcd_out(11 downto 8)
);
-- shift_reg
process(clk) begin
if clk'event and clk='1' then
if reset='1' then
shift_reg <= (others => '0');
else
if load='1' then
shift_reg <= din;
else
shift_reg <= shift_reg(8 downto 0) & '0';
end if;
end if;
end if;
end process;
-- Doneを制御する
process(clk) begin
if clk'event and clk='1' then
if reset='1' then
count <= (others =>'0');
else
if load='1' then
count <= (others => '0');
elsif unsigned(count) <= 10 then
count <= count + 1;
end if;
end if;
end if;
end process;
done_node <= '1' when count=10 else '0';
done <= done_node;
end RTL;
-- bin2bcd_tb.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
ENTITY bin2bcd_tb IS
END bin2bcd_tb;
ARCHITECTURE behavior OF bin2bcd_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT bin2bcd
PORT(
clk : in std_logic;
reset : in std_logic;
din : in std_logic_vector(9 downto 0);
load : in std_logic;
bcd_out : out std_logic_vector(11 downto 0);
done : out std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal din : std_logic_vector(9 downto 0) := (others => '0');
signal load : std_logic := '0';
--Outputs
signal bcd_out : std_logic_vector(11 downto 0) := (others => '0');
signal done : std_logic := '0';
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: bin2bcd PORT MAP (
clk => clk,
reset => reset,
din => din,
load => load,
bcd_out => bcd_out,
done => done
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
reset <= '1';
wait for 100 ns;
reset <= '0';
wait for clk_period*10;
-- insert stimulus here
STIMULUS_LOOP : for i in 0 to 1000 loop
wait until clk'event and clk='1';
wait for 1 ns;
din <= CONV_STD_LOGIC_VECTOR(i, 10);
reset<='1';
wait until clk'event and clk='1';
wait for 1 ns;
load <= '1'; reset<='0';
wait until clk'event and clk='1';
wait for 1 ns;
load <= '0';
TRANS_WAIT_LOOP : for j in 0 to 9 loop -- 11クロックwait
wait until clk'event and clk='1';
wait for 1 ns;
end loop TRANS_WAIT_LOOP;
end loop STIMULUS_LOOP;
wait for clk_period*10;
assert (false) report "Simulation End!" severity failure;
end process;
END;
module bin2bcd_m16_tb;
// Inputs
reg [15:0] bin_in;
// Outputs
wire [15:0] bcd_out;
parameter CLK_PERIOD = 10;
integer i;
reg clk;
// Instantiate the Unit Under Test (UUT)
bin2bcd_m16 uut (
.bin_in(bin_in),
.bcd_out(bcd_out)
);
always begin // clk
#(CLK_PERIOD/2) clk = 1'b1 ;
#(CLK_PERIOD/2) clk = 1'b0 ;
end
initial begin
// Initialize Inputs
bin_in = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
for (i=0; i<=1000; i=i+1) begin
@(posedge clk);
#1;
bin_in = i;
end
#50;
$stop;
end
endmodule
-- Binary to Decimal Test
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity binary_decimal_test is
port(
clk : in std_logic;
reset : in std_logic;
complete : in std_logic;
latched_quotient : in std_logic_vector(9 downto 0);
persent : out std_logic_vector(11 downto 0)
);
end binary_decimal_test;
architecture RTL of binary_decimal_test is
signal persent_node : std_logic_vector(11 downto 0);
type binary_decimal_state is (idle_bds, state_0, state_1, state_2, state_3, state_4, state_5, state_6, state_7, state_8, state_9, state_10, val_valid);
signal cs_bds : binary_decimal_state;
type complete_state is (idle_comp, divide_complete);
signal cs_div : complete_state;
begin
process(clk) begin
if clk'event and clk='1' then
if reset='1' then
cs_div <= idle_comp;
else
case cs_div is
when idle_comp =>
if complete='1' then
cs_div <= divide_complete;
end if;
when divide_complete =>
cs_div <= idle_comp;
end case;
end if;
end if;
end process;
-- 2進化10進用ステートマシン
process(clk) begin
if clk'event and clk='1' then
if reset='1' then
cs_bds <= idle_bds;
else
case cs_bds is
when idle_bds =>
if cs_div = divide_complete then
if unsigned(latched_quotient)>999 then -- 999以上は999と表示する
cs_bds <= state_9;
else
cs_bds <= state_0;
end if;
end if;
when state_0 =>
cs_bds <= state_1;
when state_1 =>
cs_bds <= state_2;
when state_2 =>
cs_bds <= state_3;
when state_3 =>
cs_bds <= state_4;
when state_4 =>
cs_bds <= state_5;
when state_5 =>
cs_bds <= state_6;
when state_6 =>
cs_bds <= state_7;
when state_7 =>
cs_bds <= state_8;
when state_8 =>
cs_bds <= state_9;
when state_9 =>
cs_bds <= state_10;
when state_10 =>
cs_bds <= val_valid;
when val_valid => -- present_nodeの値が有効
cs_bds <= idle_bds;
end case;
end if;
end if;
end process;
-- 10進数変換用のテーブル
-- 割り算で導き出したパーセンテージを10進にする
process(clk) begin
if clk'event and clk='1' then
if reset='1' then
persent_node <= (others => '0');
else
case cs_bds is
when state_0 =>
if latched_quotient(0)='1' then
persent_node <= "000000000001";
else
persent_node <= (others => '0');
end if;
when state_1 =>
if latched_quotient(1)='1' then
persent_node <= persent_node + 2;
else
persent_node <= persent_node;
end if;
when state_2 =>
if latched_quotient(2)='1' then
persent_node <= persent_node + 4;
else
persent_node <= persent_node;
end if;
when state_3 =>
if latched_quotient(3)='1' then
persent_node <= persent_node + 8;
else
persent_node <= persent_node;
end if;
when state_4 =>
if unsigned(persent_node(3 downto 0))>9 then -- 前までの総計15
if latched_quotient(4)='1' then
persent_node <= persent_node + x"01C"; -- +6+16
else
persent_node <= persent_node + x"006"; -- +6
end if;
else
if latched_quotient(4)='1' then
persent_node <= persent_node + x"016";
else
persent_node <= persent_node;
end if;
end if;
when state_5 =>
if unsigned(persent_node(3 downto 0))>9 then -- 前までの総計は31
if latched_quotient(5)='1' then
persent_node <= persent_node + x"038"; -- +6+32
else
persent_node <= persent_node + x"006"; -- +6
end if;
else
if latched_quotient(5)='1' then
persent_node <= persent_node + x"032";
else
persent_node <= persent_node;
end if;
end if;
when state_6 =>
if unsigned(persent_node(3 downto 0)) >9 then -- 前までの総計は63
if latched_quotient(6)='1' then
persent_node <= persent_node + x"06A"; -- +6+64
else
persent_node <= persent_node + x"006"; -- +6
end if;
else
if latched_quotient(6)='1' then
persent_node <= persent_node + x"064";
else
persent_node <= persent_node;
end if;
end if;
when state_7 => -- 前までの総計は127
if unsigned(persent_node(3 downto 0)) >9 then
if unsigned(persent_node(7 downto 4)) >9 then
if latched_quotient(7)='1' then
persent_node <= persent_node + x"18E"; -- +6+60+128=18E
else
persent_node <= persent_node + x"066"; -- +6+60
end if;
else -- +6補正のみ
if latched_quotient(7)='1' then
persent_node <= persent_node + x"12E"; -- +6+128
else
persent_node <= persent_node + x"006"; -- +6
end if;
end if;
else
if unsigned(persent_node(7 downto 4)) >9 then
if latched_quotient(7)='1' then
persent_node <= persent_node + x"188"; -- +60+128=18E
else
persent_node <= persent_node + x"060"; -- +60
end if;
else
if latched_quotient(7)='1' then
persent_node <= persent_node + x"128"; -- +128
else
persent_node <= persent_node;
end if;
end if;
end if;
when state_8 => -- 前までの総計は255
if unsigned(persent_node(3 downto 0)) >9 then
if unsigned(persent_node(7 downto 4)) >9 then
if latched_quotient(8)='1' then
persent_node <= persent_node + x"2BC"; -- +6+60+256=2BC
else
persent_node <= persent_node + x"066"; -- +6+60
end if;
else -- +6補正のみ
if latched_quotient(8)='1' then
persent_node <= persent_node + x"25C"; -- +6+256
else
persent_node <= persent_node + x"006"; -- +6
end if;
end if;
else
if unsigned(persent_node(7 downto 4)) >9 then
if latched_quotient(8)='1' then
persent_node <= persent_node + x"2B6"; -- +60+256=2B6
else
persent_node <= persent_node + x"060"; -- +60
end if;
else
if latched_quotient(8)='1' then
persent_node <= persent_node + x"256"; -- +256
else
persent_node <= persent_node;
end if;
end if;
end if;
when state_9 => -- 前までの総計は511
if unsigned(latched_quotient)>999 then -- 999よりも大きい
persent_node <= "100110011001"; -- 999
else
if unsigned(persent_node(3 downto 0)) >9 then
if unsigned(persent_node(7 downto 4)) >9 then
if latched_quotient(9)='1' then
persent_node <= persent_node + x"578"; -- +6+60+512=578
else
persent_node <= persent_node + x"066"; -- +6+60
end if;
else -- +6補正のみ
if latched_quotient(9)='1' then
persent_node <= persent_node + x"518"; -- +6+512
else
persent_node <= persent_node + x"006"; -- +6
end if;
end if;
else
if unsigned(persent_node(7 downto 4)) >9 then
if latched_quotient(9)='1' then
persent_node <= persent_node + x"572"; -- +60+512=572
else
persent_node <= persent_node + x"060"; -- +60
end if;
else
if latched_quotient(9)='1' then
persent_node <= persent_node + x"512"; -- +512
else
persent_node <= persent_node;
end if;
end if;
end if;
end if;
when state_10 => -- 10進補正のみ
if unsigned(persent_node(3 downto 0)) >9 then
if unsigned(persent_node(7 downto 4)) >9 or (unsigned(persent_node(3 downto 0)) >9 and unsigned(persent_node(7 downto 4))=9) then -- 桁が上がって2桁目がAになる時も+66補正をする
persent_node <= persent_node + x"066"; -- +6+60
else -- +6補正のみ
persent_node <= persent_node + x"006"; -- +6
end if;
else
if unsigned(persent_node(7 downto 4)) >9 then
persent_node <= persent_node + x"060"; -- +60
else
persent_node <= persent_node;
end if;
end if;
when others =>
persent_node <= persent_node;
end case;
end if;
end if;
end process;
process(clk) begin
if clk'event and clk='1' then
if reset='1' then
persent <= (others => '0');
else
if cs_bds=val_valid then
persent <= persent_node;
end if;
end if;
end if;
end process;
end RTL;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
ENTITY binary_decimal_test_tb IS
END binary_decimal_test_tb;
ARCHITECTURE behavior OF binary_decimal_test_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT binary_decimal_test
PORT(
clk : IN std_logic;
reset : IN std_logic;
complete : IN std_logic;
latched_quotient : IN std_logic_vector(9 downto 0);
persent : OUT std_logic_vector(11 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal complete : std_logic := '0';
signal latched_quotient : std_logic_vector(9 downto 0) := (others => '0');
--Outputs
signal persent : std_logic_vector(11 downto 0);
-- Clock period definitions
constant clk_period : time := 40 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: binary_decimal_test PORT MAP (
clk => clk,
reset => reset,
complete => complete,
latched_quotient => latched_quotient,
persent => persent
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
reset <= '1';
wait for 100 ns;
reset <= '0';
wait for clk_period*10;
-- insert stimulus here
STIMULUS_LOOP : for i in 0 to 1000 loop
wait until clk'event and clk='1';
wait for 1 ns;
latched_quotient <= CONV_STD_LOGIC_VECTOR(i, 10);
complete <= '1';
wait until clk'event and clk='1';
wait for 1 ns;
complete <= '0';
TRANS_WAIT_LOOP : for j in 0 to 10 loop -- 11クロックwait
wait until clk'event and clk='1';
wait for 1 ns;
end loop TRANS_WAIT_LOOP;
end loop STIMULUS_LOOP;
wait for clk_period*10;
assert (false) report "Simulation End!" severity failure;
end process;
END;
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE EP3C16F484C6
set_global_assignment -name TOP_LEVEL_ENTITY CLK_DATA_test
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "10.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "05:20:24 OCTOBER 21, 2010"
set_global_assignment -name LAST_QUARTUS_VERSION "10.0 SP1"
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name VERILOG_FILE CLK_DATA_test.v
set_global_assignment -name QIP_FILE clk_data_test_pll.qip
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_global_assignment -name MISC_FILE "H:/HDL/Altera/qdesigns/DE0/Test/CLK_DATA_test/CLK_DATA_test.dpf"
set_location_assignment PIN_AA3 -to clk_out
set_location_assignment PIN_Y2 -to dout[0]
set_location_assignment PIN_Y1 -to dout[1]
set_location_assignment PIN_M8 -to dout[2]
set_location_assignment PIN_N8 -to dout[3]
set_location_assignment PIN_T3 -to dout[4]
set_location_assignment PIN_M7 -to dout[5]
set_location_assignment PIN_P3 -to dout[6]
set_location_assignment PIN_M5 -to dout[7]
set_location_assignment PIN_G1 -to reset
set_location_assignment PIN_G2 -to clk
set_location_assignment PIN_V1 -to din[0]
set_location_assignment PIN_N2 -to din[1]
set_location_assignment PIN_V4 -to din[2]
set_location_assignment PIN_T4 -to din[3]
set_location_assignment PIN_W1 -to din[4]
set_location_assignment PIN_U2 -to din[5]
set_location_assignment PIN_U1 -to din[6]
set_location_assignment PIN_V2 -to din[7]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to dout[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to dout[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to dout[2]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to dout[3]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to dout[4]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to dout[5]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to dout[6]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to dout[7]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to din[0]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to din[1]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to din[2]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to din[3]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to din[4]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to din[5]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to din[6]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to din[7]
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
// CLK_DATA_test.v
`default_nettype none
module CLK_DATA_test (
input wire clk,
input wire reset,
input wire [7:0] din,
output wire clk_out,
output wire [7:0] dout
);
reg [7:0] d0, d1, d2;
wire c0_sig, c1_sig;
wire locked_sig;
wire reset_sig;
clk_data_test_pll clk_data_test_pll_inst (
.areset ( reset ),
.inclk0 ( clk ),
.c0 ( c0_sig ),
.c1 ( c1_sig ),
.locked ( locked_sig )
);
assign reset_sig = ~locked_sig;
always @(posedge c1_sig) begin
if (reset_sig) begin
d0 <= 8'd0;
d1 <= 8'd0;
d2 <= 8'd0;
end else begin
d0 <= din;
d1 <= d0;
d2 <= d1;
end
end
assign dout = d2;
assign clk_out = c0_sig;
endmodule
`default_nettype wire
Cyclone III PLL は、最大5 個のクロック出力（c0-c4）を備えています。c0 クロッ ク出力は、専用外部クロック出力ピン（推奨）、通常のユーザI/O または専用グ ローバル・クロック・ネットワークに接続することができます。
sscanf(argv[1], "%d",&bit_and);
_stscanf_s(argv[1], _T("%d"), &bit_and, sizeof(int));
// Data2BitLimit.cpp : コンソール アプリケーションのエントリ ポイントを定義します。
//
// 使い方：Data2BitLimit <落とすビット数> <元のBMPファイル名> <ビット数を落としたBMPファイル名>
//
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <iostream>
#include <cstring>
#include "stdafx.h"
int _tmain(int argc, _TCHAR* argv[])
{
_TCHAR org_file[100];
_TCHAR new_file[100];
BITMAPFILEHEADER bmpfh; // BMPファイルのファイルヘッダ
BITMAPINFOHEADER bmpih; // BMPファイルのINFOヘッダ
FILE *orgfp, *newfp;
BMP24FORMAT **bmp_data; // 24ビットのBMPファイルのデータ 640*480
int i, j;
int bit_and;
unsigned char bit_and_pt;
// 引数の処理
if (argc==1){ // 引数なしはエラー
fprintf(stderr, "使い方：Data2BitLimit <落とすビット数> <元のBMPファイル名(cam_bmp_file.bmp)> <ビット数を落としたBMPファイル名(new_bmp_file.bmp)>\n");
exit(1);
//bit_and = 2;
//_stprintf_s(org_file, 100, _T("cam_bmp_file.bmp"), 138);
//_stprintf_s(new_file, 100, _T("new_bmp_file.bmp"), 138);
} else if (argc==2) { // 引数１つ、落とすビット数
_stscanf_s(argv[1], _T("%d"), &bit_and, sizeof(int));
_stprintf_s(org_file, 100, _T("cam_bmp_file.bmp"), 138);
_stprintf_s(new_file, 100, _T("new_bmp_file.bmp"), 138);
} else if (argc==3) {
_stscanf_s(argv[1], _T("%d"), &bit_and, sizeof(int));
_stprintf_s(org_file, 100, argv[2]);
_stprintf_s(new_file, 100, _T("new_bmp_file.bmp"), 138);
} else { // それ以外
_stscanf_s(argv[1], _T("%d"), &bit_and, sizeof(int));
_stprintf_s(org_file, 100, argv[2]);
_stprintf_s(new_file, 100, argv[3]);
}
if (_tfopen_s(&orgfp, org_file, _T("rb")) != 0) { // org_fileをバイナリリードモードでオープン
fprintf(stderr, "Can't Open %s\n", org_file);
exit(1);
}
if (_tfopen_s(&newfp, new_file, _T("wb")) != 0) { // new_fileをバイナリライトモードでオープン
fprintf(stderr, "Can't Open %s\n", new_file);
exit(1);
}
// BMPファイルヘッダの読み出し
fread(&bmpfh.bfType, sizeof(short), 1, orgfp);
fread(&bmpfh.bfSize, sizeof(long), 1, orgfp);
fread(&bmpfh.bfReserved1, sizeof(short), 1, orgfp);
fread(&bmpfh.bfReserved2, sizeof(short), 1, orgfp);
fread(&bmpfh.bfOffBits, sizeof(long), 1, orgfp);
fread(&bmpih.biSize, sizeof(long), 1, orgfp);
fread(&bmpih.biWidth, sizeof(long), 1, orgfp);
fread(&bmpih.biHeight, sizeof(long), 1, orgfp);
fread(&bmpih.biPlanes, sizeof(unsigned short), 1, orgfp);
fread(&bmpih.biBitCount, sizeof(unsigned short), 1, orgfp);
fread(&bmpih.biCompression, sizeof(unsigned long), 1, orgfp);
fread(&bmpih.biSizeImage, sizeof(unsigned long), 1, orgfp);
fread(&bmpih.biXPixPerMeter, sizeof(long), 1, orgfp);
fread(&bmpih.biYPixPerMeter, sizeof(long), 1, orgfp);
fread(&bmpih.biClrUsed, sizeof(unsigned long), 1, orgfp);
fread(&bmpih.biClrImporant, sizeof(unsigned long), 1, orgfp);
// BMPファイルヘッダの書き込み
fwrite(&bmpfh.bfType, sizeof(short), 1, newfp);
fwrite(&bmpfh.bfSize, sizeof(long), 1, newfp);
fwrite(&bmpfh.bfReserved1, sizeof(short), 1, newfp);
fwrite(&bmpfh.bfReserved2, sizeof(short), 1, newfp);
fwrite(&bmpfh.bfOffBits, sizeof(long), 1, newfp);
fwrite(&bmpih.biSize, sizeof(long), 1, newfp);
fwrite(&bmpih.biWidth, sizeof(long), 1, newfp);
fwrite(&bmpih.biHeight, sizeof(long), 1, newfp);
fwrite(&bmpih.biPlanes, sizeof(unsigned short), 1, newfp);
fwrite(&bmpih.biBitCount, sizeof(unsigned short), 1, newfp);
fwrite(&bmpih.biCompression, sizeof(unsigned long), 1, newfp);
fwrite(&bmpih.biSizeImage, sizeof(unsigned long), 1, newfp);
fwrite(&bmpih.biXPixPerMeter, sizeof(long), 1, newfp);
fwrite(&bmpih.biYPixPerMeter, sizeof(long), 1, newfp);
fwrite(&bmpih.biClrUsed, sizeof(unsigned long), 1, newfp);
fwrite(&bmpih.biClrImporant, sizeof(unsigned long), 1, newfp);
// メモリをアロケートする
if ((bmp_data=(BMP24FORMAT **)malloc(sizeof(BMP24FORMAT *)*bmpih.biHeight)) == NULL){
fprintf(stderr, "bmp_dataの1次元目の480ののメモリを確保できません\n");
exit(1);
}
for (i=0; i<bmpih.biHeight; i++){
if ((bmp_data[i]=(BMP24FORMAT *)malloc(sizeof(BMP24FORMAT) * bmpih.biWidth)) == NULL){
fprintf(stderr, "bmp_dataの2次元目の%d番目のメモリが確保できません\n");
exit(1);
}
}
// ビットを落として書き込む
for (i=0, bit_and_pt=0; i<bit_and; i++)
bit_and_pt = bit_and_pt | (1<<i);
bit_and_pt = 0xff ^ bit_and_pt;
for (i=0; i<bmpih.biHeight; i+=1){
for (j=0; j<bmpih.biWidth; j+=1){
bmp_data[i][j].blue = fgetc(orgfp);
bmp_data[i][j].green = fgetc(orgfp);
bmp_data[i][j].red = fgetc(orgfp);
fputc((int)(bmp_data[i][j].blue & bit_and_pt), newfp);
fputc((int)(bmp_data[i][j].green & bit_and_pt), newfp);
fputc((int)(bmp_data[i][j].red & bit_and_pt), newfp);
}
}
fclose(orgfp);
fclose(newfp);
for (i=0; i<bmpih.biHeight; i++)
free(bmp_data[i]);
free(bmp_data);
return 0;
}
fread(&bmpfh, sizeof(BITMAPFILEHEADER), 1, orgfp);
fread(&bmpih, sizeof(BITMAPINFOHEADER), 1, orgfp);
例えばCortex-A9のハード・コアを搭載した28nm世代FPGAを2011年に発表する予定である。
set -tmpdir "xst/projnav.tmp"
set -xsthdpdir "xst"
run
-ifn CamDisp_Cntrler_DDR2.prj
-ifmt mixed
-ofn CamDisp_Cntrler_DDR2
-ofmt NGC
-p xc3s700a-4-fg484
-top CamDisp_Cntrler_DDR2
-opt_mode Speed
-opt_level 1
-iuc NO
-keep_hierarchy No
-netlist_hierarchy Rebuilt
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-sd {"ipcore_dir" }
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case Maintain
-slice_utilization_ratio 100
-bram_utilization_ratio 100
-verilog2001 YES
-vlgincdir { "H:/HDL/OVL/std_ovl" "H:/HDL/FndtnISEWork/Spartan3A_starter_kit/CamDispCntrler_DDR2_Capt_SCCB_WS/Sources" "H:/HDL/FndtnISEWork/Spartan3A_starter_kit/DDR2_SDRAM_cont_266/Sources/ddr2_sdram_cont" }
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style LUT
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-mux_style Auto
-decoder_extract YES
-priority_extract Yes
-shreg_extract YES
-shift_extract YES
-xor_collapse YES
-rom_style Auto
-auto_bram_packing NO
-mux_extract Yes
-resource_sharing YES
-async_to_sync NO
-mult_style Auto
-iobuf YES
-max_fanout 500
-bufg 24
-register_duplication YES
-register_balancing No
-slice_packing YES
-optimize_primitives NO
-use_clock_enable Yes
-use_sync_set Yes
-use_sync_reset Yes
-iob Auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5
-- Divider Test(Divider_test.vhd)
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity Divider_test is
port (
clk: IN std_logic;
ce: IN std_logic;
rfd: OUT std_logic;
dividend: IN std_logic_VECTOR(22 downto 0);
quotient: OUT std_logic_VECTOR(22 downto 0);
fractional: OUT std_logic_VECTOR(14 downto 0)
);
end Divider_test;
architecture RTL of Divider_test is
component divider_per
port (
clk: IN std_logic;
ce: IN std_logic;
rfd: OUT std_logic;
dividend: IN std_logic_VECTOR(22 downto 0);
divisor: IN std_logic_VECTOR(14 downto 0);
quotient: OUT std_logic_VECTOR(22 downto 0);
fractional: OUT std_logic_VECTOR(14 downto 0));
end component;
signal divisor: std_logic_VECTOR(14 downto 0);
begin
divider_per_inst : divider_per port map (
clk => clk,
ce => ce,
rfd => rfd,
dividend => dividend,
divisor => divisor,
quotient => quotient,
fractional => fractional
);
divisor <= "110000000000000";
end RTL;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Divider_test_tb IS
END Divider_test_tb;
ARCHITECTURE behavior OF Divider_test_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Divider_test
PORT(
clk : IN std_logic;
ce : IN std_logic;
rfd : OUT std_logic;
dividend : IN std_logic_vector(22 downto 0);
quotient : OUT std_logic_vector(22 downto 0);
fractional : OUT std_logic_vector(14 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal ce : std_logic := '0';
signal dividend : std_logic_vector(22 downto 0) := (others => '0');
--Outputs
signal rfd : std_logic;
signal quotient : std_logic_vector(22 downto 0);
signal fractional : std_logic_vector(14 downto 0);
-- Clock period definitions
constant clk_period : time := 40 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Divider_test PORT MAP (
clk => clk,
ce => ce,
rfd => rfd,
dividend => dividend,
quotient => quotient,
fractional => fractional
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
ce <= '0';
dividend <= "00000000000000000000000";
wait for clk_period*2;
ce <= '1';
dividend <= "00000000110000000000000";
wait for clk_period*2;
ce <= '1';
dividend <= "00000011100000000000000";
wait for clk_period*10;
wait;
end process;
END;
| 日 | 月 | 火 | 水 | 木 | 金 | 土 |
|---|---|---|---|---|---|---|
| - | - | - | - | - | 1 | 2 |
| 3 | 4 | 5 | 6 | 7 | 8 | 9 |
| 10 | 11 | 12 | 13 | 14 | 15 | 16 |
| 17 | 18 | 19 | 20 | 21 | 22 | 23 |
| 24 | 25 | 26 | 27 | 28 | 29 | 30 |
| 31 | - | - | - | - | - | - |