// state check
switch (setting_item) {
case AGC_SET :
if (current_state == SETTING_ITEM_ST){
if (rot_pulse == left_pulse)
setting_item = MIRROR_SET;
else if (rot_pulse == right_pulse)
setting_item = GAIN_LEVEL_SET;
} else { // AGC ON -> OFF, OFF -> ON
if (rot_pulse != no_pulse){
if (agc_reg){
agc_reg = 0;
reg13 = AGC_OFF_2_SCCB13;
}else{
agc_reg = 1;
reg13 = AGC_ON_2_SCCB13;
}
while (XIo_In8(STATUS_ADDR) & 0x08) ; // SCCB_busy
*SCCB_Reg_Write = (((0x13)<<8) | reg13); // Dummy Write
while (XIo_In8(STATUS_ADDR) & 0x08) ; // SCCB_busy
*SCCB_Reg_Write = (((0x13)<<8) | reg13); // addr data
}
}
break;
NET "cam_sio_d" LOC = "AB2" | IOSTANDARD = LVTTL | PULLUP ;
13EB
process begin
DOUT <= (others => '0');
BE <= (others => '0');
ADDR <= (others => '0');
CS <= '0';
wait for 100 ns;
-- これから下のwaitまでの間にスティミュラスを書く
-- SMM_WR_CYCLE(TIMER_ADDR, X"00000010", "1111", clk, rnw, cs, addr, dout, be); -- Timerへ書き込み、16クロックカウント
-- wait until INTERRUPT_ACK_node'event and INTERRUPT_ACK_node='1'; -- INTERRUPT_ACK_node の立ち上がりまでwait
-- wait for 1 ns;
-- SMM_WR_CYCLE(LCD_ADDR, X"12340000", "1111", clk, rnw, cs, addr, dout, be); -- LCDへ書き込み
-- -- ボタンの状況をrd_dataに読み出し
-- SMM_RD_CYCLE(BUTTON_ADDR, "1111", rd_data, clk, rnw, cs, addr, din, be);
wait for 460 us;
SMM_WR_CYCLE(SCCB_REG_WR, X"12340000", "1111", clk, rnw, cs, addr, dout, be); -- OV7670の設定レジスタへ書き込み
wait;
end process;
rm CamDispCntrler_DDR2_tb.exe
K:\HDL\Xilinx\12.4\ISE_DS\ISE\bin\nt\fuse work.CamDispCntrler_DDR2_tb work.glbl -incremental -d OVL_VERLOG -i ..\ -i ..\..\..\DDR2_SDRAM_cont_266\Simulation\512Mb_ddr2 -i H:\HDL\OVL\std_ovl -d sg3 -d x16 -d OVL_ASSERT_ON -d OVL_FINISH_OFF -L unisims_ver=%XILINX%\verilog\hdp\nt\unisims_ver -L unimacro_ver=%XILINX%\verilog\hdp\nt\unimacro_ver -L XilinxCoreLib_ver=%XILINX%\verilog\hdp\nt\xilinxcorelib_ver -L accellera_ovl_vlog=%XILINX%\verilog\hdp\nt\accellera_ovl_vlog -o CamDispCntrler_DDR2_tb.exe -prj CamDispCntrler_DDR2_Capt_SCCB_tb.prj
CamDispCntrler_DDR2_tb.exe -gui
verilog work ../../../DDR2_SDRAM_cont_266/Sources/ddr2_sdram_cont/addr_fifo.v
verilog work ../../../DDR2_SDRAM_cont_266/Sources/ddr2_sdram_cont/async_fifo_fall.v
verilog work ../../../DDR2_SDRAM_cont_266/Sources/ddr2_sdram_cont/async_fifo_rise.v
verilog work ../../../DDR2_SDRAM_cont_266/Sources/ddr2_sdram_cont/controller.v
verilog work ../../../DDR2_SDRAM_cont_266/Sources/ddr2_sdram_cont/dcm_module.v
verilog work ../../../DDR2_SDRAM_cont_266/Sources/ddr2_sdram_cont/ddr2_cont_iob.v
verilog work ../../../DDR2_SDRAM_cont_266/Sources/ddr2_sdram_cont/dm_io_pad.v
verilog work ../../../DDR2_SDRAM_cont_266/Sources/ddr2_sdram_cont/dq_io_pad.v
verilog work ../../../DDR2_SDRAM_cont_266/Sources/ddr2_sdram_cont/dqs_io_pad.v
verilog work ../../../DDR2_SDRAM_cont_266/Sources/ddr2_sdram_cont/dqsb_io_pad.v
verilog work ../../../DDR2_SDRAM_cont_266/Sources/ddr2_sdram_cont/rddata_afifo.v
verilog work ../../../DDR2_SDRAM_cont_266/Sources/ddr2_sdram_cont/read_write_io.v
verilog work ../../../DDR2_SDRAM_cont_266/Sources/ddr2_sdram_cont/REFREQSM.v
verilog work ../../../DDR2_SDRAM_cont_266/Sources/ddr2_sdram_cont/wrdata_fifo.v
verilog work ../../../DDR2_SDRAM_cont_266/Sources/ddr2_sdram_cont/ddr2_sdram_cont.v
verilog work "../../Synth122/ipcore_dir/cam_cont_afifo.v"
verilog work "../../Synth122/ipcore_dir/cam_data_afifo.v"
verilog work ../../Sources/SWDiv.v
verilog work ../../Sources/SW_Controller.v
verilog work ../../Sources/VGA_Display_Controller.v
verilog work ../../Sources/Arbiter.v
verilog work ../../Sources/Camera_Controller.v
verilog work ../../Sources/dcm_CAM_DDR2_clk.v
verilog work ../../Sources/synchronizer.v
vhdl work ../../Sources/freqdiv.vhd
vhdl work ../../Sources/One_Transaction_SCCB.vhd
vhdl work ../../Sources/SCCB_Reg_Controller.vhd
vhdl work ../../Sources/SCCB_reg_values_ROM.vhd
vhdl work ../../Sources/lcd_rot_cont.vhd
vhdl work ../SMM_noUART_sim_pack.vhd
vhdl work ../lcd_rot_cont_smm.vhd
vhdl work ../../Sources/lcd_ctlr.vhd
vhdl work ../../Sources/timer.vhd
vhdl work ../../Sources/rot_enc_cont.vhd
vhdl work ../../Sources/swdiv_rot.vhd
vhdl work ../../Sources/ROTSW_SM.vhd
verilog work ../../Sources/CamDisp_Cntrler_DDR2.v
verilog work ../OV7670_Model.v
verilog work H:\HDL\FndtnISEWork\Spartan3A_starter_kit\DDR2_SDRAM_cont_266\Simulation\512Mb_ddr2\ddr2.v
verilog work ../CamDispCntrler_DDR2_tb.v
verilog work H:\HDL\Xilinx\12.2\ISE_DS\ISE\verilog\src\glbl.v
ERROR:Pack:2310 - Too many comps of type "BSCAN" found to fit this device.
ERROR:Pack:18 - The design is too large for the given device and package.
Please check the Design Summary section to see which resource requirement for
your design exceeds the resources available in the device.
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_arith.all;
entity mult_test is
port (
clk : in std_logic;
reset : in std_logic;
ina : in std_logic_vector(7 downto 0);
mult_out : out std_logic_vector(17 downto 0)
);
end mult_test;
architecture RTL of mult_test is
signal mult : std_logic_vector(17 downto 0);
signal temp : std_logic_vector(8 downto 0);
begin
temp <= "111110000";
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
mult <= (others => '0');
else
mult <= unsigned(ina) * signed(temp);
end if;
end if;
end process;
mult_out <= mult;
end RTL;
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_arith.all;
entity mult_test is
port (
clk : in std_logic;
reset : in std_logic;
ina : in std_logic_vector(7 downto 0);
mult_out : out std_logic_vector(17 downto 0)
);
end mult_test;
architecture RTL of mult_test is
signal mult : std_logic_vector(17 downto 0);
begin
process(clk) begin
if clk'event and clk='1' then
if reset='1' then
mult <= (others => '0');
else
mult <= unsigned(ina) * signed'("111110000");
end if;
end if;
end process;
mult_out <= mult;
end RTL;
mult <= unsigned(ina) * signed'("111110000");
mult <= unsigned(ina) * signed(std_logic_vector'("111110000"));
/* _STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x400; */
_STACK_SIZE = 0x1000;
mb-size empty_application_0.elf |tee "empty_application_0.elf.size"
text data bss dec hex filename
6806 312 5186 12304 3010 empty_application_0.elf
int func1(. . . ); //func1 prototype defined here
int main(void) //main defined here
{
:
:
}
int func1(. . . ) //func1 defined here
{
:
:
}
// lcd_rot_cont.h
void Timer_Wait (Xuint32 delay);
void lcd_init (void);
void lcd_print (Xuint32 Line, Xuint8 *Str);
void lcd_clear (void);
void timer_int_handler(void * arg);
void SCCB_reg_init(void);
char *ntoxn(char *str, unsigned short int x, int n);
char *strcpyc(char *s1, char *s2);
void SCCB_reg_status_disp(Xuint8 *Str);
void SCCB_cur_reg_disp(Xuint8 *Str);
void gain_level_reg_set(void);
void aec_level_h_reg_set(void);
void aec_level_l_reg_set(void);
int main(void);
**** Build of configuration Debug for project empty_application_0 ****
make all
Building file: ../src/lcd_rot_cont.c
Invoking: MicroBlaze gcc compiler
mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -I../../empty_application_bsp_0/microblaze_0/include -mcpu=v7.30.a -mno-xl-soft-mul -MMD -MP -MF"src/lcd_rot_cont.d" -MT"src/lcd_rot_cont.d" -o"src/lcd_rot_cont.o" "../src/lcd_rot_cont.c"
Finished building: ../src/lcd_rot_cont.c
Building target: empty_application_0.elf
Invoking: MicroBlaze gcc linker
mb-gcc -Wl,-T -Wl,../src/lscript.ld -L../../empty_application_bsp_0/microblaze_0/lib -mcpu=v7.30.a -mno-xl-soft-mul -o"empty_application_0.elf" ./src/lcd_rot_cont.o
Finished building target: empty_application_0.elf
Invoking: MicroBlaze Print Size
mb-size empty_application_0.elf |tee "empty_application_0.elf.size"
text data bss dec hex filename
6730 312 2118 9160 23c8 empty_application_0.elf
Finished building: empty_application_0.elf.size
Invoking: Xilinx ELF Check
elfcheck empty_application_0.elf -hw ../../SMM_DBG_noUART_hw_platform/system.xml -pe microblaze_0 |tee "empty_application_0.elf.elfcheck"
elfcheck
Xilinx EDK 12.3 Build EDK_MS3.70d
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Command Line: elfcheck -hw ../../SMM_DBG_noUART_hw_platform/system.xml -pe
microblaze_0 empty_application_0.elf
ELF file : empty_application_0.elf
elfcheck passed.
Finished building: empty_application_0.elf.elfcheck
--------------
Number of errors : 87
Number of warnings : 91
ERROR:Xflow - Program map returned error code 2. Aborting flow execution...
Done!
smm.ngc : SMM_S3_BRAM_16K\SMM_DBG_noUART\implementation\smm.ngc
smm.bmm : SMM_S3_BRAM_16K\SMM_DBG_noUART\implementation\smm_stub.ngc
smm.xml : SMM_S3_BRAM_16K\SMM_DBG_noUART\SDK\SDK_Export\hw\smm.xml
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY mult_test_tb IS
END mult_test_tb;
ARCHITECTURE behavior OF mult_test_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT mult_test
PORT(
clk : IN std_logic;
reset : IN std_logic;
ina : IN std_logic_vector(8 downto 0);
inb : IN std_logic_vector(8 downto 0);
mult_out : OUT std_logic_vector(17 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal ina : std_logic_vector(8 downto 0) := (others => '0');
signal inb : std_logic_vector(8 downto 0) := (others => '0');
--Outputs
signal mult_out : std_logic_vector(17 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: mult_test PORT MAP (
clk => clk,
reset => reset,
ina => ina,
inb => inb,
mult_out => mult_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
reset <= '1';
wait for 100 ns;
reset <= '0';
wait for clk_period*10;
-- insert stimulus here
ina <= "000000010";
inb <= "000000011";
wait for 450 ns;
ina <= "000000011";
inb <= "111111111";
wait;
end process;
END;
-- mult test
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity mult_test is
port (
clk : in std_logic;
reset : in std_logic;
ina : in std_logic_vector(8 downto 0);
inb : in std_logic_vector(8 downto 0);
mult_out : out std_logic_vector(17 downto 0)
);
end mult_test;
architecture RTL of mult_test is
begin
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
mult_out <= (others => '0');
else
mult_out <= ina * inb;
end if;
end if;
end process;
end RTL;
mult_out <= unsigned(ina) * signed(inb);
ERROR:HDLCompiler:410 - "\HDL\FndISEWork\DWM2008_07\Graphic_board2\test\mult_test\Synth123\../mult_test.vhd" Line 32: Expression has 19 elements ; expected 18
process(clk)
variable i, j, k : integer := 0;
begin
if clk'event and clk='1' then
if reset='1' then
mult_out <= (others => '0');
else
i := CONV_INTEGER(unsigned(ina));
j := CONV_INTEGER(signed(inb));
k := i * j;
mult_out <= CONV_STD_LOGIC_VECTOR(k, 18);
end if;
end if;
end process;
mult <= unsigned(ina) * signed("111110000");
signal temp : std_logic_vector(8 downto 0);
begin
temp <= "111110000";
process(clk) begin
if clk'event and clk='1' then
if reset='1' then
mult <= (others => '0');
else
mult <= unsigned(ina) * signed(temp);
end if;
end if;
end process;
../../empty_application_bsp_0/microblaze_0/lib/libxil.a(write.o): In function `write':
/gnu/mb_gnu/src/gcc/libgloss/microblaze/write.c:36: undefined reference to `outbyte'
/gnu/mb_gnu/src/gcc/libgloss/microblaze/write.c:34: undefined reference to `outbyte'
../../empty_application_bsp_0/microblaze_0/lib/libxil.a(read.o): In function `read':
/gnu/mb_gnu/src/gcc/libgloss/microblaze/read.c:35: undefined reference to `inbyte'
このエラーは、[Software Platform Settings] で stdout が None に設定されているのに print 関数で有効な stdout が必要になるために発生します。
[Software] > [Software Platform Settings] > [OS and Libraries] で有効な stdout を設定してライブラリを生成し直すとこの問題を解決できます。
switch (setting_item) {
case AGC_SET :
if (agc_reg)
i = sprintf((char *)Str, "AGC ON");
else
i = sprintf((char *)Str, "AGC OFF");
break;
case GAIN_LEVEL_SET :
i = sprintf((char *)Str, "AGC GAIN %03x", gain_level);
break;
/cygdrive/k/HDL/Xilinx/12.3/ISE_DS/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze-xilinx-elf/4.1.2/../../../../microblaze-xilinx-elf/bin/ld: region ilmb_cntlr_dlmb_cntlr is full (empty_application_0.elf section .text)
/cygdrive/k/HDL/Xilinx/12.3/ISE_DS/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze-xilinx-elf/4.1.2/../../../../microblaze-xilinx-elf/bin/ld: empty_application_0.elf: section .text lma 0x50 overlaps previous sections
/cygdrive/k/HDL/Xilinx/12.3/ISE_DS/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze-xilinx-elf/4.1.2/../../../../microblaze-xilinx-elf/bin/ld: empty_application_0.elf: section .fini lma 0x78 overlaps previous sections
/cygdrive/k/HDL/Xilinx/12.3/ISE_DS/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze-xilinx-elf/4.1.2/../../../../microblaze-xilinx-elf/bin/ld: empty_application_0.elf: section .rodata lma 0x98 overlaps previous sections
/cygdrive/k/HDL/Xilinx/12.3/ISE_DS/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze-xilinx-elf/4.1.2/m/crtend.o:(.init+0x0): relocation truncated to fit: R_MICROBLAZE_32_PCREL_LO against `.text'
collect2: ld returned 1 exit status
make: *** [empty_application_0.elf] Error 1
/cygdrive/k/HDL/Xilinx/12.3/ISE_DS/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze-xilinx-elf/4.1.2/../../../../microblaze-xilinx-elf/bin/ld: region ilmb_cntlr_dlmb_cntlr is full (empty_application_0.elf section .heap)
#define SCCB_REG_00 0x00 // SCCB Register Address 0x00 (GAIN[7:0])
#define SCCB_REG_01 0x40 // SCCB Register Address 0x01 (AWB RED)
#define SCCB_REG_02 0x60 // SCCB Register Address 0x02 (AWB BLUE)
#define SCCB_REG_03 0x0A // SCCB Register Address 0x03 ([7:6] - GAIN LEVEL[9:8])
#define SCCB_REG_04 0x00 // SCCB Register Address 0x04 ([1:0] - AEC LEVEL L[1:0])
#define SCCB_REG_07 0x00 // SCCB Register Address 0x07 ([5:0] - AEC LVEVL H[7:2])
#define SCCB_REG_10 0x00 // SCCB Register Address 0x10 ([5:0] - AEC LEVEL L[7:2])
#define SCCB_REG_13 0xEF // SCCB Register Address 0x13 ([2] - AGC, [1] - AWB, [0] - AEC)
#define SCCB_REG_1E 0x27 // SCCB Register Address 0x1E ([5] - MIRROR)
#define awb_red reg01
#define awb_blue reg02
#define SCCB_2_AGC ((reg13 & 0x04)>>2)
#define AGC_2_SCCB ((agc_reg & 0x01)<<2)
#define SCCB_2_AWB ((reg13 & 0x02)>>1)
#define AWB_2_SCCB ((awb_reg & 0x01)<<1)
#define SCCB_2_AEC (reg13 & 0x1)
#define AEC_2_SCCB (aec_reg & 0x01)
#define SCCB_2_GAIN_LEVEL (((reg03 & 0xC0)<<2) | reg00)
#define GAIN_LEVEL_2_SCCB03 ((gain_level & 0x300)>>2)
#define GAIN_LEVEL_2_SCCB00 (gain_level & 0xFF)
/* Global Variable */
// SCCB Register Variable
unsigned char reg00 = SCCB_REG_00;
unsigned char reg01 = SCCB_REG_01;
unsigned char reg02 = SCCB_REG_02;
unsigned char reg03 = SCCB_REG_03;
unsigned char reg04 = SCCB_REG_04;
unsigned char reg07 = SCCB_REG_07;
unsigned char reg10 = SCCB_REG_10;
unsigned char reg13 = SCCB_REG_13;
unsigned char reg1E = SCCB_REG_1E;
unsigned char agc_reg;
unsigned short int gain_level;
unsigned char awb_reg;
unsigned char aec_reg;
unsigned char aec_level_h;
unsigned char aec_level_l;
unsigned char mirror_reg;
entity SCCB_Reg_Controller is
port(
clk : in std_logic; -- クロック
reset : in std_logic; -- リセット
addr_data : in std_logic_vector(15 downto 0); -- SMMから設定されるSCCB設定レジスタのアドレスとデータ
ad_enable : in std_logic; -- addr_data信号のイネーブルパルス
SCCB_busy : out std_logic; -- SCCBレジスタを設定中を表すbusyフラグ
SCL : out std_logic; -- SCCBのクロック
SDA : out std_logic -- SCCBのデータ
);
end SCCB_Reg_Controller;
-- One_Transaction_SCCB のインスタンス
One_Transaction_SCCB_inst : One_Transaction_SCCB port map(
clk => clk,
reset => reset,
SCCB_address => SCCB_address,
SCCB_data => SCCB_data,
op_enable => op_enable,
start_pulse => SCCB_start_pulse,
end_pulse => end_pulse,
SCL => SCL,
SDA => SDA
);
-- セレクタ、初期化が終了するまではROMのデータを選択して、終了した後ではSMMからの設定を選択する
SCCB_address <= ROM_data(15 downto 8) when cs_reg_set/=end_state else addr_data(15 downto 8);
SCCB_data <= ROM_data(7 downto 0) when cs_reg_set/=end_state else addr_data(7 downto 0);
SCCB_start_pulse <= start_pulse when cs_reg_set/=end_state else ad_enable;
-- SCCB_busyの制御
process(clk) begin
if clk'event and clk='1' then
if reset='1' then
cs_SCCB_busy <= idle_SCCB_busy;
SCCB_busy_node <= '1';
else
case cs_SCCB_busy is
when idle_SCCB_busy =>
if cs_reg_set=end_state then -- 初期設定が終了
cs_SCCB_busy <= initialize_end;
SCCB_busy_node <= '0';
end if;
when initialize_end =>
if ad_enable='1' then -- SMMのSCCBレジスタ設定開始
cs_SCCB_busy <= SCCB_setting;
SCCB_busy_node <= '1';
end if;
when SCCB_setting =>
if end_pulse='1' then -- SMMのSCCBレジスタ設定終了
cs_SCCB_busy <= initialize_end;
SCCB_busy_node <= '0';
end if;
end case;
end if;
end if;
end process;
SCCB_busy <= SCCB_busy_node;
entity lcd_rot_cont is
Port ( clk : in STD_LOGIC;
Reset : in STD_LOGIC;
rot_a : in std_logic;
rot_b : in std_logic;
rot_center : in std_logic;
Button_S : in STD_LOGIC;
LCD_DB : out STD_LOGIC_VECTOR (7 downto 0);
LCD_RS : out STD_LOGIC;
LCD_RW : out STD_LOGIC;
LCD_E : out STD_LOGIC;
SCCB_addr_data : out std_logic_vector(15 downto 0); -- SMMから設定されるSCCB設定レジスタのアドレスとデータ
SCCB_ad_enable : out std_logic; -- addr_data信号のイネーブルパルス
SCCB_busy : in std_logic -- SCCBレジスタを設定中を表すbusyフラグ
);
end lcd_rot_cont;
CS_SCCB_wr <= '1' when ((ADDR = X"0040") and CS = '1' and RNW = '0') else '0' ;
-- SCCB_ad_enable の生成
process(clk) begin
if clk'event and clk='1' then
if Reset='1' then
SCCB_ad_enable <= '0';
else
if CS_SCCB_wr='1' and CS_SCCB_wr_1d='0' then
SCCB_ad_enable <= '1';
else
SCCB_ad_enable <= '0';
end if;
end if;
end if;
end process;
SCCB_addr_data <= DOUT(0 to 15); -- 上位16ビット
-- ロータリーエンコーダ
rot_enc_cont_i : rot_enc_cont port map(
clk => clk,
reset => Reset,
rot_a => rot_a,
rot_b => rot_b,
rot_center => rot_center,
right_pulse => right_pulse,
left_pulse => left_pulse,
center_pulse => center_pulse
);
DIN (0) <= Button_S_int;
DIN (1) <= right_pulse;
DIN (2) <= left_pulse;
DIN (3) <= rot_center;
DIN (4 to 31) <= (others => '0') ; -- Not used
-- right_pulse, left_pulse をホールドするFF
process(clk) begin
if clk'event and clk='1' then
if Reset='1' then
right_hold <= '0';
left_hold <= '0';
else
if right_pulse = '1' then
right_hold <= '1';
elsif CS_rot_enc_wr='1' then
right_hold <= '0';
end if;
if left_pulse='1' then
left_hold <= '1';
elsif CS_rot_enc_wr='1' then
left_hold <= '0';
end if;
end if;
end if;
end process;
CS_rot_enc_wr <= '1' when ((ADDR = X"0030") and CS = '1' and RNW = '0') else '0' ;
DIN (0) <= Button_S_int;
DIN (1) <= right_hold;
DIN (2) <= left_hold;
DIN (3) <= rot_center;
DIN (4 to 31) <= (others => '0') ; -- Not used
while (1) {
while (1){
button_push = XIo_In8(STATUS_ADDR);
if (button_push == 0x10) break;
else if (button_push == 0x20) break;
else if (button_push == 0x40) break;
}
// Clear the LCD
lcd_clear();
// Print to the LCD
if (button_push == 0x10){
lcd_print(1, "rot_center ON");
} else if (button_push == 0x40){ // right -> left
XIo_Out32(ROT_ENC_ADDR, 0);
lcd_print(2, "left_pulse");
} else if (button_push == 0x20){ // left -> right
XIo_Out32(ROT_ENC_ADDR, 0);
lcd_print(2, "right_pulse");
}
}
-- DCM50_to_25MHz
Inst_DCM50_to_25MHz: DCM50_to_25MHz PORT MAP(
CLKIN_IN => Clock,
RST_IN => Reset,
CLKDV_OUT => clk,
CLKIN_IBUFG_OUT => open,
CLK0_OUT => open,
LOCKED_OUT => dcm_locked
);
reset_locked <= not dcm_locked;
constant CLK_PERIOD : integer := 40 ; -- in ns 50MHzから25MHzに変更
-- constant CLK_PERIOD : integer := 20 ; -- in ns
-- SMM_noUART用パッケージ
library ieee;
use ieee.std_logic_1164.all;
package SMM_noUART_sim_pack is
procedure SMM_WR_CYCLE(
WR_ADDR : in std_logic_vector; -- 書き込みアドレスをセットする
WR_DATA : in std_logic_vector; -- 書きこむデータをセットする
WR_BE : in std_logic_vector; -- 書きこむBEをセットする
signal clk : in std_logic;
signal rnw : out std_logic;
signal cs : out std_logic;
signal addr : out std_logic_vector;
signal dout : out std_logic_vector;
signal be : out std_logic_vector
);
procedure SMM_RD_CYCLE(
RD_ADDR : in std_logic_vector; -- 読み出しアドレスをセットする
RD_BE : in std_logic_vector; -- 読み出し時のBEをセットする
signal RD_DATA : out std_logic_vector; -- 読み出しデータ
signal clk : in std_logic;
signal rnw : out std_logic;
signal cs : out std_logic;
signal addr : out std_logic_vector;
din : in std_logic_vector;
signal be : out std_logic_vector
);
end SMM_noUART_sim_pack;
package body SMM_noUART_sim_pack is
procedure SMM_WR_CYCLE(
WR_ADDR : in std_logic_vector; -- 書き込みアドレスをセットする
WR_DATA : in std_logic_vector; -- 書きこむデータをセットする
WR_BE : in std_logic_vector; -- 書きこむBEをセットする
signal clk : in std_logic;
signal rnw : out std_logic;
signal cs : out std_logic;
signal addr : out std_logic_vector;
signal dout : out std_logic_vector;
signal be : out std_logic_vector
) is
begin
wait until clk'event and clk='1'; -- clkの立ち上がりまでwait
wait for 1 ns; -- 遅延を挟んで
rnw <= '0'; -- Write
cs <= '1'; -- enable
addr <= WR_ADDR;
dout <= WR_DATA;
be <= WR_BE;
wait until clk'event and clk='1'; -- clkの立ち上がりまでwait
wait for 1 ns; -- 遅延を挟んで
cs <= '0';
end SMM_WR_CYCLE;
procedure SMM_RD_CYCLE(
RD_ADDR : in std_logic_vector; -- 読み出しアドレスをセットする
RD_BE : in std_logic_vector; -- 読み出し時のBEをセットする
signal RD_DATA : out std_logic_vector; -- 読み出しデータ
signal clk : in std_logic;
signal rnw : out std_logic;
signal cs : out std_logic;
signal addr : out std_logic_vector;
din : in std_logic_vector;
signal be : out std_logic_vector
) is
begin
wait until clk'event and clk='1'; -- clkの立ち上がりまでwait
wait for 1 ns; -- 遅延を挟んで
rnw <= '1'; -- Read
cs <= '1'; -- enable
addr <= RD_ADDR;
be <= RD_BE;
wait until clk'event and clk='1'; -- clkの立ち上がりまでwait
RD_DATA <= din;
wait for 1 ns; -- 遅延を挟んで
cs <= '0';
end SMM_RD_CYCLE;
end SMM_noUART_sim_pack;
-- SMMのシミュレーションモデル
-- IO、Interruptのモデル、シリアル無し
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.SMM_noUART_sim_pack.all;
entity smm is
port (
CLK : in std_logic;
RESET : in std_logic;
DIN : in std_logic_vector(0 to 31);
DOUT : out std_logic_vector(0 to 31);
BE : out std_logic_vector(0 to 3);
RNW : out std_logic;
ADDR : out std_logic_vector(0 to 15);
CS : out std_logic;
INTERRUPT : in std_logic;
INTERRUPT_ACK : out std_logic
);
end smm;
architecture sim_model of smm is
constant LCD_ADDR : std_logic_vector := X"0000";
constant TIMER_ADDR : std_logic_vector := X"0010";
constant BUTTON_ADDR : std_logic_vector := X"0020";
signal rd_data : std_logic_vector(0 to 31);
type INTERRUPT_STATE is (IDLE_INTR, WAIT_INTR1, WAIT_INTR2, INTR_ACK, WAIT_INTR_LOW);
signal intr_cs : INTERRUPT_STATE;
signal INTERRUPT_ACK_node : std_logic;
begin
-- 割り込み用ステートマシン
process(clk, reset) begin
if reset='1' then
intr_cs <= IDLE_INTR;
INTERRUPT_ACK_node <= '0';
elsif clk'event and clk='1' then
case intr_cs is
when IDLE_INTR =>
if INTERRUPT='1' then -- 割り込み
intr_cs <= WAIT_INTR1;
end if;
when WAIT_INTR1 =>
intr_cs <= WAIT_INTR2;
when WAIT_INTR2 =>
intr_cs <= INTR_ACK;
INTERRUPT_ACK_node <= '1';
when INTR_ACK =>
intr_cs <= WAIT_INTR_LOW;
INTERRUPT_ACK_node <= '0';
when WAIT_INTR_LOW =>
if INTERRUPT='0' then
intr_cs <= IDLE_INTR;
end if;
end case;
end if;
end process;
INTERRUPT_ACK <= INTERRUPT_ACK_node after 1 ns;
process begin
DOUT <= (others => '0');
BE <= (others => '0');
ADDR <= (others => '0');
CS <= '0';
wait for 100 ns;
-- これから下のwaitまでの間にスティミュラスを書く
SMM_WR_CYCLE(TIMER_ADDR, X"00000010", "1111", clk, rnw, cs, addr, dout, be); -- Timerへ書き込み、16クロックカウント
wait until INTERRUPT_ACK_node'event and INTERRUPT_ACK_node='1'; -- INTERRUPT_ACK_node の立ち上がりまでwait
wait for 1 ns;
SMM_WR_CYCLE(LCD_ADDR, X"12340000", "1111", clk, rnw, cs, addr, dout, be); -- LCDへ書き込み
-- ボタンの状況をrd_dataに読み出し
SMM_RD_CYCLE(BUTTON_ADDR, "1111", rd_data, clk, rnw, cs, addr, din, be);
wait;
end process;
end sim_model;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY lcd_ref_tb IS
END lcd_ref_tb;
ARCHITECTURE behavior OF lcd_ref_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT lcd_ref
PORT(
Clock : IN std_logic;
Reset : IN std_logic;
Button_S : IN std_logic;
LCD_DB : OUT std_logic_vector(7 downto 0);
LCD_RS : OUT std_logic;
LCD_RW : OUT std_logic;
LCD_E : OUT std_logic
);
END COMPONENT;
--Inputs
signal Clock : std_logic := '0';
signal Reset : std_logic := '1';
signal Button_S : std_logic := '0';
--Outputs
signal LCD_DB : std_logic_vector(7 downto 0);
signal LCD_RS : std_logic;
signal LCD_RW : std_logic;
signal LCD_E : std_logic;
-- Clock period definitions
constant Clock_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: lcd_ref PORT MAP (
Clock => Clock,
Reset => Reset,
Button_S => Button_S,
LCD_DB => LCD_DB,
LCD_RS => LCD_RS,
LCD_RW => LCD_RW,
LCD_E => LCD_E
);
-- Clock process definitions
Clock_process :process
begin
Clock <= '0';
wait for Clock_period/2;
Clock <= '1';
wait for Clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
reset <= '0';
Button_S <= '0';
-- hold reset state for 100 ns.
wait for 100 ns;
Button_S <= '1';
reset <= '0';
wait for Clock_period*100;
-- insert stimulus here
wait;
end process;
END;
package SMM_noUART_sim_pack is
procedure SMM_WR_CYCLE(
WR_ADDR : in std_logic_vector; -- 書き込みアドレスをセットする
WR_DATA : in std_logic_vector; -- 書きこむデータをセットする
WR_BE : in std_logic_vector; -- 書きこむBEをセットする
clk : in std_logic;
signal rnw : out std_logic;
signal cs : out std_logic;
signal addr : out std_logic_vector;
signal dout : out std_logic_vector;
signal be : out std_logic_vector
);
procedure SMM_RD_CYCLE(
RD_ADDR : in std_logic_vector; -- 読み出しアドレスをセットする
RD_BE : in std_logic_vector; -- 読み出し時のBEをセットする
signal RD_DATA : out std_logic_vector; -- 読み出しデータ
clk : in std_logic;
signal rnw : out std_logic;
signal cs : out std_logic;
signal addr : out std_logic_vector;
din : in std_logic_vector;
signal be : out std_logic_vector
);
end SMM_noUART_sim_pack;
package body SMM_noUART_sim_pack is
procedure SMM_WR_CYCLE(
WR_ADDR : in std_logic_vector; -- 書き込みアドレスをセットする
WR_DATA : in std_logic_vector; -- 書きこむデータをセットする
WR_BE : in std_logic_vector; -- 書きこむBEをセットする
clk : in std_logic;
signal rnw : out std_logic;
signal cs : out std_logic;
signal addr : out std_logic_vector;
signal dout : out std_logic_vector;
signal be : out std_logic_vector
) is
begin
wait until clk'event and clk='1'; -- clkの立ち上がりまでwait
wait for 1 ns; -- 遅延を挟んで
rnw <= '0'; -- Write
cs <= '1'; -- enable
addr <= WR_ADDR;
dout <= WR_DATA;
be <= WR_BE;
wait until clk'event and clk='1'; -- clkの立ち上がりまでwait
wait for 1 ns; -- 遅延を挟んで
cs <= '0';
end SMM_WR_CYCLE;
procedure SMM_RD_CYCLE(
RD_ADDR : in std_logic_vector; -- 読み出しアドレスをセットする
RD_BE : in std_logic_vector; -- 読み出し時のBEをセットする
signal RD_DATA : out std_logic_vector; -- 読み出しデータ
clk : in std_logic;
signal rnw : out std_logic;
signal cs : out std_logic;
signal addr : out std_logic_vector;
din : in std_logic_vector;
signal be : out std_logic_vector
) is
begin
wait until clk'event and clk='1'; -- clkの立ち上がりまでwait
wait for 1 ns; -- 遅延を挟んで
rnw <= '1'; -- Read
cs <= '1'; -- enable
addr <= RD_ADDR;
be <= RD_BE;
wait until clk'event and clk='1'; -- clkの立ち上がりまでwait
RD_DATA <= din;
wait for 1 ns; -- 遅延を挟んで
cs <= '0';
end SMM_RD_CYCLE;
end SMM_noUART_sim_pack;
ERROR:HDLCompiler:989 - "H:/HDL/FndtnISEWork/Simple_MicroBlaze_xapp1141/SMM_Ref/S3A_LCD_Ref/Work/ise/../src/Simulation/SMM_noUART_sim_pack.vhd" Line 48: Attribute event requires a static signal prefix
ERROR:HDLCompiler:989 - "H:/HDL/FndtnISEWork/Simple_MicroBlaze_xapp1141/SMM_Ref/S3A_LCD_Ref/Work/ise/../src/Simulation/SMM_noUART_sim_pack.vhd" Line 56: Attribute event requires a static signal prefix
ERROR:HDLCompiler:989 - "H:/HDL/FndtnISEWork/Simple_MicroBlaze_xapp1141/SMM_Ref/S3A_LCD_Ref/Work/ise/../src/Simulation/SMM_noUART_sim_pack.vhd" Line 74: Attribute event requires a static signal prefix
ERROR:HDLCompiler:989 - "H:/HDL/FndtnISEWork/Simple_MicroBlaze_xapp1141/SMM_Ref/S3A_LCD_Ref/Work/ise/../src/Simulation/SMM_noUART_sim_pack.vhd" Line 81: Attribute event requires a static signal prefix
ERROR:HDLCompiler:854 - "H:/HDL/FndtnISEWork/Simple_MicroBlaze_xapp1141/SMM_Ref/S3A_LCD_Ref/Work/ise/../src/Simulation/SMM_noUART_sim_pack.vhd" Line 34: Unitignored due to previous errors.
| 日 | 月 | 火 | 水 | 木 | 金 | 土 |
|---|---|---|---|---|---|---|
| - | - | - | 1 | 2 | 3 | 4 |
| 5 | 6 | 7 | 8 | 9 | 10 | 11 |
| 12 | 13 | 14 | 15 | 16 | 17 | 18 |
| 19 | 20 | 21 | 22 | 23 | 24 | 25 |
| 26 | 27 | 28 | 29 | 30 | 31 | - |