declare memtest {
input in[8], adr[8] ;
output f[8] ;
func_in write ;
func_in read ;
}
module memtest {
mem m[256][8] ;
function write m[adr] := in ;
function read f = m[adr] ;
}
/*
Produced by NSL Core(version=20110119), IP ARCH, Inc. Sat Jan 29 05:42:47 2011
Licensed to :LIMITED EVALUATION USER:
*/
module memtest ( p_reset , m_clock , in , adr , f , write , read );
input p_reset, m_clock;
input [7:0] in;
input [7:0] adr;
output [7:0] f;
input write;
input read;
reg [7:0] m [0:255];
assign f = m[adr];
always @(posedge m_clock)
begin
if (write )
m[adr] <= in;
end
endmodule
/*
Produced by NSL Core(version=20110119), IP ARCH, Inc. Sat Jan 29 05:42:48 2011
Licensed to :LIMITED EVALUATION USER:
*/
// BlockRAM
declare memtest {
input in[8], adr_w[8], adr_r[8] ;
output f[8] ;
func_in write(adr_w) ;
func_in read(adr_r) ;
}
module memtest {
mem m[256][8] ;
reg ReadData[8];
func write{
m[adr_w] := in ;
}
func read{
ReadData := m[adr_r] ;
f = ReadData;
}
}
/*
Produced by NSL Core(version=20110119), IP ARCH, Inc. Sat Jan 29 19:12:22 2011
Licensed to :LIMITED EVALUATION USER:
*/
module memtest ( p_reset , m_clock , in , adr_w , adr_r , f , write , read );
input p_reset, m_clock;
input [7:0] in;
input [7:0] adr_w;
input [7:0] adr_r;
output [7:0] f;
input write;
input read;
reg [7:0] m [0:255];
reg [7:0] ReadData;
assign f = ReadData;
always @(posedge m_clock)
begin
if (write )
m[adr_w] <= in;
end
always @(posedge m_clock)
begin
if ((read))
ReadData <= m[adr_r];
end
endmodule
/*
Produced by NSL Core(version=20110119), IP ARCH, Inc. Sat Jan 29 19:12:22 2011
Licensed to :LIMITED EVALUATION USER:
*/
// 分散RAM
declare memtest {
input in[8], adr_w[8], adr_r[8] ;
output f[8] ;
func_in write(adr_w) ;
func_in read(adr_r) ;
}
module memtest {
mem m[256][8] ;
func write{
m[adr_w] := in ;
}
func read{
f = m[adr_r] ;
}
}
/*
Produced by NSL Core(version=20110119), IP ARCH, Inc. Sun Jan 30 04:40:30 2011
Licensed to :LIMITED EVALUATION USER:
*/
module memtest ( p_reset , m_clock , in , adr_w , adr_r , f , write , read );
input p_reset, m_clock;
input [7:0] in;
input [7:0] adr_w;
input [7:0] adr_r;
output [7:0] f;
input write;
input read;
reg [7:0] m [0:255];
assign f = m[adr_r];
always @(posedge m_clock)
begin
if (write )
m[adr_w] <= in;
end
endmodule
/*
Produced by NSL Core(version=20110119), IP ARCH, Inc. Sun Jan 30 04:40:30 2011
Licensed to :LIMITED EVALUATION USER:
*/
NET "clk_vga" TNM_NET = TMN_CLK_VGA;
NET "clk_ddr2" TNM_NET = TMN_CLK_DDR2;
TIMESPEC TS_CLK_DDR2_to_VGA = FROM "TMN_CLK_DDR2" TO "TMN_CLK_VGA" TIG;
TIMESPEC TS_CLK_VGA_to_DDR2 = FROM "TMN_CLK_VGA" TO "TMN_CLK_DDR2" TIG;
PATH TS_CLK_DDR2_to_VGA_path = FROM TIMEGRP "TMN_CLK_DDR2" TO TIMEGRP
"TMN_CLK_VGA";
PATH "TS_CLK_DDR2_to_VGA_path" TIG;
PATH TS_CLK_VGA_to_DDR2_path = FROM TIMEGRP "TMN_CLK_VGA" TO TIMEGRP
"TMN_CLK_DDR2";
PATH "TS_CLK_VGA_to_DDR2_path" TIG;
TIMEGRP TMN_CLK_DDR2 = BEL "reset_ddr2_node1" BEL "reset_ddr2" BEL
"camc_afifo_uf" BEL "vgadc_afifo_of" BEL
"VGAD_Cntrller_inst/cs_rdg_FSM_FFd1" BEL
"VGAD_Cntrller_inst/read_count_1" BEL
"VGAD_Cntrller_inst/read_count_2" BEL
...
TIMEGRP TMN_CLK_VGA = BEL "reset_vga_node1" BEL "reset_vga" BEL
"VGAD_Cntrller_inst/RGBX_0" BEL "VGAD_Cntrller_inst/RGBX_1" BEL
"VGAD_Cntrller_inst/RGBX_3" BEL "VGAD_Cntrller_inst/RGBX_4" BEL
"VGAD_Cntrller_inst/RGBX_5" BEL "VGAD_Cntrller_inst/RGBX_6" BEL
"VGAD_Cntrller_inst/RGBX_9" BEL "VGAD_Cntrller_inst/RGBX_10" BEL
...
//reset_vga の処理
always @(posedge clk_vga, posedge dcmv_out_reset) begin
if (dcmv_out_reset) begin
reset_vga_node1 <= 1'b1;
reset_vga <= 1'b1;
end else begin
reset_vga_node1 <= ~dcm_vga_locked | ~ddr2_initialize_end;
reset_vga <= reset_vga_node1;
end
end
// 表示タイミングの定義 (1280 x 1024)
parameter H_ACTIVE_VIDEO= 1280;
parameter H_FRONT_PORCH = 48;
parameter H_SYNC_PULSE = 112;
parameter H_BACK_PORCH = 248;
parameter H_SUM = H_ACTIVE_VIDEO + H_FRONT_PORCH + H_SYNC_PULSE + H_BACK_PORCH;
parameter V_ACTIVE_VIDEO = 1024;
parameter V_FRONT_PORCH = 1;
parameter V_SYNC_PULSE = 3;
parameter V_BACK_PORCH = 38;
parameter V_SUM = V_ACTIVE_VIDEO + V_FRONT_PORCH + V_SYNC_PULSE + V_BACK_PORCH;
parameter H_DISPLAY_SIZE = H_ACTIVE_VIDEO/8; // 横160桁
parameter V_DISPLAY_SIZE = V_ACTIVE_VIDEO/8; // 縦128行
parameter RED_DOT_POS = 9; // 9ビット目がRED
parameter GREEN_DOT_POS = 8; // 8ビット目がGREEN
parameter BLUE_DOT_POS = 7; // 7ビット目がBLUE
87nsec * 150MHz / 125MHz = 104 nsec
147nsec * 150MHz / 125MHz = 176 nsec
180nsec * 150MHz / 125MHz = 216nsec
1340nsec * 150MHz / 125MHz = 1608nsec
128 * 1/(250MHz) = 512 nsec
((108MB/sec + 48MB/sec) / 500MB/sec) * 100 = 31.2%
// UML2NSL converter Ver. 2010-03-28 Copyright (c) 2009-2010 IP ARCH, Inc. All rights reserved.
// xmi --- version 2.1 ---
#define C5MS_SECOND ( 18'd250000 - 18'd1 )
// #define C5MS_SECOND ( 19'd4 )
#define SEG_VALUE_6 8'b0111_1101
#define SEG_VALUE_5 8'b0110_1101
#define SEG_VALUE_4 8'b0110_0110
#define SEG_VALUE_3 8'b0100_1111
#define SEG_VALUE_2 8'b0101_1011
#define SEG_VALUE_1 8'b0000_0110
declare dice {
// -- dice --
input roll;
output seg_o[8];
output seg_figure[4];
}
declare counter_1to6 {
// -- counter_1to6 --
output seg1to6_o[8];
// -- counter_1to6 --
func_in countup();
}
declare hex_to_7segout {
// -- hex_to_7segout --
input hexdata[3];
output segdata_o[8] ;
// -- hex_to_7segout --
func_in output7seg(hexdata);
}
module dice {
// -- dice --
reg count_5msec[18];
reg count_20msec[3];
counter_1to6 u_counter_1to6;
/* common operations */
{
seg_o = ~u_counter_1to6.seg1to6_o;
seg_figure = 0b1110;
any {
count_5msec == C5MS_SECOND : {
count_20msec++;
count_5msec := 0;
} else : {
count_20msec++;
}
}
any {
count_20msec == 4 : {
if (roll) {
u_counter_1to6.countup();
}
count_20msec := 0;
}
}
}
}
module counter_1to6 {
// -- counter_1to6 --
reg counter1to6[3] = 1;
hex_to_7segout u_hex_to_7segout;
/* common operations */
{
seg1to6_o = u_hex_to_7segout.output7seg(counter1to6).segdata_o ;
}
/* func_in countup() operation */
function countup {
any {
counter1to6 == 3'b110 : {
counter1to6 := 3'b001;
} else : {
counter1to6++;
}
}
}
}
module hex_to_7segout {
wire hex_value[3] ;
wire seg_value[8] ;
func_self seg_decode(hex_value) : seg_value ;
/* common operations */
{
segdata_o = seg_decode(hexdata).seg_value ;
}
/* func_in output7seg(hexdata) operation */
func seg_decode {
any {
hex_value == 0b001 : seg_value = SEG_VALUE_1 ;
hex_value == 0b010 : seg_value = SEG_VALUE_2 ;
hex_value == 0b011 : seg_value = SEG_VALUE_3 ;
hex_value == 0b100 : seg_value = SEG_VALUE_4 ;
hex_value == 0b101 : seg_value = SEG_VALUE_5 ;
hex_value == 0b110 : seg_value = SEG_VALUE_6 ;
}
}
}
NET "m_clock" LOC = T9;
NET "p_reset" LOC = L14;
NET "roll" LOC = M13;
# PlanAhead Generated physical constraints
NET "seg_figure[0]" LOC = D14;
NET "seg_figure[1]" LOC = G14;
NET "seg_figure[2]" LOC = F14;
NET "seg_figure[3]" LOC = E13;
NET "seg_o[0]" LOC = E14;
NET "seg_o[1]" LOC = G13;
NET "seg_o[2]" LOC = N15;
NET "seg_o[3]" LOC = P15;
NET "seg_o[4]" LOC = R16;
NET "seg_o[5]" LOC = F13;
NET "seg_o[6]" LOC = N16;
NET "seg_o[7]" LOC = P16;
#Created by Constraints Editor (xc3s200-ft256-4) - 2011/01/16
NET "m_clock" TNM_NET = m_clock;
TIMESPEC TS_m_clock = PERIOD "m_clock" 20 ns HIGH 50%;
module hex_to_7segout {
wire hex_value[3] ;
wire seg_value[8] ;
func_self seg_decode(hex_value) : seg_value ;
/* common operations */
{
}
/* func_in output7seg(hexdata) operation */
func output7seg {
segdata_o = seg_decode(hexdata).seg_value ;
}
func seg_decode {
any {
hex_value == 0b001 : seg_value = SEG_VALUE_1 ;
hex_value == 0b010 : seg_value = SEG_VALUE_2 ;
hex_value == 0b011 : seg_value = SEG_VALUE_3 ;
hex_value == 0b100 : seg_value = SEG_VALUE_4 ;
hex_value == 0b101 : seg_value = SEG_VALUE_5 ;
hex_value == 0b110 : seg_value = SEG_VALUE_6 ;
}
}
}
<NotepadPlus>
<UserLang name="NSL" ext="nsl nsh">
<Settings>
<Global caseIgnored="no" />
<TreatAsSymbol comment="no" commentLine="no" />
<Prefix words1="yes" words2="no" words3="no" words4="no" />
</Settings>
<KeywordLists>
<Keywords name="Delimiters">000000</Keywords>
<Keywords name="Folder+">declare module any</Keywords>
<Keywords name="Folder-">}</Keywords>
<Keywords name="Operators">- ! & : [ ] ^ | ~ + < = ></Keywords>
<Keywords name="Comment">1/* 2*/ 0//</Keywords>
<Keywords name="Words1">alt any declare for generate goto interface label label_name m_clock module p_reset proc_name proc seq state state_name while finish if else</Keywords>
<Keywords name="Words2">input output inout func_in func_out func_self reg variable integer wire function func mem </Keywords>
<Keywords name="Words3">_readmemb _readmemh _finish _display _monitor #ifdef #define #else #endif #ifndef #undef #include</Keywords>
<Keywords name="Words4"></Keywords>
</KeywordLists>
<Styles>
<WordsStyle name="DEFAULT" styleID="11" fgColor="000000" bgColor="FFFFFF" fontName="" fontStyle="0" />
<WordsStyle name="FOLDEROPEN" styleID="12" fgColor="000000" bgColor="FFFFFF" fontName="" fontStyle="0" />
<WordsStyle name="FOLDERCLOSE" styleID="13" fgColor="000000" bgColor="FFFFFF" fontName="" fontStyle="0" />
<WordsStyle name="KEYWORD1" styleID="5" fgColor="0000FF" bgColor="FFFFFF" fontName="" fontStyle="0" />
<WordsStyle name="KEYWORD2" styleID="6" fgColor="C600C6" bgColor="FFFFFF" fontName="" fontStyle="0" />
<WordsStyle name="KEYWORD3" styleID="7" fgColor="800000" bgColor="FFFFFF" fontName="" fontStyle="0" />
<WordsStyle name="KEYWORD4" styleID="8" fgColor="000000" bgColor="FFFFFF" fontName="" fontStyle="0" />
<WordsStyle name="COMMENT" styleID="1" fgColor="008000" bgColor="FFFFFF" fontName="" fontStyle="0" />
<WordsStyle name="COMMENT LINE" styleID="2" fgColor="008000" bgColor="FFFFFF" fontName="" fontStyle="0" />
<WordsStyle name="NUMBER" styleID="4" fgColor="FF8040" bgColor="FFFFFF" fontName="" fontStyle="0" />
<WordsStyle name="OPERATOR" styleID="10" fgColor="8000FF" bgColor="FFFFFF" fontName="" fontStyle="0" />
<WordsStyle name="DELIMINER1" styleID="14" fgColor="000000" bgColor="FFFFFF" fontName="" fontStyle="0" />
<WordsStyle name="DELIMINER2" styleID="15" fgColor="000000" bgColor="FFFFFF" fontName="" fontStyle="0" />
<WordsStyle name="DELIMINER3" styleID="16" fgColor="000000" bgColor="FFFFFF" fontName="" fontStyle="0" />
</Styles>
</UserLang>
</NotepadPlus>
-- Write Data Path
wr_fifo_din <= wr_address & wr_data;
wr_fifo_rd_en_node <= wr_fifo_rd_en;
wr_fifo_inst : write_fifo port map(
clk => clk,
srst => reset,
din => wr_fifo_din,
wr_en => wr_enable,
rd_en => wr_fifo_rd_en,
dout => wr_fifo_dout,
full => open,
almost_full => wr_fifo_full,
empty => wr_fifo_empty,
almost_empty => wr_fifo_almost_empty,
data_count => wr_fifo_count
);
-- Read Data Path
rd_fifo_rd_en_node <= rd_fifo_rd_en;
rd_fifo_inst : read_fifo port map(
clk => clk,
srst => reset,
din => rd_address,
wr_en => rd_enable,
rd_en => rd_fifo_rd_en,
dout => rd_fifo_dout,
full => open,
almost_full => rd_fifo_full,
empty => rd_fifo_empty,
almost_empty => rd_fifo_almost_empty,
data_count => rd_fifo_count
);
-- SRAMのRead, Write 用ステートマシン(Read優先）
process(clk) begin
if clk'event and clk='1' then
if reset='1' then
cs_SRAM_RW <= SRAM_RW_STATE'(idle);
wr_fifo_rd_en <= '0';
rd_fifo_rd_en <= '0';
else
case cs_SRAM_RW is
when SRAM_RW_STATE'(idle) =>
if rd_fifo_empty='0' then
cs_SRAM_RW <= READ_STATE;
rd_fifo_rd_en <= '1';
elsif wr_fifo_empty='0' then
cs_SRAM_RW <= WRITE_STATE1;
end if;
when READ_STATE =>
if rd_fifo_almost_empty='0' then -- まだRead用FIFOに残っている
cs_SRAM_RW <= READ_STATE;
else
cs_SRAM_RW <= SRAM_RW_STATE'(idle);
rd_fifo_rd_en <= '0';
end if;
when WRITE_STATE1 =>
cs_SRAM_RW <= WRITE_STATE2;
wr_fifo_rd_en <= '1';
when WRITE_STATE2 =>
wr_fifo_rd_en <= '0';
if rd_fifo_empty='0' then -- Read優先, ReadとWriteの間は1クロック間を空ける。
cs_SRAM_RW <= SRAM_RW_STATE'(idle);
elsif wr_fifo_almost_empty='0' then -- まだWrite用FIFOに残っている
cs_SRAM_RW <= WRITE_STATE1;
else
cs_SRAM_RW <= SRAM_RW_STATE'(idle);
end if;
end case;
end if;
end if;
end process;
-- Write Data Path
wr_fifo_din <= wr_address & wr_data;
wr_fifo_rd_en_node <= wr_fifo_rd_en;
wr_fifo_inst : write_fifo port map(
clk => clk,
srst => reset,
din => wr_fifo_din,
wr_en => wr_enable,
rd_en => wr_fifo_rd_en_node,
dout => wr_fifo_dout,
full => open,
almost_full => wr_fifo_full,
empty => wr_fifo_empty,
almost_empty => wr_fifo_almost_empty,
data_count => wr_fifo_count
);
-- Read Data Path
rd_fifo_rd_en_node <= rd_fifo_rd_en;
rd_fifo_inst : read_fifo port map(
clk => clk,
srst => reset,
din => rd_address,
wr_en => rd_enable,
rd_en => rd_fifo_rd_en_node,
dout => rd_fifo_dout,
full => open,
almost_full => rd_fifo_full,
empty => rd_fifo_empty,
almost_empty => rd_fifo_almost_empty,
data_count => rd_fifo_count
);
// UML2NSL converter Ver. 2010-03-28 Copyright (c) 2009-2010 IP ARCH, Inc. All rights reserved.
// xmi --- version 2.1 ---
declare dice {
// -- dice --
input roll;
output seg_o[8];
output seg_figure[4];
}
declare counter_1to6 {
// -- counter_1to6 --
output seg0to6_o[8];
// -- counter_1to6 --
func_in countup();
}
declare hex_to_7segout {
// -- hex_to_7segout --
input hexdata[3];
// -- hex_to_7segout --
func_in output7seg(hexdata);
}
module dice {
// -- dice --
reg count_5msec[18];
reg count_20msec[3];
counter_1to6 u_counter_1to6;
/* common operations */
{
}
}
module counter_1to6 {
// -- counter_1to6 --
reg counter_1to6[3];
hex_to_7segout u_hex_to_7segout;
/* common operations */
{
}
/* func_in countup() operation */
function countup {
}
}
module hex_to_7segout {
// -- hex_to_7segout --
wire seg_value[8];
/* common operations */
{
}
/* func_in output7seg(hexdata) operation */
function output7seg {
}
}
library work;
use work.disp_timing_pack.all;
declare timer7seg {
// -- timer_30MHz_to_1sec --
input reset ;
output seg_o[8] ;
output seg_figure[4] ; // For support DYNAMIC drive.
}
.............
module timer7seg {
reg cnt_1sec[32] = 0 ;
reg cnt_100Hz[19] = 0 ;
reg seg_figure_buffer[4] = 4'b1110 ;
reg seg1_o[8] = 0xc0;
reg seg2_o[8] = 0xc0;
counter_0to9 u_counter_0to9;
/* common operations */
{
seg1_o := ~u_counter_0to9.seg0to9_o ;
seg2_o := ~u_counter_0to9.seg0to5_o ;
any {
seg_figure_buffer == 0b1101 : seg_o = seg2_o;
seg_figure_buffer == 0b1110 : seg_o = seg1_o;
}
any {
cnt_1sec == ONE_SECOND : {
if(reset) {
u_counter_0to9.reset() ;
} else {
u_counter_0to9.countup() ;
}
cnt_1sec := 0 ;
}
else : {
cnt_1sec++ ;
}
}
any {
cnt_100Hz == CNT_DYNAMIC : {
cnt_100Hz := 0 ;
any {
seg_figure_buffer == 0b1110 : seg_figure_buffer := 0b1101 ;
seg_figure_buffer == 0b1101 : seg_figure_buffer := 0b1110 ;
}
}
else : {
cnt_100Hz++ ;
}
}
seg_figure = seg_figure_buffer ;
}
}
NET "m_clock" LOC = T9;
NET "p_reset" LOC = L14;
NET "reset" LOC = M13;
# PlanAhead Generated physical constraints
NET "seg_figure[0]" LOC = D14;
NET "seg_figure[1]" LOC = G14;
NET "seg_figure[2]" LOC = F14;
NET "seg_figure[3]" LOC = E13;
NET "seg_o[0]" LOC = E14;
NET "seg_o[1]" LOC = G13;
NET "seg_o[2]" LOC = N15;
NET "seg_o[3]" LOC = P15;
NET "seg_o[4]" LOC = R16;
NET "seg_o[5]" LOC = F13;
NET "seg_o[6]" LOC = N16;
NET "seg_o[7]" LOC = P16;
#Created by Constraints Editor (xc3s200-ft256-4) - 2011/01/16
NET "m_clock" TNM_NET = m_clock;
TIMESPEC TS_m_clock = PERIOD "m_clock" 20 ns HIGH 50%;
v_net_1 <= '1' when (v_net_2) else '0' ;
ERROR:HDLParsers:802 - "H:/Documents and Settings/Masaaki/My Documents/NSL/Xilinx_ISE/VHDL/timer7seg.vhdl" Line 71. v_net_2 is not a boolean expression.
v_net_1 <= '1' when (v_net_2='1') else '0' ;
v_net_1 <= '1' when (v_net_2) else '0' ;
@E:CD648 : timer7seg.vhdl(71) | Expression does not match type boolean
declare timer7seg {
// -- timer_30MHz_to_1sec --
input reset ;
output seg1_o[8] ;
output seg2_o[8] ;
output seg_figure[2] ; // For support DYNAMIC drive.
}
module tb;
parameter tCYC=2;
parameter tPD=(tCYC/10);
reg p_reset;
reg m_clock;
reg reset;
wire [7:0] seg1_o;
wire [7:0] seg2_o;
wire [1:0] seg_figure;
timer7seg timer7seg_instance(
.p_reset(p_reset),
.m_clock(m_clock),
.reset(reset),
.seg1_o(seg1_o),
.seg2_o(seg2_o),
.seg_figure(seg_figure)
);
initial forever #(tCYC/2) m_clock = ~m_clock;
initial begin
$dumpfile("timer7seg.vcd");
$dumpvars(0,timer7seg_instance);
end
initial begin
#(tPD)
p_reset = 1;
m_clock = 0;
reset = 0;
#(tCYC)
p_reset = 0;
reset = 1;
#200000 $stop;
end
endmodule
vlogcomp -work work -incremental timer7seg.v
fuse work.tb -o tb.exe
tb.exe -gui
always @(posedge m_clock or posedge p_reset)
begin
if (p_reset)
counter <= 4'b0000;
else
//synthesis translate_off
if ((reset&countup&(~_net_5))|((reset|(countup&(~_net_5)))&countup&_net_5)) counter <= 4'bx;
else
//synthesis translate_on
if (reset)
counter <= 4'b0000;
else if (countup&(~_net_5))
counter <= (counter)+(4'b0001);
else if (countup&_net_5)
counter <= 4'b0000;
end
always @(posedge m_clock)
begin
//synthesis translate_off
if ((reset&countup&(~_net_6))|((reset|(countup&(~_net_6)))&countup&_net_6)) counter <= 3'bx;
else
//synthesis translate_on
if (reset)
counter <= 3'b000;
else if (countup&(~_net_6))
counter <= (counter)+(3'b001);
else if (countup&_net_6)
counter <= 3'b000;
end
// #define ONE_SECOND ( 32'd50000000 - 32'd1 )
// #define CNT_DYNAMIC 19'b100_1001_0011_1110_0000
#define ONE_SECOND ( 32'd4 )
#define CNT_DYNAMIC 19'b000_0000_0000_0000_1000
module counter_0to5 {
// -- counter_0to5 --
reg counter[3];
hex_to_7segout u_hex_to_7segout;
module counter_0to5 {
// -- counter_0to5 --
reg counter[3] = 0;
hex_to_7segout u_hex_to_7segout;
// DCM module (dcm_CAM_DDR2_clk.v)
// 50MHzを入力して、DDR2_SDRAM用のclkを生成する。
// 125MHzクロック出力に変更。CMOSカメラ用の25MHzも生成する
// 2011/01/11 : VGA Display Controller のクロックとCAMのクロックを独自のDCMで生成する
`default_nettype none
`timescale 1ns / 1ps
(* KEEP_HIERARCHY = "TRUE" *)module dcm_CAM_DDR2_clk (sysclk, reset, clk_ddr2, clk_cam, clk_vga, dcm_ddr2_locked, dcm_cam_locked, dcm_vga_locked);
`include "ddr2_cont_parameters.vh"
input wire sysclk;
input wire reset;
output wire clk_ddr2;
output wire clk_cam;
output wire clk_vga;
output wire dcm_ddr2_locked;
output wire dcm_cam_locked;
output wire dcm_vga_locked;
wire clk_bufg, clk_node, dcm1_locked;
wire clk_ddr2_node, clk_ddr2_bufg;
wire clk_cam_node, clk_cam_bufg;
wire clkc_bufg, clkc_node, dcmc_locked;
wire clkv_bufg, clkv_node, dcmv_locked;
wire clk_vgadc_node, clk_vgadc_bufg;
wire reset_vc_dcm;
// DDR2 SDRAM用クロック
DCM dcm_DDR2_clk_dcm (
.CLKIN(sysclk),
.CLKFB(clk_bufg),
.DSSEN(1'b0),
.PSINCDEC(1'b0),
.PSEN(1'b0),
.PSCLK(1'b0),
.RST(reset), // 前段のDCMがロックするまでリセット
.CLK0(clk_node),
.CLK90(),
.CLK180(),
.CLK270(),
.CLK2X(),
.CLK2X180(),
.CLKDV(),
.CLKFX(clk_ddr2_node),
.CLKFX180(),
.LOCKED(dcm1_locked),
.PSDONE(),
.STATUS()
);
defparam dcm_DDR2_clk_dcm.CLKIN_PERIOD = 20.0;
defparam dcm_DDR2_clk_dcm.DLL_FREQUENCY_MODE = "LOW";
defparam dcm_DDR2_clk_dcm.DUTY_CYCLE_CORRECTION = "TRUE";
defparam dcm_DDR2_clk_dcm.CLKDV_DIVIDE = 2.0;
defparam dcm_DDR2_clk_dcm.PHASE_SHIFT = 0;
defparam dcm_DDR2_clk_dcm.CLKOUT_PHASE_SHIFT = "NONE";
defparam dcm_DDR2_clk_dcm.STARTUP_WAIT = "FALSE";
defparam dcm_DDR2_clk_dcm.CLKFX_DIVIDE = 2;
defparam dcm_DDR2_clk_dcm.CLKFX_MULTIPLY = 5;
// defparam dcm_DDR2_clk_dcm.FACTORY_JF = 16'hFFFF;
BUFG CLK_BUFG_INST (
.I(clk_node),
.O(clk_bufg)
);
BUFG CLK200_BUFG_INST (
.I(clk_ddr2_node),
.O(clk_ddr2_bufg)
);
assign reset_vc_dcm = ~dcm1_locked;
// CMOSカメラ用クロック(24MHz)
DCM dcm_cam (
.CLKIN(clk_bufg),
.CLKFB(clkc_bufg),
.DSSEN(1'b0),
.PSINCDEC(1'b0),
.PSEN(1'b0),
.PSCLK(1'b0),
.RST(reset_vc_dcm), // 前段のDCMがロックするまでリセット
.CLK0(clkc_node),
.CLK90(),
.CLK180(),
.CLK270(),
.CLK2X(),
.CLK2X180(),
.CLKDV(),
.CLKFX(clk_cam_node),
.CLKFX180(),
.LOCKED(dcmc_locked),
.PSDONE(),
.STATUS()
);
defparam dcm_cam.CLKIN_PERIOD = 20.0;
defparam dcm_cam.DLL_FREQUENCY_MODE = "LOW";
defparam dcm_cam.DUTY_CYCLE_CORRECTION = "TRUE";
defparam dcm_cam.CLKDV_DIVIDE = 2.0;
defparam dcm_cam.PHASE_SHIFT = 0;
defparam dcm_cam.CLKOUT_PHASE_SHIFT = "NONE";
defparam dcm_cam.STARTUP_WAIT = "FALSE";
defparam dcm_cam.CLKFX_DIVIDE = 25;
defparam dcm_cam.CLKFX_MULTIPLY = 12;
// defparam dcm_cam.FACTORY_JF = 16'hFFFF;
BUFG CLKC_BUFG_INST (
.I(clkc_node),
.O(clkc_bufg)
);
BUFG CLK_CAM_BUFG_INST (
.I(clk_cam_node),
.O(clk_cam_bufg)
);
// VGA Display Controller 用クロック(25MHz)
DCM dcm_vgadc (
.CLKIN(clk_bufg),
.CLKFB(clkv_bufg),
.DSSEN(1'b0),
.PSINCDEC(1'b0),
.PSEN(1'b0),
.PSCLK(1'b0),
.RST(reset_vc_dcm), // 前段のDCMがロックするまでリセット
.CLK0(clkv_node),
.CLK90(),
.CLK180(),
.CLK270(),
.CLK2X(),
.CLK2X180(),
.CLKDV(),
.CLKFX(clk_vgadc_node),
.CLKFX180(),
.LOCKED(dcmv_locked),
.PSDONE(),
.STATUS()
);
defparam dcm_vgadc.CLKIN_PERIOD = 20.0;
defparam dcm_vgadc.DLL_FREQUENCY_MODE = "LOW";
defparam dcm_vgadc.DUTY_CYCLE_CORRECTION = "TRUE";
defparam dcm_vgadc.CLKDV_DIVIDE = 2.0;
defparam dcm_vgadc.PHASE_SHIFT = 0;
defparam dcm_vgadc.CLKOUT_PHASE_SHIFT = "NONE";
defparam dcm_vgadc.STARTUP_WAIT = "FALSE";
defparam dcm_vgadc.CLKFX_DIVIDE = 4;
defparam dcm_vgadc.CLKFX_MULTIPLY = 2;
// defparam dcm_vgadc.FACTORY_JF = 16'hFFFF;
BUFG CLKV_BUFG_INST (
.I(clkv_node),
.O(clkv_bufg)
);
BUFG CLK_VGADC_BUFG_INST (
.I(clk_vgadc_node),
.O(clk_vgadc_bufg)
);
assign clk_ddr2 = clk_ddr2_bufg;
assign dcm_ddr2_locked = dcm1_locked;
assign dcm_cam_locked = dcmc_locked;
assign dcm_vga_locked = dcmv_locked;
assign clk_cam = clk_cam_bufg;
assign clk_vga = clk_vgadc_bufg;
endmodule
6B0A
1267
40F0
FF00
constant ID_ADDRESS_PATTERN_SDA : std_logic_vector := "010000100";
constant ID_ADDRESS_PATTERN_SDA : std_logic_vector := "011000000";
// UML2NSL converter Ver. 2010-03-28 Copyright (c) 2009-2010 IP ARCH, Inc. All rights reserved.
// xmi --- version 2.1 ---
declare timer7seg {
// -- timer7seg --
output sig1_o[8];
output sig2_o[8];
output sig_figure[2];
}
declare counter_0to9 {
// -- counter_0to9 --
output seg0to5_o;
output seg0to9_o[8];
// -- counter_0to9 --
func_in countup();
func_in reset();
}
declare counter_0to5 {
// -- counter_0to5 --
output seg0to5_o[8];
// -- counter_0to5 --
func_in countup();
func_in reset();
}
declare hex_to_7segout {
// -- hex_to_7segout --
input hexdata[4];
// -- hex_to_7segout --
func_in output7seg(hexdata);
}
module timer7seg {
// -- timer7seg --
reg cnt_1sec[32];
reg cnt_100Hz[19];
reg sig_figure_buffer[2];
counter_0to9 u_counter_0to9;
/* common operations */
{
}
}
module counter_0to9 {
// -- counter_0to9 --
reg counter[4];
counter_0to5 counter_0to5;
hex_to_7segout u_hex_to_7segout;
/* common operations */
{
}
/* func_in countup() operation */
function countup {
}
/* func_in reset() operation */
function reset {
}
}
module counter_0to5 {
// -- counter_0to5 --
reg counter[3];
hex_to_7segout u_hex_to_7seg;
/* common operations */
{
}
/* func_in countup() operation */
function countup {
}
/* func_in reset() operation */
function reset {
}
}
module hex_to_7segout {
// -- hex_to_7segout --
wire seg_value[8];
/* common operations */
{
}
/* func_in output7seg(hexdata) operation */
function output7seg {
}
}
func_in : public
func_out : protected
proc : private
func_self : package
input, output : public
wire, reg, mem : private
integer, variable : private
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