Design Rule Check Report
------------------------
Report File : H:\Documents and Settings\All Users\Documents\DesignSpark PCB\Examples\Design_Tutorial (PCB - Design Rule Check Report).txt
Report Written : Sunday, February 27, 2011
Design Path : H:\Documents and Settings\All Users\Documents\DesignSpark PCB\Examples\Design_Tutorial.pcb
Design Title :
Created : 2011/02/22 20:21:25
Last Saved : 2011/02/27 11:37:25
Editing Time : 6003 min
Units : mm (precision 1)
Results
-------
Annular ring too small at (205.7,276.9)
Size is 0.0 should be 0.1.
Pad to Board Error (P-B) between (205.7 278.5) and (205.7 279.4) on Layer "[All]".
Error between Pad and Board, Gap is 0.9 needs to be 1.3.
Annular ring too small at (205.7,233.7)
Size is 0.0 should be 0.1.
Pad to Board Error (P-B) between (205.7 232.1) and (205.7 231.1) on Layer "[All]".
Error between Pad and Board, Gap is 0.9 needs to be 1.3.
Annular ring too small at (276.9,276.9)
Size is 0.0 should be 0.1.
Pad to Board Error (P-B) between (278.5 276.9) and (279.4 276.9) on Layer "[All]".
Error between Pad and Board, Gap is 0.9 needs to be 1.3.
Annular ring too small at (276.9,233.7)
Size is 0.0 should be 0.1.
Pad to Board Error (P-B) between (276.9 232.1) and (276.9 231.1) on Layer "[All]".
Error between Pad and Board, Gap is 0.9 needs to be 1.3.
Pad to Silkscreen Error (P-S) at (270.8 259.8) on Layer "Top Silkscreen".
Silkscreen text 'R6' overlaps pad.
Via to Silkscreen Error (V-S) at (262.9 241.3) on Layer "Top Silkscreen".
Silkscreen text 'R7' overlaps via.
Number of errors found : 10
Settings
--------
Spacings
Tracks Yes
Pads and Vias Yes
Shapes Yes
Text Yes
Board Yes
Drills Yes
Components Yes
Manufacturing
Drill Breakout Yes
Drill Backoff Yes
Silkscreen Overlap Yes
Copper Text In Board Yes
Min Track Width Yes
Min Annular Ring Yes
Min Paste Size Yes
Vias In Pads Yes
Unplated Vias Yes
Unplated Pads With Inner Tracks Yes
Nets
Net Completion Yes
Dangling Tracks Yes
Net Track Length Differences No
End Of Report.
any {
u_disp_timing.h_addr[2:0] == 3'd2 : {
char_data_node := char_data[7:1];
temp_color := display_dout[RED_DOT_POS : BLUE_DOT_POS];
if (char_data[0] && display_on_d2) {
red_node := display_dout[RED_DOT_POS];
green_node := display_dout[GREEN_DOT_POS];
blue_node := display_dout[BLUE_DOT_POS];
} else {
red_node := 1'b0;
green_node := 1'b0;
blue_node := 1'b0;
}
}
else : {
char_data_node := { 1'b0, char_data_node[6:1] };
// if (char_data_node && display_on_d2) {
if (char_data_node[0] && display_on_d2) {
red_node := temp_color[2];
green_node := temp_color[1];
blue_node := temp_color[0];
} else {
red_node := 1'b0;
green_node := 1'b0;
blue_node := 1'b0;
}
}
}
// UML2NSL converter Ver. 2010-03-28 Copyright (c) 2009-2010 IP ARCH, Inc. All rights reserved.
// xmi --- version 2.1 ---
#define C200MS_SECOND ( 23'd230000 - 23'd1)
#define H_ACTIVE_VIDEO 640
#define H_FRONT_PORCH 16
#define H_SYNC_PULSE 96
#define H_BACK_PORCH 48
#define H_SUM H_ACTIVE_VIDEO+H_FRONT_PORCH+H_SYNC_PULSE+H_BACK_PORCH
#define V_ACTIVE_VIDEO 480
#define V_FRONT_PORCH 11
#define V_SYNC_PULSE 2
#define V_BACK_PORCH 31
#define V_SUM V_ACTIVE_VIDEO+V_FRONT_PORCH+V_SYNC_PULSE+V_BACK_PORCH
#define H_DISPLAY_SIZE H_ACTIVE_VIDEO/8 // 横80桁
#define V_DISPLAY_SIZE V_ACTIVE_VIDEO/8 // 縦60行
#define RED_DOT_POS 9 // 9ビット目がRED
#define GREEN_DOT_POS 8 // 8ビット目がGREEN
#define BLUE_DOT_POS 7 // 7ビット目がBLUE
declare CharDispCtrlerTest interface {
input m_clock;
input p_reset;
// -- CharDispCtrlerTest --
output VGA_RED[4];
output VGA_GREEN[4];
output VGA_BLUE[4];
output VGA_HSYNC;
output VGA_VSYNC;
}
declare CharDispCtrler {
// -- CharDispCtrler --
output VGA_RED[4];
output VGA_GREEN[4];
output VGA_BLUE[4];
output VGA_HSYNC;
output VGA_VSYNC;
input char_addr[13];
input char_din[10];
// -- CharDispCtrler --
func_in char_write(char_addr,char_din);
}
declare Top_wDCM {
// -- Top_wDCM --
output VGA_RED[4];
output VGA_GREEN[4];
output VGA_BLUE[4];
output VGA_HSYNC;
output VGA_VSYNC;
}
declare frame_buffer {
// -- frame_buffer --
input char_addr[13];
input char_din[10];
input char_we;
input display_addr[13];
output display_dout[10];
// -- frame_buffer --
func_in fb_write(char_addr, char_din);
func_in fb_read(display_addr) ;
}
declare disp_timing {
// -- disp_timing --
output page_start;
output display_on;
output h_addr[10];
output v_addr[10];
output h_sync;
output h_sync_pulse;
output v_sync;
}
declare dcm_inst interface {
input clkin;
input reset;
output clkout;
output clkfx;
output clkdv;
output locked;
}
declare char_gen_rom interface {
input clk;
input reset;
input char_addr[7];
input row_addr[3];
output dout[8];
}
module CharDispCtrlerTest {
// -- CharDispCtrlerTest --
reg char_addr[13] = 0;
reg count_200ms[23] = 0;
reg char_code[7] = 7'h21;
reg color_data[3] = 1;
wire char_data[10];
func_self char_addr_inc();
func_self char_code_inc();
func_self color_data_inc();
CharDispCtrler u_charDispCtrler;
/* common operations */
{
VGA_RED = u_charDispCtrler.VGA_RED;
VGA_GREEN = u_charDispCtrler.VGA_GREEN;
VGA_BLUE = u_charDispCtrler.VGA_BLUE;
VGA_HSYNC = u_charDispCtrler.VGA_HSYNC;
VGA_VSYNC = u_charDispCtrler.VGA_VSYNC;
char_data = { color_data, char_code };
any {
count_200ms == C200MS_SECOND : {
count_200ms := 0;
u_charDispCtrler.char_write(char_addr, char_data); // キャラクタを描画
char_addr_inc(); // キャラクタのアドレスをインクリメント
char_code_inc(); // キャラクタをインクリメント
color_data_inc(); // カラーをインクリメント
} else : {
count_200ms++;
}
}
}
function char_addr_inc {
if (char_addr == 13'd4799) { // 終了
char_addr := 0;
} else {
char_addr++;
}
}
function char_code_inc {
if (char_code == 7'h7E) {
char_code := 7'h21;
} else {
char_code++;
}
}
function color_data_inc {
if (color_data == 3'h7) {
color_data := 3'h1;
} else {
color_data ++;
}
}
}
module CharDispCtrler {
// -- CharDispCtrler --
wire h_sync_pulse;
reg char_data_node[7] = 0;
reg temp_pointer[13] = 0;
reg page_start = 0;
reg display_addr[13] = 0;
wire char_data[8];
wire display_out[10];
reg display_on_d1 = 0, display_on_d2 = 0;
reg h_sync_1 = 0, v_sync_1 = 0;
reg h_sync_2 = 0, v_sync_2 = 0;
reg h_sync_3 = 0, v_sync_3 = 0;
wire display_dout[10];
reg temp_color[3] = 0;
reg red_node = 0, green_node = 0, blue_node = 0;
frame_buffer u_frame_buffer;
char_gen_rom u_char_gen_rom;
disp_timing u_disp_timing;
/* common operations */
{
u_char_gen_rom.clk = m_clock;
u_char_gen_rom.reset = p_reset;
u_char_gen_rom.char_addr = u_frame_buffer.display_dout[6:0];
u_char_gen_rom.row_addr = u_disp_timing.v_addr[2:0];
char_data = u_char_gen_rom.dout;
display_dout = u_frame_buffer.fb_read(display_addr).display_dout;
any {
u_disp_timing.display_on : {
if (u_disp_timing.h_addr[2:0] == 3'd7) {
display_addr++;
}
}
u_disp_timing.v_sync : {
display_addr := 0;
temp_pointer := 0;
}
u_disp_timing.h_sync_pulse : {
if (u_disp_timing.v_addr[2:0] == 3'd7)
temp_pointer := display_addr;
else
display_addr := temp_pointer;
}
}
any {
u_disp_timing.h_addr[2:0] == 3'd2 : {
char_data_node := char_data[7:1];
temp_color := display_dout[RED_DOT_POS : BLUE_DOT_POS];
if (char_data[0] && display_on_d2) {
red_node := display_dout[RED_DOT_POS];
green_node := display_dout[GREEN_DOT_POS];
blue_node := display_dout[BLUE_DOT_POS];
} else {
red_node := 1'b0;
green_node := 1'b0;
blue_node := 1'b0;
}
}
else : {
char_data_node := { 1'b0, char_data_node[6:1] };
// if (char_data_node && display_on_d2) {
if (char_data_node[0] && display_on_d2) {
red_node := temp_color[2];
green_node := temp_color[1];
blue_node := temp_color[0];
} else {
red_node := 1'b0;
green_node := 1'b0;
blue_node := 1'b0;
}
}
}
VGA_RED = {4{red_node}};
VGA_GREEN = {4{green_node}};
VGA_BLUE = {4{blue_node}};
display_on_d1 := u_disp_timing.display_on;
display_on_d2 := display_on_d1;
h_sync_1 := u_disp_timing.h_sync;
v_sync_1 := u_disp_timing.v_sync;
h_sync_2 := h_sync_1;
v_sync_2 := v_sync_1;
h_sync_3 := h_sync_2;
v_sync_3 := v_sync_2;
VGA_HSYNC = ~h_sync_3;
VGA_VSYNC = ~v_sync_3;
}
/* func_in char_write(char_addr,char_dout) operation */
function char_write {
u_frame_buffer.fb_write(char_addr, char_din);
}
}
module Top_wDCM {
dcm_inst u_dcm_inst;
CharDispCtrlerTest u_charDispCtrlerTest;
wire clkdv;
wire locked;
u_dcm_inst.clkin = m_clock;
u_dcm_inst.reset = p_reset;
clkdv = u_dcm_inst.clkdv;
locked = u_dcm_inst.locked;
u_charDispCtrlerTest.m_clock = clkdv;
u_charDispCtrlerTest.p_reset = ~locked;
VGA_RED = u_charDispCtrlerTest.VGA_RED;
VGA_GREEN = u_charDispCtrlerTest.VGA_GREEN;
VGA_BLUE = u_charDispCtrlerTest.VGA_BLUE;
VGA_HSYNC = u_charDispCtrlerTest.VGA_HSYNC;
VGA_VSYNC = u_charDispCtrlerTest.VGA_VSYNC;
}
module frame_buffer {
mem m[8192][10] ;
reg ReadData[10];
/* common operations */
{
display_dout = ReadData;
}
/* func_in fb_read(display_addr) operation */
function fb_read {
ReadData := m[display_addr] ;
}
/* function fb_write(char_addr,char_din) operation */
function fb_write {
m[char_addr] := char_din ;
}
}
module disp_timing {
reg h_point[11] = 0, h_addr_node[11] = 0; // 1024までOK
reg v_point[11] = 0, v_addr_node[11] = 0; // 1024までOK
reg page_start_node = 0;
reg display_on_node = 0;
reg h_sync_node = 0;
reg v_sync_node = 0;
reg h_sync_pulse_node = 0;
any {
h_point == H_SUM-1 :
h_point := 0;
else :
h_point++;
}
h_addr_node := h_point;
h_addr = h_addr_node[9:0];
any {
v_point == V_SUM-1 :
v_point := 0;
else : {
if (h_point == H_SUM-1)
v_point++;
}
}
v_addr_node := v_point;
v_addr = v_addr_node[9:0];
any {
h_point<H_ACTIVE_VIDEO && v_point<V_ACTIVE_VIDEO :
display_on_node := 1'b1;
else :
display_on_node := 1'b0;
}
display_on = display_on_node;
any {
h_point==0 :
page_start_node := 1'b1;
else :
page_start_node := 1'b0;
}
page_start = page_start_node;
any {
(h_point>=(H_ACTIVE_VIDEO + H_FRONT_PORCH)) && (h_point < (H_SUM-H_BACK_PORCH)) :
h_sync_node := 1'b1;
else :
h_sync_node := 1'b0;
}
h_sync = h_sync_node;
any {
h_point==(H_ACTIVE_VIDEO+H_FRONT_PORCH) :
h_sync_pulse_node := 1'b1;
else :
h_sync_pulse_node := 1'b0;
}
h_sync_pulse = h_sync_pulse_node;
any {
(v_point>=(V_ACTIVE_VIDEO + V_FRONT_PORCH)) && (v_point<(V_SUM-V_BACK_PORCH)) :
v_sync_node := 1'b1;
else :
v_sync_node := 1'b0;
}
v_sync = v_sync_node;
}
// Top Module is Top_wDCM
`timescale 1ns/1ps
module Top_wDCM_tb;
`include "disp_timing_parameters.vh"
reg m_clock = 1'b0;
reg p_reset = 1'b1;
wire [3:0] VGA_RED;
wire [3:0] VGA_GREEN;
wire [3:0] VGA_BLUE;
wire VGA_HSYNC;
wire VGA_VSYNC;
integer i, j, k, m, n;
parameter PERIOD = 20;
parameter real DUTY_CYCLE = 0.5;
parameter OFFSET = 0;
initial // Clock process for m_clock
begin
#OFFSET;
forever
begin
m_clock = 1'b0;
#(PERIOD-(PERIOD*DUTY_CYCLE)) m_clock = 1'b1;
#(PERIOD*DUTY_CYCLE);
end
end
Top_wDCM UUT (
.m_clock(m_clock),
.p_reset(p_reset),
.VGA_RED(VGA_RED),
.VGA_GREEN(VGA_GREEN),
.VGA_BLUE(VGA_BLUE),
.VGA_HSYNC(VGA_HSYNC),
.VGA_VSYNC(VGA_VSYNC));
initial begin // キャラクタを*で表示する
#(PERIOD*10);
p_reset = 1'b0;
@(posedge VGA_VSYNC); // 垂直同期の立ち上がりまでWAIT
for(i=0; i<= V_FRONT_PORCH-1-10; i=i+1) // V_FRONT_PORCHの10ライン前まで数える(表示範囲を広げるため)
@(posedge VGA_HSYNC); // 水平同期の立ち上がりまでWAIT
for(j=0; j<= H_FRONT_PORCH-1-10; j=j+1) // H_FRONT_PORCHの10ピクセルクロック前まで数える(表示範囲を広げるため)
@(posedge m_clock);
for(k=0; k<(8*5); k=k+1) begin // 8行(1キャラクタ)*5行
for(m=0; m<(8*12); m=m+1) begin // 8ピクセル(1キャラクタ)*12列
#1; // wait
if(VGA_RED>0 || VGA_GREEN>0 || VGA_BLUE>0)
$write("*");
else
$write(" ");
@(posedge m_clock); // 次のクロックへ
end
$write("\n");
@(posedge VGA_HSYNC) ; // 水平同期の立ち上がりまでWAIT
for(n=0; n<= H_FRONT_PORCH-1-10; n=n+1) // H_FRONT_PORCHの10ピクセルクロック前まで数える(表示範囲を広げるため)
@(posedge m_clock);
end
$stop; // 終了
end
endmodule
verilog work ../char_gen_rom.v
verilog work ../dcm_inst.v
verilog work ../Papyrus_work/CharDispCntrler/CharDispCntrler.v
verilog work Top_wDCM_tb.v
verilog work K:\HDL\Xilinx\12.4\ISE_DS\ISE\verilog\src\glbl.v
del Top_wDCM_tb.exe
K:\HDL\Xilinx\12.4\ISE_DS\ISE\bin\nt\fuse work.Top_wDCM_tb work.glbl -incremental -L unisims_ver=K:\HDL\Xilinx\12.4\ISE_DS\ISE\verilog\hdp\nt\unisims_ver -o Top_wDCM_tb.exe -prj Top_wDCM_tb.prj
Top_wDCM_tb.exe -gui
regtemp_pointer[13];
always @(posedge m_clock)
begin
if ((_u_disp_timing_v_sync)|(_net_12))
temp_pointer <= ((_u_disp_timing_v_sync) ?13'b0000000000000:13'b0)|
((_net_12) ?display_addr:13'b0);
end
regtemp_pointer[13] = 0;
always @(posedge m_clock or posedge p_reset)
begin
if (p_reset)
temp_pointer <= 13'b0000000000000;
else if ((_u_disp_timing_v_sync)|(_net_12))
temp_pointer <= ((_u_disp_timing_v_sync) ?13'b0000000000000:13'b0)|
((_net_12) ?display_addr:13'b0);
end
NET "p_reset" IOSTANDARD = LVTTL;
NET "p_reset" PULLDOWN;
NET "m_clock" IOSTANDARD = LVCMOS33;
NET "VGA_VSYNC" DRIVE = 8;
NET "VGA_VSYNC" SLEW = FAST;
NET "VGA_VSYNC" IOSTANDARD = LVTTL;
INST "u_dcm_inst/IBUFG_inst" LOC = E12;
INST "VGA_VSYNC_OBUF" LOC = B11;
NET "p_reset" LOC = T15;
NET "VGA_VSYNC" LOC = B11;
NET "u_dcm_inst/clkin" LOC = E12;
NET "VGA_BLUE[0]" LOC = C7;
NET "VGA_BLUE[1]" LOC = D7;
NET "VGA_BLUE[2]" LOC = B9;
NET "VGA_BLUE[3]" LOC = C9;
NET "VGA_GREEN[0]" LOC = C5;
NET "VGA_GREEN[1]" LOC = D5;
NET "VGA_GREEN[2]" LOC = C6;
NET "VGA_GREEN[3]" LOC = D6;
NET "VGA_HSYNC" LOC = C11;
NET "VGA_RED[0]" LOC = A3;
NET "VGA_RED[1]" LOC = B3;
NET "VGA_RED[2]" LOC = B8;
NET "VGA_RED[3]" LOC = C8;
NET "VGA_BLUE[0]" IOSTANDARD = LVTTL;
NET "VGA_BLUE[1]" IOSTANDARD = LVTTL;
NET "VGA_BLUE[2]" IOSTANDARD = LVTTL;
NET "VGA_BLUE[3]" IOSTANDARD = LVTTL;
NET "VGA_GREEN[0]" IOSTANDARD = LVTTL;
NET "VGA_GREEN[1]" IOSTANDARD = LVTTL;
NET "VGA_GREEN[2]" IOSTANDARD = LVTTL;
NET "VGA_GREEN[3]" IOSTANDARD = LVTTL;
NET "VGA_HSYNC" IOSTANDARD = LVTTL;
NET "VGA_RED[0]" IOSTANDARD = LVTTL;
NET "VGA_RED[1]" IOSTANDARD = LVTTL;
NET "VGA_RED[2]" IOSTANDARD = LVTTL;
NET "VGA_RED[3]" IOSTANDARD = LVTTL;
NET "VGA_BLUE[0]" DRIVE = 8;
NET "VGA_BLUE[1]" DRIVE = 8;
NET "VGA_BLUE[2]" DRIVE = 8;
NET "VGA_BLUE[3]" DRIVE = 8;
NET "VGA_GREEN[0]" DRIVE = 8;
NET "VGA_GREEN[1]" DRIVE = 8;
NET "VGA_GREEN[2]" DRIVE = 8;
NET "VGA_GREEN[3]" DRIVE = 8;
NET "VGA_HSYNC" DRIVE = 8;
NET "VGA_RED[0]" DRIVE = 8;
NET "VGA_RED[1]" DRIVE = 8;
NET "VGA_RED[2]" DRIVE = 8;
NET "VGA_RED[3]" DRIVE = 8;
NET "VGA_BLUE[0]" SLEW = FAST;
NET "VGA_BLUE[1]" SLEW = FAST;
NET "VGA_BLUE[2]" SLEW = FAST;
NET "VGA_BLUE[3]" SLEW = FAST;
NET "VGA_GREEN[0]" SLEW = FAST;
NET "VGA_GREEN[1]" SLEW = FAST;
NET "VGA_GREEN[2]" SLEW = FAST;
NET "VGA_GREEN[3]" SLEW = FAST;
NET "VGA_HSYNC" SLEW = FAST;
NET "VGA_RED[0]" SLEW = FAST;
NET "VGA_RED[1]" SLEW = FAST;
NET "VGA_RED[2]" SLEW = FAST;
NET "VGA_RED[3]" SLEW = FAST;
に対して、parameter RED_DOT_POS = 9; // 9ビット目がRED
parameter GREEN_DOT_POS = 8; // 8ビット目がGREEN
parameter BLUE_DOT_POS = 7; // 7ビット目がBLUE
reg [RED_DOT_POS:BLUE_DOT_POS] temp_color;
if (char_data_node && display_on_d2) {
red_node := temp_color[RED_DOT_POS];
green_node := temp_color[GREEN_DOT_POS];
blue_node := temp_color[BLUE_DOT_POS];
if (char_data_node && display_on_d2) {
red_node := temp_color[2];
green_node := temp_color[1];
blue_node := temp_color[0];
module Top_wDCM {
dcm_inst u_dcm_inst;
CharDispCtrlerTest u_charDispCtrlerTest;
wire clkdv;
wire locked;
u_dcm_inst.clkin = m_clock;
u_dcm_inst.reset = p_reset;
clkdv = u_dcm_inst.clkdv;
locked = u_dcm_inst.locked;
u_charDispCtrlerTest.m_clock = clkdv;
u_charDispCtrlerTest.p_reset = ~locked;
VGA_RED = u_charDispCtrlerTest.VGA_RED;
VGA_GREEN = u_charDispCtrlerTest.VGA_GREEN;
VGA_BLUE = u_charDispCtrlerTest.VGA_BLUE;
VGA_HSYNC = u_charDispCtrlerTest.VGA_HSYNC;
VGA_VSYNC = u_charDispCtrlerTest.VGA_VSYNC;
}
declare CharDispCtrlerTest {
// -- CharDispCtrlerTest --
output VGA_RED[4];
output VGA_GREEN[4];
output VGA_BLUE[4];
output VGA_HSYNC;
output VGA_VSYNC;
}
declareCharDispCtrlerTest interface {
inputm_clock;
inputp_reset;
// -- CharDispCtrlerTest --
outputVGA_RED[4];
outputVGA_GREEN[4];
outputVGA_BLUE[4];
outputVGA_HSYNC;
outputVGA_VSYNC;
}
display_dout = u_frame_buffer.fb_read(display_address).display_dout;
// UML2NSL converter Ver. 2010-03-28 Copyright (c) 2009-2010 IP ARCH, Inc. All rights reserved.
// xmi --- version 2.1 ---
#define C200MS_SECOND ( 23'd230000 - 23'd1)
#define H_ACTIVE_VIDEO 640
#define H_FRONT_PORCH 16
#define H_SYNC_PULSE 96
#define H_BACK_PORCH 48
#define H_SUM H_ACTIVE_VIDEO+H_FRONT_PORCH+H_SYNC_PULSE+H_BACK_PORCH
#define V_ACTIVE_VIDEO 480
#define V_FRONT_PORCH 11
#define V_SYNC_PULSE 2
#define V_BACK_PORCH 31
#define V_SUM V_ACTIVE_VIDEO+V_FRONT_PORCH+V_SYNC_PULSE+V_BACK_PORCH
#define H_DISPLAY_SIZE H_ACTIVE_VIDEO/8 // 横80桁
#define V_DISPLAY_SIZE V_ACTIVE_VIDEO/8 // 縦60行
#define RED_DOT_POS 9 // 9ビット目がRED
#define GREEN_DOT_POS 8 // 8ビット目がGREEN
#define BLUE_DOT_POS 7 // 7ビット目がBLUE
declare CharDispCtrlerTest {
// -- CharDispCtrlerTest --
output VGA_RED[4];
output VGA_GREEN[4];
output VGA_BLUE[4];
output VGA_HSYNC;
output VGA_VSYNC;
}
declare CharDispCtrler {
// -- CharDispCtrler --
output VGA_RED[4];
output VGA_GREEN[4];
output VGA_BLUE[4];
output VGA_HSYNC;
output VGA_VSYNC;
input char_addr[13];
input char_din[10];
// -- CharDispCtrler --
func_in char_write(char_addr,char_din);
}
declare Top_wDCM {
// -- Top_wDCM --
output VGA_RED[4];
output VGA_GREEN[4];
output VGA_BLUE[4];
output VGA_HSYNC;
output VGA_VSYNC;
}
declare frame_buffer {
// -- frame_buffer --
input char_addr[13];
input char_din[10];
input char_we;
input display_addr[13];
output display_dout[10];
// -- frame_buffer --
func_in fb_write(char_addr, char_din);
func_in fb_read(display_addr) ;
}
declare char_gen_rom_nsl {
// -- char_gen_rom_nsl --
input char_addr[7];
input row_addr[3];
output dout[8];
}
declare disp_timing {
// -- disp_timing --
output page_start;
output display_on;
output h_addr[10];
output v_addr[10];
output h_sync;
output h_sync_pulse;
output v_sync;
}
declare dcm_inst interface {
input clkin;
input reset;
output clkout;
output clkfx;
output clkdv;
output locked;
}
declare char_gen_rom interface {
input clk;
input reset;
input char_addr[7];
input rom_addr[3];
output dout[8];
}
module CharDispCtrlerTest {
// -- CharDispCtrlerTest --
reg char_addr[13];
reg char_we;
reg count_200ms[23];
reg char_code[7] = 7'h21;
reg color_data[3] = 1;
wire char_data[10];
func_self char_code_inc();
func_self color_data_inc();
CharDispCtrler u_charDispCtrler;
/* common operations */
{
VGA_RED = u_charDispCtrler.VGA_RED;
VGA_GREEN = u_charDispCtrler.VGA_GREEN;
VGA_BLUE = u_charDispCtrler.VGA_BLUE;
VGA_HSYNC = u_charDispCtrler.VGA_HSYNC;
VGA_VSYNC = u_charDispCtrler.VGA_VSYNC;
char_data = { color_data, char_code };
any {
count_200ms == C200MS_SECOND : {
count_200ms := 0;
u_charDispCtrler.char_write(char_addr, char_data); // キャラクタを描画
char_code_inc(); // キャラクタをインクリメント
color_data_inc(); // カラーをインクリメント
} else : {
count_200ms++;
}
}
}
function char_code_inc {
if (char_code == 7'h7E) {
char_code := 7'h21;
} else {
char_code++;
}
}
function color_data_inc {
if (color_data == 3'h7) {
color_data := 3'h1;
} else {
color_data ++;
}
}
}
module CharDispCtrler {
// -- CharDispCtrler --
wire h_sync_pulse;
reg char_data_node[7];
reg temp_pointer[13];
reg page_start;
reg display_address[13];
wire char_data[8];
wire display_out[10];
reg display_on_d1, display_on_d2;
reg h_sync_1, v_sync_1;
reg h_sync_2, v_sync_2;
reg h_sync_3, v_sync_3;
wire display_dout[10];
reg temp_color[3];
reg red_node, green_node, blue_node;
frame_buffer u_frame_buffer;
char_gen_rom_nsl u_char_gen_rom_nsl;
disp_timing u_disp_timing;
/* common operations */
{
u_frame_buffer.display_addr = display_address;
u_char_gen_rom_nsl.char_addr = u_frame_buffer.display_dout[6:0];
u_char_gen_rom_nsl.row_addr = u_disp_timing.v_addr[2:0];
char_data = u_char_gen_rom_nsl.dout;
display_dout = u_frame_buffer.fb_read(display_address).display_dout;
any {
u_disp_timing.display_on : {
if (u_disp_timing.h_addr[2:0] == 3'd7) {
display_address++;
}
}
u_disp_timing.v_sync : {
display_address := 0;
temp_pointer := 0;
}
u_disp_timing.h_sync_pulse : {
if (u_disp_timing.v_addr[2:0] == 3'd7)
temp_pointer := display_address;
else
display_address := temp_pointer;
}
}
any {
u_disp_timing.h_addr[2:0] == 3'd2 : {
char_data_node := char_data[7:1];
temp_color := display_dout[RED_DOT_POS : BLUE_DOT_POS];
if (char_data[0] && display_on_d2) {
red_node := display_dout[RED_DOT_POS];
green_node := display_dout[GREEN_DOT_POS];
blue_node := display_dout[BLUE_DOT_POS];
} else {
red_node := 1'b0;
green_node := 1'b0;
blue_node := 1'b0;
}
}
else : {
char_data_node := { 1'b0, char_data_node[6:1] };
if (char_data_node && display_on_d2) {
red_node := temp_color[RED_DOT_POS];
green_node := temp_color[GREEN_DOT_POS];
blue_node := temp_color[BLUE_DOT_POS];
} else {
red_node := 1'b0;
green_node := 1'b0;
blue_node := 1'b0;
}
}
}
VGA_RED = {4{red_node}};
VGA_GREEN = {4{green_node}};
VGA_BLUE = {4{blue_node}};
display_on_d1 := u_disp_timing.display_on;
display_on_d2 := display_on_d1;
h_sync_1 := u_disp_timing.h_sync;
v_sync_1 := u_disp_timing.v_sync;
h_sync_2 := h_sync_1;
v_sync_2 := v_sync_1;
h_sync_3 := h_sync_2;
v_sync_3 := v_sync_3;
VGA_HSYNC = ~h_sync_3;
VGA_VSYNC = ~v_sync_3;
}
/* func_in char_write(char_addr,char_dout) operation */
function char_write {
u_frame_buffer.fb_write(char_addr, char_data);
}
}
module Top_wDCM {
dcm_inst u_dcm_inst;
CharDispCtrlerTest u_charDispCtrlerTest;
wire clkdv;
wire locked;
u_dcm_inst.clkin = m_clock;
u_dcm_inst.reset = p_reset;
clkdv = u_dcm_inst.clkdv;
locked = u_dcm_inst.locked;
u_charDispCtrlerTest.m_clock = clkdv;
u_charDispCtrlerTest.p_reset = ~locked;
VGA_RED = u_charDispCtrlerTest.VGA_RED;
VGA_GREEN = u_charDispCtrlerTest.VGA_GREEN;
VGA_BLUE = u_charDispCtrlerTest.VGA_BLUE;
VGA_HSYNC = u_charDispCtrlerTest.VGA_HSYNC;
VGA_VSYNC = u_charDispCtrlerTest.VGA_VSYNC;
}
module frame_buffer {
mem m[8192][10] ;
reg ReadData[10];
/* common operations */
{
display_dout = ReadData;
}
/* func_in fb_read(display_addr) operation */
function fb_read {
ReadData := m[display_addr] ;
}
/* function fb_write(char_addr,char_din) operation */
function fb_write {
m[char_addr] := char_din ;
}
}
module char_gen_rom_nsl {
char_gen_rom u_char_gen_rom;
u_char_gen_rom.clk = m_clock;
u_char_gen_rom.reset = p_reset;
u_char_gen_rom.char_addr = char_addr;
u_char_gen_rom.row_addr = row_addr;
dout = u_char_gen_rom.dout;
}
module disp_timing {
reg h_point, h_addr_node[11]; // 1024までOK
reg v_point, v_addr_node[11]; // 1024までOK
reg page_start_node;
reg display_on_node;
reg h_sync_node;
reg v_sync_node;
reg h_sync_pulse_node;
any {
h_point == H_SUM-1 :
h_point := 0;
else :
h_point++;
}
h_addr_node := h_point;
h_addr = h_addr_node[9:0];
any {
v_point == V_SUM-1 :
v_point := 0;
else :
v_point++;
}
v_addr_node := v_point;
v_addr = v_addr_node[9:0];
any {
h_point<H_ACTIVE_VIDEO && v_point<V_ACTIVE_VIDEO :
display_on_node := 1'b1;
else :
display_on_node := 1'b0;
}
display_on = display_on_node;
any {
h_point==0 :
page_start_node := 1'b1;
else :
page_start_node := 1'b0;
}
page_start = page_start_node;
any {
(h_point>=(H_ACTIVE_VIDEO + H_FRONT_PORCH)) && (h_point < (H_SUM-H_BACK_PORCH)) :
h_sync_node := 1'b1;
else :
h_sync_node := 1'b0;
}
h_sync = h_sync_node;
any {
h_point==(H_ACTIVE_VIDEO+H_FRONT_PORCH) :
h_sync_pulse_node := 1'b1;
else :
h_sync_pulse_node := 1'b0;
}
h_sync_pulse = h_sync_pulse_node;
any {
(v_point>=(V_ACTIVE_VIDEO + V_FRONT_PORCH)) && (v_point<(V_SUM-V_BACK_PORCH)) :
v_sync_node := 1'b1;
else :
v_sync_node := 1'b0;
}
v_sync = v_sync_node;
}
// DCM module
`default_nettype none
`timescale 1ns / 1ps
module dcm_inst(clkin, reset, clkout, clkfx, clkdv, locked);
input clkin;
input reset;
output clkout;
output clkfx;
output clkdv;
output locked;
wire clkin;
wire reset;
wire clkout;
wire clkfx;
wire clkdv;
wire locked;
wire clk_ibuf;
wire clkfb, clkfx_node;
wire gnd, clk_node;
wire clkdv_node, clkdv_bufg;
assign gnd = 1'b0;
IBUFG IBUFG_inst (
.I(clkin),
.O(clk_ibuf)
);
DCM DCM_INST1 (
.CLKIN(clk_ibuf),
.CLKFB(clkfb),
.DSSEN(gnd),
.PSINCDEC(gnd),
.PSEN(gnd),
.PSCLK(gnd),
.RST(gnd), // リセットごとにDCMのロックが外れないようにgndにしておく
.CLK0(clk_node),
.CLK90(),
.CLK180(),
.CLK270(),
.CLK2X(),
.CLK2X180(),
.CLKDV(clkdv_node),
.CLKFX(clkfx_node),
.CLKFX180(),
.LOCKED(locked),
.PSDONE(),
.STATUS()
);
defparam DCM_INST1.CLKIN_PERIOD = 20.0;
defparam DCM_INST1.DLL_FREQUENCY_MODE = "LOW";
defparam DCM_INST1.DUTY_CYCLE_CORRECTION = "TRUE";
defparam DCM_INST1.CLKDV_DIVIDE = 2.0;
defparam DCM_INST1.PHASE_SHIFT = 0;
defparam DCM_INST1.CLKOUT_PHASE_SHIFT = "NONE";
defparam DCM_INST1.STARTUP_WAIT = "FALSE";
defparam DCM_INST1.FACTORY_JF = 16'hFFFF;
BUFG BUFG_inst(
.I(clk_node),
.O(clkfb)
);
BUFG BUFG_clkfx(
.I(clkfx_node),
.O(clkfx)
);
BUFG BUFG_clkdv(
.I(clkdv_node),
.O(clkdv_bufg)
);
assign clkout = clkdv_bufg;
assign clkdv = clkdv_bufg;
endmodule
// キャラクタジェネレータ用ROM
`default_nettype none
`timescale 1ns / 1ps
module char_gen_rom(clk, reset, char_addr, row_addr, dout);
input clk;
input reset;
input [6:0] char_addr;
input [2:0] row_addr;
output [7:0] dout;
wire clk;
wire reset;
wire [6:0] char_addr;
wire [2:0] row_addr;
wire [7:0] dout;
wire [10:0] addr;
assign addr = {1'b0, char_addr, row_addr};
RAMB16_S9 #(
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0014147F147F1414000000000012243600080008080808080000000000000000), // #,",!,
.INIT_09(256'h0000000000081018004C322254081408002152240812254200083E483E093E08), // ',&,%,$
.INIT_0A(256'h000808087F08080800492A1C7F1C2A4900040810101008040020100808081020), // +,*,),(
.INIT_0B(256'h00010204081020400006060000000000000000007F0000000002040600000000), // /,.,-,,
.INIT_0C(256'h001C22201820221C003E02041820221C001C080808080C080018244242422418), // 3,2,1,0
.INIT_0D(256'h001010202040407E003C42423E02423C001E20201E02023E0020207E22242830), // 7,6,5,4
.INIT_0E(256'h0004080C00000C000000000C00000C00003C42407C42423C003C42423C42423C), // ;,:,9,8
.INIT_0F(256'h000800081020221C00040810201008040000003E003E00000020100804081020), // ?,>,=,<
.INIT_10(256'h001C22010101221C003F41413F41413F0041417F2236141C005C2A155549221E), // C,B,A,@
.INIT_11(256'h001C22710101221C000101013F01017F007F01013F01017F001F21414141211F), // G,F,E,D
.INIT_12(256'h0022120A060A1222000E11101010103E001C08080808081C004141417F414141), // K,J,I,H
.INIT_13(256'h001C22414141221C00416151494543410041414149556341003E020202020202),// O,N,M,L
.INIT_14(256'h003C42403C02423C002111093F41413F005C26594141221C000101013F41413F), // S,R,Q,P
.INIT_15(256'h00225555554949490008141422224141001C224141414141000808080808087F), // W,V,U,T
.INIT_16(256'h0038080808080838003F02040810203F00080808081422410041221408142241), // [,Z,Y,X
.INIT_17(256'h007F0000000000000000000000221408001C10101010101C0008083E083E1422), // _,^,],\
.INIT_18(256'h0038040438000000001E22221E020200003C223C201C00000000000000180810), // c,b,a,`
.INIT_19(256'h001C221C0C122C00000808081C081000001C021E221C0000003C22223C202000), // g,f,e,d
.INIT_1A(256'h0024140C14240400000C1210100010000008080800080000002424241C040400), // k,j,i,h
.INIT_1B(256'h0018242424180000002828282814000000545454542A00000018080808080800), // o,n,m,l
.INIT_1C(256'h0018201804180000000404040C34000000202038243800000004041C241C0000), // s,r,q,p
.INIT_1D(256'h00142A2A2A2200000008141422220000001824242424000000180808081C0800), // w,v,u,t
.INIT_1E(256'h001008080C080810003E0408103E000000020408142200000022140814220000), // {,z,y,x
.INIT_1F(256'h0000000000000000000000000000142800040808180808040008080808080808), // ,~,},|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
) CHAR_GEN_ROM_INST (
.DO(dout),
.DOP(),
.ADDR(addr),
.CLK(clk),
.DI(8'd0),
.DIP(1'b0),
.EN(1'b1),
.SSR(reset),
.WE(1'b0)
);
endmodule
u_frame_buffer.display_addr = display_address;
display_dout = u_frame_buffer.fb_read(display_address).display_dout
reg h_point, h_addr_node[11];
reg h_point[11], h_addr_node[11];
// wire [20:0] camc_addr;
wire [18:0] camc_addr;
日 | 月 | 火 | 水 | 木 | 金 | 土 |
---|---|---|---|---|---|---|
- | - | 1 | 2 | 3 | 4 | 5 |
6 | 7 | 8 | 9 | 10 | 11 | 12 |
13 | 14 | 15 | 16 | 17 | 18 | 19 |
20 | 21 | 22 | 23 | 24 | 25 | 26 |
27 | 28 | - | - | - | - | - |