library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all;
library unisim; use unisim.vcomponents.all;
entity CharDispCtrlerTest is port( clk : in std_logic; reset : in std_logic; -- dvi_reset : in std_logic;
dvi_xclk_p : out std_logic; dvi_xclk_n : out std_logic; dvi_reset_b : out std_logic; dvi_hsync : out std_logic; dvi_vsync : out std_logic; dvi_de : out std_logic; dvi_d : out std_logic_vector(11 downto 0); dvi_sda : out std_logic; dvi_scl : out std_logic ); end CharDispCtrlerTest;
architecture RTL of CharDispCtrlerTest is
...
-- CH7301C へ出力する dvi_reset_b <= '1';
ODDR_dvi_xclk_p : ODDR generic map( DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" INIT => '0', -- Initial value for Q port (’1’ or ’0’) SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC") port map( Q => dvi_xclk_p, C => clk90, CE => '1', D1 => '1', D2 => '0', R => reset_node, S => '0' );
ODDR_dvi_xclk_n : ODDR generic map( DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" INIT => '1', -- Initial value for Q port (’1’ or ’0’) SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC") port map( Q => dvi_xclk_n, C => clk90, CE => '1', D1 => '0', D2 => '1', R => reset_node, S => '0' );
ODDR_dvi_d0 : ODDR generic map( DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" INIT => '0', -- Initial value for Q port (’1’ or ’0’) SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC") port map( Q => dvi_d(0), C => clk0, CE => '1', D1 => VGA_BLUE, -- B[0] D2 => VGA_GREEN, -- G[4] R => reset_node, S => '0' );
ODDR_dvi_d1 : ODDR generic map( DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" INIT => '0', -- Initial value for Q port (’1’ or ’0’) SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC") port map( Q => dvi_d(1), C => clk0, CE => '1', D1 => VGA_BLUE, -- B[1] D2 =>VGA_GREEN, -- G[5] R => reset_node, S => '0' );
ODDR_dvi_d2 : ODDR generic map( DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" INIT => '0', -- Initial value for Q port (’1’ or ’0’) SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC") port map( Q => dvi_d(2), C => clk0, CE => '1', D1 => VGA_BLUE, -- B[2] D2 => VGA_GREEN, -- G[6] R => reset_node, S => '0' );
ODDR_dvi_d3 : ODDR generic map( DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" INIT => '0', -- Initial value for Q port (’1’ or ’0’) SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC") port map( Q => dvi_d(3), C => clk0, CE => '1', D1 => VGA_BLUE, -- B[3] D2 => VGA_GREEN, -- G[7] R => reset_node, S => '0' );
ODDR_dvi_d4 : ODDR generic map( DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" INIT => '0', -- Initial value for Q port (’1’ or ’0’) SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC") port map( Q => dvi_d(4), C => clk0, CE => '1', D1 => VGA_BLUE, -- B[4] D2 => VGA_RED, -- R[0] R => reset_node, S => '0' );
ODDR_dvi_d5 : ODDR generic map( DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" INIT => '0', -- Initial value for Q port (’1’ or ’0’) SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC") port map( Q => dvi_d(5), C => clk0, CE => '1', D1 => VGA_BLUE, -- B[5] D2 => VGA_RED, -- R[1] R => reset_node, S => '0' );
ODDR_dvi_d6 : ODDR generic map( DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" INIT => '0', -- Initial value for Q port (’1’ or ’0’) SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC") port map( Q => dvi_d(6), C => clk0, CE => '1', D1 => VGA_BLUE, -- B[6] D2 => VGA_RED, -- R[2] R => reset_node, S => '0' );
ODDR_dvi_d7 : ODDR generic map( DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" INIT => '0', -- Initial value for Q port (’1’ or ’0’) SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC") port map( Q => dvi_d(7), C => clk0, CE => '1', D1 => VGA_BLUE, -- B[7] D2 => VGA_RED, -- R[3] R => reset_node, S => '0' );
ODDR_dvi_d8 : ODDR generic map( DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" INIT => '0', -- Initial value for Q port (’1’ or ’0’) SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC") port map( Q => dvi_d(8), C => clk0, CE => '1', D1 => VGA_GREEN, -- G[0] D2 => VGA_RED, -- R[4] R => reset_node, S => '0' );
ODDR_dvi_d9 : ODDR generic map( DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" INIT => '0', -- Initial value for Q port (’1’ or ’0’) SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC") port map( Q => dvi_d(9), C => clk0, CE => '1', D1 => VGA_GREEN, -- G[1] D2 => VGA_RED, -- R[5] R => reset_node, S => '0' );
ODDR_dvi_d10 : ODDR generic map( DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" INIT => '0', -- Initial value for Q port (’1’ or ’0’) SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC") port map( Q => dvi_d(10), C => clk0, CE => '1', D1 => VGA_GREEN, -- G[2] D2 => VGA_RED, -- R[6] R => reset_node, S => '0' );
ODDR_dvi_d11 : ODDR generic map( DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" INIT => '0', -- Initial value for Q port (’1’ or ’0’) SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC") port map( Q => dvi_d(11), C => clk0, CE => '1', D1 => VGA_GREEN, -- G[3] D2 => VGA_RED, -- R[7] R => reset_node, S => '0' );
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all;
entity CharDispCtrlerTest is port( clk : in std_logic; reset : in std_logic;
dvi_xclk_p : out std_logic; dvi_xclk_n : out std_logic; dvi_reset_b : out std_logic; dvi_hsync : out std_logic; dvi_vsync : out std_logic; dvi_de : out std_logic; dvi_d : out std_logic_vector(11 downto 0) ); end CharDispCtrlerTest;
ODDR_dvi_xclk_p : ODDR port map( Q => dvi_xclk_p, C => clkdv, CE => '1', D1 => '1', D2 => '0', R => reset, S => '0' );
ODDR_dvi_xclk_n : ODDR generic map( DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" INIT => '1', -- Initial value for Q port (’1’ or ’0’) SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC") port map( Q => dvi_xclk_n, C => clkdv, CE => '1', D1 => '0', D2 => '1', R => reset, S => '0' );
左のInstance and Process Nameウインドウを見ても、ODDRのインスタンスがない。 ISimでは下のようなワーニングが出ている。
WARNING:HDLCompiler:89 - "C:/HDL/FndISEWork/Virtex5_VLX110T/CharDispCtrler/CharDispCtrlerTest/CharDispCtrlerTest_synth/../CharDispCtrlerTest.vhd" Line 191: remains a black-box since it has no binding entity.
そこで、umisimライブラリ書き足した。
-- CharDispCtrlerTest.vhd
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all;
library unisim; use unisim.vcomponents.all;
こうすると、ちゃんと左のInstance and Process NameウインドウにODDRがインスタンスされて、シミュレーションが正常になった。
library ieee; use ieee.std_logic_1164.all; -- pragma translate_off library unisim; use unisim.vcomponents.all; -- pragma translate_on library work;
entity dcm_inst is port ( clkin : in std_logic; reset : in std_logic; clkout : out std_logic; clk90 : out std_logic; locked : out std_logic ); end dcm_inst;
architecture RTL of dcm_inst is component DCM generic ( CLKDV_DIVIDE : real := 2.0; CLKFX_DIVIDE : integer := 1; CLKFX_MULTIPLY : integer := 4; CLKIN_DIVIDE_BY_2 : boolean := false; CLKIN_PERIOD : real := 10.0; CLKOUT_PHASE_SHIFT : string := "NONE"; CLK_FEEDBACK : string := "1X"; DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"; DFS_FREQUENCY_MODE : string := "LOW"; DLL_FREQUENCY_MODE : string := "LOW"; DSS_MODE : string := "NONE"; DUTY_CYCLE_CORRECTION : boolean := true; FACTORY_JF : bit_vector := X"C080"; PHASE_SHIFT : integer := 0; SIM_MODE : string := "SAFE"; STARTUP_WAIT : boolean := false ); port ( CLKIN : in std_logic; CLKFB : in std_logic; DSSEN : in std_logic; PSINCDEC : in std_logic; PSEN : in std_logic; PSCLK : in std_logic; RST : in std_logic; CLK0 : out std_logic; CLK90 : out std_logic; CLK180 : out std_logic; CLK270 : out std_logic; CLK2X : out std_logic; CLK2X180 : out std_logic; CLKDV : out std_logic; CLKFX : out std_logic; CLKFX180 : out std_logic; LOCKED : out std_logic; PSDONE : out std_logic; STATUS : out std_logic_vector(7 downto 0) ); end component; component BUFG port ( I : in std_logic; O : out std_logic ); end component; component IBUFG port ( I : in std_logic; O : out std_logic ); end component;
signal clk_ibuf : std_logic; signal clkfb : std_logic; signal gnd, clk_node : std_logic; signal clkdv_node, clkdv_bufg : std_logic; signal clk_node2, clk90_node : std_logic; signal clk90_bufg, clk_bufg : std_logic; signal dcm1_locked : std_logic; signal dcm2_reset : std_logic; begin gnd <= '0';
ibufg_inst : ibufg port map( i => clkin, o => clk_ibuf );
SRL16E_inst : SRL16E generic map ( INIT => X"0000") port map ( Q => Q, -- SRL data output A0 => A0, -- Select[0] input A1 => A1, -- Select[1] input A2 => A2, -- Select[2] input A3 => A3, -- Select[3] input CE => CE, -- Clock enable input CLK => CLK, -- Clock input D => D -- SRL data input );
これを参考に、上のVHDLコードを修正した。VHDLを下に示す。
-- DCM module
library ieee; use ieee.std_logic_1164.all; library unisim; use unisim.vcomponents.all; library work;
entity dcm_inst is port ( clkin : in std_logic; reset : in std_logic; clkout : out std_logic; clk90 : out std_logic; locked : out std_logic ); end dcm_inst;
architecture RTL of dcm_inst is component DCM generic ( CLKDV_DIVIDE : real := 2.0; CLKFX_DIVIDE : integer := 2; CLKFX_MULTIPLY : integer := 4; CLKIN_DIVIDE_BY_2 : boolean := false; CLKIN_PERIOD : real := 10.0; CLKOUT_PHASE_SHIFT : string := "NONE"; CLK_FEEDBACK : string := "1X"; DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"; DFS_FREQUENCY_MODE : string := "LOW"; DLL_FREQUENCY_MODE : string := "LOW"; DSS_MODE : string := "NONE"; DUTY_CYCLE_CORRECTION : boolean := true; FACTORY_JF : bit_vector := X"C080"; PHASE_SHIFT : integer := 0; SIM_MODE : string := "SAFE"; STARTUP_WAIT : boolean := false ); port ( CLKIN : in std_logic; CLKFB : in std_logic; DSSEN : in std_logic; PSINCDEC : in std_logic; PSEN : in std_logic; PSCLK : in std_logic; RST : in std_logic; CLK0 : out std_logic; CLK90 : out std_logic; CLK180 : out std_logic; CLK270 : out std_logic; CLK2X : out std_logic; CLK2X180 : out std_logic; CLKDV : out std_logic; CLKFX : out std_logic; CLKFX180 : out std_logic; LOCKED : out std_logic; PSDONE : out std_logic; STATUS : out std_logic_vector(7 downto 0) ); end component; component BUFG port ( I : in std_logic; O : out std_logic ); end component; component IBUFG port ( I : in std_logic; O : out std_logic ); end component;
signal clk_ibuf : std_logic; signal clkfb : std_logic; signal gnd, clk_node : std_logic; signal clkdv_node, clkdv_bufg : std_logic; signal clk_node2, clk90_node : std_logic; signal clk90_bufg, clk_bufg : std_logic; signal dcm1_locked : std_logic; signal dcm2_reset : std_logic; signal dcm2_reset_SRL16E : std_logic; begin gnd <= '0';
ibufg_inst : ibufg port map( i => clkin, o => clk_ibuf );
XUPV5-LX110T Development SystemでCMOSカメラの画像を表示するために、XGA用の1024*768*3bit(RGB)のフレームバッファを付けた回路を実装している。 VHDLで書き終えたので、ISE13.1のISimでシミュレーションしようとしたら、Simulation Terminatedダイアログが出て、シミュレーションできない。OSはWindows7 32ビット版 SP1。使用言語はVHDL。
isim.log を見ても情報がない。
ISim log file Running: ......(実行コマンド、一応伏せてあります) This is a Full version of ISim. Time resolution is 1 fs # onerror resume # wave add / No active Database # run 1000 ns Unable to execute live simulation command.