// dice_top_tb_sc.cpp
#include "Vdice_top.h"
#include "verilated_vcd_sc.h"
int sc_main(int argc, char **argv) {
Verilated::commandArgs(argc, argv); // Remember args
sc_clock clk ("clk", 10, SC_NS);
sc_signal<bool> reset_sw, roll;
sc_signal<uint32_t> an_n;
sc_signal<bool> a_n, b_n, c_n, d_n, e_n, f_n, g_n, dp_n;
int clk_count;
Vdice_top *top;
top = new Vdice_top("top");
top->clk(clk);
top->reset_sw(reset_sw);
top->roll(roll);
top->an_n(an_n);
top->a_n(a_n);
top->b_n(b_n);
top->c_n(c_n);
top->d_n(d_n);
top->e_n(e_n);
top->f_n(f_n);
top->g_n(g_n);
top->dp_n(dp_n);
Verilated::traceEverOn(true);
VerilatedVcdC* tfp = new VerilatedVcdC;
top->trace (tfp, 99);
tfp->open ("simx_sc.vcd");
reset_sw = 1; // Set some inputs
roll = 0;
sc_start(11, SC_NS); // 1nsずらす
reset_sw = 0;
sc_start(10, SC_NS);
roll = 1;
for (clk_count=0; clk_count<98; clk_count++){
sc_start(10, SC_NS);
}
// sc_start(980, SC_NS);
roll = 0;
sc_start(20, SC_NS);
roll = 1;
tfp->close();
delete top;
exit(0); // シミュレーション終了
}
$ verilator -Wno-lint -sc --trace dice_top.v --exe dice_top_tb_sc.cpp
$ cd obj_dir/
$ make -j -f Vdice_top.mk Vdice_top
$ ./Vdice_top.exe
// dice_top_tb_sc2.cpp
#include <systemc.h>
#include "Vdice_top.h"
int sc_main(int argc, char **argv) {
Verilated::commandArgs(argc, argv); // Remember args
sc_clock clk ("clk", 10, SC_NS);
sc_signal<bool> reset_sw, roll;
sc_signal<uint32_t> an_n;
sc_signal<bool> a_n, b_n, c_n, d_n, e_n, f_n, g_n, dp_n;
int clk_count;
Vdice_top *top;
top = new Vdice_top("top");
top->clk(clk);
top->reset_sw(reset_sw);
top->roll(roll);
top->an_n(an_n);
top->a_n(a_n);
top->b_n(b_n);
top->c_n(c_n);
top->d_n(d_n);
top->e_n(e_n);
top->f_n(f_n);
top->g_n(g_n);
top->dp_n(dp_n);
sc_trace_file *trace_f;
trace_f = sc_create_vcd_trace_file("simx_sc2");
trace_f->set_time_unit(1.0, SC_NS);
sc_trace(trace_f, clk, "clk");
sc_trace(trace_f, reset_sw, "reset_sw");
sc_trace(trace_f, roll, "roll");
sc_trace(trace_f, an_n, "an_n");
sc_trace(trace_f, a_n, "a_n");
sc_trace(trace_f, b_n, "b_n");
sc_trace(trace_f, c_n, "c_n");
sc_trace(trace_f, d_n, "d_n");
sc_trace(trace_f, e_n, "e_n");
sc_trace(trace_f, f_n, "f_n");
sc_trace(trace_f, g_n, "g_n");
sc_trace(trace_f, dp_n, "dp_n");
sc_trace(trace_f, top->v__DOT__roll_ena, "roll_ena");
sc_trace(trace_f, top->v__DOT__inst_dice_sm__DOT__spots_node, "spots");
sc_trace(trace_f, top->v__DOT__inst_dice_sm__DOT__DICE_STATE, "DICE_STATE");
reset_sw = 1; // Set some inputs
roll = 0;
sc_start(11, SC_NS); // 1nsずらす
reset_sw = 0;
sc_start(10, SC_NS);
roll = 1;
for (clk_count=0; clk_count<98; clk_count++){
sc_start(10, SC_NS);
}
// sc_start(980, SC_NS);
roll = 0;
sc_start(20, SC_NS);
roll = 1;
sc_close_vcd_trace_file( trace_f );
delete top;
exit(0); // シミュレーション終了
}
#include "Vdice_state_machine.h"
int sc_main(int argc, char **argv) {
Verilated::commandArgs(argc, argv);
sc_clock clk ("clk", 10, SC_NS);
sc_signal<bool> reset_sw, roll, roll_ena;
sc_signal<uint32_t> spots;
Vdice_state_machine *top;
int clk_count;
top = new Vdice_state_machine("top");
top->clk(clk);
top->reset_sw(reset_sw);
top->roll(roll);
top->roll_ena(roll_ena);
top->spots(spots);
reset_sw = 1;
roll = 0;
roll_ena = 0;
sc_start(11, SC_NS); // 1nsずらす
reset_sw = 0;
sc_start(10, SC_NS);
roll = 1;
for (clk_count=0; clk_count<20; clk_count++){
sc_start(10, SC_NS);
roll_ena = !roll_ena;
cout << "roll_ena = " << roll_ena << " spots = " << spots << endl;
}
delete top;
exit(0); // シミュレーション終了
}
$ verlator -Wno-lint -sc dice_sta_machine.v --exe dsm_sc.cpp
$ cd obj_dir
$ make -j -f Vdice_state_machine.mk Vdice_state_machine
$ ./Vdice_state_machine.exe
#include "Vdice_state_machine.h"
#include "verilated_vcd_sc.h"
int sc_main(int argc, char **argv) {
Verilated::commandArgs(argc, argv);
sc_clock clk ("clk", 10, SC_NS);
sc_signal<bool> reset_sw, roll, roll_ena;
sc_signal<uint32_t> spots;
Vdice_state_machine *top;
int clk_count;
top = new Vdice_state_machine("top");
top->clk(clk);
top->reset_sw(reset_sw);
top->roll(roll);
top->roll_ena(roll_ena);
top->spots(spots);
Verilated::traceEverOn(true);
VerilatedVcdSc* tfp = new VerilatedVcdSc;
top->trace (tfp, 99);
tfp->open ("simx.vcd");
reset_sw = 1;
roll = 0;
roll_ena = 0;
sc_start(11, SC_NS); // 1nsずらす
reset_sw = 0;
sc_start(10, SC_NS);
roll = 1;
for (clk_count=0; clk_count<20; clk_count++){
sc_start(10, SC_NS);
roll_ena = !roll_ena;
cout << "roll_ena = " << roll_ena << " spots = " << spots << endl;
}
tfp->close();
delete top;
exit(0); // シミュレーション終了
}
$ verilator -Wno-lint --trace -sc dice_state_machine.v --exe dsm_sc_vcd.cpp
$ cd obj_dir
$ make -j -f Vdice_state_machine.mk Vdice_state_machine
$ ./Vdice_state_machine.exe
#include "string.h"
#include "cstdlib"
const int SC_DEFAULT_STACK_SIZE = 0x50000;
$ mkdir objdir
$ cd objdir/
$ export CXX=g++
$ ../configure
$ make pthreads
$ make install
$ make check
$ make pthreads_check
while(busy){
sc_start(10, SC_NS);
cout << "bcd = ";
cout << hex << showbase << bcd << endl;
}
`default_nettype none
`timescale 1ns / 1ps
// 電子サイコロ Verilog2001
module dice_top(
input wire reset_sw,
input wire clk,
input wire roll,
output wire [3:0] an_n,
output wire a_n,
output wire b_n,
output wire c_n,
output wire d_n,
output wire e_n,
output wire f_n,
output wire g_n,
output wire dp_n
);
wire roll_sig;
wire roll_ena;
wire [2:0] binary;
assign an_n = 4'b1110; // AN0のみ点灯
assign dp_n = 1'b1; // ドットの消灯
reject_chatter inst_reject_chatter(
.reset_sw(reset_sw),
.clk(clk),
.roll(roll),
.roll_sig(roll_sig),
.roll_ena(roll_ena)
);
dice_state_machine inst_dice_sm(
.reset_sw(reset_sw),
.clk(clk),
.roll(roll_sig),
.roll_ena(roll_ena),
.spots(binary)
);
seven_seg_dec inst_seven_seg_dec(
.binary(binary),
.a_n(a_n),
.b_n(b_n),
.c_n(c_n),
.d_n(d_n),
.e_n(e_n),
.f_n(f_n),
.g_n(g_n)
);
endmodule
`default_nettype wire
`default_nettype none
`timescale 1ns / 1ps
// 7セグメントLEDデコーダ、0で点灯します。
(* bram_map="yes" *)
module seven_seg_dec(
input wire [2:0] binary,
output reg a_n,
output reg b_n,
output reg c_n,
output reg d_n,
output reg e_n,
output reg f_n,
output reg g_n
);
always @* begin
case (binary)
3'd1 : begin
a_n=1'b1; b_n=1'b0; c_n=1'b0; d_n=1'b1; e_n=1'b1; f_n=1'b1; g_n=1'b1;
end
3'd2 : begin
a_n=1'b0; b_n=1'b0; c_n=1'b1; d_n=1'b0; e_n=1'b0; f_n=1'b1; g_n=1'b0;
end
3'd3 : begin
a_n=1'b0; b_n=1'b0; c_n=1'b0; d_n=1'b0; e_n=1'b1; f_n=1'b1; g_n=1'b0;
end
3'd4 : begin
a_n=1'b1; b_n=1'b0; c_n=1'b0; d_n=1'b1; e_n=1'b1; f_n=1'b0; g_n=1'b0;
end
3'd5 : begin
a_n=1'b0; b_n=1'b1; c_n=1'b0; d_n=1'b0; e_n=1'b1; f_n=1'b0; g_n=1'b0;
end
3'd6 : begin
a_n=1'b0; b_n=1'b1; c_n=1'b0; d_n=1'b0; e_n=1'b0; f_n=1'b0; g_n=1'b0;
end
default : begin
a_n=1'b1; b_n=1'b0; c_n=1'b0; d_n=1'b1; e_n=1'b1; f_n=1'b1; g_n=1'b1;
end
endcase
end
endmodule
`default_nettype wire
`default_nettype none
`timescale 1ns / 1ps
// スイッチのチャタリング除去とサイコロの表示変更タイミング20msをカウントする
// Verilog2001
module reject_chatter(
input wire reset_sw,
input wire clk,
input wire roll,
output wire roll_sig,
output reg roll_ena
);
reg [17:0] sw_cnt;
reg [1:0] roll_cnt;
reg roll_node;
parameter frequency_KHz = 1; // KHz単位でのクロック周波数(シミュレーション用に値を変更)
// parameter frequency_KHz = 50000; // KHz単位でのクロック周波数
parameter divided_200Hz = frequency_KHz * 5; // 200Hzに分周するための分周比
// 200Hz, 5ms
always @(posedge clk) begin
if (reset_sw)
sw_cnt <= 18'd0;
else begin
if (sw_cnt == (divided_200Hz-1))
sw_cnt <= 18'd0;
else
sw_cnt <= sw_cnt + 18'd1;
end
end
always @(posedge clk) begin
if (reset_sw)
roll_node <= 1'b0;
else
if (sw_cnt == (divided_200Hz-1))
roll_node <= roll;
end
assign roll_sig = roll_node;
// 50Hz, 20ms
always @(posedge clk) begin
if (reset_sw) begin
roll_cnt <= 2'd0;
roll_ena <= 1'b0;
end else begin
if (sw_cnt==(divided_200Hz-1)) begin
if (roll_cnt==2'b11) begin
roll_cnt <= 2'd0;
roll_ena <= 1'b1;
end else begin
roll_cnt <= roll_cnt + 2'd1;
roll_ena <= 1'b0;
end
end else
roll_ena <= 1'b0;
end
end
endmodule
`default_nettype wire
// dice_top_tb.cpp
#include <iostream>
#include <verilated.h> // Defines common routines
#include "verilated_vcd_c.h"
#include "Vdice_top.h"
unsigned int main_time = 0; // Current simulation time
double sc_time_stamp () { // Called by $time in Verilog
return main_time;
}
int main(int argc, char** argv) {
Verilated::commandArgs(argc, argv); // Remember args
Vdice_top *top = new Vdice_top();
Verilated::traceEverOn(true);
VerilatedVcdC* tfp = new VerilatedVcdC;
top->trace (tfp, 99);
tfp->open ("simx.vcd");
top->reset_sw = 1; // Set some inputs
top->clk = 0;
top->roll = 0;
while (!Verilated::gotFinish()) {
if (main_time > 10)
top->reset_sw = 0; // リセットを解除する
if ((main_time % 5) == 0) // クロックを生成する
top->clk = !top->clk;
if (main_time > 20 && main_time < 980) // roll を1にする
top->roll = 1;
else
top->roll = 0;
top->eval(); // 評価
printf("Time %d : clk = %d spots = %d\n", main_time, top->clk, top->v__DOT__inst_dice_sm__DOT__spots_node);
tfp->dump(main_time);
if (main_time>1000)
break; // 終了
main_time++;
}
tfp->close();
top->final(); // シミュレーション終了
}
verilator --cc --trace -Wno-lint dice_top.v --exe dice_top_tb.cpp
cd obj_dir/
make -j -f Vdice_top.mk Vdice_top
./Vdice_top.exe
#include <iostream>
#include <verilated.h> // Defines common routines
#include "verilated_vcd_c.h"
#include "Vdice_state_machine.h"
unsigned int main_time = 0; // Current simulation time
double sc_time_stamp () { // Called by $time in Verilog
return main_time;
}
int main(int argc, char** argv) {
Verilated::commandArgs(argc, argv); // Remember args
Vdice_state_machine *top = new Vdice_state_machine();
Verilated::traceEverOn(true);
VerilatedVcdC* tfp = new VerilatedVcdC;
top->trace (tfp, 99);
tfp->open ("simx.vcd");
top->reset_sw = 1; // Set some inputs
top->clk = 0;
top->roll = 0;
top->roll_ena = 0;
while (!Verilated::gotFinish()) {
if (main_time > 10)
top->reset_sw = 0; // リセットを解除する
if ((main_time % 5) == 0) // クロックを生成する
top->clk = !top->clk;
if (main_time > 20) // roll を1にする
top->roll = 1;
if (!top->reset_sw) { // リセットが解除された後で
if ((main_time % 10) == 1) // クロックが立ち上がった1デルタ時間後
top->roll_ena = !top->roll_ena;
}
top->eval(); // 評価
printf("Time %d : clk = %d roll_ena = %d spots = %d current_state = %.2x\n", main_time, top->clk, top->roll_ena, top->spots, top->v__DOT__current_state);
tfp->dump(main_time);
if (main_time>200)
break; // 終了
main_time++;
}
tfp->close();
top->final(); // シミュレーション終了
}
verilator --cc --trace -Wno-lint dice_state_machine.v --exe dsm_test.cpp
verilator --cc -Wno-lint dice_state_machine.v --exe dsm_test.cpp
VL_MODULE(Vdice_state_machine) {
public:
// CELLS
// Public to allow access to /*verilator_public*/ items;
// otherwise the application code can consider these internals.
// PORTS
// The application code writes and reads these signals to
// propagate new values into/out from the Verilated model.
VL_IN8(clk,0,0);
VL_IN8(reset_sw,0,0);
VL_IN8(roll,0,0);
VL_IN8(roll_ena,0,0);
VL_OUT8(spots,2,0);
//char __VpadToAlign5[3];
// LOCAL SIGNALS
// Internals; generally not touched by application code
VL_SIG8(v__DOT__current_state,5,0);
VL_SIG8(v__DOT__spots_node,2,0);
//char __VpadToAlign14[2];
printf("Time %d : clk = %d roll_ena = %d spots = %d current_state = %.2x\n", main_time, top->clk, top->roll_ena, top->spots, top->v__DOT__current_state);
Time 0 : clk = 1 roll_ena = 0 spots = 1 current_state = 01
Time 1 : clk = 1 roll_ena = 0 spots = 1 current_state = 01
Time 2 : clk = 1 roll_ena = 0 spots = 1 current_state = 01
Time 3 : clk = 1 roll_ena = 0 spots = 1 current_state = 01
Time 4 : clk = 1 roll_ena = 0 spots = 1 current_state = 01
Time 5 : clk = 0 roll_ena = 0 spots = 1 current_state = 01
Time 6 : clk = 0 roll_ena = 0 spots = 1 current_state = 01
Time 7 : clk = 0 roll_ena = 0 spots = 1 current_state = 01
Time 8 : clk = 0 roll_ena = 0 spots = 1 current_state = 01
Time 9 : clk = 0 roll_ena = 0 spots = 1 current_state = 01
Time 10 : clk = 1 roll_ena = 0 spots = 1 current_state = 01
Time 11 : clk = 1 roll_ena = 1 spots = 1 current_state = 01
Time 12 : clk = 1 roll_ena = 1 spots = 1 current_state = 01
Time 13 : clk = 1 roll_ena = 1 spots = 1 current_state = 01
Time 14 : clk = 1 roll_ena = 1 spots = 1 current_state = 01
Time 15 : clk = 0 roll_ena = 1 spots = 1 current_state = 01
Time 16 : clk = 0 roll_ena = 1 spots = 1 current_state = 01
Time 17 : clk = 0 roll_ena = 1 spots = 1 current_state = 01
Time 18 : clk = 0 roll_ena = 1 spots = 1 current_state = 01
Time 19 : clk = 0 roll_ena = 1 spots = 1 current_state = 01
Time 20 : clk = 1 roll_ena = 1 spots = 1 current_state = 01
Time 21 : clk = 1 roll_ena = 0 spots = 1 current_state = 01
Time 22 : clk = 1 roll_ena = 0 spots = 1 current_state = 01
Time 23 : clk = 1 roll_ena = 0 spots = 1 current_state = 01
Time 24 : clk = 1 roll_ena = 0 spots = 1 current_state = 01
Time 25 : clk = 0 roll_ena = 0 spots = 1 current_state = 01
Time 26 : clk = 0 roll_ena = 0 spots = 1 current_state = 01
Time 27 : clk = 0 roll_ena = 0 spots = 1 current_state = 01
Time 28 : clk = 0 roll_ena = 0 spots = 1 current_state = 01
Time 29 : clk = 0 roll_ena = 0 spots = 1 current_state = 01
Time 30 : clk = 1 roll_ena = 0 spots = 1 current_state = 01
Time 31 : clk = 1 roll_ena = 1 spots = 1 current_state = 01
Time 32 : clk = 1 roll_ena = 1 spots = 1 current_state = 01
Time 33 : clk = 1 roll_ena = 1 spots = 1 current_state = 01
Time 34 : clk = 1 roll_ena = 1 spots = 1 current_state = 01
Time 35 : clk = 0 roll_ena = 1 spots = 1 current_state = 01
Time 36 : clk = 0 roll_ena = 1 spots = 1 current_state = 01
Time 37 : clk = 0 roll_ena = 1 spots = 1 current_state = 01
Time 38 : clk = 0 roll_ena = 1 spots = 1 current_state = 01
Time 39 : clk = 0 roll_ena = 1 spots = 1 current_state = 01
Time 40 : clk = 1 roll_ena = 1 spots = 1 current_state = 02
Time 41 : clk = 1 roll_ena = 0 spots = 1 current_state = 02
Time 42 : clk = 1 roll_ena = 0 spots = 1 current_state = 02
Time 43 : clk = 1 roll_ena = 0 spots = 1 current_state = 02
Time 44 : clk = 1 roll_ena = 0 spots = 1 current_state = 02
Time 45 : clk = 0 roll_ena = 0 spots = 1 current_state = 02
Time 46 : clk = 0 roll_ena = 0 spots = 1 current_state = 02
Time 47 : clk = 0 roll_ena = 0 spots = 1 current_state = 02
Time 48 : clk = 0 roll_ena = 0 spots = 1 current_state = 02
Time 49 : clk = 0 roll_ena = 0 spots = 1 current_state = 02
Time 50 : clk = 1 roll_ena = 0 spots = 2 current_state = 02
Time 51 : clk = 1 roll_ena = 1 spots = 2 current_state = 02
Time 52 : clk = 1 roll_ena = 1 spots = 2 current_state = 02
Time 53 : clk = 1 roll_ena = 1 spots = 2 current_state = 02
Time 54 : clk = 1 roll_ena = 1 spots = 2 current_state = 02
Time 55 : clk = 0 roll_ena = 1 spots = 2 current_state = 02
Time 56 : clk = 0 roll_ena = 1 spots = 2 current_state = 02
Time 57 : clk = 0 roll_ena = 1 spots = 2 current_state = 02
Time 58 : clk = 0 roll_ena = 1 spots = 2 current_state = 02
Time 59 : clk = 0 roll_ena = 1 spots = 2 current_state = 02
Time 60 : clk = 1 roll_ena = 1 spots = 2 current_state = 04
Time 61 : clk = 1 roll_ena = 0 spots = 2 current_state = 04
Time 62 : clk = 1 roll_ena = 0 spots = 2 current_state = 04
Time 63 : clk = 1 roll_ena = 0 spots = 2 current_state = 04
Time 64 : clk = 1 roll_ena = 0 spots = 2 current_state = 04
Time 65 : clk = 0 roll_ena = 0 spots = 2 current_state = 04
Time 66 : clk = 0 roll_ena = 0 spots = 2 current_state = 04
Time 67 : clk = 0 roll_ena = 0 spots = 2 current_state = 04
Time 68 : clk = 0 roll_ena = 0 spots = 2 current_state = 04
Time 69 : clk = 0 roll_ena = 0 spots = 2 current_state = 04
Time 70 : clk = 1 roll_ena = 0 spots = 3 current_state = 04
Time 71 : clk = 1 roll_ena = 1 spots = 3 current_state = 04
Time 72 : clk = 1 roll_ena = 1 spots = 3 current_state = 04
Time 73 : clk = 1 roll_ena = 1 spots = 3 current_state = 04
Time 74 : clk = 1 roll_ena = 1 spots = 3 current_state = 04
Time 75 : clk = 0 roll_ena = 1 spots = 3 current_state = 04
Time 76 : clk = 0 roll_ena = 1 spots = 3 current_state = 04
Time 77 : clk = 0 roll_ena = 1 spots = 3 current_state = 04
Time 78 : clk = 0 roll_ena = 1 spots = 3 current_state = 04
Time 79 : clk = 0 roll_ena = 1 spots = 3 current_state = 04
Time 80 : clk = 1 roll_ena = 1 spots = 3 current_state = 08
Time 81 : clk = 1 roll_ena = 0 spots = 3 current_state = 08
Time 82 : clk = 1 roll_ena = 0 spots = 3 current_state = 08
Time 83 : clk = 1 roll_ena = 0 spots = 3 current_state = 08
Time 84 : clk = 1 roll_ena = 0 spots = 3 current_state = 08
Time 85 : clk = 0 roll_ena = 0 spots = 3 current_state = 08
Time 86 : clk = 0 roll_ena = 0 spots = 3 current_state = 08
Time 87 : clk = 0 roll_ena = 0 spots = 3 current_state = 08
Time 88 : clk = 0 roll_ena = 0 spots = 3 current_state = 08
Time 89 : clk = 0 roll_ena = 0 spots = 3 current_state = 08
Time 90 : clk = 1 roll_ena = 0 spots = 4 current_state = 08
Time 91 : clk = 1 roll_ena = 1 spots = 4 current_state = 08
Time 92 : clk = 1 roll_ena = 1 spots = 4 current_state = 08
Time 93 : clk = 1 roll_ena = 1 spots = 4 current_state = 08
Time 94 : clk = 1 roll_ena = 1 spots = 4 current_state = 08
Time 95 : clk = 0 roll_ena = 1 spots = 4 current_state = 08
Time 96 : clk = 0 roll_ena = 1 spots = 4 current_state = 08
Time 97 : clk = 0 roll_ena = 1 spots = 4 current_state = 08
Time 98 : clk = 0 roll_ena = 1 spots = 4 current_state = 08
Time 99 : clk = 0 roll_ena = 1 spots = 4 current_state = 08
Time 100 : clk = 1 roll_ena = 1 spots = 4 current_state = 10
Time 101 : clk = 1 roll_ena = 0 spots = 4 current_state = 10
Time 102 : clk = 1 roll_ena = 0 spots = 4 current_state = 10
Time 103 : clk = 1 roll_ena = 0 spots = 4 current_state = 10
Time 104 : clk = 1 roll_ena = 0 spots = 4 current_state = 10
Time 105 : clk = 0 roll_ena = 0 spots = 4 current_state = 10
Time 106 : clk = 0 roll_ena = 0 spots = 4 current_state = 10
Time 107 : clk = 0 roll_ena = 0 spots = 4 current_state = 10
Time 108 : clk = 0 roll_ena = 0 spots = 4 current_state = 10
Time 109 : clk = 0 roll_ena = 0 spots = 4 current_state = 10
Time 110 : clk = 1 roll_ena = 0 spots = 5 current_state = 10
Time 111 : clk = 1 roll_ena = 1 spots = 5 current_state = 10
Time 112 : clk = 1 roll_ena = 1 spots = 5 current_state = 10
Time 113 : clk = 1 roll_ena = 1 spots = 5 current_state = 10
Time 114 : clk = 1 roll_ena = 1 spots = 5 current_state = 10
Time 115 : clk = 0 roll_ena = 1 spots = 5 current_state = 10
Time 116 : clk = 0 roll_ena = 1 spots = 5 current_state = 10
Time 117 : clk = 0 roll_ena = 1 spots = 5 current_state = 10
Time 118 : clk = 0 roll_ena = 1 spots = 5 current_state = 10
Time 119 : clk = 0 roll_ena = 1 spots = 5 current_state = 10
Time 120 : clk = 1 roll_ena = 1 spots = 5 current_state = 20
Time 121 : clk = 1 roll_ena = 0 spots = 5 current_state = 20
Time 122 : clk = 1 roll_ena = 0 spots = 5 current_state = 20
Time 123 : clk = 1 roll_ena = 0 spots = 5 current_state = 20
Time 124 : clk = 1 roll_ena = 0 spots = 5 current_state = 20
Time 125 : clk = 0 roll_ena = 0 spots = 5 current_state = 20
Time 126 : clk = 0 roll_ena = 0 spots = 5 current_state = 20
Time 127 : clk = 0 roll_ena = 0 spots = 5 current_state = 20
Time 128 : clk = 0 roll_ena = 0 spots = 5 current_state = 20
Time 129 : clk = 0 roll_ena = 0 spots = 5 current_state = 20
Time 130 : clk = 1 roll_ena = 0 spots = 6 current_state = 20
Time 131 : clk = 1 roll_ena = 1 spots = 6 current_state = 20
Time 132 : clk = 1 roll_ena = 1 spots = 6 current_state = 20
Time 133 : clk = 1 roll_ena = 1 spots = 6 current_state = 20
Time 134 : clk = 1 roll_ena = 1 spots = 6 current_state = 20
Time 135 : clk = 0 roll_ena = 1 spots = 6 current_state = 20
Time 136 : clk = 0 roll_ena = 1 spots = 6 current_state = 20
Time 137 : clk = 0 roll_ena = 1 spots = 6 current_state = 20
Time 138 : clk = 0 roll_ena = 1 spots = 6 current_state = 20
Time 139 : clk = 0 roll_ena = 1 spots = 6 current_state = 20
Time 140 : clk = 1 roll_ena = 1 spots = 6 current_state = 01
Time 141 : clk = 1 roll_ena = 0 spots = 6 current_state = 01
Time 142 : clk = 1 roll_ena = 0 spots = 6 current_state = 01
Time 143 : clk = 1 roll_ena = 0 spots = 6 current_state = 01
Time 144 : clk = 1 roll_ena = 0 spots = 6 current_state = 01
Time 145 : clk = 0 roll_ena = 0 spots = 6 current_state = 01
Time 146 : clk = 0 roll_ena = 0 spots = 6 current_state = 01
Time 147 : clk = 0 roll_ena = 0 spots = 6 current_state = 01
Time 148 : clk = 0 roll_ena = 0 spots = 6 current_state = 01
Time 149 : clk = 0 roll_ena = 0 spots = 6 current_state = 01
Time 150 : clk = 1 roll_ena = 0 spots = 1 current_state = 01
Time 151 : clk = 1 roll_ena = 1 spots = 1 current_state = 01
Time 152 : clk = 1 roll_ena = 1 spots = 1 current_state = 01
Time 153 : clk = 1 roll_ena = 1 spots = 1 current_state = 01
Time 154 : clk = 1 roll_ena = 1 spots = 1 current_state = 01
Time 155 : clk = 0 roll_ena = 1 spots = 1 current_state = 01
Time 156 : clk = 0 roll_ena = 1 spots = 1 current_state = 01
Time 157 : clk = 0 roll_ena = 1 spots = 1 current_state = 01
Time 158 : clk = 0 roll_ena = 1 spots = 1 current_state = 01
Time 159 : clk = 0 roll_ena = 1 spots = 1 current_state = 01
Time 160 : clk = 1 roll_ena = 1 spots = 1 current_state = 02
Time 161 : clk = 1 roll_ena = 0 spots = 1 current_state = 02
Time 162 : clk = 1 roll_ena = 0 spots = 1 current_state = 02
Time 163 : clk = 1 roll_ena = 0 spots = 1 current_state = 02
Time 164 : clk = 1 roll_ena = 0 spots = 1 current_state = 02
Time 165 : clk = 0 roll_ena = 0 spots = 1 current_state = 02
Time 166 : clk = 0 roll_ena = 0 spots = 1 current_state = 02
Time 167 : clk = 0 roll_ena = 0 spots = 1 current_state = 02
Time 168 : clk = 0 roll_ena = 0 spots = 1 current_state = 02
Time 169 : clk = 0 roll_ena = 0 spots = 1 current_state = 02
Time 170 : clk = 1 roll_ena = 0 spots = 2 current_state = 02
Time 171 : clk = 1 roll_ena = 1 spots = 2 current_state = 02
Time 172 : clk = 1 roll_ena = 1 spots = 2 current_state = 02
Time 173 : clk = 1 roll_ena = 1 spots = 2 current_state = 02
Time 174 : clk = 1 roll_ena = 1 spots = 2 current_state = 02
Time 175 : clk = 0 roll_ena = 1 spots = 2 current_state = 02
Time 176 : clk = 0 roll_ena = 1 spots = 2 current_state = 02
Time 177 : clk = 0 roll_ena = 1 spots = 2 current_state = 02
Time 178 : clk = 0 roll_ena = 1 spots = 2 current_state = 02
Time 179 : clk = 0 roll_ena = 1 spots = 2 current_state = 02
Time 180 : clk = 1 roll_ena = 1 spots = 2 current_state = 04
Time 181 : clk = 1 roll_ena = 0 spots = 2 current_state = 04
Time 182 : clk = 1 roll_ena = 0 spots = 2 current_state = 04
Time 183 : clk = 1 roll_ena = 0 spots = 2 current_state = 04
Time 184 : clk = 1 roll_ena = 0 spots = 2 current_state = 04
Time 185 : clk = 0 roll_ena = 0 spots = 2 current_state = 04
Time 186 : clk = 0 roll_ena = 0 spots = 2 current_state = 04
Time 187 : clk = 0 roll_ena = 0 spots = 2 current_state = 04
Time 188 : clk = 0 roll_ena = 0 spots = 2 current_state = 04
Time 189 : clk = 0 roll_ena = 0 spots = 2 current_state = 04
Time 190 : clk = 1 roll_ena = 0 spots = 3 current_state = 04
Time 191 : clk = 1 roll_ena = 1 spots = 3 current_state = 04
Time 192 : clk = 1 roll_ena = 1 spots = 3 current_state = 04
Time 193 : clk = 1 roll_ena = 1 spots = 3 current_state = 04
Time 194 : clk = 1 roll_ena = 1 spots = 3 current_state = 04
Time 195 : clk = 0 roll_ena = 1 spots = 3 current_state = 04
Time 196 : clk = 0 roll_ena = 1 spots = 3 current_state = 04
Time 197 : clk = 0 roll_ena = 1 spots = 3 current_state = 04
Time 198 : clk = 0 roll_ena = 1 spots = 3 current_state = 04
Time 199 : clk = 0 roll_ena = 1 spots = 3 current_state = 04
Time 200 : clk = 1 roll_ena = 1 spots = 3 current_state = 08
Time 201 : clk = 1 roll_ena = 0 spots = 3 current_state = 08
`default_nettype none
`timescale 1ns / 1ps
// 1から6までのサイコロの目を表すステートマシン,Direct Verilog2001
module dice_state_machine(
input wire reset_sw,
input wire clk,
input wire roll,
input wire roll_ena,
output wire [2:0] spots
);
parameter st_one = 6'b000001,
st_two = 6'b000010,
st_three = 6'b000100,
st_four = 6'b001000,
st_five = 6'b010000,
st_six = 6'b100000;
reg [5:0] current_state;
reg [2:0] spots_node;
always @(posedge clk) begin
if (reset_sw) begin
spots_node <= 3'd1;
current_state <= st_one;
end else begin
case (current_state)
st_one : begin
spots_node <= 3'd1;
if (roll && roll_ena)
current_state <= st_two;
end
st_two : begin
spots_node <= 3'd2;
if (roll && roll_ena)
current_state <= st_three;
end
st_three : begin
spots_node <= 3'd3;
if (roll && roll_ena)
current_state <= st_four;
end
st_four : begin
spots_node <= 3'd4;
if (roll && roll_ena)
current_state <= st_five;
end
st_five : begin
spots_node <= 3'd5;
if (roll && roll_ena)
current_state <= st_six;
end
st_six : begin
spots_node <= 3'd6;
if (roll && roll_ena)
current_state <= st_one;
end
endcase
end
end
assign spots = spots_node;
// synthesis translate_off
reg [20*8:1] DICE_STATE;
always @(current_state) begin
case (current_state)
st_one : DICE_STATE = "ST_ONE";
st_two : DICE_STATE = "ST_TWO";
st_three: DICE_STATE = "ST_THREE";
st_four : DICE_STATE = "ST_FOUR";
st_five : DICE_STATE = "ST_FIVE";
st_six : DICE_STATE = "ST_SIX";
default : DICE_STATE = "ST_ONE";
endcase
end
// synthesis translate_on
endmodule
`default_nettype wire
#include <iostream>
#include <verilated.h> // Defines common routines
#include "Vdice_state_machine.h"
unsigned int main_time = 0; // Current simulation time
double sc_time_stamp () { // Called by $time in Verilog
return main_time;
}
int main(int argc, char** argv) {
Verilated::commandArgs(argc, argv); // Remember args
Vdice_state_machine *top = new Vdice_state_machine();
top->reset_sw = 1; // Set some inputs
top->clk = 0;
top->roll = 0;
top->roll_ena = 0;
while (!Verilated::gotFinish()) {
if (main_time > 10)
top->reset_sw = 0; // リセットを解除する
if ((main_time % 5) == 0) // クロックを生成する
top->clk = !top->clk;
if (main_time > 20) // roll を1にする
top->roll = 1;
if (!top->reset_sw) { // リセットが解除された後で
if ((main_time % 10) == 1) // クロックが立ち上がった1デルタ時間後
top->roll_ena = !top->roll_ena;
}
top->eval(); // 評価
printf("Time %d : clk = %d roll_ena = %d spots = %d\n", main_time, top->clk, top->roll_ena, top->spots);
if (main_time>200)
break; // 終了
main_time++;
}
top->final(); // シミュレーション終了
}
verilator --cc -Wno-lint dice_state_machine.v --exe dsm_test.cpp
cd obj_dir/
make -j -f Vdice_state_machine.mk Vdice_state_machine
./Vdice_state_machine.exe
Time 0 : clk = 1 roll_ena = 0 spots = 1
Time 1 : clk = 1 roll_ena = 0 spots = 1
Time 2 : clk = 1 roll_ena = 0 spots = 1
Time 3 : clk = 1 roll_ena = 0 spots = 1
Time 4 : clk = 1 roll_ena = 0 spots = 1
Time 5 : clk = 0 roll_ena = 0 spots = 1
Time 6 : clk = 0 roll_ena = 0 spots = 1
Time 7 : clk = 0 roll_ena = 0 spots = 1
Time 8 : clk = 0 roll_ena = 0 spots = 1
Time 9 : clk = 0 roll_ena = 0 spots = 1
Time 10 : clk = 1 roll_ena = 0 spots = 1
Time 11 : clk = 1 roll_ena = 1 spots = 1
Time 12 : clk = 1 roll_ena = 1 spots = 1
Time 13 : clk = 1 roll_ena = 1 spots = 1
Time 14 : clk = 1 roll_ena = 1 spots = 1
Time 15 : clk = 0 roll_ena = 1 spots = 1
Time 16 : clk = 0 roll_ena = 1 spots = 1
Time 17 : clk = 0 roll_ena = 1 spots = 1
Time 18 : clk = 0 roll_ena = 1 spots = 1
Time 19 : clk = 0 roll_ena = 1 spots = 1
Time 20 : clk = 1 roll_ena = 1 spots = 1
Time 21 : clk = 1 roll_ena = 0 spots = 1
Time 22 : clk = 1 roll_ena = 0 spots = 1
Time 23 : clk = 1 roll_ena = 0 spots = 1
Time 24 : clk = 1 roll_ena = 0 spots = 1
Time 25 : clk = 0 roll_ena = 0 spots = 1
Time 26 : clk = 0 roll_ena = 0 spots = 1
Time 27 : clk = 0 roll_ena = 0 spots = 1
Time 28 : clk = 0 roll_ena = 0 spots = 1
Time 29 : clk = 0 roll_ena = 0 spots = 1
Time 30 : clk = 1 roll_ena = 0 spots = 1
Time 31 : clk = 1 roll_ena = 1 spots = 1
Time 32 : clk = 1 roll_ena = 1 spots = 1
Time 33 : clk = 1 roll_ena = 1 spots = 1
Time 34 : clk = 1 roll_ena = 1 spots = 1
Time 35 : clk = 0 roll_ena = 1 spots = 1
Time 36 : clk = 0 roll_ena = 1 spots = 1
Time 37 : clk = 0 roll_ena = 1 spots = 1
Time 38 : clk = 0 roll_ena = 1 spots = 1
Time 39 : clk = 0 roll_ena = 1 spots = 1
Time 40 : clk = 1 roll_ena = 1 spots = 1
Time 41 : clk = 1 roll_ena = 0 spots = 1
Time 42 : clk = 1 roll_ena = 0 spots = 1
Time 43 : clk = 1 roll_ena = 0 spots = 1
Time 44 : clk = 1 roll_ena = 0 spots = 1
Time 45 : clk = 0 roll_ena = 0 spots = 1
Time 46 : clk = 0 roll_ena = 0 spots = 1
Time 47 : clk = 0 roll_ena = 0 spots = 1
Time 48 : clk = 0 roll_ena = 0 spots = 1
Time 49 : clk = 0 roll_ena = 0 spots = 1
Time 50 : clk = 1 roll_ena = 0 spots = 2
Time 51 : clk = 1 roll_ena = 1 spots = 2
Time 52 : clk = 1 roll_ena = 1 spots = 2
Time 53 : clk = 1 roll_ena = 1 spots = 2
Time 54 : clk = 1 roll_ena = 1 spots = 2
Time 55 : clk = 0 roll_ena = 1 spots = 2
Time 56 : clk = 0 roll_ena = 1 spots = 2
Time 57 : clk = 0 roll_ena = 1 spots = 2
Time 58 : clk = 0 roll_ena = 1 spots = 2
Time 59 : clk = 0 roll_ena = 1 spots = 2
Time 60 : clk = 1 roll_ena = 1 spots = 2
Time 61 : clk = 1 roll_ena = 0 spots = 2
Time 62 : clk = 1 roll_ena = 0 spots = 2
Time 63 : clk = 1 roll_ena = 0 spots = 2
Time 64 : clk = 1 roll_ena = 0 spots = 2
Time 65 : clk = 0 roll_ena = 0 spots = 2
Time 66 : clk = 0 roll_ena = 0 spots = 2
Time 67 : clk = 0 roll_ena = 0 spots = 2
Time 68 : clk = 0 roll_ena = 0 spots = 2
Time 69 : clk = 0 roll_ena = 0 spots = 2
Time 70 : clk = 1 roll_ena = 0 spots = 3
Time 71 : clk = 1 roll_ena = 1 spots = 3
Time 72 : clk = 1 roll_ena = 1 spots = 3
Time 73 : clk = 1 roll_ena = 1 spots = 3
Time 74 : clk = 1 roll_ena = 1 spots = 3
Time 75 : clk = 0 roll_ena = 1 spots = 3
Time 76 : clk = 0 roll_ena = 1 spots = 3
Time 77 : clk = 0 roll_ena = 1 spots = 3
Time 78 : clk = 0 roll_ena = 1 spots = 3
Time 79 : clk = 0 roll_ena = 1 spots = 3
Time 80 : clk = 1 roll_ena = 1 spots = 3
Time 81 : clk = 1 roll_ena = 0 spots = 3
Time 82 : clk = 1 roll_ena = 0 spots = 3
Time 83 : clk = 1 roll_ena = 0 spots = 3
Time 84 : clk = 1 roll_ena = 0 spots = 3
Time 85 : clk = 0 roll_ena = 0 spots = 3
Time 86 : clk = 0 roll_ena = 0 spots = 3
Time 87 : clk = 0 roll_ena = 0 spots = 3
Time 88 : clk = 0 roll_ena = 0 spots = 3
Time 89 : clk = 0 roll_ena = 0 spots = 3
Time 90 : clk = 1 roll_ena = 0 spots = 4
Time 91 : clk = 1 roll_ena = 1 spots = 4
Time 92 : clk = 1 roll_ena = 1 spots = 4
Time 93 : clk = 1 roll_ena = 1 spots = 4
Time 94 : clk = 1 roll_ena = 1 spots = 4
Time 95 : clk = 0 roll_ena = 1 spots = 4
Time 96 : clk = 0 roll_ena = 1 spots = 4
Time 97 : clk = 0 roll_ena = 1 spots = 4
Time 98 : clk = 0 roll_ena = 1 spots = 4
Time 99 : clk = 0 roll_ena = 1 spots = 4
Time 100 : clk = 1 roll_ena = 1 spots = 4
Time 101 : clk = 1 roll_ena = 0 spots = 4
Time 102 : clk = 1 roll_ena = 0 spots = 4
Time 103 : clk = 1 roll_ena = 0 spots = 4
Time 104 : clk = 1 roll_ena = 0 spots = 4
Time 105 : clk = 0 roll_ena = 0 spots = 4
Time 106 : clk = 0 roll_ena = 0 spots = 4
Time 107 : clk = 0 roll_ena = 0 spots = 4
Time 108 : clk = 0 roll_ena = 0 spots = 4
Time 109 : clk = 0 roll_ena = 0 spots = 4
Time 110 : clk = 1 roll_ena = 0 spots = 5
Time 111 : clk = 1 roll_ena = 1 spots = 5
Time 112 : clk = 1 roll_ena = 1 spots = 5
Time 113 : clk = 1 roll_ena = 1 spots = 5
Time 114 : clk = 1 roll_ena = 1 spots = 5
Time 115 : clk = 0 roll_ena = 1 spots = 5
Time 116 : clk = 0 roll_ena = 1 spots = 5
Time 117 : clk = 0 roll_ena = 1 spots = 5
Time 118 : clk = 0 roll_ena = 1 spots = 5
Time 119 : clk = 0 roll_ena = 1 spots = 5
Time 120 : clk = 1 roll_ena = 1 spots = 5
Time 121 : clk = 1 roll_ena = 0 spots = 5
Time 122 : clk = 1 roll_ena = 0 spots = 5
Time 123 : clk = 1 roll_ena = 0 spots = 5
Time 124 : clk = 1 roll_ena = 0 spots = 5
Time 125 : clk = 0 roll_ena = 0 spots = 5
Time 126 : clk = 0 roll_ena = 0 spots = 5
Time 127 : clk = 0 roll_ena = 0 spots = 5
Time 128 : clk = 0 roll_ena = 0 spots = 5
Time 129 : clk = 0 roll_ena = 0 spots = 5
Time 130 : clk = 1 roll_ena = 0 spots = 6
Time 131 : clk = 1 roll_ena = 1 spots = 6
Time 132 : clk = 1 roll_ena = 1 spots = 6
Time 133 : clk = 1 roll_ena = 1 spots = 6
Time 134 : clk = 1 roll_ena = 1 spots = 6
Time 135 : clk = 0 roll_ena = 1 spots = 6
Time 136 : clk = 0 roll_ena = 1 spots = 6
Time 137 : clk = 0 roll_ena = 1 spots = 6
Time 138 : clk = 0 roll_ena = 1 spots = 6
Time 139 : clk = 0 roll_ena = 1 spots = 6
Time 140 : clk = 1 roll_ena = 1 spots = 6
Time 141 : clk = 1 roll_ena = 0 spots = 6
Time 142 : clk = 1 roll_ena = 0 spots = 6
Time 143 : clk = 1 roll_ena = 0 spots = 6
Time 144 : clk = 1 roll_ena = 0 spots = 6
Time 145 : clk = 0 roll_ena = 0 spots = 6
Time 146 : clk = 0 roll_ena = 0 spots = 6
Time 147 : clk = 0 roll_ena = 0 spots = 6
Time 148 : clk = 0 roll_ena = 0 spots = 6
Time 149 : clk = 0 roll_ena = 0 spots = 6
Time 150 : clk = 1 roll_ena = 0 spots = 1
Time 151 : clk = 1 roll_ena = 1 spots = 1
Time 152 : clk = 1 roll_ena = 1 spots = 1
Time 153 : clk = 1 roll_ena = 1 spots = 1
Time 154 : clk = 1 roll_ena = 1 spots = 1
Time 155 : clk = 0 roll_ena = 1 spots = 1
Time 156 : clk = 0 roll_ena = 1 spots = 1
Time 157 : clk = 0 roll_ena = 1 spots = 1
Time 158 : clk = 0 roll_ena = 1 spots = 1
Time 159 : clk = 0 roll_ena = 1 spots = 1
Time 160 : clk = 1 roll_ena = 1 spots = 1
Time 161 : clk = 1 roll_ena = 0 spots = 1
Time 162 : clk = 1 roll_ena = 0 spots = 1
Time 163 : clk = 1 roll_ena = 0 spots = 1
Time 164 : clk = 1 roll_ena = 0 spots = 1
Time 165 : clk = 0 roll_ena = 0 spots = 1
Time 166 : clk = 0 roll_ena = 0 spots = 1
Time 167 : clk = 0 roll_ena = 0 spots = 1
Time 168 : clk = 0 roll_ena = 0 spots = 1
Time 169 : clk = 0 roll_ena = 0 spots = 1
Time 170 : clk = 1 roll_ena = 0 spots = 2
Time 171 : clk = 1 roll_ena = 1 spots = 2
Time 172 : clk = 1 roll_ena = 1 spots = 2
Time 173 : clk = 1 roll_ena = 1 spots = 2
Time 174 : clk = 1 roll_ena = 1 spots = 2
Time 175 : clk = 0 roll_ena = 1 spots = 2
Time 176 : clk = 0 roll_ena = 1 spots = 2
Time 177 : clk = 0 roll_ena = 1 spots = 2
Time 178 : clk = 0 roll_ena = 1 spots = 2
Time 179 : clk = 0 roll_ena = 1 spots = 2
Time 180 : clk = 1 roll_ena = 1 spots = 2
Time 181 : clk = 1 roll_ena = 0 spots = 2
Time 182 : clk = 1 roll_ena = 0 spots = 2
Time 183 : clk = 1 roll_ena = 0 spots = 2
Time 184 : clk = 1 roll_ena = 0 spots = 2
Time 185 : clk = 0 roll_ena = 0 spots = 2
Time 186 : clk = 0 roll_ena = 0 spots = 2
Time 187 : clk = 0 roll_ena = 0 spots = 2
Time 188 : clk = 0 roll_ena = 0 spots = 2
Time 189 : clk = 0 roll_ena = 0 spots = 2
Time 190 : clk = 1 roll_ena = 0 spots = 3
Time 191 : clk = 1 roll_ena = 1 spots = 3
Time 192 : clk = 1 roll_ena = 1 spots = 3
Time 193 : clk = 1 roll_ena = 1 spots = 3
Time 194 : clk = 1 roll_ena = 1 spots = 3
Time 195 : clk = 0 roll_ena = 1 spots = 3
Time 196 : clk = 0 roll_ena = 1 spots = 3
Time 197 : clk = 0 roll_ena = 1 spots = 3
Time 198 : clk = 0 roll_ena = 1 spots = 3
Time 199 : clk = 0 roll_ena = 1 spots = 3
Time 200 : clk = 1 roll_ena = 1 spots = 3
Time 201 : clk = 1 roll_ena = 0 spots = 3
app_af_cmd[2:0]:(入力) 3ビットのコマンド。000がWriteコマンド、001がReadコマンド。それ以外は不正値。
app_af_addr[30:0]:(入力) 31ビットのアドレス。今回は25ビット幅、26ビット目はChip Select。アドレスの割当はBank + Row + Column address。
app_af_wren:(入力) User Address FIFOへのWrite enable。これが1の時は、app_af_cmdとapp_af_addrが有効。
aff_wdf_data[2*DQ_WIDTH-1:0]:(入力) User Input Data。DDR2 SDRAMのデータ幅の2倍のデータ幅がある。クロックの立ち上がりのデータが下位、クロックの立ち下がりのデータが上位。128ビット幅。
app_wdf_mask_data[2*DM_WIDTH–1:0]:(入力) User Data Mask。DDR2 SDRAMのマスク幅の2倍の幅がある。 クロックの立ち上がりのマスクが下位、クロックの立ち下がりのマスクが上位。16ビット幅。
app_wdf_wren:(入力) User Write FIFOのWrite enable。これが1の時は、aff_wdf_dataとapp_wdf_mask_dataが有効。
app_af_afull:(出力) Address FIFOのAlmost Full。残り12以下の時に1になる。
app_wdf_afull:(出力) User Write FIFOのAlmost Full。残り12以下の時に1になる。
rd_data_valid:(出力) rd_data_fifo_outのデータが有効であることを示す。
rd_data_fifo_out[2*DQ_WIDTH–1:0]:(出力) メモリからReadしたデータ。128ビット幅。
phy_init_done:(出力) DDR2 SDRAMコントローラの初期化とキャリブレーションが終了した。
clk0_tb:(出力) ユーザー回路へのclk0出力
268252100.0 ps INFO: Precharge All
268372100.0 ps INFO: Load Mode 2
268372100.0 ps INFO: Load Mode 2 High Temperature Self Refresh rate = 1X (0C-85C)
268492100.0 ps INFO: Load Mode 3
268612100.0 ps INFO: Load Mode 1
268612100.0 ps INFO: Load Mode 1 DLL Enable = Enabled
268612100.0 ps INFO: Load Mode 1 Output Drive Strength = Full
268612100.0 ps INFO: Load Mode 1 ODT Rtt = Disabled
268612100.0 ps INFO: Load Mode 1 Additive Latency = 0
268612100.0 ps INFO: Load Mode 1 OCD Program = OCD Exit
268612100.0 ps INFO: Load Mode 1 DQS_N Enable = Enabled
268612100.0 ps INFO: Load Mode 1 RDQS Enable = Disabled
268612100.0 ps INFO: Load Mode 1 Output Enable = Enabled
268732100.0 ps INFO: Load Mode 0
268732100.0 ps INFO: Load Mode 0 Burst Length = 4
268732100.0 ps INFO: Load Mode 0 Burst Order = Sequential
268732100.0 ps INFO: Load Mode 0 CAS Latency = 3
268732100.0 ps INFO: Load Mode 0 Test Mode = Normal
268732100.0 ps INFO: Load Mode 0 DLL Reset = Reset DLL
268732100.0 ps INFO: Load Mode 0 Write Recovery = 3
268732100.0 ps INFO: Load Mode 0 Power Down Mode = Fast Exit
268852100.0 ps INFO: Precharge All
268972100.0 ps INFO: Refresh
269092100.0 ps INFO: Refresh
269212100.0 ps INFO: Load Mode 0
269212100.0 ps INFO: Load Mode 0 Burst Length = 4
269212100.0 ps INFO: Load Mode 0 Burst Order = Sequential
269212100.0 ps INFO: Load Mode 0 CAS Latency = 3
269212100.0 ps INFO: Load Mode 0 Test Mode = Normal
269212100.0 ps INFO: Load Mode 0 DLL Reset = Normal
269212100.0 ps INFO: Load Mode 0 Write Recovery = 3
269212100.0 ps INFO: Load Mode 0 Power Down Mode = Fast Exit
269332100.0 ps INFO: Load Mode 1
269332100.0 ps INFO: Load Mode 1 DLL Enable = Enabled
269332100.0 ps INFO: Load Mode 1 Output Drive Strength = Full
269332100.0 ps INFO: Load Mode 1 ODT Rtt = Disabled
269332100.0 ps INFO: Load Mode 1 Additive Latency = 0
269332100.0 ps INFO: Load Mode 1 OCD Program = OCD Default
269332100.0 ps INFO: Load Mode 1 DQS_N Enable = Enabled
269332100.0 ps INFO: Load Mode 1 RDQS Enable = Disabled
269332100.0 ps INFO: Load Mode 1 Output Enable = Enabled
269452100.0 ps INFO: Load Mode 1
269452100.0 ps INFO: Load Mode 1 DLL Enable = Enabled
269452100.0 ps INFO: Load Mode 1 Output Drive Strength = Full
269452100.0 ps INFO: Load Mode 1 ODT Rtt = Disabled
269452100.0 ps INFO: Load Mode 1 Additive Latency = 0
269452100.0 ps INFO: Load Mode 1 OCD Program = OCD Exit
269452100.0 ps INFO: Load Mode 1 DQS_N Enable = Enabled
269452100.0 ps INFO: Load Mode 1 RDQS Enable = Disabled
269452100.0 ps INFO: Load Mode 1 Output Enable = Enabled
269452100.0 ps INFO: Initialization Sequence is complete
clk0:位相0度のクロック
clk90:位相90度のクロック
user_command_register:Write Request(100) やRead Request(110)、NOP(000) などのコマンド。Initialize memory(010)。(clk0の立ち下がりに同期)
user_cmd_ack:MIGからコマンドをうけとれるという返事。リフレッシュなどの用事があってコマンドを受け取れない場合はアサートされない。(clk0の立ち下がりに同期)
user_input_address:アドレス入力。使いにくいことにROW+COLUMN+BANKの順番になっているので、まともに使用するためには、COLUMNとBANKのアドレスを入れ替える必要がありそう。(clk0の立ち下がりに同期)
burst_done:バーストの終了時に4バーストモードは2クロック間、8バーストモードは4クロック間アサートする。(clk0の立ち下がりに同期)
user_input_data:clk90に同期してデータを出力する(Writeのみ)。(clk90の立ち上がりに同期)
user_data_valid:user_output_dataが有効。(Readのみ)(clk90の立ち上がりに同期)
user_output_data:Readしたデータ。(Readのみ)(clk90の立ち上がりに同期)
1.clk0の立ち下がりに同期して、ユーザー回路はWriteコマンドを発行し始める。
2.最低1クロック後にMIGは、clk0の立ち下がりに同期してuser_cmd_ackをアサートし、Writeコマンドを受け付けたことをユーザー回路に知らせる。ただし、リフレッシュ動作中でuser_cmd_ackのアサートが遅れることもある。
3.user_cmd_ackがアサートされた後のclk90の立ち上がりに同期して、ユーザー回路はuser_input_dataにWriteするデータを入力する。user_input_dataはDDR2 SDRAMのデータ幅の2倍幅となっている。4バーストモードならば、2つのデータを入力する必要がある。
4.ユーザー回路が入力するアドレス(row+column+bank address)は、user_cmd_ackがアサートされた後の3クロック間維持する。その後のバーストアドレスは2クロック維持する。(clk0の立ち下がりに同期)
5.write burstを終了させるときに、ユーザー回路はburst_doneをアサートしてMIGに知らせる。4バーストモードの時は2クロック間アサートする。
6.burst_doneのアサート後にWriteコマンドをデアサートする。(NOPコマンドに変更)
7.プリチャージをした後に、MIGはuser_cmd_ackをデアサートする。user_cmd_ackをデアサートされたら、ユーザー回路は次のコマンドを入力することができる。
1.clk0の立ち下がりに同期して、ユーザー回路はReadコマンドを発行し始める。
2.最低1クロック後にMIGは、clk0の立ち下がりに同期してuser_cmd_ackをアサートし、Readコマンドを受け付けたことをユーザー回路に知らせる。ただし、リフレッシュ動作中でuser_cmd_ackのアサートが遅れることもある。
3.ユーザー回路が入力するアドレス(row+column+bank address)は、user_cmd_ackがアサートされた後の3クロック間維持する。その後のバーストアドレスは2クロック維持する。(clk0の立ち下がりに同期)
4.user_output_dataが有効なのは、user_data_validがアサートされた時である。
5.DDR2 SDRAMのReadしたデータがuser_output_dataに出力される。user_output_dataはDDR2 SDRAMのバス幅の2倍の幅がある。DDR2 SDRAMは1クロックで2つのデータを読み書きするが、その2つのデータがuser_output_dataにSDR1クロックで出力される。4バーストモードでは、2つのデータがclk90の立ち上がりに同期して出力される。
6.read burstを終了させるときに、ユーザー回路はburst_doneをアサートしてMIGに知らせる。4バーストモードの時は2クロック間アサートする。
7.burst_doneのアサート後にReadコマンドをデアサートする。(NOPコマンドに変更)
8.プリチャージをした後に、MIGはuser_cmd_ackをデアサートする。user_cmd_ackをデアサートされたら、ユーザー回路は次のコマンドを入力することができる。大体、Readコマンドを発行してからデータが来るまで17クロックかかるようだ。
`define x512Mb
`define sg3
`define x16
restart; run 300us
ODDR2 #(
.DDR_ALIGNMENT("NONE"),
.SRTYPE("ASYNC")
) ODDR2_TRI(
.Q(tri_out),
.C0(clk270),
.C1(clk90),
.CE(tri_ddr_ce_to_io),
.D0(tri_ddr_d0_to_io),
.D1(tri_ddr_d1_to_io),
.R(1'b0),
.S(reset)
);
ODDR2 #(
.DDR_ALIGNMENT("NONE"),
.SRTYPE("SYNC")
) ODDR2_DATA(
.Q(to_io_pad),
.C0(clk270),
.C1(clk90),
.CE(data_ddr_ce_to_io),
.D0(data_ddr_d0_to_io),
.D1(data_ddr_d1_to_io),
.R(1'b0),
.S(reset)
);
IOBUF IOBUF_DQ(
.O(dq_data_from_io),
.IO(io_pad),
.I(to_io_pad),
.T(tri_out)
);
driver - comp.pin "cntrl0_ddr2_dq[0].I", site.pin "AA1.I"
0.464ns - comp.pin "main_00/top0/data_path0/data_read0/fifo_1_data_out[0].BY", site.pin "SLICE_X0Y3.BY"
0.464ns - comp.pin "main_00/top0/data_path0/data_read0/fifo_0_data_out[0].BY", site.pin "SLICE_X0Y2.BY"
driver - comp.pin "ddr2_dq<0>.I", site.pin "H1.I"
0.411ns - comp.pin "ddr2_sdram_cont_inst/read_write_io_inst/dout<16>.BY", site.pin "SLICE_X2Y63.BY"
0.411ns - comp.pin "ddr2_sdram_cont_inst/read_write_io_inst/dout<0>.BY", site.pin "SLICE_X2Y62.BY"
NET "cntrl0_ddr2_ck[0]" LOC = "M1" ; #bank 3
NET "cntrl0_ddr2_ck_n[0]" LOC = "M2" ; #bank 3
NET "cntrl0_ddr2_dm[0]" LOC = "J3" ; #bank 3
NET "cntrl0_ddr2_dm[1]" LOC = "E3" ; #bank 3
NET "cntrl0_ddr2_a[12]" LOC = "Y2" ; #bank 3
NET "cntrl0_ddr2_a[11]" LOC = "V1" ; #bank 3
NET "cntrl0_ddr2_a[10]" LOC = "T3" ; #bank 3
NET "cntrl0_ddr2_a[9]" LOC = "W2" ; #bank 3
NET "cntrl0_ddr2_a[8]" LOC = "W1" ; #bank 3
NET "cntrl0_ddr2_a[7]" LOC = "Y1" ; #bank 3
NET "cntrl0_ddr2_a[6]" LOC = "U1" ; #bank 3
NET "cntrl0_ddr2_a[5]" LOC = "U4" ; #bank 3
NET "cntrl0_ddr2_a[4]" LOC = "U2" ; #bank 3
NET "cntrl0_ddr2_a[3]" LOC = "U3" ; #bank 3
NET "cntrl0_ddr2_a[2]" LOC = "R1" ; #bank 3
NET "cntrl0_ddr2_a[1]" LOC = "T4" ; #bank 3
NET "cntrl0_ddr2_a[0]" LOC = "R2" ; #bank 3
NET "cntrl0_ddr2_ba[1]" LOC = "R3" ; #bank 3
NET "cntrl0_ddr2_ba[0]" LOC = "P3" ; #bank 3
NET "cntrl0_ddr2_cke" LOC = "N3" ; #bank 3
NET "cntrl0_ddr2_cs_n" LOC = "M5" ; #bank 3
NET "cntrl0_ddr2_ras_n" LOC = "M3" ; #bank 3
NET "cntrl0_ddr2_cas_n" LOC = "M4" ; #bank 3
NET "cntrl0_ddr2_we_n" LOC = "N4" ; #bank 3
NET "cntrl0_ddr2_odt" LOC = "P1" ; #bank 3
NET "cntrl0_ddr2_dq[15]" LOC = "F3"; #bank 3
NET "cntrl0_ddr2_dq[14]" LOC = "G3"; #bank 3
NET "cntrl0_ddr2_dq[13]" LOC = "F1"; #bank 3
NET "cntrl0_ddr2_dq[12]" LOC = "H5"; #bank 3
NET "cntrl0_ddr2_dq[11]" LOC = "H6"; #bank 3
NET "cntrl0_ddr2_dq[10]" LOC = "G1"; #bank 3
NET "cntrl0_ddr2_dq[9]" LOC = "G4"; #bank 3
NET "cntrl0_ddr2_dq[8]" LOC = "F2"; #bank 3
NET "cntrl0_ddr2_dq[7]" LOC = "H2"; #bank 3
NET "cntrl0_ddr2_dq[6]" LOC = "K4"; #bank 3
NET "cntrl0_ddr2_dq[5]" LOC = "L1"; #bank 3
NET "cntrl0_ddr2_dq[4]" LOC = "L5"; #bank 3
NET "cntrl0_ddr2_dq[3]" LOC = "L3"; #bank 3
NET "cntrl0_ddr2_dq[2]" LOC = "K1"; #bank 3
NET "cntrl0_ddr2_dq[1]" LOC = "K5"; #bank 3
NET "cntrl0_ddr2_dq[0]" LOC = "H1"; #bank 3
NET "cntrl0_ddr2_dqs[1]" LOC = "K6"; #bank 3
NET "cntrl0_ddr2_dqs_n[1]" LOC = "J5"; #bank 3
NET "cntrl0_ddr2_dqs[0]" LOC = "K3"; #bank 3
NET "cntrl0_ddr2_dqs_n[0]" LOC = "K2"; #bank 3
NET "cntrl0_rst_dqs_div_in" LOC = "H4"; #bank 3
NET "cntrl0_rst_dqs_div_out" LOC = "H3"; #bank 3
NET "reset_in_n" LOC = "T15" ; #bank 3
Verification Report
Generated by MIG Version 3.6.1 on 金 5 13 05:35:49 2011
Reading design libraries of xc3s700a-fg484... successful !
/*******************************************************/
/* Controller 0
/*******************************************************/
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/five-slice_x3y27" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/four-slice_x2y26" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/one-slice_x2y27" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/six-slice_x3y26" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/three-slice_x2y26" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/two-slice_x2y27" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/five-slice_x1y27" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/four-slice_x0y26" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/one-slice_x0y27" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/six-slice_x1y26" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/three-slice_x0y26" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/two-slice_x0y27" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/five-g" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/four-f" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/one-f" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/six-g" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/three-g" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/two-g" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/five-g" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/four-f" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/one-f" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/six-g" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/three-g" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/two-g" for dqs_delayed column of dqs[1] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_0_wr_addr_inst/bit0-slice_x1y22" for Fifo write address or write enable of dqs[1] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_0_wr_addr_inst/bit1-slice_x1y22" for Fifo write address or write enable of dqs[1] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_0_wr_addr_inst/bit2-slice_x1y23" for Fifo write address or write enable of dqs[1] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_0_wr_addr_inst/bit3-slice_x1y23" for Fifo write address or write enable of dqs[1] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_1_wr_addr_inst/bit0-slice_x3y22" for Fifo write address or write enable of dqs[1] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_1_wr_addr_inst/bit1-slice_x3y22" for Fifo write address or write enable of dqs[1] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_1_wr_addr_inst/bit2-slice_x3y23" for Fifo write address or write enable of dqs[1] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_1_wr_addr_inst/bit3-slice_x3y23" for Fifo write address or write enable of dqs[1] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_en[1].fifo_0_wr_en_inst-slice_x1y25" for Fifo write address or write enable of dqs[1] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_en[1].fifo_1_wr_en_inst-slice_x3y25" for Fifo write address or write enable of dqs[1] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit7-slice_x2y30" allocated for dq[15] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit7-slice_x2y31" allocated for dq[15] is invalid.
ERROR: Trying to allocate dq[15] to a wrong PAD in an IO tile in the bank 3. All the even dq
signals (e.g. dq[0],dq[2]) should be allocated to the top pad and odd dq signals to
the bottom pad in an IO tile in the bank 3 for the selected Spartan device. Use FPGA
editor to know the PAD info of any pin.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit6-slice_x0y30" allocated for dq[14] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit6-slice_x0y31" allocated for dq[14] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit5-slice_x2y28" allocated for dq[13] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit5-slice_x2y29" allocated for dq[13] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit4-slice_x0y28" allocated for dq[12] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit4-slice_x0y29" allocated for dq[12] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit3-slice_x2y22" allocated for dq[11] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit3-slice_x2y23" allocated for dq[11] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit2-slice_x0y20" allocated for dq[10] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit2-slice_x0y21" allocated for dq[10] is invalid.
ERROR: Trying to allocate dq[10] to a wrong PAD in an IO tile in the bank 3. All the even dq
signals (e.g. dq[0],dq[2]) should be allocated to the top pad and odd dq signals to
the bottom pad in an IO tile in the bank 3 for the selected Spartan device. Use FPGA
editor to know the PAD info of any pin.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit1-slice_x2y20" allocated for dq[9] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit1-slice_x2y21" allocated for dq[9] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit0-slice_x0y18" allocated for dq[8] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit0-slice_x0y19" allocated for dq[8] is invalid.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/five-slice_x3y7" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/four-slice_x2y6" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/one-slice_x2y7" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/six-slice_x3y6" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/three-slice_x2y6" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/two-slice_x2y7" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/five-slice_x1y7" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/four-slice_x0y6" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/one-slice_x0y7" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/six-slice_x1y6" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/three-slice_x0y6" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay location constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/two-slice_x0y7" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/five-g" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/four-f" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/one-f" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/six-g" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/three-g" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/two-g" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/five-g" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/four-f" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/one-f" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/six-g" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/three-g" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
LUT delay BEL constraint "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/two-g" for dqs_delayed column of dqs[0] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_0_wr_addr_inst/bit0-slice_x1y2" for Fifo write address or write enable of dqs[0] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_0_wr_addr_inst/bit1-slice_x1y2" for Fifo write address or write enable of dqs[0] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_0_wr_addr_inst/bit2-slice_x1y3" for Fifo write address or write enable of dqs[0] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_0_wr_addr_inst/bit3-slice_x1y3" for Fifo write address or write enable of dqs[0] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_1_wr_addr_inst/bit0-slice_x3y2" for Fifo write address or write enable of dqs[0] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_1_wr_addr_inst/bit1-slice_x3y2" for Fifo write address or write enable of dqs[0] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_1_wr_addr_inst/bit2-slice_x3y3" for Fifo write address or write enable of dqs[0] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_1_wr_addr_inst/bit3-slice_x3y3" for Fifo write address or write enable of dqs[0] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_en[0].fifo_0_wr_en_inst-slice_x1y5" for Fifo write address or write enable of dqs[0] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/gen_wr_en[0].fifo_1_wr_en_inst-slice_x3y5" for Fifo write address or write enable of dqs[0] is invalid or missing.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit7-slice_x2y12" allocated for dq[7] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit7-slice_x2y13" allocated for dq[7] is invalid.
ERROR: Trying to allocate dq[7] to a wrong PAD in an IO tile in the bank 3. All the even dq
signals (e.g. dq[0],dq[2]) should be allocated to the top pad and odd dq signals to
the bottom pad in an IO tile in the bank 3 for the selected Spartan device. Use FPGA
editor to know the PAD info of any pin.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit6-slice_x0y12" allocated for dq[6] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit6-slice_x0y13" allocated for dq[6] is invalid.
ERROR: Trying to allocate dq[6] to a wrong PAD in an IO tile in the bank 3. All the even dq
signals (e.g. dq[0],dq[2]) should be allocated to the top pad and odd dq signals to
the bottom pad in an IO tile in the bank 3 for the selected Spartan device. Use FPGA
editor to know the PAD info of any pin.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit5-slice_x2y10" allocated for dq[5] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit5-slice_x2y11" allocated for dq[5] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit4-slice_x0y10" allocated for dq[4] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit4-slice_x0y11" allocated for dq[4] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit3-slice_x2y4" allocated for dq[3] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit3-slice_x2y5" allocated for dq[3] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit2-slice_x0y4" allocated for dq[2] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit2-slice_x0y5" allocated for dq[2] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit1-slice_x2y2" allocated for dq[1] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit1-slice_x2y3" allocated for dq[1] is invalid.
ERROR: Trying to allocate dq[1] to a wrong PAD in an IO tile in the bank 3. All the even dq
signals (e.g. dq[0],dq[2]) should be allocated to the top pad and odd dq signals to
the bottom pad in an IO tile in the bank 3 for the selected Spartan device. Use FPGA
editor to know the PAD info of any pin.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit0-slice_x0y2" allocated for dq[0] is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit0-slice_x0y3" allocated for dq[0] is invalid.
ERROR: Trying to allocate dq[0] to a wrong PAD in an IO tile in the bank 3. All the even dq
signals (e.g. dq[0],dq[2]) should be allocated to the top pad and odd dq signals to
the bottom pad in an IO tile in the bank 3 for the selected Spartan device. Use FPGA
editor to know the PAD info of any pin.
WARNING: The signal reset_in_n is missing or allocated to invalid I/O.
WARNING:
Slice location constraint for delayed rst_dqs_div_out signal is not correct.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/five-slice_x1y14" for delayed rst_dqs_div_in signal is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/four-slice_x1y14" for delayed rst_dqs_div_in signal is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/one-slice_x0y15" for delayed rst_dqs_div_in signal is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/six-slice_x1y15" for delayed rst_dqs_div_in signal is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/three-slice_x0y15" for delayed rst_dqs_div_in signal is invalid.
WARNING:
Slice location constraint "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/two-slice_x0y14" for delayed rst_dqs_div_in signal is invalid.
Verification completed. Found the following warnings.
Number of warnings in the input UCF = 108.
Verification completed. Found the following errors.
Number of errors in the input UCF = 6.
sim_tb_top.\gen_cs[0].gen[0].u_mem0 .cmd_task: at time 20718860.0 ps ERROR: Activate Failure. Initialization sequence is not complete.
1. 9129.485 ns All banks PRECHARGE
2. 10111.985 ns LOAD MODE
BA=2, EMR2 値は0000、1X refresh rate
3. 11094.485 ns LOAD MODE
BA=3, EMR3 値は0000
4. 12076.985 ns LOAD MODE
BA=1, EMR1 値は0004、Outputs Enable, RDQS Disable, DQS# Enable, OCD exit, Rtt=75Ω, Posted CAS# = 0, Output Drive Strength Full, DLL Enable
5. 13059.485 ns LOAD MODE
BA=0, MR 値は0742、Fast exit, Write Recovery = 4, DLL Reast = Yes, CAS Latency = 4, Sequential, Burst Length = 4
6. 14821.985 ns All banks PRECHARGE
7. 15804.485 ns REFRESH
8. 16786.985 ns REFRESH
9. 17769.485 ns LOAD MODE
BA=0, MR 値は0642、Fast exit, Write Recovery = 4, DLL Reast = No, CAS Latency = 4, Sequential, Burst Length = 4
10. 18751.985 ns LOAD MODE
BA=1, EMR1 値は0384、Outputs Enable, RDQS Disable, DQS# Enable, Enable OCD defaults, Rtt=75Ω, Posted CAS# = 0, Output Drive Strength Full, DLL Enable
11. 19734.485 ns LOAD MODE
BA=1, EMR1 値は0004、Outputs Enable, RDQS Disable, DQS# Enable, OCD exit, Rtt=75Ω, Posted CAS# = 0, Output Drive Strength Full, DLL Enable
12. 20716.985 ns Activate ここでエラーになる。ERROR: Activate Failure. Initialization sequence is not complete.
BA=0, address=0000
13. 21691.985 ns Write 当然、ここでもエラー。ERROR: Write Failure. Initialization sequence is not complete.
BA=0, address=0000、データはFFFFFFFFFFFFFFFFと0000000000000000の繰り返し
14. 21699.485 ns Write 当然、ここでもエラー。ERROR: Write Failure. Initialization sequence is not complete.
BA=0, address=0004、データはFFFFFFFFFFFFFFFFと0000000000000000の繰り返し
vlog +incdir+. +define+x512Mb +define+sg37E +define+x16 ddr2_model.v
`define x512Mb
`define sg37E
`define x16
INST "infrastructure_top0/cal_top0/tap_dly0/l0" RLOC=X0Y6;
INST "infrastructure_top0/cal_top0/tap_dly0/l0" U_SET = delay_calibration_chain;
デザイン階層全体に分散されているデザインエレメントに RLOC 制約を設定し、1 つの集合にグループ化できるようにします。
TIMESPEC "TS_CLK" = FROM "clk0" TO "dqs_clk" 18 ns DATAPATHONLY;
FROM:TO (マルチサ イ ク ル) 制約の解析には、ソースと デステ ィネーション同期エレメント間のクロックスキューが含まれます。クロックスキーは、デスティネーション同期エレメントへのクロックパスからソース同期エレメントへのクロックパスの値を引いて計算されます。クロックスキー解析は、制約の付けられたすべてのクロック に対して自動的に実行されます。 解析には、すべてのデバイスファミリでセットアップ解析、 Virtex-5以降のデバ イ ス の場合はセットアップ とホールド解析の両方が含まれます。FROM:TO制約のクロックスキューを 無視す る 場合は、DATAPATHONLY キーワー ド を使用し ます。
DATAPATHONLY では、解析中にFROM:TO 制約でクロックスキューや位相情報が考慮されないように指定できます。こ のキーワードを使用すると 、データパスのみが解析されます。
NET "cntrl0_ddr2_dqs[*]" IOSTANDARD = DIFF_SSTL18_II;
NET "cntrl0_ddr2_dqs_n[*]" IOSTANDARD = DIFF_SSTL18_II;
INST "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/six" LOC = SLICE_X3Y6;
INST "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/six" BEL = G;
NET "cntrl0_ddr2_ck[0]" LOC = "M5" ; #bank 3
NET "cntrl0_ddr2_ck_n[0]" LOC = "N4" ; #bank 3
NET "cntrl0_ddr2_dm[0]" LOC = "V3" ; #bank 3
NET "cntrl0_ddr2_dm[1]" LOC = "P3" ; #bank 3
NET "cntrl0_ddr2_a[12]" LOC = "P1" ; #bank 3
NET "cntrl0_ddr2_a[11]" LOC = "P2" ; #bank 3
NET "cntrl0_ddr2_a[10]" LOC = "M3" ; #bank 3
NET "cntrl0_ddr2_a[9]" LOC = "M4" ; #bank 3
NET "cntrl0_ddr2_a[8]" LOC = "M1" ; #bank 3
NET "cntrl0_ddr2_a[7]" LOC = "M2" ; #bank 3
NET "cntrl0_ddr2_a[6]" LOC = "K1" ; #bank 3
NET "cntrl0_ddr2_a[5]" LOC = "L1" ; #bank 3
NET "cntrl0_ddr2_a[4]" LOC = "L5" ; #bank 3
NET "cntrl0_ddr2_a[3]" LOC = "L3" ; #bank 3
NET "cntrl0_ddr2_a[2]" LOC = "K3" ; #bank 3
NET "cntrl0_ddr2_a[1]" LOC = "K2" ; #bank 3
NET "cntrl0_ddr2_a[0]" LOC = "K5" ; #bank 3
NET "cntrl0_ddr2_ba[1]" LOC = "K4" ; #bank 3
NET "cntrl0_ddr2_ba[0]" LOC = "H2" ; #bank 3
NET "cntrl0_ddr2_cke" LOC = "H1" ; #bank 3
NET "cntrl0_ddr2_cs_n" LOC = "H4" ; #bank 3
NET "cntrl0_ddr2_ras_n" LOC = "H3" ; #bank 3
NET "cntrl0_ddr2_cas_n" LOC = "G3" ; #bank 3
NET "cntrl0_ddr2_we_n" LOC = "G1" ; #bank 3
NET "cntrl0_ddr2_odt" LOC = "F2" ; #bank 3
NET "reset_in_n" LOC = "K6" ; #bank 3
NET "SD_CK_P" LOC = "M1" | IOSTANDARD = SSTL18_II ;
NET "SD_CK_N" LOC = "M2" | IOSTANDARD = SSTL18_II ;
NET "SD_UDM" LOC = "E3" | IOSTANDARD = SSTL18_II ;
NET "SD_LDM" LOC = "J3" | IOSTANDARD = SSTL18_II ;
NET "SD_A<12>" LOC = "Y2" | IOSTANDARD = SSTL18_II ;
NET "SD_A<11>" LOC = "V1" | IOSTANDARD = SSTL18_II ;
NET "SD_A<10>" LOC = "T3" | IOSTANDARD = SSTL18_II ;
NET "SD_A<9>" LOC = "W2" | IOSTANDARD = SSTL18_II ;
NET "SD_A<8>" LOC = "W1" | IOSTANDARD = SSTL18_II ;
NET "SD_A<7>" LOC = "Y1" | IOSTANDARD = SSTL18_II ;
NET "SD_A<6>" LOC = "U1" | IOSTANDARD = SSTL18_II ;
NET "SD_A<5>" LOC = "U4" | IOSTANDARD = SSTL18_II ;
NET "SD_A<4>" LOC = "U2" | IOSTANDARD = SSTL18_II ;
NET "SD_A<3>" LOC = "U3" | IOSTANDARD = SSTL18_II ;
NET "SD_A<2>" LOC = "R1" | IOSTANDARD = SSTL18_II ;
NET "SD_A<1>" LOC = "T4" | IOSTANDARD = SSTL18_II ;
NET "SD_A<0>" LOC = "R2" | IOSTANDARD = SSTL18_II ;
・ このMIGデザインは、SMAコネクタのクロック入力J10とJ11から200MHzの差動クロックを入力している。SMAコネクタから入力された差動クロックは、回路図の2ページ右上のH14(SMA_DIFF_CLKIN_P), H15(SMA_DIFF_CLKIN_N)に入力されている。
・ クロックが出力されるのはJ12とJ13で、これは、ICS843001-21から出力された差動クロックだ。回路図9ページ。
・ SW6が設定スイッチとして割り当てられている。SW6が01001010と設定されていると、N0-0, N1-1, N2-0, M0-0, M1-1, M2-0, SEL1-1, SEL0-0 となる。
・ SEL1, SEL0で入力を選択していて、この値の時はTEST_CLK入力となる。TEST_CLKには、25MHzの水晶発振器がつながっている。
・ ICS843001-21は上記の設定だと、25MHz入力、M分周比=24, N分周比=3となって、出力周波数は200MHzとなる。(TABLE 3A. COMMON CONFIGURATIONS TABLE 参照)
NET "sys_clk_p" LOC = "K18" ; #Bank 3
NET "sys_clk_n" LOC = "J19" ; #Bank 3
日 | 月 | 火 | 水 | 木 | 金 | 土 |
---|---|---|---|---|---|---|
1 | 2 | 3 | 4 | 5 | 6 | 7 |
8 | 9 | 10 | 11 | 12 | 13 | 14 |
15 | 16 | 17 | 18 | 19 | 20 | 21 |
22 | 23 | 24 | 25 | 26 | 27 | 28 |
29 | 30 | 31 | - | - | - | - |