##############################################################################
## Filename: H:/HDL/FndtnISEWork/Spartan3A_starter_kit/CamDisp_EDK_OV7670_LCD/system/pcores/rotary_encoder_v1_00_a/data/rotary_encoder_v2_1_0.pao
## Description: Peripheral Analysis Order
## Date: Tue Sep 27 05:24:05 2011 (by Create and Import Peripheral Wizard)
##############################################################################
lib proc_common_v3_00_a all
lib plbv46_slave_single_v1_01_a all
lib rotary_encoder_v1_00_a user_logic vhdl
lib rotary_encoder_v1_00_a rotary_encoder vhdl
lib rotary_encoder_v1_00_a rot_enc_cont.vhd vhdl
lib rotary_encoder_v1_00_a ROTSW_SM.vhd vhdl
lib rotary_encoder_v1_00_a swdiv_rot.vhd vhdl
##############################################################################
## Filename: H:/HDL/FndtnISEWork/Spartan3A_starter_kit/CamDisp_EDK_OV7670_LCD/system/pcores/lcd_controller_v1_00_a/data/lcd_controller_v2_1_0.pao
## Description: Peripheral Analysis Order
## Date: Tue Sep 27 05:26:28 2011 (by Create and Import Peripheral Wizard)
##############################################################################
lib proc_common_v3_00_a all
lib plbv46_slave_single_v1_01_a all
lib lcd_controller_v1_00_a user_logic vhdl
lib lcd_controller_v1_00_a lcd_controller vhdl
lib lcd_controller_v1_00_a lcd_ctlr.vhd vhdl
（注）もう一度、元のEDKプロジェクトをコピーして、カスタムIPを作りなおしても、（PAOファイルが完全でも）やはり同様にワーニングが出ている。PAOファイルは関係なかったみたいだ。
もしかすると、複数PLBバスがあると何処にアサインするか分からないのかもしれない？
# ロータリーエンコーダ
NET "rot_center" LOC = "R13" | IOSTANDARD = LVTTL | PULLDOWN ;
NET "rot_a" LOC = "T13" | IOSTANDARD = LVTTL | PULLUP ;
NET "rot_b" LOC = "R14" | IOSTANDARD = LVTTL | PULLUP ;
# LCD
NET "LCD_E" LOC = "AB4" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = QUIETIO ;
NET "LCD_RS" LOC = "Y14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = QUIETIO ;
NET "LCD_RW" LOC = "W13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = QUIETIO ;
NET "LCD_DB<7>" LOC = "Y15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = QUIETIO ;
NET "LCD_DB<6>" LOC = "AB16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = QUIETIO ;
NET "LCD_DB<5>" LOC = "Y16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = QUIETIO ;
NET "LCD_DB<4>" LOC = "AA12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = QUIETIO ;
NET "LCD_DB<3>" LOC = "AB12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = QUIETIO ;
NET "LCD_DB<2>" LOC = "AB17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = QUIETIO ;
NET "LCD_DB<1>" LOC = "AB18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = QUIETIO ;
NET "LCD_DB<0>" LOC = "Y13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = QUIETIO ;
ERROR:MapLib:979 - LUT2 symbol "system_i/rotary_encoder_0/rotary_encoder_0/USER_LOGIC_I/rot_enc_cont_i/ROTSW_SM_inst/next_center_pulse1" (output signal=system_i/rotary_encoder_0/rotary_encoder_0/USER_LOGIC_I/rot_enc_cont_i/ROTSW_SM_inst/next_center_pulse) has input signal "system_i/rotary_encoder_0/rotary_encoder_0/USER_LOGIC_I/rot_enc_cont_i/rot_center_node" which will be trimmed. See Section 5 of the Map Report File for details about why the input signal will become undriven.
elease 13.2 Map O.61xd (nt)
Xilinx Mapping Report File for Design 'system_top'
Design Information
------------------
Command Line : map -intstyle ise -p xc3s700a-fg484-4 -cm speed -ir off -pr off
-c 100 -o system_top_map.ncd system_top.ngd system_top.pcf
Target Device : xc3s700a
Target Package : fg484
Target Speed : -4
Mapper Version : spartan3a -- $Revision: 1.55 $
Mapped Date : FRI 30 SEP 5:23:31 2011
Design Summary
--------------
Number of errors: 0
Number of warnings: 251
Logic Utilization:
Number of Slice Flip Flops: 5,830 out of 11,776 49%
Number of 4 input LUTs: 6,458 out of 11,776 54%
Logic Distribution:
Number of occupied Slices: 5,551 out of 5,888 94%
Number of Slices containing only related logic: 5,551 out of 5,551 100%
Number of Slices containing unrelated logic: 0 out of 5,551 0%
*See NOTES below for an explanation of the effects of unrelated logic.
Total Number of 4 input LUTs: 6,836 out of 11,776 58%
Number used as logic: 5,900
Number used as a route-thru: 378
Number used for Dual Port RAMs: 320
(Two LUTs used per Dual Port RAM)
Number used as Shift registers: 238
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
Number of bonded IOBs: 114 out of 372 30%
IOB Flip Flops: 23
IOB Master Pads: 3
IOB Slave Pads: 3
Number of ODDR2s used: 24
Number of DDR_ALIGNMENT = NONE 24
Number of DDR_ALIGNMENT = C0 0
Number of DDR_ALIGNMENT = C1 0
Number of BUFGMUXs: 10 out of 24 41%
Number of DCMs: 4 out of 8 50%
Number of BSCANs: 1 out of 1 100%
Number of BSCAN_SPARTAN3As: 1 out of 1 100%
Number of MULT18X18SIOs: 3 out of 20 15%
Number of RAMB16BWEs: 19 out of 20 95%
Number of RPM macros: 1
Average Fanout of Non-Clock Nets: 3.28
Peak Memory Usage: 242 MB
Total REAL time to MAP completion: 29 secs
Total CPU time to MAP completion: 25 secs
-- lcd_ctlr.vhd を接続
-- data_ena を生成する
process( Bus2IP_Clk ) begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
data_ena <= '0';
else
if slv_reg_write_sel="1" then
data_ena <= '1';
else
data_ena <= '0';
end if;
end if;
end if;
end process;
LCD_ctlr_i : LCD_ctlr port map (
CLK => Bus2IP_Clk,
RESET => Bus2IP_Reset,
DIN => slv_reg0(C_SLV_DWIDTH-1-15 to C_SLV_DWIDTH-1); -- 下位16ビット
CS => data_ena,
LCD_DB => LCD_DB,
LCD_RS => LCD_RS,
LCD_RW => LCD_RW,
LCD_E => LCD_E
);
entity lcd_controller is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
...
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
LCD_DB : out std_logic_vector(7 downto 0);
LCD_RS : out std_logic;
LCD_RW : out std_logic;
LCD_E : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
PORT rot_a = "", DIR = I
PORT rot_b = "", DIR = I
PORT rot_center = "", DIR = I
PORT LCD_DB = "", DIR = O, VEC = [7:0]
PORT LCD_RS = "", DIR = O
PORT LCD_RW = "", DIR = O
PORT LCD_E = "", DIR = O
WARNING:EDK:2137 - Peripheral rotary_encoder_0 is not accessible from any processor in the system. Check Bus Interface connections and address parameters.
WARNING:EDK:2137 - Peripheral lcd_controller_0 is not accessible from any processor in the system. Check Bus Interface connections and address parameters.
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0 ) is
begin
case slv_reg_read_sel is
when "1" =>
slv_ip2bus_data(0 to C_SLV_DWIDTH-5) <= (others => '0');
slv_ip2bus_data(C_SLV_DWIDTH-4) <= center_hold;
slv_ip2bus_data(C_SLV_DWIDTH-3) <= left_hold;
slv_ip2bus_data(C_SLV_DWIDTH-2) <= right_hold;
slv_ip2bus_data(C_SLV_DWIDTH-1) <= '0';
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
-- rot_enc_cont.vhd を接続
-- CS_rot_enc_wr を生成する
process( Bus2IP_Clk ) begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
CS_rot_enc_wr <= '0';
else
if slv_reg_write_sel="1" then
CS_rot_enc_wr <= '1';
else
CS_rot_enc_wr <= '0';
end if;
end if;
end if;
end process;
-- ロータリーエンコーダ
rot_enc_cont_i : rot_enc_cont port map(
clk => Bus2IP_Clk,
reset => Bus2IP_Reset,
rot_a => rot_a,
rot_b => rot_b,
rot_center => rot_center,
right_pulse => right_pulse,
left_pulse => left_pulse,
center_pulse => center_pulse
);
-- right_pulse, left_pulse をホールドするFF
process(Bus2IP_Clk) begin
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
if Bus2IP_Reset='1' then
right_hold <= '0';
left_hold <= '0';
center_hold <= '0';
else
if right_pulse = '1' then
right_hold <= '1';
elsif CS_rot_enc_wr='1' then
right_hold <= '0';
end if;
if left_pulse='1' then
left_hold <= '1';
elsif CS_rot_enc_wr='1' then
left_hold <= '0';
end if;
if center_pulse='1' then
center_hold <= '1';
elsif CS_rot_enc_wr='1' then
center_hold <= '0';
end if;
end if;
end if;
end process;
entity rotary_encoder is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
...
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
rot_a : in std_logic;
rot_b : in std_logic;
rot_center : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
640ドット / 37.6cm × 7.7cm ≒ 131ドット
ERROR:Place:1138 - Automatic clock placement failed. Please attempt to analyze the global clocking required for this design and either lock the clock placement or area locate the logic driven by the clocks so that the clocks may be placed in such a way that all logic driven by them may be routed. The main restriction on clock placement is that only one clock output signal for any competing Global / Side pair of clocks may enter any region. For further information see the "Quadrant Clock Routing" section in the Spartan3a Family Datasheet.
INST "system_i/clock_generator_0/clock_generator_0/DCM1_INST/Using_Virtex.DCM_INST" LOC = DCM_X2Y3;
INST "system_i/clock_generator_0/clock_generator_0/DCM0_INST/Using_Virtex.DCM_INST" LOC = DCM_X1Y0;
INST "system_i/clock_generator_0/clock_generator_0/DCM0_INST/Using_Virtex.DCM_INST" LOC = DCM_X1Y3;
INST "system_i/clock_generator_0/clock_generator_0/DCM1_INST/Using_Virtex.DCM_INST" LOC = DCM_X0Y2;
NET "fpga_0_clk_1_sys_clk_pin" CLOCK_DEDICATED_ROUTE = FALSE;
PIN "system_i/clock_generator_0/clock_generator_0/DCM1_INST/Using_Virtex.DCM_INST/DCM_SP.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE;
Release 13.2 Map O.61xd (nt)
Xilinx Mapping Report File for Design 'system_top'
Design Information
------------------
Command Line : map -intstyle ise -p xc3s700a-fg484-4 -cm speed -ir off -pr off
-c 100 -o system_top_map.ncd system_top.ngd system_top.pcf
Target Device : xc3s700a
Target Package : fg484
Target Speed : -4
Mapper Version : spartan3a -- $Revision: 1.55 $
Mapped Date : THU 22 SEP 23:18:57 2011
Design Summary
--------------
Number of errors: 0
Number of warnings: 251
Logic Utilization:
Number of Slice Flip Flops: 5,598 out of 11,776 47%
Number of 4 input LUTs: 6,271 out of 11,776 53%
Logic Distribution:
Number of occupied Slices: 5,366 out of 5,888 91%
Number of Slices containing only related logic: 5,366 out of 5,366 100%
Number of Slices containing unrelated logic: 0 out of 5,366 0%
*See NOTES below for an explanation of the effects of unrelated logic.
Total Number of 4 input LUTs: 6,629 out of 11,776 56%
Number used as logic: 5,713
Number used as a route-thru: 358
Number used for Dual Port RAMs: 320
(Two LUTs used per Dual Port RAM)
Number used as Shift registers: 238
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
Number of bonded IOBs: 100 out of 372 26%
IOB Flip Flops: 23
IOB Master Pads: 3
IOB Slave Pads: 3
Number of ODDR2s used: 24
Number of DDR_ALIGNMENT = NONE 24
Number of DDR_ALIGNMENT = C0 0
Number of DDR_ALIGNMENT = C1 0
Number of BUFGMUXs: 10 out of 24 41%
Number of DCMs: 4 out of 8 50%
Number of BSCANs: 1 out of 1 100%
Number of BSCAN_SPARTAN3As: 1 out of 1 100%
Number of MULT18X18SIOs: 3 out of 20 15%
Number of RAMB16BWEs: 19 out of 20 95%
Number of RPM macros: 1
Average Fanout of Non-Clock Nets: 3.30
Peak Memory Usage: 240 MB
Total REAL time to MAP completion: 39 secs
Total CPU time to MAP completion: 25 secs
PORT MPMC_InitDone = "", DIR = I
assign resetx = ~fpga_0_rst_1_sys_rst_pin;
OV7670_Model OV7670_inst (
.clk(fpga_0_rst_1_sys_rst_pin),
.resetx(resetx),
.vsync(cam_vsync),
.href(cam_href),
.pclk(cam_pclk),
.ydata(cam_data)
);
parameter PERIOD = 200; // 200MHz clock
parameter real DUTY_CYCLE = 0.5;
parameter OFFSET = 0;
initial // Clock process for clk
begin
fpga_0_clk_1_sys_clk_pin = 1'b0;
#OFFSET;
forever begin
fpga_0_clk_1_sys_clk_pin = 1'b0;
#(PERIOD-(PERIOD*DUTY_CYCLE)) fpga_0_clk_1_sys_clk_pin = 1'b1;
#(PERIOD*DUTY_CYCLE);
end
end
initial begin
// Initialize Inputs
fpga_0_RS232_DTE_RX_pin = 0;
fpga_0_RS232_DCE_RX_pin = 0;
fpga_0_DIPs_4Bit_GPIO_IO_I_pin = 0;
fpga_0_BTNs_4Bit_GPIO_IO_I_pin = 0;
fpga_0_DDR2_SDRAM_DDR2_DQS_Div_I_pin = 0;
fpga_0_rst_1_sys_rst_pin = 1'b1;
// Wait 100 ns for global reset to finish
#1000;
// Add stimulus here
#500
fpga_0_rst_1_sys_rst_pin = 1'b0;
end
plb_v46_1_wrapper
plb_v46_1 (
.PLB_Clk ( net_gnd0 ),
BEGIN plb_v46
PARAMETER INSTANCE = mb_plb
PARAMETER HW_VER = 1.05.a
PORT PLB_Clk = clk_62_5000MHz
PORT SYS_Rst = sys_bus_reset
END
BEGIN plb_v46
PARAMETER INSTANCE = plb_v46_0
PARAMETER HW_VER = 1.05.a
PARAMETER C_ARB_TYPE = 0
END
BEGIN plb_v46
PARAMETER INSTANCE = plb_v46_1
PARAMETER HW_VER = 1.05.a
END
BEGIN plb_v46
PARAMETER INSTANCE = plb_v46_0
PARAMETER HW_VER = 1.05.a
PARAMETER C_ARB_TYPE = 0
PORT PLB_Clk = clk_62_5000MHz
PORT SYS_Rst = sys_bus_reset
END
BEGIN plb_v46
PARAMETER INSTANCE = plb_v46_1
PARAMETER HW_VER = 1.05.a
PORT PLB_Clk = clk_62_5000MHz
PORT SYS_Rst = sys_bus_reset
END
plb_v46_1_wrapper
plb_v46_1 (
.PLB_Clk ( clk_62_5000MHz ),
.SYS_Rst ( sys_bus_reset[0] ),
PORT cam_href = "", DIR = I
PORT cam_vsync ="", DIR = I
PORT cam_pclk = "", DIR = I
PORT cam_data = "", DIR = I, VEC = [7:0]
PORT cam_clk = "", DIR = O
PORT afifo_overflow = "", DIR = O
PORT afifo_underflow = "", DIR = O
PORT red_out = "", DIR = O, VEC = [3:0]
PORT green_out = "", DIR = O, VEC = [3:0]
PORT blue_out = "", DIR = O, VEC = [3:0]
PORT hsyncx = "", DIR = O
PORT vsyncx = "", DIR = O
PORT afifo_overflow = "", DIR = O
PORT afifo_underflow = "", DIR = O
PORT addr_is_zero = "", DIR = O
PORT h_v_is_zero = "", DIR = O
PORT SCL = "", DIR = O
PORT SDA = "", DIR = O
NET "cam_clk" LOC = B4;
NET "cam_data[0]" LOC = A5;
NET "cam_data[1]" LOC = B6;
NET "cam_data[2]" LOC = A6;
NET "cam_data[3]" LOC = A7;
NET "cam_data[4]" LOC = A8;
NET "cam_data[5]" LOC = A9;
NET "cam_data[6]" LOC = C10;
NET "cam_data[7]" LOC = A10;
NET "cam_href" LOC = A11;
NET "cam_pclk" LOC = A12;
NET "cam_vsync" LOC = A4;
NET "cam_clk" IOSTANDARD = LVTTL;
NET "cam_data[0]" IOSTANDARD = LVTTL;
NET "cam_data[1]" IOSTANDARD = LVTTL;
NET "cam_data[2]" IOSTANDARD = LVTTL;
NET "cam_data[3]" IOSTANDARD = LVTTL;
NET "cam_data[4]" IOSTANDARD = LVTTL;
NET "cam_data[5]" IOSTANDARD = LVTTL;
NET "cam_data[6]" IOSTANDARD = LVTTL;
NET "cam_data[7]" IOSTANDARD = LVTTL;
NET "cam_href" IOSTANDARD = LVTTL;
NET "cam_pclk" IOSTANDARD = LVTTL;
NET "cam_vsync" IOSTANDARD = LVTTL;
NET "disp_red_out[3]" IOSTANDARD = LVTTL;
NET "disp_red_out[3]" DRIVE = 8;
NET "disp_red_out[3]" SLEW = FAST;
NET "disp_red_out[3]" LOC = C8;
NET "disp_red_out[2]" IOSTANDARD = LVTTL;
NET "disp_red_out[2]" DRIVE = 8;
NET "disp_red_out[2]" SLEW = FAST;
NET "disp_red_out[2]" LOC = B8;
NET "disp_red_out[1]" IOSTANDARD = LVTTL;
NET "disp_red_out[1]" DRIVE = 8;
NET "disp_red_out[1]" SLEW = FAST;
NET "disp_red_out[1]" LOC = B3;
NET "disp_red_out[0]" IOSTANDARD = LVTTL;
NET "disp_red_out[0]" DRIVE = 8;
NET "disp_red_out[0]" SLEW = FAST;
NET "disp_red_out[0]" LOC = A3;
NET "disp_green_out[3]" IOSTANDARD = LVTTL;
NET "disp_green_out[3]" DRIVE = 8;
NET "disp_green_out[3]" SLEW = FAST;
NET "disp_green_out[3]" LOC = D6;
NET "disp_green_out[2]" IOSTANDARD = LVTTL;
NET "disp_green_out[2]" DRIVE = 8;
NET "disp_green_out[2]" SLEW = FAST;
NET "disp_green_out[2]" LOC = C6;
NET "disp_green_out[1]" IOSTANDARD = LVTTL;
NET "disp_green_out[1]" DRIVE = 8;
NET "disp_green_out[1]" SLEW = FAST;
NET "disp_green_out[1]" LOC = D5;
NET "disp_green_out[0]" IOSTANDARD = LVTTL;
NET "disp_green_out[0]" DRIVE = 8;
NET "disp_green_out[0]" SLEW = FAST;
NET "disp_green_out[0]" LOC = C5;
NET "disp_blue_out[3]" IOSTANDARD = LVTTL;
NET "disp_blue_out[3]" DRIVE = 8;
NET "disp_blue_out[3]" SLEW = FAST;
NET "disp_blue_out[3]" LOC = C9;
NET "disp_blue_out[2]" IOSTANDARD = LVTTL;
NET "disp_blue_out[2]" DRIVE = 8;
NET "disp_blue_out[2]" SLEW = FAST;
NET "disp_blue_out[2]" LOC = B9;
NET "disp_blue_out[1]" IOSTANDARD = LVTTL;
NET "disp_blue_out[1]" DRIVE = 8;
NET "disp_blue_out[1]" SLEW = FAST;
NET "disp_blue_out[1]" LOC = D7;
NET "disp_blue_out[0]" IOSTANDARD = LVTTL;
NET "disp_blue_out[0]" DRIVE = 8;
NET "disp_blue_out[0]" SLEW = FAST;
NET "disp_blue_out[0]" LOC = C7;
NET "disp_hsyncx" IOSTANDARD = LVTTL;
NET "disp_hsyncx" DRIVE = 8;
NET "disp_hsyncx" SLEW = FAST;
NET "disp_hsyncx" LOC = C11;
NET "disp_vsyncx" IOSTANDARD = LVTTL;
NET "disp_vsyncx" DRIVE = 8;
NET "disp_vsyncx" SLEW = FAST;
NET "disp_vsyncx" LOC = B11;
NET "sccb_SCL" LOC = "AA3" | IOSTANDARD = LVTTL;
NET "sccb_SDA" LOC = "AB2" | IOSTANDARD = LVTTL;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, SCCBbusy ) is
begin
-- スレーブIPのReadは、最下位ビットにSCCBbusy が割り当てられる。
case slv_reg_read_sel is
when "1" =>
slv_ip2bus_data(0 to C_SLV_DWIDTH-2) <= (others => '0');
slv_ip2bus_data(C_SLV_DWIDTH-1) <= SCCBbusy;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
-- SCCB_Reg_Controller.vhd を接続
-- ad_enable を生成する
process( Bus2IP_Clk ) begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Resetn = '0' then
ad_enable <= '0';
else
if slv_reg_write_sel="01" then
ad_enable <= '1';
else
ad_enable <= '0';
end if;
end if;
end if;
end process;
Bus2IP_Reset <= not Bus2IP_Resetn;
addr_data <= slv_reg0(16 to 31); -- 下位16ビット
SCCB_Reg_Controller_inst : SCCB_Reg_Controller port map(
clkin => Bus2IP_Clk,
reset => Bus2IP_Reset,
addr_data => addr_data,
ad_enable => ad_enable,
SCCBbusy => SCCBbusy,
SCL => SCL,
SDA => SDA
);
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 1
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
SCL : out std_logic; -- SCCBのクロック
SDA : out std_logic; -- SCCBのデータ
-- ADD USER PORTS ABOVE THIS LINE ------------------
entity sccb_controller is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 1;
C_FAMILY : string := "virtex6"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
SCL : out std_logic; -- SCCBのクロック
SDA : out std_logic; -- SCCBのデータ
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
USER_LOGIC_I : entity sccb_controller_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_NUM_REG => USER_NUM_REG
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
SCL => SCL,
SDA => SDA
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
##############################################################################
## Filename: H:/HDL/FndtnISEWork/Spartan3A_starter_kit/CamDisp_EDK_OV7670/system/pcores/sccb_controller_v1_00_a/data/sccb_controller_v2_1_0.pao
## Description: Peripheral Analysis Order
## Date: Sun Aug 21 18:10:38 2011 (by Create and Import Peripheral Wizard)
##############################################################################
lib proc_common_v3_00_a all
lib plbv46_slave_single_v1_01_a all
lib sccb_controller_v1_00_a user_logic vhdl
lib sccb_controller_v1_00_a sccb_controller vhdl
lib sccb_controller_v1_00_a SCCB_reg_values_ROM.vhd vhdl
lib sccb_controller_v1_00_a freqdiv.vhd vhdl
lib sccb_controller_v1_00_a One_Transaction_SCCB.vhd vhdl
lib sccb_controller_v1_00_a SCCB_Reg_Controller.vhd vhdl
const int ledPin = 0 ; // LED connected to digital pin 13
// The setup() method runs once, when the sketch starts
void setup() {
// initialize the digital pin as an output:
pinMode(ledPin, OUTPUT);
pinMode(1, OUTPUT);
}
// the loop() method runs over and over again,
// as long as the Arduino has power
void loop()
{
digitalWrite(ledPin, HIGH); // set the LED on
digitalWrite(1, LOW);
delay(1000); // wait for a second
digitalWrite(ledPin, LOW); // set the LED off
digitalWrite(1, HIGH);
delay(1000); // wait for a second
}
-- Master Read (Disp_Controller_Top.vhd)
Disp_Controller_Top : Disp_Cont_Top generic map(
C_SLV_DWIDTH => C_SLV_DWIDTH,
C_MST_AWIDTH => C_MST_AWIDTH,
C_MST_DWIDTH => C_MST_DWIDTH,
C_NUM_REG => C_NUM_REG
) port map (
red_out => red_out,
green_out => green_out,
blue_out => blue_out,
hsyncx => hsyncx,
vsyncx => vsyncx,
afifo_overflow => afifo_overflow,
afifo_underflow => afifo_underflow,
addr_is_zero => addr_is_zero,
h_v_is_zero => h_v_is_zero,
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Reset => Bus2IP_Reset,
IP2Bus_MstRd_Req => IP2Bus_MstRd_Req,
IP2Bus_MstWr_Req => IP2Bus_MstWr_Req,
IP2Bus_Mst_Addr => IP2Bus_Mst_Addr,
IP2Bus_Mst_BE => IP2Bus_Mst_BE,
IP2Bus_Mst_Length => IP2Bus_Mst_Length,
IP2Bus_Mst_Type => IP2Bus_Mst_Type,
IP2Bus_Mst_Lock => IP2Bus_Mst_Lock,
IP2Bus_Mst_Reset => IP2Bus_Mst_Reset,
Bus2IP_Mst_CmdAck => Bus2IP_Mst_CmdAck,
Bus2IP_Mst_Cmplt => Bus2IP_Mst_Cmplt,
Bus2IP_Mst_Error => Bus2IP_Mst_Error,
Bus2IP_Mst_Rearbitrate => Bus2IP_Mst_Rearbitrate,
Bus2IP_Mst_Cmd_Timeout => Bus2IP_Mst_Cmd_Timeout,
Bus2IP_MstRd_d => Bus2IP_MstRd_d,
Bus2IP_MstRd_rem => Bus2IP_MstRd_rem,
Bus2IP_MstRd_sof_n => Bus2IP_MstRd_sof_n,
Bus2IP_MstRd_eof_n => Bus2IP_MstRd_eof_n,
Bus2IP_MstRd_src_rdy_n => Bus2IP_MstRd_src_rdy_n,
Bus2IP_MstRd_src_dsc_n => Bus2IP_MstRd_src_dsc_n,
IP2Bus_MstRd_dst_rdy_n => IP2Bus_MstRd_dst_rdy_n,
IP2Bus_MstRd_dst_dsc_n => IP2Bus_MstRd_dst_dsc_n,
IP2Bus_MstWr_d => IP2Bus_MstWr_d,
IP2Bus_MstWr_rem => IP2Bus_MstWr_rem,
IP2Bus_MstWr_sof_n => IP2Bus_MstWr_sof_n,
IP2Bus_MstWr_eof_n => IP2Bus_MstWr_eof_n,
IP2Bus_MstWr_src_rdy_n => IP2Bus_MstWr_src_rdy_n,
IP2Bus_MstWr_src_dsc_n => IP2Bus_MstWr_src_dsc_n
);
###################################################################
##
## Name : display_controller
## Desc : Microprocessor Peripheral Description
## : Automatically generated by PsfUtility
##
###################################################################
BEGIN display_controller
## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = VHDL
OPTION IP_GROUP = MICROBLAZE:PPC:USER
OPTION DESC = DISPLAY_CONTROLLER
OPTION ARCH_SUPPORT_MAP = (others=DEVELOPMENT)
OPTION STYLE = MIX
FILES
cam_data_afifo.ngc
##############################################################################
## Filename: H:/HDL/FndtnISEWork/Spartan3A_starter_kit/CamDisp_EDK_OV7670/system/pcores/display_controller_v1_00_a/data/display_controller_v2_1_0.pao
## Description: Peripheral Analysis Order
## Date: Sun Aug 21 18:03:25 2011 (by Create and Import Peripheral Wizard)
##############################################################################
lib proc_common_v3_00_a all
lib plbv46_slave_single_v1_01_a all
lib plbv46_master_burst_v1_01_a all
lib display_controller_v1_00_a user_logic vhdl
lib display_controller_v1_00_a display_controller vhdl
lib display_controller_v1_00_a Disp_Controller_Top.vhd vhdl
lib display_controller_v1_00_a dcm_DISP_clk.v verilog
lib display_controller_v1_00_a VGA_Display_Controller.v verilog
lib display_controller_v1_00_a cam_data_afifo vhdl
entity display_controller is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 1;
C_FAMILY : string := "virtex6";
C_MPLB_AWIDTH : integer := 32;
C_MPLB_DWIDTH : integer := 128;
C_MPLB_NATIVE_DWIDTH : integer := 32;
C_MPLB_P2P : integer := 0;
C_MPLB_SMALLEST_SLAVE : integer := 32;
C_MPLB_CLK_PERIOD_PS : integer := 10000
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
red_out : out std_logic_vector(3 downto 0);
green_out : out std_logic_vector(3 downto 0);
blue_out : out std_logic_vector(3 downto 0);
hsyncx : out std_logic;
vsyncx : out std_logic;
afifo_overflow : out std_logic;
afifo_underflow : out std_logic;
addr_is_zero : out std_logic;
h_v_is_zero : out std_logic
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
USER_LOGIC_I : entity display_controller_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_MST_AWIDTH => USER_MST_AWIDTH,
C_MST_DWIDTH => USER_MST_DWIDTH,
C_NUM_REG => USER_NUM_REG
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
red_out => red_out,
green_out => green_out,
blue_out => blue_out,
hsyncx => hsyncx,
vsyncx => vsyncx,
afifo_overflow => afifo_overflow,
afifo_underflow => afifo_underflow,
addr_is_zero => addr_is_zero,
h_v_is_zero => h_v_is_zero,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
VHDL デザインでは、VHDL タイプ、ジェネリック、およびポートの制限されたサブセットを Verilog モジュールとの境界に使用できます。
architecture RTL of Disp_Controller_Top is
constant DDR2_SDRAM_ADDR_START : std_logic_vector(31 downto 0) := x"46000000"; -- 32MB目から1MBを使用する。
constant TRANSFER_LENGTH : integer := 128;
...
VGA_Disp_Cont_inst : VGA_Display_Controller generic map(
AFIFO_FULL_VAL => TRANSFER_LENGTH*2,
AFIFO_HALF_FULL_VAL => TRANSFER_LENGTH
) port map (
clk_disp => clk_disp,
clk_ddr2 => Bus2IP_Clk,
reset_disp => reset_disp,
reset_ddr2 => Bus2IP_Reset,
request => request,
grant => grant,
address => open,
req_we => req_we,
addr_fifo_full => '0',
data_in => Bus2IP_MstRd_d,
data_valid => Bus2IP_MstRd_src_rdy,
red_out => red,
green_out => green,
blue_out => blue,
hsyncx => hsyncx_node,
vsyncx => vsyncx_node,
afifo_overflow => afifo_overflow,
afifo_underflow => afifo_underflow,
addr_is_zero => addr_is_zero,
h_v_is_zero => h_v_is_zero
);
module VGA_Display_Controller #(
parameter AFIFO_FULL_VAL = 256,
parameter AFIFO_HALF_FULL_VAL = 128
)
(
input wire clk_disp, // 25MHzのディスプレイ表示用クロック
input wire clk_ddr2, // 133.33MHzのDDR2 SDRAM用クロック
input wire reset_disp, // clk_disp 用リセット
input wire reset_ddr2, // clk_ddr2 用リセット
output reg request, // データ転送のrequest
input wire grant, // データ転送のgrant
output wire [18:0] address, // DDR2 SDRAMのアドレス
output reg req_we, // Read要求のWrite Enable
input wire addr_fifo_full, // Read要求用FIFOのFULL
input wire [31:0] data_in, // DDR2 SDRAMの画像データ(YUV)
input wire data_valid,
output reg [7:0] red_out,
output reg [7:0] green_out,
output reg [7:0] blue_out,
output reg hsyncx,
output reg vsyncx,
output wire afifo_overflow, // 非同期FIFO のオーバーフロー・エラー
output wire afifo_underflow, // 非同期FIFO のアンダーフロー・エラー
output reg addr_is_zero, // for test
output reg h_v_is_zero // for test
);
AFIFO_HALF_FULL_VAL => TRANSFER_LENGTH
AFIFO_HALF_FULL_VAL => TRANSFER_LENGTH+1
// VGA Display Controller
// SRAMから24MHz、16bit幅で2回に1回読みだされた輝度情報をRGBに変換してカラーで表示する
// UVデータを入力して、YUV-RGB変換を行う。変換式は以下のものを使用する
// R = (Y<<8 + "1_0110_0100"*V - X"B380")>>8
// G = (Y<<8 - "1011_0111"*V - "0101_1000"*U + X"8780")>>8
// B = (Y<<8 + "1_1100_0110"*U - X"E300")>>8
// 上の式で計算を行う。ビット長は19ビット
// YUVデータ保存用非同期FIFO, Wirte側32ビット幅128深度、Read側16ビット256深度とする。これはAFIFO_FULL_VALにwr_data_countに達したときにリクエストを止めると、その時点で要求されていたRead要求分のデータが帰ってくるためである
// RGB444用に変更
`default_nettype none
// synthesis translate_off
// `include "std_ovl_defines.h"
// synthesis translate_on
module VGA_Display_Controller #(
parameter AFIFO_FULL_VAL = 256,
parameter AFIFO_HALF_FULL_VAL = 128
)
(
input wire clk_disp, // 25MHzのディスプレイ表示用クロック
input wire clk_ddr2, // 133.33MHzのDDR2 SDRAM用クロック
input wire reset_disp, // clk_disp 用リセット
input wire reset_ddr2, // clk_ddr2 用リセット
output reg request, // データ転送のrequest
input wire grant, // データ転送のgrant
output wire [18:0] address, // DDR2 SDRAMのアドレス
output reg req_we, // Read要求のWrite Enable
input wire addr_fifo_full, // Read要求用FIFOのFULL
input wire [31:0] data_in, // DDR2 SDRAMの画像データ(YUV)
input wire data_valid,
output reg [7:0] red_out,
output reg [7:0] green_out,
output reg [7:0] blue_out,
output reg hsyncx,
output reg vsyncx,
output wire afifo_overflow, // 非同期FIFO のオーバーフロー・エラー
output wire afifo_underflow, // 非同期FIFO のアンダーフロー・エラー
output reg addr_is_zero, // for test
output reg h_v_is_zero // for test
);
`include "./disp_timing_parameters.vh"
// parameter AFIFO_FULL_VAL = 10'b01_0000_0000; // Write側の値。Write側は32ビットなので、64でRead側は128となる
// parameter AFIFO_HALF_FULL_VAL = 10'b00_1000_0000; // Write側の値。Write側は32ビットなので、32でRead側は64となる
parameter [3:0] idle_rdg= 4'b0001,
init_full_mode= 4'b0010,
wait_half_full= 4'b0100,
req_burst= 4'b1000;
reg [3:0] cs_rdg;
parameter [1:0] req_we_low= 2'b01,
req_we_high= 2'b10; // active
reg [1:0] cs_vrw;
reg afifo_rd_en;
wire [15:0] afifo_dout;
wire afifo_full;
wire afifo_empty;
wire [9:0] wr_data_count;
reg [18:0] addr_count;
wire hv_count_enable;
reg [9:0] read_count;
reg hv_cnt_ena_d1, hv_cnt_ena_d2;
reg [10:0] h_count;
reg [9:0] v_count;
reg [7:0] red_node, green_node, blue_node;
reg hsyncx_node, vsyncx_node;
reg [15:0] RGBX;
reg addr_is_zero_node, h_v_is_zero_node;
parameter VGA_CON_STAR_ADDR = 8;
// synthesis translate_off
// wire [`OVL_FIRE_WIDTH-1:0] fire_overflow, fire_underflow;
// synthesis translate_on
// YUVデータ保存用非同期FIFO, Wirte側32ビット幅128深度、Read側16ビット256深度とする
cam_data_afifo camd_afifo_inst (
.rst(reset_ddr2),
.wr_clk(clk_ddr2),
.rd_clk(clk_disp),
.din(data_in), // Bus [31 : 0]
.wr_en(data_valid),
.rd_en(afifo_rd_en),
.dout(afifo_dout), // Bus [15 : 0]
.full(afifo_full),
.overflow(afifo_overflow),
.empty(afifo_empty),
.underflow(afifo_underflow),
.wr_data_count(wr_data_count) // ouput [9 : 0] wr_data_count
);
// DDR2 SDRAMのアドレスカウンタ（DDR2 SDRAMクロックドメイン）カウンタの単位は16ビット=1画素（UYまたはVY）
always @(posedge clk_ddr2) begin
if (reset_ddr2)
addr_count <= VGA_CON_STAR_ADDR;
else begin
if (addr_count>=(H_ACTIVE_VIDEO * V_ACTIVE_VIDEO)) // 1フレーム分描画終了したので、0にクリアする
addr_count <= 0;
else if (req_we) // DDR2 SDRAMへのRead要求のweがでたらカウントアップ
addr_count <= addr_count + 19'd4; // DDR2 SDRAMは4バーストするので、＋4
end
end
assign address = addr_count;
// Read コマンド生成モジュール
// Read コマンド生成モジュール用ステートマシン
always @(posedge clk_ddr2) begin
if (reset_ddr2)
cs_rdg <= idle_rdg;
else begin
case (cs_rdg)
idle_rdg :
cs_rdg <= init_full_mode;
init_full_mode : // 最初にcam_data_afifo をFULLにするステート、このステートではVGA信号は出力しないで、ひたすらcam_data_afifo がFULLになるのを待つ。
if (wr_data_count>=AFIFO_FULL_VAL)
cs_rdg <= wait_half_full;
else
cs_rdg <= init_full_mode;
wait_half_full : // cam_data_afifo がHALF_FULLになるまでこのステートで待機
if (wr_data_count<=AFIFO_HALF_FULL_VAL)
cs_rdg <= req_burst;
else
cs_rdg <= wait_half_full;
req_burst :
if (read_count==0 && wr_data_count>AFIFO_HALF_FULL_VAL) // VRAMのREAD要求をカウントするカウンタが0になって、wr_data_count がHALF_FULL以上になったら
cs_rdg <= wait_half_full;
else
cs_rdg <= req_burst;
endcase
end
end
assign hv_count_enable = (cs_rdg==wait_half_full || cs_rdg==req_burst) ? 1'b1 : 1'b0;
// request の実装。VRAMのデータをReadしたいときにアクティベート。アービタへ
always @(posedge clk_ddr2) begin
if (reset_ddr2)
request <= 1'b0;
else begin
if (cs_rdg==req_burst || cs_rdg==init_full_mode)
request <= 1'b1;
else
request <= 1'b0;
end
end
// read_count の実装、DDR2 SDRAM へのRead要求のカウントをする。
always @(posedge clk_ddr2) begin
if (reset_ddr2)
read_count <= AFIFO_HALF_FULL_VAL;
else begin
if (cs_rdg==wait_half_full)
read_count <= AFIFO_HALF_FULL_VAL;
else if (cs_rdg==req_burst) begin
if (read_count!=0 && addr_fifo_full==1'b0) // 0になるまで、VRAMへの要求アドレスFIFOがFULLでない時に要求を書き込む
read_count <= read_count - 1;
end
end
end
// req_we の実装、req_we はクロック2回に1回出力する。こうすることによってaddr_fifo_full のみでも、req_we をFF出力とすることができる。READのレイテンシは長いので、2回に1回のRead要求発行でも問題ないはず。。。
always @(posedge clk_ddr2) begin
if (reset_ddr2) begin
cs_vrw <= req_we_low;
req_we <= 1'b0;
end else begin
case (cs_vrw)
req_we_low :
if ((cs_rdg==req_burst || cs_rdg==init_full_mode) && read_count!=0 && ~addr_fifo_full && grant) begin // 最初にpixel_async_fifo をFULLにする時とHALFまで行ってFULLにするとき
cs_vrw <= req_we_high;
req_we <= 1'b1;
end
req_we_high : begin
cs_vrw <= req_we_low;
req_we <= 1'b0;
end
endcase
end
end
// Read コマンド生成モジュール,終了
// ビットマップVGAコントローラのclk_disp (25MHz)動作部
// h_count、v_count用に133.33MHz動作のcs_rdg の値を使用するので2回25MHz動作のFFでラッチする
always @(posedge clk_disp) begin
if (reset_disp) begin
hv_cnt_ena_d1 <= 1'b0;
hv_cnt_ena_d2 <= 1'b0;
end else begin
hv_cnt_ena_d1 <= hv_count_enable;
hv_cnt_ena_d2 <= hv_cnt_ena_d1;
end
end
// h_countの実装（水平カウンタ）
always @(posedge clk_disp) begin
if (reset_disp)
h_count <= 0;
else if (h_count>=(H_SUM-1)) // h_count がH_SUM-1よりも大きければ0に戻す(mod H_SUM)
h_count <= 0;
else if (hv_cnt_ena_d2) // 最初に非同期FIFOをフルにするまではカウントしない
h_count <= h_count + 11'd1;
end
// v_countの実装（垂直カウンタ）
always @(posedge clk_disp) begin
if (reset_disp)
v_count <= 0;
else if (h_count>=(H_SUM-1)) begin // 水平カウンタがクリアされるとき
if (v_count>=(V_SUM-1)) // v_count がV_SUM-1よりも大きければ0に戻す(mode V_SUM)
v_count <= 0;
else if (hv_cnt_ena_d2) // 最初に非同期FIFOをフルにするまではカウントしない
v_count <= v_count + 10'd1;
end
end
// RGBXを保存しておく
always @(posedge clk_disp) begin // U
if (reset_disp)
RGBX <= 0;
else
RGBX <= afifo_dout;
end
// Red, Green, Blue出力
always @(posedge clk_disp) begin
if (reset_disp) begin
red_node <= 0;
green_node <= 0;
blue_node <= 0;
end else begin
if (~hv_cnt_ena_d2) begin // 最初にpixel_async_fifo がフルになるまで画像データを出力しない。
red_node <= 0;
green_node <= 0;
blue_node <= 0;
end else if (h_count<H_ACTIVE_VIDEO && v_count<V_ACTIVE_VIDEO) begin // 表示している期間のみ画像データを出力する R 11:8 G 15:12 B 7:4
// red_node <= {RGBX[11:8], 4'b000};
// green_node <= {RGBX[7:4], 4'b000};
// blue_node <= {RGBX[3:0], 4'b000};
red_node <= {RGBX[3:0], 4'b000};
green_node <= {RGBX[7:4], 4'b000};
blue_node <= {RGBX[11:8], 4'b000};
end else begin
red_node <= 0;
green_node <= 0;
blue_node <= 0;
end
end
end
always @(posedge clk_disp) begin
if (reset_disp) begin
red_out <= 0;
green_out <= 0;
blue_out <= 0;
end else begin
red_out <= red_node;
green_out <= green_node;
blue_out <= blue_node;
end
end
// hsyncx 出力（水平同期信号）
always @(posedge clk_disp) begin
if (reset_disp)
hsyncx_node <= 1'b1;
else
if (h_count>(H_ACTIVE_VIDEO + H_FRONT_PORCH-1) && h_count<=(H_ACTIVE_VIDEO + H_FRONT_PORCH + H_SYNC_PULSE-1)) // 水平同期期間
hsyncx_node <= 1'b0;
else
hsyncx_node <= 1'b1;
end
always @(posedge clk_disp) begin
if (reset_disp)
hsyncx <= 1'b1;
else
hsyncx <= hsyncx_node;
end
// vsyncx 出力（水平同期信号）
always @(posedge clk_disp) begin
if (reset_disp)
vsyncx_node <= 1'b1;
else
if (v_count>(V_ACTIVE_VIDEO + V_FRONT_PORCH-1) && v_count<=(V_ACTIVE_VIDEO + V_FRONT_PORCH + V_SYNC_PULSE-1)) // 垂直同期期間
vsyncx_node <= 1'b0;
else
vsyncx_node <= 1'b1;
end
always @(posedge clk_disp) begin
if (reset_disp)
vsyncx <= 1'b1;
else
vsyncx <= vsyncx_node;
end
// afifo_rd_en の処理
always @(posedge clk_disp) begin
if (reset_disp)
afifo_rd_en <= 1'b0;
else begin
if (~hv_cnt_ena_d2) // 初期化中
afifo_rd_en <= 1'b0;
else if (h_count<H_ACTIVE_VIDEO && v_count<V_ACTIVE_VIDEO) // 表示期間
afifo_rd_en <= 1'b1;
else
afifo_rd_en <= 1'b0;
end
end
// アサーション
// synthesis translate_off
always @ (posedge clk_ddr2) begin
if (reset_ddr2)
;
else begin
if (afifo_overflow) begin
$display("%m: at time %t ERROR : FIFOがフルなのにライトした",$time);
$stop;
end
end
end
always @(posedge clk_disp) begin
if (reset_disp)
;
else begin
if (afifo_underflow) begin
$display("%m: at time %t ERROR : FIFOが空なのにリードした",$time);
$stop;
end
end
end
// ovl_never #(
// `OVL_ERROR, // severity_level
// `OVL_ASSERT, // property_type
// "ERROR : FIFOがフルなのにライトした", // msg
// `OVL_COVER_DEFAULT, // coverage_level
// `OVL_POSEDGE, // clock_edge
// `OVL_ACTIVE_HIGH, // reset_polarity
// `OVL_GATE_CLOCK // gating_type
// ) afifo_overflow_assertion (
// clk_ddr2,
// reset_ddr2,
// 1'b1,
// afifo_overflow,
// fire_overflow
// );
// ovl_never #(
// `OVL_ERROR, // severity_level
// `OVL_ASSERT, // property_type
// "ERROR : FIFOが空なのにリードした", // msg
// `OVL_COVER_DEFAULT, // coverage_level
// `OVL_POSEDGE, // clock_edge
// `OVL_ACTIVE_HIGH, // reset_polarity
// `OVL_GATE_CLOCK // gating_type
// ) afifo_underflow_assertion (
// clk_disp,
// reset_disp,
// 1'b1,
// afifo_underflow,
// fire_underflow
// );
// synthesis translate_on
// for test
always @(posedge clk_ddr2) begin
if (reset_ddr2) begin
addr_is_zero_node <= 1'b0;
addr_is_zero <= 1'b0;
end else begin
if (addr_count == 0)
addr_is_zero_node <= 1'b1;
else
addr_is_zero_node <= 1'b0;
addr_is_zero <= addr_is_zero_node;
end
end
always @(posedge clk_disp) begin
if (reset_disp) begin
h_v_is_zero_node <= 1'b0;
h_v_is_zero <= 1'b0;
end else begin
if (h_count==0 && v_count==0)
h_v_is_zero_node <= 1'b1;
else
h_v_is_zero_node <= 1'b0;
h_v_is_zero <= h_v_is_zero_node;
end
end
endmodule
`default_nettype wire
// 表示タイミングの定義
parameter H_ACTIVE_VIDEO= 640;
parameter H_FRONT_PORCH = 16;
parameter H_SYNC_PULSE = 96;
parameter H_BACK_PORCH = 48;
parameter H_SUM = H_ACTIVE_VIDEO + H_FRONT_PORCH + H_SYNC_PULSE + H_BACK_PORCH;
parameter V_ACTIVE_VIDEO = 480;
parameter V_FRONT_PORCH = 10;
parameter V_SYNC_PULSE = 2;
parameter V_BACK_PORCH = 29;
parameter V_SUM = V_ACTIVE_VIDEO + V_FRONT_PORCH + V_SYNC_PULSE + V_BACK_PORCH;
parameter H_DISPLAY_SIZE = H_ACTIVE_VIDEO/8; // 横80桁
parameter V_DISPLAY_SIZE = V_ACTIVE_VIDEO/8; // 縦60行
parameter RED_DOT_POS = 9; // 9ビット目がRED
parameter GREEN_DOT_POS = 8; // 8ビット目がGREEN
parameter BLUE_DOT_POS = 7; // 7ビット目がBLUE
// DCM module
// 62.5MHzを入力して、25MHzの表示用のclkを生成する(VGA)。
`default_nettype none
`timescale 1ns / 1ps
(* KEEP_HIERARCHY = "TRUE" *)module dcm_DISP_clk (sysclk, reset, clk_disp, dcm_locked_out);
input wire sysclk;
input wire reset;
output wire clk_disp;
output wire dcm_locked_out;
wire clk_bufg, clk_node, dcm1_locked;
wire clk_cam_node, clk_cam_bufg;
DCM dcm_DDR2_clk_dcm (
.CLKIN(sysclk),
.CLKFB(clk_bufg),
.DSSEN(1'b0),
.PSINCDEC(1'b0),
.PSEN(1'b0),
.PSCLK(1'b0),
.RST(reset), // 前段のDCMがロックするまでリセット
.CLK0(clk_node),
.CLK90(),
.CLK180(),
.CLK270(),
.CLK2X(),
.CLK2X180(),
.CLKDV(),
.CLKFX(clk_cam_node),
.CLKFX180(),
.LOCKED(dcm1_locked),
.PSDONE(),
.STATUS()
);
defparam dcm_DDR2_clk_dcm.CLKIN_PERIOD = 16.0;
defparam dcm_DDR2_clk_dcm.DLL_FREQUENCY_MODE = "LOW";
defparam dcm_DDR2_clk_dcm.DUTY_CYCLE_CORRECTION = "TRUE";
defparam dcm_DDR2_clk_dcm.CLKDV_DIVIDE = 2.0;
defparam dcm_DDR2_clk_dcm.PHASE_SHIFT = 0;
defparam dcm_DDR2_clk_dcm.CLKOUT_PHASE_SHIFT = "NONE";
defparam dcm_DDR2_clk_dcm.STARTUP_WAIT = "FALSE";
defparam dcm_DDR2_clk_dcm.CLKFX_DIVIDE = 5;
defparam dcm_DDR2_clk_dcm.CLKFX_MULTIPLY = 2;
BUFG CLK_BUFG_INST (
.I(clk_node),
.O(clk_bufg)
);
BUFG CLK_CAM_BUFG_INST (
.I(clk_cam_node),
.O(clk_cam_bufg)
);
assign dcm_locked_out = dcm1_locked;
assign clk_disp = clk_cam_bufg;
endmodule
`default_nettype wire
##############################################################
#
# Xilinx Core Generator version 13.2
# Date: Thu Sep 08 19:15:36 2011
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:fifo_generator:6.1
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc3s700a
SET devicefamily = spartan3a
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Fifo_Generator family Xilinx,_Inc. 6.1
# END Select
# BEGIN Parameters
CSET almost_empty_flag=false
CSET almost_full_flag=false
CSET component_name=cam_data_afifo
CSET data_count=false
CSET data_count_width=9
CSET disable_timing_violations=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=4
CSET empty_threshold_negate_value=5
CSET enable_ecc=false
CSET enable_int_clk=false
CSET enable_reset_synchronization=true
CSET fifo_implementation=Independent_Clocks_Block_RAM
CSET full_flags_reset_value=1
CSET full_threshold_assert_value=509
CSET full_threshold_negate_value=508
CSET inject_dbit_error=false
CSET inject_sbit_error=false
CSET input_data_width=32
CSET input_depth=512
CSET output_data_width=16
CSET output_depth=1024
CSET overflow_flag=true
CSET overflow_sense=Active_High
CSET performance_options=First_Word_Fall_Through
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_full_type=No_Programmable_Full_Threshold
CSET read_clock_frequency=1
CSET read_data_count=false
CSET read_data_count_width=11
CSET reset_pin=true
CSET reset_type=Asynchronous_Reset
CSET underflow_flag=true
CSET underflow_sense=Active_High
CSET use_dout_reset=true
CSET use_embedded_registers=false
CSET use_extra_logic=true
CSET valid_flag=false
CSET valid_sense=Active_High
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=true
CSET write_data_count_width=10
# END Parameters
GENERATE
# CRC: 2418f0c5
-- Master Write (Cam_Controller_Top.vhd)
Cam_Controller_Top : Cam_Cont_Top generic map (
C_SLV_DWIDTH => C_SLV_DWIDTH,
C_MST_AWIDTH => C_MST_AWIDTH,
C_MST_DWIDTH => C_MST_DWIDTH,
C_NUM_REG => C_NUM_REG
) port map (
cam_href => cam_href,
cam_vsync => cam_vsync,
cam_pclk => cam_pclk,
cam_data => cam_data,
cam_clk => cam_clk,
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Reset => Bus2IP_Reset,
IP2Bus_MstRd_Req => IP2Bus_MstRd_Req,
IP2Bus_MstWr_Req => IP2Bus_MstWr_Req,
IP2Bus_Mst_Addr => IP2Bus_Mst_Addr,
IP2Bus_Mst_BE => IP2Bus_Mst_BE,
IP2Bus_Mst_Length => IP2Bus_Mst_Length,
IP2Bus_Mst_Type => IP2Bus_Mst_Type,
IP2Bus_Mst_Lock => IP2Bus_Mst_Lock,
IP2Bus_Mst_Reset => IP2Bus_Mst_Reset,
Bus2IP_Mst_CmdAck => Bus2IP_Mst_CmdAck,
Bus2IP_Mst_Cmplt => Bus2IP_Mst_Cmplt,
Bus2IP_Mst_Error => Bus2IP_Mst_Error,
Bus2IP_Mst_Rearbitrate => Bus2IP_Mst_Rearbitrate,
Bus2IP_Mst_Cmd_Timeout => Bus2IP_Mst_Cmd_Timeout,
IP2Bus_MstWr_d => IP2Bus_MstWr_d,
IP2Bus_MstWr_rem => IP2Bus_MstWr_rem,
IP2Bus_MstWr_sof_n => IP2Bus_MstWr_sof_n,
IP2Bus_MstWr_eof_n => IP2Bus_MstWr_eof_n,
IP2Bus_MstWr_src_rdy_n => IP2Bus_MstWr_src_rdy_n,
IP2Bus_MstWr_src_dsc_n => IP2Bus_MstWr_src_dsc_n,
Bus2IP_MstWr_dst_rdy_n => Bus2IP_MstWr_dst_rdy_n,
Bus2IP_MstWr_dst_dsc_n => Bus2IP_MstWr_dst_dsc_n,
IP2Bus_MstRd_dst_rdy_n => IP2Bus_MstRd_dst_rdy_n,
IP2Bus_MstRd_dst_dsc_n => IP2Bus_MstRd_dst_dsc_n,
afifo_overflow => afifo_overflow,
afifo_underflow => afifo_underflow
);
BEGIN camera_controller
## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = VHDL
OPTION IP_GROUP = MICROBLAZE:PPC:USER
OPTION DESC = CAMERA_CONTROLLER
OPTION ARCH_SUPPORT_MAP = (others=DEVELOPMENT)
OPTION STYLE = MIX
FILES
cam_cont_afifo.ngc
##############################################################################
## Filename: H:/HDL/FndtnISEWork/Spartan3A_starter_kit/CamDisp_EDK_OV7670/system/pcores/camera_controller_v1_00_a/data/camera_controller_v2_1_0.pao
## Description: Peripheral Analysis Order
## Date: Sun Aug 21 17:39:47 2011 (by Create and Import Peripheral Wizard)
##############################################################################
lib proc_common_v3_00_a all
lib plbv46_slave_single_v1_01_a all
lib plbv46_master_burst_v1_01_a all
lib camera_controller_v1_00_a user_logic vhdl
lib camera_controller_v1_00_a camera_controller vhdl
lib camera_controller_v1_00_a Cam_Controller_Top vhdl
lib camera_controller_v1_00_a Camera_Cntrler verilog
lib camera_controller_v1_00_a dcm_CAM_clk verilog
lib camera_controller_v1_00_a synchronizer verilog
lib camera_controller_v1_00_a cam_cont_afifo vhdl
entity camera_controller is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 1;
C_FAMILY : string := "virtex6";
C_MPLB_AWIDTH : integer := 32;
C_MPLB_DWIDTH : integer := 128;
C_MPLB_NATIVE_DWIDTH : integer := 32;
C_MPLB_P2P : integer := 0;
C_MPLB_SMALLEST_SLAVE : integer := 32;
C_MPLB_CLK_PERIOD_PS : integer := 10000
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
cam_href : in std_logic; -- CMOSカメラからのHREF
cam_vsync : in std_logic; -- CMOSカメラからのVSYNC
cam_pclk : in std_logic; -- CMOSカメラからのpclk
cam_data : in std_logic_vector(7 downto 0); -- CMOSカメラからのデータ
cam_clk : out std_logic;
afifo_overflow : out std_logic;
afifo_underflow : out std_logic
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
USER_LOGIC_I : entity camera_controller_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_MST_AWIDTH => USER_MST_AWIDTH,
C_MST_DWIDTH => USER_MST_DWIDTH,
C_NUM_REG => USER_NUM_REG
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
cam_href => cam_href,
cam_vsync => cam_vsync,
cam_pclk => cam_pclk,
cam_data => cam_data,
cam_clk => cam_clk,
afifo_overflow => afifo_overflow,
afifo_underflow => afifo_underflow,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
##############################################################################
## Filename: H:/HDL/FndtnISEWork/Spartan6/SP605_AXI_CharDispCtrler/system/pcores/chardispc_v1_00_a/data/chardispc_v2_1_0.pao
## Description: Peripheral Analysis Order
## Date: Sat Jul 30 05:47:37 2011 (by Create and Import Peripheral Wizard)
##############################################################################
lib proc_common_v3_00_a all
lib axi_lite_ipif_v1_01_a all
lib chardispc_v1_00_a user_logic vhdl
lib chardispc_v1_00_a chardispc vhdl
lib chardispc_v1_00_a char_gen_rom.v verilog
lib chardispc_v1_00_a CharDispCtrler.v verilog
lib chardispc_v1_00_a CharDispCtrler_SP605.v verilog
lib chardispc_v1_00_a dcm_inst.vhd vhdl
lib chardispc_v1_00_a disp_timing.v verilog
lib chardispc_v1_00_a frame_buffer.v verilog
lib chardispc_v1_00_a freqdiv.vhd vhdl
lib chardispc_v1_00_a One_Transaction_SCCB.vhd vhdl
lib chardispc_v1_00_a SCCB_Reg_Controller.vhd vhdl
lib chardispc_v1_00_a SCCB_reg_values_ROM.vhd vhdl
１．MPDファイルに”OPTION STYLE = MIX”と宣言する。
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = VHDL
OPTION IP_GROUP = MICROBLAZE:PPC:USER
OPTION CORE_STATE = DEVELOPMENT
OPTION STYLE = MIX
２．system\pcores\[カスタムIP名]に、netlistフォルダを作る。
３．system\pcores\[カスタムIP名]\dataフォルダに、[カスタムIP名].bbdを新規作成する。
４．[カスタムIP名].bbdファイルに、使用するネットリストファイルのリストを入力する。FILES
cam_cont_afifo.ngc, cam_data_fifo.ngc, disp_netlist.edn
５．カスタムIPに含めるネットリストファイルをすべて、system\pcores\[カスタムIP名]\netlistフォルダに入れる。
（注）
これだけでは論理合成でエラーになってしまう。.ngc ファイルのVerilog かVHDLファイルをフォルダ(Verilog またはVHDL) に追加して、.pao ファイルにそのHDLファイルのエントリを追加する必要がある。
-- Cam_Controller_Top.vhd
-- Camera_Cntrler.v とsynchronizer.v のトップ
-- DDR2 SDRAM 64MBの内の真ん中から1MBを使用する。データバス幅は32ビット
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity Cam_Controller_Top is
generic(
C_SLV_DWIDTH : integer := 32;
C_MST_AWIDTH : integer := 32;
C_MST_DWIDTH : integer := 32;
C_NUM_REG : integer := 3
);
port(
cam_href : in std_logic; -- CMOSカメラからのHREF
cam_vsync : in std_logic; -- CMOSカメラからのVSYNC
cam_pclk : in std_logic; -- CMOSカメラからのpclk
cam_data : in std_logic_vector(7 downto 0); -- CMOSカメラからのデータ
cam_clk : out std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
IP2Bus_MstRd_Req : out std_logic;
IP2Bus_MstWr_Req : out std_logic;
IP2Bus_Mst_Addr : out std_logic_vector(0 to C_MST_AWIDTH-1);
IP2Bus_Mst_BE : out std_logic_vector(0 to C_MST_DWIDTH/8-1);
IP2Bus_Mst_Length : out std_logic_vector(0 to 11);
IP2Bus_Mst_Type : out std_logic;
IP2Bus_Mst_Lock : out std_logic;
IP2Bus_Mst_Reset : out std_logic;
Bus2IP_Mst_CmdAck : in std_logic;
Bus2IP_Mst_Cmplt : in std_logic;
Bus2IP_Mst_Error : in std_logic;
Bus2IP_Mst_Rearbitrate : in std_logic;
Bus2IP_Mst_Cmd_Timeout : in std_logic;
IP2Bus_MstWr_d : out std_logic_vector(0 to C_MST_DWIDTH-1);
IP2Bus_MstWr_rem : out std_logic_vector(0 to C_MST_DWIDTH/8-1);
IP2Bus_MstWr_sof_n : out std_logic;
IP2Bus_MstWr_eof_n : out std_logic;
IP2Bus_MstWr_src_rdy_n : out std_logic;
IP2Bus_MstWr_src_dsc_n : out std_logic;
Bus2IP_MstWr_dst_rdy_n : in std_logic;
Bus2IP_MstWr_dst_dsc_n : in std_logic;
IP2Bus_MstRd_dst_rdy_n : out std_logic;
IP2Bus_MstRd_dst_dsc_n : out std_logic;
afifo_overflow : out std_logic;
afifo_underflow : out std_logic
);
end Cam_Controller_Top;
architecture RTL of Cam_Controller_Top is
constant DDR2_SDRAM_ADDR_START : std_logic_vector(31 downto 0) := x"46000000"; -- 32MB目から1MBを使用する。
component Camera_Cntrler
port(
clk_cam : in std_logic;
clk_ddr2 : in std_logic;
reset_cam : in std_logic;
reset_ddr2 : in std_logic;
cam_href_2d : in std_logic;
cam_vsync_2d : in std_logic;
master_sync : in std_logic;
cam_data_2d : in std_logic_vector(7 downto 0);
address : out std_logic_vector(18 downto 0);
data_out : out std_logic_vector(31 downto 0);
addr_enable : in std_logic;
data_enable : in std_logic;
capture_ena : in std_logic;
afifo_empty : out std_logic;
afifo_rd_data_count : out std_logic_vector(7 downto 0);
afifo_overflow : out std_logic;
afifo_underflow : out std_logic
);
end component;
component synchronizer
port(
clk : in std_logic;
reset : in std_logic;
cam_vsync_1d : in std_logic;
cam_href_1d : in std_logic;
master_sync : out std_logic
);
end component;
component dcm_CAM_clk
port(
sysclk : in std_logic;
reset : in std_logic;
clk_cam : out std_logic;
dcm_locked_out : out std_logic
);
end component;
signal cam_href_1d, cam_href_2d : std_logic;
signal cam_vsync_1d, cam_vsync_2d : std_logic;
signal cam_data_1d, cam_data_2d : std_logic_vector(7 downto 0);
signal addr_ena, data_ena : std_logic;
signal master_sync : std_logic;
signal dcm_locked : std_logic;
signal clk_cam : std_logic;
signal reset_cam_node, reset_cam : std_logic;
signal reset_cam_srl : std_logic;
signal reset_cam_srl_1d, reset_cam_srl_2d : std_logic;
signal camc_addr : std_logic_vector(18 downto 0);
signal camc_data : std_logic_vector(31 downto 0);
signal afifo_empty : std_logic;
signal afifo_rd_data_count : std_logic_vector(7 downto 0);
type MST_TRANS_STATE is (IDLE_WR, COUNTER_SET, MPMC_WRITE_ST);
signal cs_wr : MST_TRANS_STATE;
type MST_CMD_STATE is (IDLE_CMD, CMD_ASSORT, WAIT_TRANSACTION);
signal cs_cmd : MST_CMD_STATE;
signal trans_count, trans_val : std_logic_vector(4 downto 0);
type MST_SOF_STATE is (IDLE_SOF, SOF_ASSORT, SOF_HOLD);
signal cs_wr_sof : MST_SOF_STATE;
signal wr_sof : std_logic;
signal wr_eof : std_logic;
signal wr_src_rdy : std_logic;
signal mst_addr, addr_cnt : std_logic_vector(31 downto 0);
begin
IP2Bus_MstRd_Req <= '0';
IP2Bus_Mst_Lock <= '0';
IP2Bus_Mst_Reset <= '0';
IP2Bus_MstRd_dst_rdy_n <= '1';
IP2Bus_MstRd_dst_dsc_n <= '1';
dcm_CAM_clk_inst : dcm_CAM_clk port map(
sysclk => Bus2IP_Clk,
reset => Bus2IP_Reset,
clk_cam => clk_cam,
dcm_locked_out => dcm_locked
);
reset_cam_node <= not dcm_locked;
-- reset_cam を16クロック遅延される。クロックが出始めてすぐ、dcm_lockedが1になるため同期リセットFFがリセットされない。
SRL16E_SDA_ena : SRL16E generic map(
INIT => X"0000")
port map(
Q => reset_cam_srl,
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
CE => '1',
CLK => Bus2IP_Clk,
D => reset_cam_node
);
-- clk_cam で同期化
process(clk_cam) begin
if clk_cam'event and clk_cam='1' then
reset_cam_srl_1d <= reset_cam_srl;
reset_cam_srl_2d <= reset_cam_srl_1d;
end if;
end process;
reset_cam <= reset_cam_srl_2d;
cam_clk <= clk_cam;
process(clk_cam) begin
if clk_cam'event and clk_cam='1' then
if (reset_cam='1') then
cam_vsync_1d <= '0';
cam_vsync_2d <= '0';
cam_href_1d <= '0';
cam_href_2d <= '0';
cam_data_1d <= (others => '0');
cam_data_2d <= (others => '0');
else
cam_vsync_1d <= cam_vsync;
cam_vsync_2d <= cam_vsync_1d;
cam_href_1d <= cam_href;
cam_href_2d <= cam_href_1d;
cam_data_1d <= cam_data;
cam_data_2d <= cam_data_1d;
end if;
end if;
end process;
Camera_Cntrler_inst : Camera_Cntrler port map(
clk_cam => clk_cam,
clk_ddr2 => Bus2IP_Clk,
reset_cam => reset_cam,
reset_ddr2 => Bus2IP_Reset,
cam_href_2d => cam_href_2d,
cam_vsync_2d => cam_vsync_2d,
master_sync => master_sync,
cam_data_2d => cam_data_2d,
address => camc_addr,
data_out => camc_data,
addr_enable => addr_ena,
data_enable => data_ena,
capture_ena => '1',
afifo_empty => afifo_empty,
afifo_rd_data_count => afifo_rd_data_count,
afifo_overflow => afifo_overflow,
afifo_underflow => afifo_underflow
);
addr_ena <= '0';
synchronizer_inst : synchronizer port map(
clk => clk_cam,
reset => reset_cam,
cam_vsync_1d => cam_vsync_1d,
cam_href_1d => cam_href_1d,
master_sync => master_sync
);
-- afifo_rd_data_count が16以上になったらMPMCへWrite
process(Bus2IP_Clk) begin
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
if Bus2IP_Reset='1' then
cs_wr <= IDLE_WR;
else
case cs_wr is
when IDLE_WR =>
if afifo_rd_data_count(7 downto 4)/=0 then -- 16以上
cs_wr <= COUNTER_SET;
end if;
when COUNTER_SET =>
cs_wr <= MPMC_WRITE_ST;
when MPMC_WRITE_ST =>
if trans_count=0 then
cs_wr <= IDLE_WR;
end if;
end case;
end if;
end if;
end process;
IP2Bus_Mst_BE <= (others => '1');
IP2Bus_Mst_Length <= CONV_STD_LOGIC_VECTOR(64, 12); -- 128バイト、32ビット幅、16バースト
IP2Bus_MstWr_src_dsc_n <= '1';
IP2Bus_MstWr_rem <= (others => '0');
-- コマンド用ステートマシン
process(Bus2IP_Clk) begin
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
if Bus2IP_Reset='1' then
cs_cmd <= IDLE_CMD;
IP2Bus_MstWr_Req <= '0';
IP2Bus_Mst_Type <= '0';
else
case cs_cmd is
when IDLE_CMD =>
if cs_wr=COUNTER_SET then
cs_cmd <= CMD_ASSORT;
IP2Bus_MstWr_Req <= '1';
IP2Bus_Mst_Type <= '1';
end if;
when CMD_ASSORT =>
if Bus2IP_Mst_CmdAck='1' then
cs_cmd <= WAIT_TRANSACTION;
IP2Bus_MstWr_Req <= '0';
IP2Bus_Mst_Type <= '0';
end if;
when WAIT_TRANSACTION =>
if Bus2IP_Mst_Cmplt='1' then
cs_cmd <= IDLE_CMD;
IP2Bus_MstWr_Req <= '0';
IP2Bus_Mst_Type <= '0';
end if;
end case;
end if;
end if;
end process;
-- trans_count の処理
process(Bus2IP_Clk) begin
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
if Bus2IP_Reset='1' then
trans_count <= (others => '0');
trans_val <= (others => '0');
else
if cs_wr=COUNTER_SET then
trans_count <= "10000";
trans_val <= "10000";
elsif cs_wr=MPMC_WRITE_ST and trans_count/=0 and Bus2IP_MstWr_dst_rdy_n='0' then
trans_count <= trans_count - 1;
elsif cs_wr=IDLE_WR then
trans_val <= (others => '0');
end if;
end if;
end if;
end process;
-- IP2Bus_MstWr_sof_n のアサート
process(Bus2IP_Clk) begin
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
if Bus2IP_Reset='1' then
cs_wr_sof <= IDLE_SOF;
wr_sof <= '0';
else
case cs_wr_sof is
when IDLE_SOF =>
if cs_wr=COUNTER_SET then
cs_wr_sof <= SOF_ASSORT;
wr_sof <= '1';
end if;
when SOF_ASSORT =>
if cs_wr=MPMC_WRITE_ST and trans_val=trans_count and Bus2IP_MstWr_dst_rdy_n='0' then
cs_wr_sof <= SOF_HOLD;
wr_sof <= '0';
end if;
when SOF_HOLD =>
if cs_wr=MPMC_WRITE_ST and trans_count=0 then
cs_wr_sof <= IDLE_SOF;
wr_sof <= '0';
end if;
end case;
end if;
end if;
end process;
IP2Bus_MstWr_sof_n <= not wr_sof;
-- IP2Bus_MstWr_eof_n のアサート
process(Bus2IP_Clk) begin
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
if Bus2IP_Reset='1' then
wr_eof <= '0';
elsif trans_count=2 and Bus2IP_MstWr_dst_rdy_n='0' then
wr_eof <= '1';
elsif trans_count=1 and Bus2IP_MstWr_dst_rdy_n='0' then
wr_eof <= '0';
end if;
end if;
end process;
IP2Bus_MstWr_eof_n <= not wr_eof;
-- IP2Bus_MstWr_src_rdy_n のアサート
process(Bus2IP_Clk) begin
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
if Bus2IP_Reset='1' then
wr_src_rdy <= '0';
elsif cs_wr=COUNTER_SET then
wr_src_rdy <= '1';
elsif trans_count=1 and Bus2IP_MstWr_dst_rdy_n='0' then
wr_src_rdy <= '0';
end if;
end if;
end process;
IP2Bus_MstWr_src_rdy_n <= not wr_src_rdy;
IP2Bus_MstWr_d <= camc_data;
-- addr_cnt の処理
process(Bus2IP_Clk) begin
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
if Bus2IP_Reset='1' then
addr_cnt <= DDR2_SDRAM_ADDR_START;
else
if cam_vsync_1d='1' then
addr_cnt <= DDR2_SDRAM_ADDR_START;
elsif wr_src_rdy='1' and Bus2IP_MstWr_dst_rdy_n='0' then
addr_cnt <= addr_cnt + 4;
end if;
end if;
end if;
end process;
-- mst_addr の処理、コマンド転送の初めにaddr_cnt をmst_addr にコピーする
process(Bus2IP_Clk) begin
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
if Bus2IP_Reset='1' then
mst_addr <= DDR2_SDRAM_ADDR_START;
else
if cs_wr=COUNTER_SET then
mst_addr <= addr_cnt;
end if;
end if;
end if;
end process;
IP2Bus_Mst_Addr <= mst_addr;
data_ena <= '1' when wr_src_rdy='1' and Bus2IP_MstWr_dst_rdy_n='0' else '0';
end RTL;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Cam_Controller_Top_tb IS
END Cam_Controller_Top_tb;
ARCHITECTURE behavior OF Cam_Controller_Top_tb IS
constant C_MST_DWIDTH : integer := 32;
-- wait を入れるバースト位置、バーストの最初でwaitすることはできない。0を入れるとwaitはなしになる
constant RDY_WAIT_VAL1 : integer := 10;
constant RDY_WAIT_VAL2 : integer := 5;
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Cam_Controller_Top
generic(
C_SLV_DWIDTH : integer := 32;
C_MST_AWIDTH : integer := 32;
C_MST_DWIDTH : integer := 32;
C_NUM_REG : integer := 3
);
PORT(
cam_href : IN std_logic;
cam_vsync : IN std_logic;
cam_pclk : IN std_logic;
cam_data : IN std_logic_vector(7 downto 0);
cam_clk : OUT std_logic;
Bus2IP_Clk : IN std_logic;
Bus2IP_Reset : IN std_logic;
IP2Bus_MstRd_Req : OUT std_logic;
IP2Bus_MstWr_Req : OUT std_logic;
IP2Bus_Mst_Addr : OUT std_logic_vector(0 to 31);
IP2Bus_Mst_BE : OUT std_logic_vector(0 to C_MST_DWIDTH/8-1);
IP2Bus_Mst_Length : OUT std_logic_vector(0 to 11);
IP2Bus_Mst_Type : OUT std_logic;
IP2Bus_Mst_Lock : OUT std_logic;
IP2Bus_Mst_Reset : OUT std_logic;
Bus2IP_Mst_CmdAck : IN std_logic;
Bus2IP_Mst_Cmplt : IN std_logic;
Bus2IP_Mst_Error : IN std_logic;
Bus2IP_Mst_Rearbitrate : IN std_logic;
Bus2IP_Mst_Cmd_Timeout : IN std_logic;
IP2Bus_MstWr_d : OUT std_logic_vector(0 to C_MST_DWIDTH-1);
IP2Bus_MstWr_rem : OUT std_logic_vector(0 to C_MST_DWIDTH/8-1);
IP2Bus_MstWr_sof_n : OUT std_logic;
IP2Bus_MstWr_eof_n : OUT std_logic;
IP2Bus_MstWr_src_rdy_n : OUT std_logic;
IP2Bus_MstWr_src_dsc_n : OUT std_logic;
Bus2IP_MstWr_dst_rdy_n : IN std_logic;
Bus2IP_MstWr_dst_dsc_n : IN std_logic;
IP2Bus_MstRd_dst_rdy_n : OUT std_logic;
IP2Bus_MstRd_dst_dsc_n : OUT std_logic;
afifo_overflow : OUT std_logic;
afifo_underflow : OUT std_logic
);
END COMPONENT;
component OV7670_Model
port(
clk : in std_logic;
resetx : in std_logic;
vsync : out std_logic;
href : out std_logic;
pclk : out std_logic;
ydata : out std_logic_vector(7 downto 0)
);
end component;
--Inputs
signal cam_href : std_logic := '0';
signal cam_vsync : std_logic := '0';
signal cam_pclk : std_logic := '0';
signal cam_data : std_logic_vector(7 downto 0) := (others => '0');
signal Bus2IP_Clk : std_logic := '0';
signal Bus2IP_Reset : std_logic := '0';
signal Bus2IP_Mst_CmdAck : std_logic := '0';
signal Bus2IP_Mst_Cmplt : std_logic := '0';
signal Bus2IP_Mst_Error : std_logic := '0';
signal Bus2IP_Mst_Rearbitrate : std_logic := '0';
signal Bus2IP_Mst_Cmd_Timeout : std_logic := '0';
signal Bus2IP_MstWr_dst_rdy_n : std_logic := '1';
signal Bus2IP_MstWr_dst_dsc_n : std_logic := '1';
--Outputs
signal cam_clk : std_logic;
signal IP2Bus_MstRd_Req : std_logic;
signal IP2Bus_MstWr_Req : std_logic;
signal IP2Bus_Mst_Addr : std_logic_vector(0 to 31);
signal IP2Bus_Mst_BE : std_logic_vector(0 to 3);
signal IP2Bus_Mst_Length : std_logic_vector(0 to 11);
signal IP2Bus_Mst_Type : std_logic;
signal IP2Bus_Mst_Lock : std_logic;
signal IP2Bus_Mst_Reset : std_logic;
signal IP2Bus_MstWr_d : std_logic_vector(0 to 31);
signal IP2Bus_MstWr_rem : std_logic_vector(0 to 3);
signal IP2Bus_MstWr_sof_n : std_logic;
signal IP2Bus_MstWr_eof_n : std_logic;
signal IP2Bus_MstWr_src_rdy_n : std_logic;
signal IP2Bus_MstWr_src_dsc_n : std_logic;
signal IP2Bus_MstRd_dst_rdy_n : std_logic;
signal IP2Bus_MstRd_dst_dsc_n : std_logic;
signal afifo_overflow : std_logic;
signal afifo_underflow : std_logic;
type CMD_ACK_STATE is (IDLE_CMD_ACK, CMD_TRANS_1, CMD_TRANS_2, CMD_TRANS_3, CMD_TRANS_4, CMD_ACK_ST);
signal cs_cmd_ack : CMD_ACK_STATE;
signal cmd_ack : std_logic;
type MST_WR_TRANS_STATE is (IDLE_MST_D, LOAD_COUNT_MST_D, MST_WR_TRANS_ST, COMPLETE_MST_D);
signal cs_mst_d : MST_WR_TRANS_STATE;
signal mst_wr_cnt, mst_length : std_logic_vector(11 downto 0);
signal cam_resetx : std_logic;
-- Clock period definitions
constant Bus2IP_Clk_period : time := 16 ns; -- 62.5MHz
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Cam_Controller_Top
generic map(
C_MST_AWIDTH => 32,
C_MST_DWIDTH => C_MST_DWIDTH
) PORT MAP (
cam_href => cam_href,
cam_vsync => cam_vsync,
cam_pclk => cam_pclk,
cam_data => cam_data,
cam_clk => cam_clk,
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Reset => Bus2IP_Reset,
IP2Bus_MstRd_Req => IP2Bus_MstRd_Req,
IP2Bus_MstWr_Req => IP2Bus_MstWr_Req,
IP2Bus_Mst_Addr => IP2Bus_Mst_Addr,
IP2Bus_Mst_BE => IP2Bus_Mst_BE,
IP2Bus_Mst_Length => IP2Bus_Mst_Length,
IP2Bus_Mst_Type => IP2Bus_Mst_Type,
IP2Bus_Mst_Lock => IP2Bus_Mst_Lock,
IP2Bus_Mst_Reset => IP2Bus_Mst_Reset,
Bus2IP_Mst_CmdAck => Bus2IP_Mst_CmdAck,
Bus2IP_Mst_Cmplt => Bus2IP_Mst_Cmplt,
Bus2IP_Mst_Error => Bus2IP_Mst_Error,
Bus2IP_Mst_Rearbitrate => Bus2IP_Mst_Rearbitrate,
Bus2IP_Mst_Cmd_Timeout => Bus2IP_Mst_Cmd_Timeout,
IP2Bus_MstWr_d => IP2Bus_MstWr_d,
IP2Bus_MstWr_rem => IP2Bus_MstWr_rem,
IP2Bus_MstWr_sof_n => IP2Bus_MstWr_sof_n,
IP2Bus_MstWr_eof_n => IP2Bus_MstWr_eof_n,
IP2Bus_MstWr_src_rdy_n => IP2Bus_MstWr_src_rdy_n,
IP2Bus_MstWr_src_dsc_n => IP2Bus_MstWr_src_dsc_n,
Bus2IP_MstWr_dst_rdy_n => Bus2IP_MstWr_dst_rdy_n,
Bus2IP_MstWr_dst_dsc_n => Bus2IP_MstWr_dst_dsc_n,
IP2Bus_MstRd_dst_rdy_n => IP2Bus_MstRd_dst_rdy_n,
IP2Bus_MstRd_dst_dsc_n => IP2Bus_MstRd_dst_dsc_n,
afifo_overflow => afifo_overflow,
afifo_underflow => afifo_underflow
);
-- Clock process definitions
Bus2IP_Clk_process :process
begin
Bus2IP_Clk <= '0';
wait for Bus2IP_Clk_period/2;
Bus2IP_Clk <= '1';
wait for Bus2IP_Clk_period/2;
end process;
-- IPIC のマスタRead, Writeの対応をするモジュール、バースト対応のみ
-- まず、コマンド転送に応答して、Bus2IP_Mst_CmdAck を返す
process(Bus2IP_Clk) begin
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
if Bus2IP_Reset='1' then
cs_cmd_ack <= IDLE_CMD_ACK;
cmd_ack <= '0';
else
case cs_cmd_ack is
when IDLE_CMD_ACK =>
if IP2Bus_MstRd_Req='1' or IP2Bus_MstWr_Req='1' then
cs_cmd_ack <= CMD_TRANS_1;
end if;
when CMD_TRANS_1 =>
cs_cmd_ack <= CMD_TRANS_2;
when CMD_TRANS_2 =>
cs_cmd_ack <= CMD_TRANS_3;
when CMD_TRANS_3 =>
cs_cmd_ack <= CMD_TRANS_4;
when CMD_TRANS_4 =>
cs_cmd_ack <= CMD_ACK_ST;
cmd_ack <= '1';
when CMD_ACK_ST =>
cs_cmd_ack <= IDLE_CMD_ACK;
cmd_ack <= '0';
end case;
end if;
end if;
end process;
Bus2IP_Mst_CmdAck <= cmd_ack;
-- バーストWriteを受ける
-- IP2Bus_Mst_Lengthはバイト単位なので、C_MST_DWIDTH/8 で割ってバースト長を計算する
-- データ転送の状態を表すステートマシン
process(Bus2IP_Clk) begin
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
if Bus2IP_Reset='1' then
cs_mst_d <= IDLE_MST_D;
Bus2IP_Mst_Cmplt <= '0';
else
case cs_mst_d is
when IDLE_MST_D =>
Bus2IP_Mst_Cmplt <= '0';
if IP2Bus_MstWr_Req='1' then
cs_mst_d <= LOAD_COUNT_MST_D;
end if;
when LOAD_COUNT_MST_D =>
cs_mst_d <= MST_WR_TRANS_ST;
when MST_WR_TRANS_ST =>
if mst_wr_cnt=(C_MST_DWIDTH/8) and IP2Bus_MstWr_src_rdy_n='0' and Bus2IP_MstWr_dst_rdy_n='0' then
cs_mst_d <= COMPLETE_MST_D;
Bus2IP_Mst_Cmplt <= '1';
end if;
when COMPLETE_MST_D =>
cs_mst_d <= IDLE_MST_D;
Bus2IP_Mst_Cmplt <= '0';
end case;
end if;
end if;
end process;
-- mst_wr_cnt の処理
process(Bus2IP_Clk) begin
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
if Bus2IP_Reset='1' then
mst_wr_cnt <= (others => '0');
mst_length <= (others => '0');
Bus2IP_MstWr_dst_rdy_n <= '1';
else
if cs_mst_d=LOAD_COUNT_MST_D then
mst_wr_cnt <= IP2Bus_Mst_Length;
mst_length <= IP2Bus_Mst_Length;
Bus2IP_MstWr_dst_rdy_n <= '0';
elsif cs_mst_d=MST_WR_TRANS_ST then
if Bus2IP_MstWr_dst_rdy_n='0' then
mst_wr_cnt <= mst_wr_cnt - (C_MST_DWIDTH/8);
end if;
if mst_wr_cnt=((RDY_WAIT_VAL1+1)*(C_MST_DWIDTH/8)) and Bus2IP_MstWr_dst_rdy_n='0' then -- 1度wait
Bus2IP_MstWr_dst_rdy_n <= '1';
elsif mst_wr_cnt=((RDY_WAIT_VAL2+1)*(C_MST_DWIDTH/8)) and Bus2IP_MstWr_dst_rdy_n='0' then -- 1度wait
Bus2IP_MstWr_dst_rdy_n <= '1';
elsif mst_wr_cnt=(C_MST_DWIDTH/8) and IP2Bus_MstWr_src_rdy_n='0' and Bus2IP_MstWr_dst_rdy_n='0' then -- 最後なので、レディを1にする
Bus2IP_MstWr_dst_rdy_n <= '1';
else
Bus2IP_MstWr_dst_rdy_n <= '0';
end if;
else
Bus2IP_MstWr_dst_rdy_n <= '1';
end if;
end if;
end if;
end process;
Bus2IP_MstWr_dst_dsc_n <= '1';
Bus2IP_Mst_Error <= '0';
Bus2IP_Mst_Rearbitrate <= '0';
Bus2IP_Mst_Cmd_Timeout <= '0';
-- OV7670_Model のインスタンス
cam_resetx <= not Bus2IP_Reset;
OV7670_Model_inst : OV7670_Model port map(
clk => cam_clk,
resetx => cam_resetx,
vsync => cam_vsync,
href => cam_href,
pclk => cam_pclk,
ydata => cam_data
);
-- Stimulus process
stim_proc: process
begin
Bus2IP_Reset <= '1';
-- hold reset state for 100 ns.
wait for 100 ns;
wait for Bus2IP_Clk_period*10;
Bus2IP_Reset <= '0';
-- insert stimulus here
wait;
end process;
END;
| 日 | 月 | 火 | 水 | 木 | 金 | 土 |
|---|---|---|---|---|---|---|
| - | - | - | - | 1 | 2 | 3 |
| 4 | 5 | 6 | 7 | 8 | 9 | 10 |
| 11 | 12 | 13 | 14 | 15 | 16 | 17 |
| 18 | 19 | 20 | 21 | 22 | 23 | 24 |
| 25 | 26 | 27 | 28 | 29 | 30 | - |