-- lcd_ctlr.vhd を接続
-- data_ena を生成する
process( Bus2IP_Clk ) begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
data_ena <= '0';
else
if slv_reg_write_sel="1" then
data_ena <= '1';
else
data_ena <= '0';
end if;
end if;
end if;
end process;
LCD_ctlr_i : LCD_ctlr port map (
CLK => Bus2IP_Clk,
RESET => Bus2IP_Reset,
DIN => slv_reg0(C_SLV_DWIDTH-1-15 to C_SLV_DWIDTH-1); -- 下位16ビット
CS => data_ena,
LCD_DB => LCD_DB,
LCD_RS => LCD_RS,
LCD_RW => LCD_RW,
LCD_E => LCD_E
);
entity lcd_controller is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
...
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
LCD_DB : out std_logic_vector(7 downto 0);
LCD_RS : out std_logic;
LCD_RW : out std_logic;
LCD_E : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
PORT rot_a = "", DIR = I
PORT rot_b = "", DIR = I
PORT rot_center = "", DIR = I
PORT LCD_DB = "", DIR = O, VEC = [7:0]
PORT LCD_RS = "", DIR = O
PORT LCD_RW = "", DIR = O
PORT LCD_E = "", DIR = O
WARNING:EDK:2137 - Peripheral rotary_encoder_0 is not accessible from any processor in the system. Check Bus Interface connections and address parameters.
WARNING:EDK:2137 - Peripheral lcd_controller_0 is not accessible from any processor in the system. Check Bus Interface connections and address parameters.
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