信号名 | 信号ソース | 使用条件 | 信号の役割 | 注意事項 |
---|---|---|---|---|
TVALID | Master | 必須 | Master が有効な転送を送っていることを示す。TVALIDとTREADYが1の時が有効なデータ転送。 | |
TREADY | Slave | オプション | Slave は現在のサイクルのデータ転送を受け入れることを示す。 | 使用は任意だが、強く推奨 |
TDATA | Master | オプション | ストリームデータ。バイト単位 | |
TSTRB | Master | オプション | バイト・イネーブル。該当するバイトが有効かどうかを示す。 | スパース・ストリーム信号で使用可能 |
TKEEP | Master | 未使用 | 対応するバイトがSlaveに転送されるか、NULLバイトとしてストリームから削除されるかを示す。TRTRBとどう違う? | |
TLAST | Master | オプション | パケット境界を示す。例えば、複素数で、実数、虚数と送るとすると虚数を送るときにアサートする。パケットがない場合はアサート | |
TID | Master | オプション | データ・ストリームID。データ・ストリーム種類 | エンドポイントIPでは使用されない。インフラストラクチャIPで使用可能 |
TDEST | Master | オプション | データストリームのルーティング情報 | エンドポイントIPでは使用されない。インフラストラクチャIPで使用可能 |
TURER | Master | オプション | データストリームと同時に転送できるユーザー定義のサイドバンド情報 |
// autocorrelation.cpp : コンソール アプリケーションのエントリ ポイントを定義します。
//
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <iostream>
#include <cstring>
#include "stdafx.h"
// 1 になっているビットを数える
int count_bit(unsigned int val){
int count=0;
for (int i=0; i<(sizeof(val)*8); i++){
if (val & 1)
count++;
val >>= 1;
}
return count;
}
int _tmain(int argc, _TCHAR* argv[])
{
unsigned int data[2050];
FILE *wfp, *rfp;
int i, j, k;
int retval;
unsigned int xnor_val;
int sum;
char readfile[100], writefile[100], width_num_s[50];
size_t r_ret_val, w_ret_val, wid_ret_val;
int width_num;
if (argc < 3){
fprintf(stderr, "Usage : autocorrelation \"width_num\" \"input data file name\" <output file name>\n");
exit(1);
} else {
wcstombs_s(&wid_ret_val, width_num_s, argv[1], sizeof(width_num_s));
wcstombs_s(&r_ret_val, readfile, argv[2], sizeof(readfile));
if (argc == 3) // width_num + read file
strcpy_s(writefile, sizeof(writefile), "autocorre.txt");
else
wcstombs_s(&w_ret_val, writefile, argv[3], sizeof(writefile));
}
if (fopen_s(&rfp, readfile, "r") != 0){ // 自己相関を取るデータファイルをオープン
fprintf(stderr, "%s read file open error!\n", readfile);
exit(1);
}
if (fopen_s(&wfp, writefile, "w") != 0){ // 自己相関をとった結果を格納するログファイルをオープン
fprintf(stderr, "%s write file open error!\n", writefile);
exit(1);
}
sscanf_s(width_num_s, "%d", &width_num, sizeof(int));
for (i=0; i<2000; i++){ // データの読み込み
retval = fscanf_s(rfp, "%x\n", &data[i]);
if (retval == EOF){
fprintf(stderr, "data read error!\n");
exit(1);
}
}
fclose(rfp);
// 最初にwidth_num個(data[0]~data[999])のデータの自分自身とのXNORを取り、1になる数を調べる。この値は32 x width_num 個のはず。
// 次に、最初にwidth_num個(data[0]~data[width_num-1])と位置を1つずらしたwidth_num個(data[1]~data[width_num])のXNORを取り、1になる数を調べる。
// これを1000回行う
for (i=0; i<1000; i++){
sum = 0;
for (j=0, k=i; j<width_num; j++, k++){
xnor_val = ~(data[j] ^ data[k]);
sum += count_bit(xnor_val);
}
fprintf(wfp, "%d\n", sum);
}
fclose(wfp);
return 0;
}
32000
16123
15910
16084
15946
16009
16083
16089
16003
16016
15959
16042
15934
16067
15982
16091
32000
15606
16306
16102
16306
15980
16337
15816
16480
16831
15360
16765
14963
15764
15700
15600
17163
17070
// M sequence test(m_seq_32.v)
`default_nettype none
module m_seq_32(
input wire clk,
input wire reset,
output reg [31:0] mseq32
);
function [31:0] mseqf32 (input [31:0] din);
reg xor_result;
begin
xor_result = din[31] ^ din[21] ^ din[1] ^ din[0];
mseqf32 = {din[30:0], xor_result};
end
endfunction
always @(posedge clk) begin
if (reset)
mseq32 <= 32'h789ABCDE;
else
mseq32 <= mseqf32(mseq32);
end
endmodule
`default_nettype wire
// m_seq_32_test_tb.v
// m_seq_32.v のテスト
// 2000個のM系列の出力をRAMDOM_NUM_LIMIT個、ファイルに書き出す
//
`default_nettype none
`timescale 100ps / 1ps
module m_seq_32_test_tb;
parameter RAMDOM_NUM_LIMIT = 2000;
integer F_HANDLE;
integer count = 0;
wire clk;
wire reset;
wire [31:0] result;
// clk のインスタンス
clk_gen #(
.CLK_PERIOD(100), // 10nsec, 100MHz
.CLK_DUTY_CYCLE(0.5),
.CLK_OFFSET(0),
.START_STATE(1'b0)
) ACLKi (
.clk_out(clk)
);
// reset_gen のインスタンス
reset_gen #(
.RESET_STATE(1'b1),
.RESET_TIME(1000) // 100nsec
) RESETi (
.reset_out(reset)
);
// m_seq_32 のインスタンス
m_seq_32 m_seq_32_i (
.clk(clk),
.reset(reset),
.mseq32(result)
);
initial F_HANDLE = $fopen("mseq32_dump.log");
always @(posedge clk) begin
if (reset == 1'b0) begin
if (count < RAMDOM_NUM_LIMIT) begin
#1;
$fdisplay(F_HANDLE, "%x", result);
count = count + 1;
end else begin
$fclose(F_HANDLE);
$stop;
end
end
end
endmodule
module clk_gen #(
parameter CLK_PERIOD = 100,
parameter real CLK_DUTY_CYCLE = 0.5,
parameter CLK_OFFSET = 0,
parameter START_STATE = 1'b0 )
(
output reg clk_out
);
begin
initial begin
#CLK_OFFSET;
forever
begin
clk_out = START_STATE;
#(CLK_PERIOD-(CLK_PERIOD*CLK_DUTY_CYCLE)) clk_out = ~START_STATE;
#(CLK_PERIOD*CLK_DUTY_CYCLE);
end
end
end
endmodule
module reset_gen #(
parameter RESET_STATE = 1'b1,
parameter RESET_TIME = 100 )
(
output reg reset_out
);
begin
initial begin
reset_out = RESET_STATE;
#RESET_TIME;
reset_out = ~RESET_STATE;
end
end
endmodule
`default_nettype wire
f13579bd
e26af37b
c4d5e6f6
89abcdec
13579bd8
26af37b0
4d5e6f61
9abcdec3
3579bd86
6af37b0c
d5e6f619
abcdec33
579bd867
af37b0ce
5e6f619d
bcdec33a
79bd8674
f37b0ce9
e6f619d3
cdec33a6
00000003
00000006
0000000d
0000001b
00000036
0000006d
000000db
000001b6
0000036d
000006db
00000db6
00001b6d
000036db
00006db6
0000db6d
0001b6db
00036db6
0006db6d
000db6db
001b6db6
0036db6d
006db6da
00db6db4
01b6db68
036db6d1
06db6da2
0db6db45
1b6db68a
aaaaaaab
55555556
aaaaaaad
5555555b
aaaaaab6
5555556d
aaaaaadb
555555b6
aaaaab6d
555556db
aaaaadb6
55555b6d
aaaab6db
55556db6
aaaadb6d
5555b6db
aaab6db6
5556db6d
aaadb6db
555b6db6
aab6db6d
556db6db
aadb6db7
-- XORShift.vhd
-- 擬似乱数発生回路
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
entity XORShift is
port(
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
result : out std_logic_vector(31 downto 0)
);
end XORShift;
architecture RTL of XORShift is
signal x: unsigned(31 downto 0);
signal y: unsigned(31 downto 0);
signal z: unsigned(31 downto 0);
signal w: unsigned(31 downto 0);
begin
process(clk)
variable t: unsigned(31 downto 0);
begin
if clk'event and clk='1' then
if reset='1' then
x <= TO_UNSIGNED(123456789, 32);
y <= TO_UNSIGNED(362436069, 32);
z <= TO_UNSIGNED(521288629, 32);
w <= TO_UNSIGNED(88675123, 32);
elsif enable='1' then
t := x xor (x(20 downto 0) & TO_UNSIGNED(0, 11));
x <= y;
y <= z;
z <= w;
w <= (w xor (TO_UNSIGNED(0, 19) & w(31 downto 19))) xor (t xor (TO_UNSIGNED(0, 8) & t(31 downto 8)));
end if;
end if;
end process;
result <= STD_LOGIC_VECTOR(w);
end RTL;
// XORShift_test_tb.v
// XORShift.vhd のテスト
// 2000個のXORShiftの出力をRAMDOM_NUM_LIMIT個、ファイルに書き出す
//
`default_nettype none
`timescale 100ps / 1ps
module XORShift_test_tb;
parameter RAMDOM_NUM_LIMIT = 2000;
integer F_HANDLE;
integer count = 0;
wire clk;
wire reset;
wire [31:0] result;
// clk のインスタンス
clk_gen #(
.CLK_PERIOD(100), // 10nsec, 100MHz
.CLK_DUTY_CYCLE(0.5),
.CLK_OFFSET(0),
.START_STATE(1'b0)
) ACLKi (
.clk_out(clk)
);
// reset_gen のインスタンス
reset_gen #(
.RESET_STATE(1'b1),
.RESET_TIME(1000) // 100nsec
) RESETi (
.reset_out(reset)
);
// XORShift のインスタンス
XORShift XORShift_i (
.clk(clk),
.reset(reset),
.enable(1'b1),
.result(result)
);
initial F_HANDLE = $fopen("XORShift_dump.log");
always @(posedge clk) begin
if (reset == 1'b0) begin
if (count < RAMDOM_NUM_LIMIT) begin
#1;
$fdisplay(F_HANDLE, "%x", result);
count = count + 1;
end else begin
$fclose(F_HANDLE);
$stop;
end
end
end
endmodule
module clk_gen #(
parameter CLK_PERIOD = 100,
parameter real CLK_DUTY_CYCLE = 0.5,
parameter CLK_OFFSET = 0,
parameter START_STATE = 1'b0 )
(
output reg clk_out
);
begin
initial begin
#CLK_OFFSET;
forever
begin
clk_out = START_STATE;
#(CLK_PERIOD-(CLK_PERIOD*CLK_DUTY_CYCLE)) clk_out = ~START_STATE;
#(CLK_PERIOD*CLK_DUTY_CYCLE);
end
end
end
endmodule
module reset_gen #(
parameter RESET_STATE = 1'b1,
parameter RESET_TIME = 100 )
(
output reg reset_out
);
begin
initial begin
reset_out = RESET_STATE;
#RESET_TIME;
reset_out = ~RESET_STATE;
end
end
endmodule
`default_nettype wire
dca345ea
1b5116e6
951049aa
d88d00b0
1ec7825e
8db24146
9af81443
2ac00f2c
0837ad58
17906569
4d9031d4
6703ee25
d2ebd2f0
46c45ee9
8a16d974
f21c7cd5
7eec4c34
1abb6616
265ac14c
// cam_disp3_linux.c
//
// GPIOを1にして、カメラ表示回路を生かし、MT9D111の設定レジスタにRGB565を設定する
//
// 2013/02/11
// 2013/04/20 : カメラ・インターフェイスIPとビットマップ・ディスプレイ・コントローラIPのフレームバッファ・スタート・レジスタに
// Linuxの既存のフレームバッファのアドレスをWrite するように変更。
//
#define XPAR_AXI_GPIO_0_BASEADDR 0x44000000
#define XPAR_AXI_IIC_MT9D111_BASEADDR 0x45000000
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <dirent.h>
#include <fcntl.h>
#include <assert.h>
#include <ctype.h>
#include <sys/mman.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <unistd.h>
#define PAGE_SIZE (4*1024)
#define BLOCK_SIZE (4*1024)
#define BUFSIZE 1024
// I/O access
volatile unsigned *setup_io(off_t addr);
int chkhex(char *str);
volatile unsigned *cam_i2c_control_reg;
volatile unsigned *cam_i2c_status_reg;
volatile unsigned *cam_i2c_tx_fifo;
volatile unsigned *cam_i2c_rx_fifo;
void cam_i2c_init(void) {
*cam_i2c_control_reg = 0x2; // reset tx fifo
*cam_i2c_control_reg = 0x1; // enable i2c
}
void cam_i2x_write_sync(void) {
// unsigned c;
// c = *cam_i2c_rx_fifo;
// while ((c & 0x84) != 0x80)
// c = *cam_i2c_rx_fifo; // No Bus Busy and TX_FIFO_Empty = 1
usleep(1000);
}
void cam_i2c_write(unsigned int device_addr, unsigned int write_addr, unsigned int write_data){
*cam_i2c_tx_fifo = 0x100 | (device_addr & 0xfe); // Slave IIC Write Address
*cam_i2c_tx_fifo = write_addr;
*cam_i2c_tx_fifo = (write_data >> 8)|0xff; // first data
*cam_i2c_tx_fifo = 0x200 | (write_data & 0xff); // second data
cam_i2x_write_sync();
}
int main()
{
volatile unsigned *cam_i2c, *axi_gpio;
volatile unsigned *axi_gpio_tri;
FILE *fd;
char buf[BUFSIZE], *token;
char *str0x;
unsigned int read_num;
unsigned int mt9d111_reg_addr, bitmap_dc_reg_addr;
volatile unsigned *mt9d111_inf_reg;
volatile unsigned *bm_disp_cnt_reg;
unsigned int fb_addr;
unsigned int val;
cam_i2c = setup_io((off_t)XPAR_AXI_IIC_MT9D111_BASEADDR);
axi_gpio = setup_io((off_t)XPAR_AXI_GPIO_0_BASEADDR);
cam_i2c_control_reg = cam_i2c + 0x40; // 0x100番地
cam_i2c_status_reg = cam_i2c + 0x41; // 0x104番地
cam_i2c_tx_fifo = cam_i2c + 0x42; // 0x108番地
cam_i2c_rx_fifo = cam_i2c + 0x43; // 0x10C番地
axi_gpio_tri = axi_gpio + 0x1; // 0x4番地
// フレームバッファのアドレスを取得
memset(buf, '\0', sizeof(buf)); // buf すべてに\0 を入れる
// dmesg で、fbi->fix.smem_start の書いてある行をパイプに入れる
fd = popen("dmesg | grep \"fbi->fix.smem_start\"", "r");
if (fd != NULL){ // fbi->fix.smem_start の値を抽出
read_num = fread(buf, sizeof(unsigned char), BUFSIZE, fd);
if (read_num > 0){
if ((str0x = strstr(buf, "0x")) != NULL){
str0x += 2;
sscanf(str0x, "%x\n", &fb_addr);
}
}
}
pclose(fd);
// mt9d111-inf-axi-master と bitmap-disp-cntrler-axi-master のアドレスを取得
memset(buf, '\0', sizeof(buf)); // buf すべてに\0 を入れる
// ls /sys/devices/axi.0 の内容をパイプに入れる
fd = popen("ls /sys/devices/axi.0", "r");
if (fd != NULL){
read_num = fread(buf, sizeof(unsigned char), BUFSIZE, fd);
if (read_num > 0){
token = buf;
if ((token=strtok(token, ".\n")) != NULL){
do {
if (chkhex(token)){ // 16進数
sscanf(token, "%x", &val);
} else {
if (strcmp(token, "mt9d111-inf-axi-master") == 0)
mt9d111_reg_addr = val;
else if (strcmp(token, "bitmap-disp-cntrler-axi-master") == 0)
bitmap_dc_reg_addr = val;
}
}while((token=strtok(NULL, ".\n")) != NULL);
}
}
}
pclose(fd);
mt9d111_inf_reg = setup_io((off_t)mt9d111_reg_addr);
bm_disp_cnt_reg = setup_io((off_t)bitmap_dc_reg_addr);
// フレームバッファのアドレスをAXI4 Lite Slave 経由でレジスタにWrite
fb_addr = fb_addr + (140 * 1920 * 4); // 2頭のペンギンが表示されるようにペンギンの描画領域を外す。140ライン飛ばす
*bm_disp_cnt_reg = fb_addr;
*mt9d111_inf_reg = fb_addr;
// GPIOに1を書いて、カメラ表示回路を動作させる
*axi_gpio_tri = 0; // set output
*axi_gpio = 0x1; // output '1'
// CMOS Camera initialize, MT9D111
cam_i2c_init();
cam_i2c_write(0xba, 0xf0, 0x1); // IFP page 1 へレジスタ・マップを切り替える
cam_i2c_write(0xba, 0x97, 0x20); // RGB Mode, RGB565
return(0);
}
//
// Set up a memory regions to access GPIO
//
volatile unsigned *setup_io(off_t mapped_addr)
// void setup_io()
{
int mem_fd;
char *gpio_mem, *gpio_map;
/* open /dev/mem */
if ((mem_fd = open("/dev/mem", O_RDWR|O_SYNC) ) < 0) {
printf("can't open /dev/mem \n");
exit (-1);
}
/* mmap GPIO */
// Allocate MAP block
if ((gpio_mem = malloc(BLOCK_SIZE + (PAGE_SIZE-1))) == NULL) {
printf("allocation error \n");
exit (-1);
}
// Make sure pointer is on 4K boundary
if ((unsigned long)gpio_mem % PAGE_SIZE)
gpio_mem += PAGE_SIZE - ((unsigned long)gpio_mem % PAGE_SIZE);
// Now map it
gpio_map = (unsigned char *)mmap(
(caddr_t)gpio_mem,
BLOCK_SIZE,
PROT_READ|PROT_WRITE,
MAP_SHARED|MAP_FIXED,
mem_fd,
mapped_addr
);
if ((long)gpio_map < 0) {
printf("mmap error %d\n", (int)gpio_map);
exit (-1);
}
// Always use volatile pointer!
// gpio = (volatile unsigned *)gpio_map;
return((volatile unsigned *)gpio_map);
} // setup_io
// 文字列が16進数かを調べる
int chkhex(char *str){
while (*str != '\0'){
if (!isxdigit(*str))
return 0;
str++;
}
return 1;
}
Release 14.4 Map P.49d (nt64)
Xilinx Mapping Report File for Design 'system_top'
Design Information
------------------
Command Line : map -intstyle ise -p xc7z020-clg484-1 -w -logic_opt off -ol
high -t 1 -xt 0 -register_duplication off -r 4 -mt off -ir off -pr off -lc off
-power off -o system_top_map.ncd system_top.ngd system_top.pcf
Target Device : xc7z020
Target Package : clg484
Target Speed : -1
Mapper Version : zynq -- $Revision: 1.55 $
Mapped Date : FRI 19 APR 6:41:49 2013
Design Summary
--------------
Number of errors: 0
Number of warnings: 276
Slice Logic Utilization:
Number of Slice Registers: 18,637 out of 106,400 17%
Number used as Flip Flops: 18,543
Number used as Latches: 4
Number used as Latch-thrus: 0
Number used as AND/OR logics: 90
Number of Slice LUTs: 14,268 out of 53,200 26%
Number used as logic: 10,455 out of 53,200 19%
Number using O6 output only: 7,151
Number using O5 output only: 334
Number using O5 and O6: 2,970
Number used as ROM: 0
Number used as Memory: 2,579 out of 17,400 14%
Number used as Dual Port RAM: 498
Number using O6 output only: 114
Number using O5 output only: 14
Number using O5 and O6: 370
Number used as Single Port RAM: 0
Number used as Shift Register: 2,081
Number using O6 output only: 1,233
Number using O5 output only: 8
Number using O5 and O6: 840
Number used exclusively as route-thrus: 1,234
Number with same-slice register load: 994
Number with same-slice carry load: 239
Number with other load: 1
Slice Logic Distribution:
Number of occupied Slices: 7,161 out of 13,300 53%
Number of LUT Flip Flop pairs used: 21,697
Number with an unused Flip Flop: 5,567 out of 21,697 25%
Number with an unused LUT: 7,429 out of 21,697 34%
Number of fully used LUT-FF pairs: 8,701 out of 21,697 40%
Number of unique control sets: 1,012
Number of slice register sites lost
to control set restrictions: 4,368 out of 106,400 4%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
OVERMAPPING of BRAM resources should be ignored if the design is
over-mapped for a non-BRAM resource or if placement fails.
IO Utilization:
Number of bonded IOBs: 55 out of 200 27%
Number of LOCed IOBs: 55 out of 55 100%
Number of bonded IOPAD: 130 out of 130 100%
IOB Flip Flops: 16
Specific Feature Utilization:
Number of RAMB36E1/FIFO36E1s: 33 out of 140 23%
Number using RAMB36E1 only: 33
Number using FIFO36E1 only: 0
Number of RAMB18E1/FIFO18E1s: 2 out of 280 1%
Number using RAMB18E1 only: 2
Number using FIFO18E1 only: 0
Number of BUFG/BUFGCTRLs: 9 out of 32 28%
Number used as BUFGs: 9
Number used as BUFGCTRLs: 0
Number of IDELAYE2/IDELAYE2_FINEDELAYs: 0 out of 200 0%
Number of ILOGICE2/ILOGICE3/ISERDESE2s: 0 out of 200 0%
Number of ODELAYE2/ODELAYE2_FINEDELAYs: 0
Number of OLOGICE2/OLOGICE3/OSERDESE2s: 16 out of 200 8%
Number used as OLOGICE2s: 16
Number used as OLOGICE3s: 0
Number used as OSERDESE2s: 0
Number of PHASER_IN/PHASER_IN_PHYs: 0 out of 16 0%
Number of PHASER_OUT/PHASER_OUT_PHYs: 0 out of 16 0%
Number of BSCANs: 1 out of 4 25%
Number of BUFHCEs: 0 out of 72 0%
Number of BUFRs: 0 out of 16 0%
Number of CAPTUREs: 0 out of 1 0%
Number of DNA_PORTs: 0 out of 1 0%
Number of DSP48E1s: 0 out of 220 0%
Number of EFUSE_USRs: 0 out of 1 0%
Number of FRAME_ECCs: 0 out of 1 0%
Number of ICAPs: 0 out of 2 0%
Number of IDELAYCTRLs: 0 out of 4 0%
Number of IN_FIFOs: 0 out of 16 0%
Number of MMCME2_ADVs: 3 out of 4 75%
Number of OUT_FIFOs: 0 out of 16 0%
Number of PHASER_REFs: 0 out of 4 0%
Number of PHY_CONTROLs: 0 out of 4 0%
Number of PLLE2_ADVs: 0 out of 4 0%
Number of PS7s: 1 out of 1 100%
Number of STARTUPs: 0 out of 1 0%
Number of XADCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.15
Peak Memory Usage: 1349 MB
Total REAL time to MAP completion: 16 mins
Total CPU time to MAP completion: 15 mins 32 secs
誤
// AXI4 Lite Slave Write Transaction State Machine
always @(posedge aclk) begin
if (reset) begin
wrt_cs <= IDLE_WR;
awready <= 1'b1;
bvalid <= 1'b0;
end else begin
case (wrt_cs)
IDLE_WR :
if (s_axi_lite_awvalid & ~s_axi_lite_wvalid) begin // Write Transaction Start
wrt_cs <= DATA_WRITE_HOLD;
awready <= 1'b0;
end else if (s_axi_lite_awvalid & s_axi_lite_wvalid) begin // Write Transaction Start with data
wrt_cs <= BREADY_ASSERT;
awready <= 1'b0;
end
DATA_WRITE_HOLD :
if (s_axi_lite_wvalid) begin // Write data just valid
wrt_cs <= BREADY_ASSERT;
bvalid <= 1'b1;
end
BREADY_ASSERT :
if (s_axi_lite_bready) begin // The write transaction was terminated.
wrt_cs <= IDLE_WR;
bvalid <= 1'b0;
awready <= 1'b1;
end
endcase
end
end
正
// AXI4 Lite Slave Write Transaction State Machine
always @(posedge aclk) begin
if (reset) begin
wrt_cs <= IDLE_WR;
awready <= 1'b1;
bvalid <= 1'b0;
end else begin
case (wrt_cs)
IDLE_WR :
if (s_axi_lite_awvalid & ~s_axi_lite_wvalid) begin // Write Transaction Start
wrt_cs <= DATA_WRITE_HOLD;
awready <= 1'b0;
end else if (s_axi_lite_awvalid & s_axi_lite_wvalid) begin // Write Transaction Start with data
wrt_cs <= BREADY_ASSERT;
awready <= 1'b0;
bvalid <= 1'b1;
end
DATA_WRITE_HOLD :
if (s_axi_lite_wvalid) begin // Write data just valid
wrt_cs <= BREADY_ASSERT;
bvalid <= 1'b1;
end
BREADY_ASSERT :
if (s_axi_lite_bready) begin // The write transaction was terminated.
wrt_cs <= IDLE_WR;
bvalid <= 1'b0;
awready <= 1'b1;
end
endcase
end
end
PORT s_axi_lite_rdata = RDATA, DIR = O, VEC = [3-1:0], BUS = S_AXI_LITE, ENDIAN = LITTLE
PORT s_axi_lite_rdata = RDATA, DIR = O, VEC = [C_S_AXI_LITE_DATA_WIDTH-1:0], BUS = S_AXI_LITE, ENDIAN = LITTLE
[ 0.960000] fbi->fix.smem_start = 0x19000000
[ 1.370000] fbi->fix.smem_start = 0x19800000
// AXI_Lite_test_linux.c
//
// AXI Lite Slave interface check program for mt9d111_inf_axi_master IP and bitmap_disp_cntrler_axi_master IP.
//
// 2013/04/13
//
#define MT9D111_INF_BASEADDR 0x46000000
#define BITMAP_DISP_CNTRLER_BASEADDR 0x47000000
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <dirent.h>
#include <fcntl.h>
#include <assert.h>
#include <sys/mman.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <unistd.h>
#define PAGE_SIZE (4*1024)
#define BLOCK_SIZE (4*1024)
// I/O access
volatile unsigned *setup_io(off_t addr);
volatile unsigned *mt9d111_inf_reg;
volatile unsigned *bm_disp_cnt_reg;
int main()
{
volatile unsigned mt9d111_inf_reg_d, bm_disp_cnt_reg_d;
mt9d111_inf_reg = setup_io((off_t)MT9D111_INF_BASEADDR);
bm_disp_cnt_reg = setup_io((off_t)BITMAP_DISP_CNTRLER_BASEADDR);
mt9d111_inf_reg_d = *mt9d111_inf_reg;
bm_disp_cnt_reg_d = *bm_disp_cnt_reg;
*mt9d111_inf_reg = 0x19800000;
*bm_disp_cnt_reg = 0x19800000;
mt9d111_inf_reg_d = *mt9d111_inf_reg;
bm_disp_cnt_reg_d = *bm_disp_cnt_reg;
return 0;
}
//
// Set up a memory regions to access GPIO
//
volatile unsigned *setup_io(off_t mapped_addr)
// void setup_io()
{
int mem_fd;
char *gpio_mem, *gpio_map;
/* open /dev/mem */
if ((mem_fd = open("/dev/mem", O_RDWR|O_SYNC) ) < 0) {
printf("can't open /dev/mem \n");
exit (-1);
}
/* mmap GPIO */
// Allocate MAP block
if ((gpio_mem = malloc(BLOCK_SIZE + (PAGE_SIZE-1))) == NULL) {
printf("allocation error \n");
exit (-1);
}
// Make sure pointer is on 4K boundary
if ((unsigned long)gpio_mem % PAGE_SIZE)
gpio_mem += PAGE_SIZE - ((unsigned long)gpio_mem % PAGE_SIZE);
// Now map it
gpio_map = (unsigned char *)mmap(
(caddr_t)gpio_mem,
BLOCK_SIZE,
PROT_READ|PROT_WRITE,
MAP_SHARED|MAP_FIXED,
mem_fd,
mapped_addr
);
if ((long)gpio_map < 0) {
printf("mmap error %d\n", (int)gpio_map);
exit (-1);
}
// Always use volatile pointer!
// gpio = (volatile unsigned *)gpio_map;
return((volatile unsigned *)gpio_map);
} // setup_io
[ 0.990000] fbi->fix.smem_start = 0x19000000
U-Boot 2012.04.01-00297-gc319bf9-dirty (Sep 13 2012 - 09:30:49)
DRAM: 512 MiB
WARNING: Caches not enabled
MMC: SDHCI: 0
Using default environment
In: serial
Out: serial
Err: serial
Net: zynq_gem
Hit any key to stop autoboot: 0
Copying Linux from SD to RAM...
Device: SDHCI
Manufacturer ID: 73
OEM: 4247
Name: NCard
Tran Speed: 25000000
Rd Block Len: 512
SD version 1.0
High Capacity: Yes
Capacity: 7.5 GiB
Bus Width: 1-bit
reading zImage
2450208 bytes read
reading devicetree_ramdisk.dtb
6578 bytes read
reading ramdisk8M.image.gz
3699284 bytes read
## Starting application at 0x00008000 ...
Uncompressing Linux... done, booting the kernel.
[ 0.000000] Booting Linux on physical CPU 0
[ 0.000000] Linux version 3.6.0-digilent-13.01 (masaaki@masaaki-VirtualBox) (gcc version 4.6.3 (Sourcery CodeBench Lite 2012.03-79) ) #6 SMP PREEMPT Fri Mar 8 19:52:15 JST 2013
[ 0.000000] CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
[ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
[ 0.000000] Machine: Xilinx Zynq Platform, model: Xilinx Zynq ZED
[ 0.000000] bootconsole [earlycon0] enabled
[ 0.000000] Memory policy: ECC disabled, Data cache writealloc
[ 0.000000] BUG: mapping for 0xe0001000 at 0xfe001000 out of vmalloc space
[ 0.000000] PERCPU: Embedded 7 pages/cpu @c1408000 s6976 r8192 d13504 u32768
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 130048
[ 0.000000] Kernel command line: console=ttyPS0,115200 root=/dev/ram rw initrd=0x800000,8M earlyprintk rootfstype=ext4 rootwait devtmpfs.mount=0
[ 0.000000] PID hash table entries: 2048 (order: 1, 8192 bytes)
[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
[ 0.000000] Memory: 512MB = 512MB total
[ 0.000000] Memory: 506768k/506768k available, 17520k reserved, 0K highmem
[ 0.000000] Virtual kernel memory layout:
[ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB)
[ 0.000000] fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
[ 0.000000] vmalloc : 0xe0800000 - 0xfd000000 ( 456 MB)
[ 0.000000] lowmem : 0xc0000000 - 0xe0000000 ( 512 MB)
[ 0.000000] pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB)
[ 0.000000] modules : 0xbf000000 - 0xbfe00000 ( 14 MB)
[ 0.000000] .text : 0xc0008000 - 0xc0423984 (4207 kB)
[ 0.000000] .init : 0xc0424000 - 0xc0449b40 ( 151 kB)
[ 0.000000] .data : 0xc044a000 - 0xc04828e0 ( 227 kB)
[ 0.000000] .bss : 0xc0482904 - 0xc04990b0 ( 90 kB)
[ 0.000000] Preemptible hierarchical RCU implementation.
[ 0.000000] Dump stacks of tasks blocking RCU-preempt GP.
[ 0.000000] RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
[ 0.000000] NR_IRQS:512
[ 0.000000] Zynq clock init
[ 0.000000] xlnx,ps7-ttc-1.00.a #0 at 0xe0800000, irq=43
[ 0.000000] ------------[ cut here ]------------
[ 0.000000] WARNING: at arch/arm/kernel/smp_twd.c:389 time_init+0x20/0x30()
[ 0.000000] twd_local_timer_of_register failed (-19)
[ 0.000000] Modules linked in:
[ 0.000000] [] (unwind_backtrace+0x0/0xe0) from [ ] (warn_slowpath_common+0x4c/0x64)
[ 0.000000] [] (warn_slowpath_common+0x4c/0x64) from [ ] (warn_slowpath_fmt+0x2c/0x3c)
[ 0.000000] [] (warn_slowpath_fmt+0x2c/0x3c) from [ ] (time_init+0x20/0x30)
[ 0.000000] [] (time_init+0x20/0x30) from [ ] (start_kernel+0x1ac/0x2f0)
[ 0.000000] [] (start_kernel+0x1ac/0x2f0) from [<00008044>] (0x8044)
[ 0.000000] ---[ end trace 1b75b31a2719ed1c ]---
[ 0.000000] sched_clock: 32 bits at 100 Hz, resolution 10000000ns, wraps every 4294967286ms
[ 0.000000] Console: colour dummy device 80x30
[ 0.020000] Calibrating delay loop... 1332.01 BogoMIPS (lpj=6660096)
[ 0.110000] pid_max: default: 32768 minimum: 301
[ 0.110000] Mount-cache hash table entries: 512
[ 0.110000] CPU: Testing write buffer coherency: ok
[ 0.120000] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[ 0.120000] hw perfevents: enabled with ARMv7 Cortex-A9 PMU driver, 7 counters available
[ 0.120000] Setting up static identity map for 0x2ed340 - 0x2ed374
[ 0.130000] L310 cache controller enabled
[ 0.130000] l2x0: 8 ways, CACHE_ID 0x410000c8, AUX_CTRL 0x72360000, Cache size: 524288 B
[ 0.200000] Map SLCR registers
[ 0.200000] CPU1: Booted secondary processor
[ 0.290000] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
[ 0.290000] Brought up 2 CPUs
[ 0.290000] SMP: Total of 2 processors activated (2664.03 BogoMIPS).
[ 0.300000] devtmpfs: initialized
[ 0.300000] NET: Registered protocol family 16
[ 0.310000] DMA: preallocated 256 KiB pool for atomic coherent allocations
[ 0.320000] xgpiops e000a000.gpio: gpio at 0xe000a000 mapped to 0xe084a000
[ 0.320000] registering platform device 'pl330' id 0
[ 0.330000] registering platform device 'arm-pmu' id 0
[ 0.330000] registering platform device 'zynq-dvfs' id 0
[ 0.340000]
[ 0.340000] ###############################################
[ 0.340000] # #
[ 0.350000] # Board ZED Init #
[ 0.350000] # #
[ 0.360000] ###############################################
[ 0.360000]
[ 0.370000] hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
[ 0.380000] hw-breakpoint: maximum watchpoint size is 4 bytes.
[ 0.400000] xslcr xslcr.0: at 0xF8000000 mapped to 0xF8000000
[ 0.420000] bio: create slabat 0
[ 0.420000] SCSI subsystem initialized
[ 0.420000] usbcore: registered new interface driver usbfs
[ 0.420000] usbcore: registered new interface driver hub
[ 0.430000] usbcore: registered new device driver usb
[ 0.440000] Advanced Linux Sound Architecture Driver Version 1.0.25.
[ 0.440000] Switching to clocksource xttcpss_timer1
[ 0.460000] Clockevents: could not switch to one-shot mode:
[ 0.460000] Clockevents: could not switch to one-shot mode: dummy_timer is not functional.
[ 0.460000] Could not switch to high resolution mode on CPU 1
[ 0.460000] dummy_timer is not functional.
[ 0.470000] Could not switch to high resolution mode on CPU 0
[ 0.490000] NET: Registered protocol family 2
[ 0.490000] TCP established hash table entries: 16384 (order: 5, 131072 bytes)
[ 0.490000] TCP bind hash table entries: 16384 (order: 5, 131072 bytes)
[ 0.500000] TCP: Hash tables configured (established 16384 bind 16384)
[ 0.510000] TCP: reno registered
[ 0.510000] UDP hash table entries: 256 (order: 1, 8192 bytes)
[ 0.510000] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
[ 0.520000] NET: Registered protocol family 1
[ 0.530000] Trying to unpack rootfs image as initramfs...
[ 0.530000] rootfs image is not initramfs (no cpio magic); looks like an initrd
[ 0.570000] Freeing initrd memory: 8192K
[ 0.570000] pl330 dev 0 probe success
[ 0.580000] msgmni has been set to 1005
[ 0.580000] io scheduler noop registered
[ 0.580000] io scheduler deadline registered
[ 0.590000] io scheduler cfq registered (default)
[ 0.590000] xuartps e0001000.uart: failed to get alias id, errno -19
[ 0.600000] e00rイconsole [ttyPS0] enabled, bootconsole disabled
[ 0.600000] console [ttyPS0] enabled, bootconsole disabled
[ 0.610000] xdevcfg f8007000.devcfg: ioremap f8007000 to e0852000 with size 1000
[ 0.620000] [drm] Initialized drm 1.1.0 20060810
[ 0.640000] brd: module loaded
[ 0.650000] loop: module loaded
[ 0.650000] xqspips e000d000.qspi: master is unqueued, this is deprecated
[ 0.660000] xqspips e000d000.qspi: at 0xE000D000 mapped to 0xE0854000, irq=51
[ 0.670000] libphy: XEMACPS mii bus: probed
[ 0.670000] xemacps e000b000.eth: Could not find MAC address in device tree, use default
[ 0.680000] xemacps e000b000.eth: pdev->id -1, baseaddr 0xe000b000, irq 54
[ 0.690000] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[ 0.690000] xusbps-ehci xusbps-ehci.0: Xilinx PS USB EHCI Host Controller
[ 0.700000] xusbps-ehci xusbps-ehci.0: new USB bus registered, assigned bus number 1
[ 0.740000] xusbps-ehci xusbps-ehci.0: irq 53, io mem 0x00000000
[ 0.760000] xusbps-ehci xusbps-ehci.0: USB 2.0 started, EHCI 1.00
[ 0.760000] hub 1-0:1.0: USB hub found
[ 0.770000] hub 1-0:1.0: 1 port detected
[ 0.770000] Initializing USB Mass Storage driver...
[ 0.770000] usbcore: registered new interface driver usb-storage
[ 0.780000] USB Mass Storage support registered.
[ 0.790000] mousedev: PS/2 mouse device common for all mice
[ 0.790000] xwdtps f8005000.swdt: Xilinx Watchdog Timer at 0xe085c000 with timeout 10s
[ 0.800000] sdhci: Secure Digital Host Controller Interface driver
[ 0.810000] sdhci: Copyright(c) Pierre Ossman
[ 0.810000] sdhci-pltfm: SDHCI platform and OF driver helper
[ 0.820000] mmc0: Invalid maximum block size, assuming 512 bytes
[ 0.870000] mmc0: SDHCI controller on e0100000.sdhci [e0100000.sdhci] using ADMA
[ 0.880000] usbcore: registered new interface driver usbhid
[ 0.880000] usbhid: USB HID core driver
[ 0.900000] adv7511-hdmi-snd adv7511_hdmi_snd.2: CODEC adv7511.2-0039 not registered
[ 0.900000] platform adv7511_hdmi_snd.2: Driver adv7511-hdmi-snd requests probe deferral
[ 0.910000] TCP: cubic registered
[ 0.920000] NET: Registered protocol family 17
[ 0.920000] VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
[ 0.930000] Registering SWP/SWPB emulation handler
[ 0.930000] registered taskstats version 1
[ 0.940000] adv7511-hdmi-snd adv7511_hdmi_snd.2: CODEC adv7511.2-0039 not registered
[ 0.950000] drivers/rtc/hctosys.c: unable to open rtc device (rtc0)
[ 0.950000] platform adv7511_hdmi_snd.2: Driver adv7511-hdmi-snd requests probe deferral
[ 0.960000] ALSA device list:
[ 0.960000] No soundcards found.
[ 0.970000] new mode: 1920x1080 2200x1125 148500
[ 0.970000] new mode: 720x480 858x525 27000
[ 0.970000] new mode: 1280x720 1650x750 74250
[ 0.970000] new mode: 720x576 864x625 27000
[ 0.970000] new mode: 1680x1050 1840x1080 119000
[ 0.970000] new mode: 1280x1024 1728x1067 132840
[ 0.970000] new mode: 1280x1024 1728x1066 128946
[ 0.970000] new mode: 1280x1024 1688x1066 108000
[ 0.970000] new mode: 1280x960 1800x1000 108000
[ 0.970000] new mode: 1280x800 1440x823 71000
[ 0.970000] new mode: 800x600 1056x628 40000
[ 0.970000] new mode: 800x600 1024x625 36000
[ 0.970000] new mode: 640x480 840x500 31500
[ 0.970000] new mode: 640x480 832x520 31500
[ 0.970000] new mode: 640x480 864x525 30240
[ 0.970000] new mode: 640x480 800x525 25200
[ 0.970000] new mode: 720x400 900x449 28320
[ 0.970000] new mode: 1280x1024 1688x1066 135000
[ 0.970000] new mode: 1024x768 1312x800 78800
[ 0.970000] new mode: 1024x768 1328x806 75000
[ 0.970000] new mode: 1024x768 1344x806 65000
[ 0.970000] new mode: 832x624 1152x667 57284
[ 0.970000] new mode: 800x600 1056x625 49500
[ 0.970000] new mode: 800x600 1040x666 50000
[ 0.970000] new mode: 848x480 1088x517 33750
[ 0.970000] new mode: 1152x864 1600x900 108000
[ 0.970000] new mode: 1280x768 1440x790 68250
[ 0.970000] new mode: 1280x768 1696x805 102250
[ 0.970000] new mode: 1280x800 1696x838 106500
[ 0.970000] new mode: 1360x768 1792x795 85500
[ 0.970000] new mode: 1400x1050 1560x1080 101000
[ 0.970000] new mode: 1400x1050 1896x1099 156000
[ 0.970000] new mode: 1440x900 1600x926 88750
[ 0.970000] new mode: 1440x900 1936x942 136750
[ 0.970000] new mode: 1024x576 1312x597 46970
[ 0.970000] new mode: 1366x768 1800x795 85885
[ 0.970000] new mode: 1600x900 2128x932 118963
[ 0.970000] new mode: 1680x945 2240x978 131481
[ 0.970000] new mode: 640x480 800x525 25175
[ 0.970000] new mode: 720x480 858x525 27000
[ 0.970000] new mode: 720x480 858x525 27000
[ 0.970000] new mode: 1280x720 1650x750 74250
[ 0.970000] new mode: 1920x1080 2200x1125 74250
[ 0.970000] new mode: 1920x1080 2200x1125 148500
[ 0.970000] new mode: 720x576 864x625 27000
[ 0.970000] new mode: 720x576 864x625 27000
[ 0.970000] new mode: 1280x720 1980x750 74250
[ 0.970000] new mode: 1920x1080 2640x1125 74250
[ 0.970000] new mode: 1440x576 1728x625 54000
[ 0.970000] new mode: 1920x1080 2640x1125 148500
[ 0.970000] new mode: 1920x1080 2200x1125 148500
[ 0.970000] new mode: 720x480 858x525 27000
[ 0.970000] new mode: 1280x720 1650x750 74250
[ 0.970000] new mode: 720x576 864x625 27000
[ 0.970000] new mode: 800x600 1056x628 40000
[ 0.970000] new mode: 800x600 1024x625 36000
[ 0.970000] new mode: 640x480 840x500 31500
[ 0.970000] new mode: 640x480 832x520 31500
[ 0.970000] new mode: 640x480 864x525 30240
[ 0.970000] new mode: 640x480 800x525 25200
[ 0.970000] new mode: 720x400 900x449 28320
[ 0.970000] new mode: 1280x1024 1688x1066 135000
[ 0.970000] new mode: 1024x768 1312x800 78800
[ 0.970000] new mode: 1024x768 1328x806 75000
[ 0.970000] new mode: 1024x768 1344x806 65000
[ 0.970000] new mode: 832x624 1152x667 57284
[ 0.970000] new mode: 800x600 1056x625 49500
[ 0.970000] new mode: 800x600 1040x666 50000
[ 0.970000] new mode: 640x480 800x525 25175
[ 0.970000] new mode: 720x480 858x525 27000
[ 0.970000] new mode: 720x480 858x525 27000
[ 0.970000] new mode: 1280x720 1650x750 74250
[ 0.970000] new mode: 1920x1080 2200x1125 74250
[ 0.970000] new mode: 1920x1080 2200x1125 148500
[ 0.970000] new mode: 720x576 864x625 27000
[ 0.970000] new mode: 720x576 864x625 27000
[ 0.970000] new mode: 1280x720 1980x750 74250
[ 0.970000] new mode: 1920x1080 2640x1125 74250
[ 0.970000] new mode: 1440x576 1728x625 54000
[ 0.970000] new mode: 1920x1080 2640x1125 148500
[ 0.980000] mmc0: new high speed SDHC card at address b368
[ 0.990000] fbi->screen_base = 0xe08d1000
[ 0.990000] fbi->fix.smem_start = 0x19000000
[ 0.990000] fbi->screen_size = 0x7e9000
[ 0.990000] mmcblk0: mmc0:b368 NCard 7.48 GiB
[ 0.990000] mmcblk0: p1
[ 1.000000] adv7511-hdmi-snd adv7511_hdmi_snd.2: CODEC adv7511.2-0039 not registered
[ 1.000000] platform adv7511_hdmi_snd.2: Driver adv7511-hdmi-snd requests probe deferral
[ 1.360000] RAMDISK: gzip image found at block 0
[ 1.360000] setting clock to: 148500
[ 1.360000] raw_edid: d8c03c80 7
[ 1.360000] Using YCbCr output
[ 1.400000] Console: switching to colour frame buffer device 240x67
[ 1.450000] fb0: frame buffer device
[ 1.450000] drm: registered panic notifier
[ 1.460000] [drm] Initialized analog_drm 1.0.0 20110530 on minor 0
[ 1.670000] EXT4-fs (ram0): warning: mounting unchecked fs, running e2fsck is recommended
[ 1.680000] EXT4-fs (ram0): mounted filesystem without journal. Opts: (null)
[ 1.690000] VFS: Mounted root (ext4 filesystem) on device 1:0.
[ 1.690000] Freeing init memory: 148K
Starting rcS...
++ Mounting filesystem
++ Setting up mdev
++ Configure static IP 192.168.3.130
++ Starting telnet daemon
++ Starting http daemon
++ Starting ftp daemon
++ Starting dropbear (ssh) daemon
++ Starting OLED Display
insmod: can't read '/lib/modules/3.6.0-digilent-13.01/pmodoled-gpio.ko': No such file or directory
++ Exporting LEDs & SWs
rcS Complete
zynq> [ 4.930000] xemacps e000b000.eth: Set clk to 24999999 Hz
[ 4.930000] xemacps e000b000.eth: link up (100/FULL)
bitmap_disp_cntrler_axi_master_0: bitmap-disp-cntrler-axi-master@47000000 {
compatible = "xlnx,bitmap-disp-cntrler-axi-master-1.00.a";
reg = < 0x47000000 0x10000 >;
xlnx,display-start-address = <0x1a000000>;
xlnx,offset-width = <0x9>;
} ;
mt9d111_inf_axi_master_0: mt9d111-inf-axi-master@46000000 {
compatible = "xlnx,mt9d111-inf-axi-master-1.00.a";
reg = < 0x46000000 0x10000 >;
xlnx,display-start-address = <0x1a000000>;
xlnx,offset-width = <0x9>;
xlnx,upside-down = <0x0>;
} ;
~/HDL/ZedBoard/linux-digilent-master/scripts/dtc/dtc -O dtb -I dts -o devicetree_ramdisk.dtb devicetree_ramdisk_mt9d111.dts
bitmap_disp_cntrler_axi_master_0: bitmap-disp-cntrler-axi-master@47000000 {
compatible = "xlnx,bitmap-disp-cntrler-axi-master-1.00.a";
reg = < 0x47000000 0x10000 >;
xlnx,display-start-address = <0x1a000000>;
xlnx,offset-width = <0x9>;
} ;
mt9d111_inf_axi_master_0: mt9d111-inf-axi-master@46000000 {
compatible = "xlnx,mt9d111-inf-axi-master-1.00.a";
reg = < 0x46000000 0x10000 >;
xlnx,display-start-address = <0x1a000000>;
xlnx,offset-width = <0x9>;
xlnx,upside-down = <0x0>;
} ;
SDKでDevice Treeを生成する1(Device Tree の概要)
SDKでDevice Treeを生成する2(SDKでxilinx.dtsを生成)
とあった。普通には使えないらしい。。。Vivado 2013.1 のZynq のプロジェクトでは EDK は使えないとの表示が出てきたので、Vivado 2013.1 で、Zynq に対応したと言っているのだが、通常の方法では使うことは出来ないようだ。(IPをHDLで接続すれば使えるのかもしれない?)アーリー アクセス版のライセンス取得に関しては、最寄りの販売代理店へお問い合わせください。
と書かれていました。リリースノートには記述されていました。Device Support
• Zynq™-7000 devices now supported
°Requires Early Access to Vivado IP integrator
ERROR:HDLCompiler:267 - "D:\HDL\FndtnISEWork\Zynq-7000\ZedBoard\ZedBoard_OOB_Design2\hw\xps_proj\hdl\system_mt9d111_inf_axi_master_0_wrapper.v" Line 185: Cannot find port s_axi_lite_awprot on this module
ERROR:HDLCompiler:267 - "D:\HDL\FndtnISEWork\Zynq-7000\ZedBoard\ZedBoard_OOB_Design2\hw\xps_proj\hdl\system_mt9d111_inf_axi_master_0_wrapper.v" Line 195: Cannot find port s_axi_lite_arprot on this module
ERROR:EDK:546 - Aborting XST flow execution!
// bitmap_disp_cntrler_axi_master.v
//
// Read Only IP, 64 bit bus
//
// 2012/06/28
// 2012/11/22 : HDMI portを追加
`default_nettype none
module bitmap_disp_cntrler_axi_master #
(
// AXI4 Lite Slave Interface
parameter integer C_S_AXI_LITE_ADDR_WIDTH = 9,
parameter integer C_S_AXI_LITE_DATA_WIDTH = 32,
// AXI Master Interface
parameter integer C_INTERCONNECT_M_AXI_WRITE_ISSUING = 8,
parameter integer C_M_AXI_THREAD_ID_WIDTH = 1,
parameter integer C_M_AXI_ADDR_WIDTH = 32,
parameter integer C_M_AXI_DATA_WIDTH = 64,
parameter integer C_M_AXI_AWUSER_WIDTH = 1,
parameter integer C_M_AXI_ARUSER_WIDTH = 1,
parameter integer C_M_AXI_WUSER_WIDTH = 1,
parameter integer C_M_AXI_RUSER_WIDTH = 1,
parameter integer C_M_AXI_BUSER_WIDTH = 1,
parameter [31:0] C_M_AXI_TARGET = 32'h00000000,
parameter integer C_M_AXI_BURST_LEN = 256,
parameter integer C_OFFSET_WIDTH = 32,
/* Disabling these parameters will remove any throttling.
The resulting ERROR flag will not be useful */
parameter integer C_M_AXI_SUPPORTS_WRITE = 0,
parameter integer C_M_AXI_SUPPORTS_READ = 1,
parameter [31:0] C_DISPLAY_START_ADDRESS = 32'h1A000000 // フレームバッファのスタートアドレス
)
(
// Clocks and Reset
input wire s_axi_lite_aclk,
input wire M_AXI_ACLK,
input wire ARESETN,
///////////////////////////////
// AXI4 Lite Slave Interface //
///////////////////////////////
// AXI Lite Write Address Channel
input wire s_axi_lite_awvalid,
output wire s_axi_lite_awready,
input wire [C_S_AXI_LITE_ADDR_WIDTH-1:0] s_axi_lite_awaddr,
// AXI Lite Write Data Channel
input wire s_axi_lite_wvalid,
output wire s_axi_lite_wready,
input wire [C_S_AXI_LITE_DATA_WIDTH-1:0] s_axi_lite_wdata,
// AXI Lite Write Response Channel
output wire [1:0] s_axi_lite_bresp,
output wire s_axi_lite_bvalid,
input wire s_axi_lite_bready,
// AXI Lite Read Address Channel
input wire s_axi_lite_arvalid,
output wire s_axi_lite_arready,
input wire [C_S_AXI_LITE_ADDR_WIDTH-1:0] s_axi_lite_araddr,
// AXI Lite Read Data Channel
output wire s_axi_lite_rvalid,
input wire s_axi_lite_rready,
output wire [C_S_AXI_LITE_DATA_WIDTH-1:0] s_axi_lite_rdata,
output wire [1:0] s_axi_lite_rresp,
///////////////////////////////
// AXI4 Master Interface //
///////////////////////////////
// Master Interface Write Address
output wire [C_M_AXI_THREAD_ID_WIDTH-1:0] M_AXI_AWID,
output wire [C_M_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [8-1:0] M_AXI_AWLEN,
output wire [3-1:0] M_AXI_AWSIZE,
output wire [2-1:0] M_AXI_AWBURST,
output wire M_AXI_AWLOCK,
output wire [4-1:0] M_AXI_AWCACHE,
output wire [3-1:0] M_AXI_AWPROT,
// AXI3 output wire [4-1:0] M_AXI_AWREGION,
output wire [4-1:0] M_AXI_AWQOS,
output wire [C_M_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
// Master Interface Write Data
// AXI3 output wire [C_M_AXI_THREAD_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_M_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_M_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
// Master Interface Write Response
input wire [C_M_AXI_THREAD_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_M_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Master Interface Read Address
output wire [C_M_AXI_THREAD_ID_WIDTH-1:0] M_AXI_ARID,
output wire [C_M_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [8-1:0] M_AXI_ARLEN,
output wire [3-1:0] M_AXI_ARSIZE,
output wire [2-1:0] M_AXI_ARBURST,
output wire [2-1:0] M_AXI_ARLOCK,
output wire [4-1:0] M_AXI_ARCACHE,
output wire [3-1:0] M_AXI_ARPROT,
// AXI3 output wire [4-1:0] M_AXI_ARREGION,
output wire [4-1:0] M_AXI_ARQOS,
output wire [C_M_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
// Master Interface Read Data
input wire [C_M_AXI_THREAD_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_M_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY,
// User Ports
input wire pixclk,
(* IOB = "FORCE" *) output reg [3:0] vga_red,
(* IOB = "FORCE" *) output reg [3:0] vga_green,
(* IOB = "FORCE" *) output reg [3:0] vga_blue,
(* IOB = "FORCE" *) output reg vga_hsync,
(* IOB = "FORCE" *) output reg vga_vsync,
(* IOB = "TRUE" *) output wire hdmi_clk,
(* IOB = "TRUE" *) output wire hdmi_vsync,
(* IOB = "TRUE" *) output wire hdmi_hsync,
(* IOB = "TRUE" *) output wire hdmi_data_e,
(* IOB = "TRUE" *) output wire [15:0] hdmi_data,
input wire init_done
);
#-- DISCLAIMER OF LIABILITY
#--
#-- This file contains proprietary and confidential information of
#-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
#-- from Xilinx, and may be used, copied and/or disclosed only
#-- pursuant to the terms of a valid license agreement with Xilinx.
#--
#-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
#-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
#-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
#-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
#-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
#-- does not warrant that functions included in the Materials will
#-- meet the requirements of Licensee, or that the operation of the
#-- Materials will be uninterrupted or error-free, or that defects
#-- in the Materials will be corrected. Furthermore, Xilinx does
#-- not warrant or make any representations regarding use, or the
#-- results of the use, of the Materials in terms of correctness,
#-- accuracy, reliability or otherwise.
#--
#-- Xilinx products are not designed or intended to be fail-safe,
#-- or for use in any application requiring fail-safe performance,
#-- such as life-support or safety devices or systems, Class III
#-- medical devices, nuclear facilities, applications related to
#-- the deployment of airbags, or any other applications that could
#-- lead to death, personal injury or severe property or
#-- environmental damage (individually and collectively, "critical
#-- applications"). Customer assumes the sole risk and liability
#-- of any use of Xilinx products in critical applications,
#-- subject only to applicable laws and regulations governing
#-- limitations on product liability.
#--
#-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
#--
#-- This disclaimer and copyright notice must be retained as part
#-- of this file at all times.
#--###################################################################
##
## Name : mt9d111_inf_axi_master
## Desc : Microprocessor Peripheral Description
## : Automatically generated by PsfUtility
##
###################################################################
BEGIN mt9d111_inf_axi_master
## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION STYLE = MIX
OPTION DESC = mt9d111_inf_axi_master
OPTION LONG_DESC = An AXI Master Camera Interface
OPTION HDL = MIXED
OPTION RUN_NGCBUILD = FALSE
IO_INTERFACE IO_IF = mt9d111_inf
## Bus Interfaces
BUS_INTERFACE BUS = S_AXI_LITE, BUS_STD = AXI, BUS_TYPE = SLAVE
BUS_INTERFACE BUS = M_AXI, BUS_STD = AXI, BUS_TYPE = MASTER
## Generics for VHDL or Parameters for Verilog
PARAMETER C_S_AXI_LITE_ADDR_WIDTH = 9, DT = INTEGER, BUS = S_AXI_LITE
PARAMETER C_S_AXI_LITE_DATA_WIDTH = 32, DT = INTEGER, BUS = S_AXI_LITE
PARAMETER C_BASEADDR = 0xffffffff, DT = STD_LOGIC_VECTOR(31 downto 0), PAIR = C_HIGHADDR, ADDRESS = BASE, BUS = S_AXI_LITE, MIN_SIZE = 0x1000, ASSIGNMENT = REQUIRE, TYPE = NON_HDL
PARAMETER C_HIGHADDR = 0x00000000, DT = STD_LOGIC_VECTOR(31 downto 0), PAIR = C_BASEADDR, ADDRESS = HIGH, BUS = S_AXI_LITE, ASSIGNMENT = REQUIRE, TYPE = NON_HDL
PARAMETER C_S_AXI_LITE_PROTOCOL = AXI4LITE, DT = STRING, BUS = S_AXI_LITE, ASSIGNMENT = CONSTANT, TYPE = NON_HDL
PARAMETER C_S_AXI_LITE_SUPPORTS_READ = 1, DT = INTEGER, RANGE = (0,1), BUS = S_AXI_LITE, TYPE = NON_HDL
PARAMETER C_S_AXI_LITE_SUPPORTS_WRITE = 1, DT = INTEGER, RANGE = (0,1), BUS = S_AXI_LITE, TYPE = NON_HDL
PARAMETER C_M_AXI_SUPPORTS_THREADS = 0, DT = integer, RANGE = (0,1), TYPE = NON_HDL, BUS = M_AXI
PARAMETER C_M_AXI_THREAD_ID_WIDTH = 1, DT = integer, RANGE = (1:16), BUS = M_AXI
PARAMETER C_M_AXI_ADDR_WIDTH = 32, DT = integer, ASSIGNMENT = CONSTANT, BUS = M_AXI
PARAMETER C_M_AXI_DATA_WIDTH = 64, DT = integer, RANGE = (32, 64, 128, 256), BUS = M_AXI
PARAMETER C_M_AXI_PROTOCOL = AXI4, DT = string, TYPE = NON_HDL, VALUES = (AXI4 = AXI4, AXI4Lite = AXI4Lite), BUS = M_AXI
# Max number of write commands able to be issued without responses
# In this example, issued writes + unread writes will throttle write address channel
PARAMETER C_INTERCONNECT_M_AXI_WRITE_ISSUING = 8, DT = INTEGER, BUS = M_AXI
#Read Issuing in this example HDL will go as high as write issuing parameter
PARAMETER C_INTERCONNECT_M_AXI_READ_ISSUING = 8, DT = INTEGER, BUS = M_AXI, TYPE = NON_HDL
PARAMETER C_M_AXI_SUPPORTS_READ = 1, DT = integer, RANGE = (0,1), BUS = M_AXI #,TYPE = NON_HDL
PARAMETER C_M_AXI_SUPPORTS_WRITE = 1, DT = integer, RANGE = (0,1), BUS = M_AXI #,TYPE = NON_HDL
PARAMETER C_M_AXI_SUPPORTS_USER_SIGNALS = 0, DT = integer, RANGE = (0,1), TYPE = NON_HDL, BUS = M_AXI
PARAMETER C_M_AXI_AWUSER_WIDTH = 1, DT = integer, ISVALID = (C_M_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = M_AXI
PARAMETER C_M_AXI_ARUSER_WIDTH = 1, DT = integer, ISVALID = (C_M_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = M_AXI
PARAMETER C_M_AXI_WUSER_WIDTH = 1, DT = integer, ISVALID = (C_M_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = M_AXI
PARAMETER C_M_AXI_RUSER_WIDTH = 1, DT = integer, ISVALID = (C_M_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = M_AXI
PARAMETER C_M_AXI_BUSER_WIDTH = 1, DT = integer, ISVALID = (C_M_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = M_AXI
PARAMETER C_M_AXI_SUPPORTS_NARROW_BURST = 0, DT = integer, RANGE = (0,1), TYPE = NON_HDL, BUS = M_AXI
# Example Parameters
# Base address of targeted slave
PARAMETER C_M_AXI_TARGET = 0x00000000, DT = std_logic_vector(31 downto 0)
# Burst length for transactions, in C_M_AXI_DATA_WIDTHs
PARAMETER C_M_AXI_BURST_LEN = 16, DT = integer
# Number of address bits to test before wrapping
PARAMETER C_OFFSET_WIDTH = 9, DT = integer
PARAMETER C_DISPLAY_START_ADDRESS = 0x1A000000, DT = std_logic_vector(31 downto 0)
PARAMETER C_UPSIDE_DOWN = 0, DT = INTEGER, VALUES = (1= TRUE, 0= FALSE)
## Ports
PORT s_axi_lite_aclk = "", DIR = I, SIGIS = CLK, BUS = S_AXI_LITE
PORT M_AXI_ACLK = "", BUS = M_AXI, DIR = I, SIGIS = CLK
PORT ARESETN = ARESETN, BUS = M_AXI:S_AXI_LITE, DIR = I, SIGIS = RST
PORT s_axi_lite_awvalid = AWVALID, DIR = I, BUS = S_AXI_LITE
PORT s_axi_lite_awready = AWREADY, DIR = O, BUS = S_AXI_LITE
PORT s_axi_lite_awaddr = AWADDR, DIR = I, VEC = [C_S_AXI_LITE_ADDR_WIDTH-1:0], BUS = S_AXI_LITE, ENDIAN = LITTLE
PORT s_axi_lite_wvalid = WVALID, DIR = I, BUS = S_AXI_LITE
PORT s_axi_lite_wready = WREADY, DIR = O, BUS = S_AXI_LITE
PORT s_axi_lite_wdata = WDATA, DIR = I, VEC = [C_S_AXI_LITE_DATA_WIDTH-1:0], BUS = S_AXI_LITE, ENDIAN = LITTLE
PORT s_axi_lite_bresp = BRESP, DIR = O, VEC = [1:0], BUS = S_AXI_LITE, ENDIAN = LITTLE
PORT s_axi_lite_bvalid = BVALID, DIR = O, BUS = S_AXI_LITE
PORT s_axi_lite_bready = BREADY, DIR = I, BUS = S_AXI_LITE
PORT s_axi_lite_arvalid = ARVALID, DIR = I, BUS = S_AXI_LITE
PORT s_axi_lite_arready = ARREADY, DIR = O, BUS = S_AXI_LITE
PORT s_axi_lite_araddr = ARADDR, DIR = I, VEC = [C_S_AXI_LITE_ADDR_WIDTH-1:0], BUS = S_AXI_LITE, ENDIAN = LITTLE
PORT s_axi_lite_rvalid = RVALID, DIR = O, BUS = S_AXI_LITE
PORT s_axi_lite_rready = RREADY, DIR = I, BUS = S_AXI_LITE
PORT s_axi_lite_rdata = RDATA, DIR = O, VEC = [C_S_AXI_LITE_DATA_WIDTH-1:0], BUS = S_AXI_LITE, ENDIAN = LITTLE
PORT s_axi_lite_rresp = RRESP, DIR = O, VEC = [1:0], BUS = S_AXI_LITE, ENDIAN = LITTLE
PORT M_AXI_AWID = AWID, BUS = M_AXI, DIR = O, VEC = [(C_M_AXI_THREAD_ID_WIDTH-1):0], ENDIAN = LITTLE
PORT M_AXI_AWADDR = AWADDR, BUS = M_AXI, DIR = O, VEC = [(C_M_AXI_ADDR_WIDTH-1):0], ENDIAN = LITTLE
PORT M_AXI_AWLEN = AWLEN, BUS = M_AXI, DIR = O, VEC = [7:0], ENDIAN = LITTLE
PORT M_AXI_AWSIZE = AWSIZE, BUS = M_AXI, DIR = O, VEC = [2:0], ENDIAN = LITTLE
PORT M_AXI_AWBURST = AWBURST, BUS = M_AXI, DIR = O, VEC = [1:0], ENDIAN = LITTLE
PORT M_AXI_AWLOCK = AWLOCK, BUS = M_AXI, DIR = O #, VEC = [1:0], ENDIAN = LITTLE
PORT M_AXI_AWCACHE = AWCACHE, BUS = M_AXI, DIR = O, VEC = [3:0], ENDIAN = LITTLE
PORT M_AXI_AWPROT = AWPROT, BUS = M_AXI, DIR = O, VEC = [2:0], ENDIAN = LITTLE
PORT M_AXI_AWQOS = AWQOS, BUS = M_AXI, DIR = O, VEC = [3:0], ENDIAN = LITTLE
PORT M_AXI_AWUSER = AWUSER, BUS = M_AXI, DIR = O, VEC = [C_M_AXI_AWUSER_WIDTH-1:0], ENDIAN = LITTLE
PORT M_AXI_AWVALID = AWVALID, BUS = M_AXI, DIR = O
PORT M_AXI_AWREADY = AWREADY, BUS = M_AXI, DIR = I
PORT M_AXI_WDATA = WDATA, BUS = M_AXI, DIR = O, VEC = [(C_M_AXI_DATA_WIDTH-1):0], ENDIAN = LITTLE
PORT M_AXI_WSTRB = WSTRB, BUS = M_AXI, DIR = O, VEC = [((C_M_AXI_DATA_WIDTH/8) -1):0], ENDIAN = LITTLE
PORT M_AXI_WLAST = WLAST, BUS = M_AXI, DIR = O
PORT M_AXI_WUSER = WUSER, BUS = M_AXI, DIR = O, VEC = [(C_M_AXI_WUSER_WIDTH-1):0], ENDIAN = LITTLE
PORT M_AXI_WVALID = WVALID, BUS = M_AXI, DIR = O
PORT M_AXI_WREADY = WREADY, BUS = M_AXI, DIR = I
PORT M_AXI_BID = BID, BUS = M_AXI, DIR = I, VEC = [(C_M_AXI_THREAD_ID_WIDTH-1):0], ENDIAN = LITTLE
PORT M_AXI_BRESP = BRESP, BUS = M_AXI, DIR = I, VEC = [1:0], ENDIAN = LITTLE
PORT M_AXI_BUSER = BUSER, BUS = M_AXI, DIR = I, VEC = [(C_M_AXI_BUSER_WIDTH-1):0], ENDIAN = LITTLE
PORT M_AXI_BVALID = BVALID, BUS = M_AXI, DIR = I
PORT M_AXI_BREADY = BREADY, BUS = M_AXI, DIR = O
PORT M_AXI_ARID = ARID, BUS = M_AXI, DIR = O, VEC = [(C_M_AXI_THREAD_ID_WIDTH-1):0], ENDIAN = LITTLE
PORT M_AXI_ARADDR = ARADDR, BUS = M_AXI, DIR = O, VEC = [(C_M_AXI_ADDR_WIDTH-1):0], ENDIAN = LITTLE
PORT M_AXI_ARLEN = ARLEN, BUS = M_AXI, DIR = O, VEC = [7:0], ENDIAN = LITTLE
PORT M_AXI_ARSIZE = ARSIZE, BUS = M_AXI, DIR = O, VEC = [2:0], ENDIAN = LITTLE
PORT M_AXI_ARBURST = ARBURST, BUS = M_AXI, DIR = O, VEC = [1:0], ENDIAN = LITTLE
PORT M_AXI_ARLOCK = ARLOCK, BUS = M_AXI, DIR = O, VEC = [1:0], ENDIAN = LITTLE
PORT M_AXI_ARCACHE = ARCACHE, BUS = M_AXI, DIR = O, VEC = [3:0], ENDIAN = LITTLE
PORT M_AXI_ARPROT = ARPROT, BUS = M_AXI, DIR = O, VEC = [2:0], ENDIAN = LITTLE
PORT M_AXI_ARQOS = ARQOS, BUS = M_AXI, DIR = O, VEC = [3:0], ENDIAN = LITTLE
PORT M_AXI_ARUSER = ARUSER, BUS = M_AXI, DIR = O, VEC = [(C_M_AXI_ARUSER_WIDTH-1):0], ENDIAN = LITTLE
PORT M_AXI_ARVALID = ARVALID, BUS = M_AXI, DIR = O
PORT M_AXI_ARREADY = ARREADY, BUS = M_AXI, DIR = I
PORT M_AXI_RID = RID, BUS = M_AXI, DIR = I, VEC = [(C_M_AXI_THREAD_ID_WIDTH-1):0], ENDIAN = LITTLE
PORT M_AXI_RDATA = RDATA, BUS = M_AXI, DIR = I, VEC = [(C_M_AXI_DATA_WIDTH-1):0], ENDIAN = LITTLE
PORT M_AXI_RRESP = RRESP, BUS = M_AXI, DIR = I, VEC = [1:0], ENDIAN = LITTLE
PORT M_AXI_RLAST = RLAST, BUS = M_AXI, DIR = I
PORT M_AXI_RUSER = RUSER, BUS = M_AXI, DIR = I, VEC = [(C_M_AXI_RUSER_WIDTH-1):0], ENDIAN = LITTLE
PORT M_AXI_RVALID = RVALID, BUS = M_AXI, DIR = I
PORT M_AXI_RREADY = RREADY, BUS = M_AXI, DIR = O
#Example IO port
PORT init_done = "", DIR = I, IO_IF = mt9d111_inf, IO_IS = init_done
PORT wr_error = "", DIR = O, IO_IF = mt9d111_inf, IO_IS = wr_error
PORT pclk_from_pll = "", DIR = I, SIGIS = CLK, IO_IF = mt9d111_inf, IO_IS = pclk_from_pll
PORT pclk = "", DIR = I, SIGIS = CLK, IO_IF = mt9d111_inf, IO_IS = pclk
PORT xck = "", DIR =O, SIGIS = CLK, IO_IF = mt9d111_inf, IO_IS = xck
PORT href = "", DIR = I, IO_IF = mt9d111_inf, IO_IS = href
PORT vsync = "", DIR = I, IO_IF = mt9d111_inf, IO_IS = vsync
PORT cam_data = "", DIR = I, VEC = [7:0], IO_IF = mt9d111_inf, IO_IS = cam_data
PORT standby = "", DIR = O, IO_IF = mt9d111_inf, IO_IS = standby
PORT pfifo_overflow = "", DIR = O, IO_IF = mt9d111_inf, IO_IS = pfifo_overflow
PORT pfifo_underflow = "", DIR = O, IO_IF = mt9d111_inf, IO_IS = pfifo_underflow
END
<?xml version="1.0" encoding="ISO-8859-1"?>
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## medical devices, nuclear facilities, applications related to
## the deployment of airbags, or any other applications that could
## lead to death, personal injury or severe property or
## environmental damage (individually and collectively, "critical
## applications"). Customer assumes the sole risk and liability
## of any use of Xilinx products in critical applications,
## subject only to applicable laws and regulations governing
## limitations on product liability.
##
## Copyright 2009 Xilinx, Inc.
## All rights reserved.
##
## This disclaimer and copyright notice must be retained as part
## of this file at all times.
##
###############################################################################
-->
<!DOCTYPE doc SYSTEM "../../ipdialog.dtd" [
<!-- -->
<!ENTITY C_M_AXI_SUPPORTS_THREADS '
<widget id="C_M_AXI_SUPPORTS_THREADS">
<key>C_M_AXI_SUPPORTS_THREADS</key>
<label>C_M_AXI_SUPPORTS_THREADS</label>
<tip></tip>
</widget>
'>
<!ENTITY C_M_AXI_THREAD_ID_WIDTH '
<widget id="C_M_AXI_THREAD_ID_WIDTH">
<key>C_M_AXI_THREAD_ID_WIDTH</key>
<label>C_M_AXI_THREAD_ID_WIDTH</label>
<tip></tip>
</widget>
'>
<!ENTITY C_HIGHADDR '
<widget id="C_HIGHADDR">
<key>C_HIGHADDR</key>
<label>High Address</label>
<tip></tip>
</widget>
'>
<!ENTITY C_BASEADDR '
<widget id="C_BASEADDR">
<key>C_BASEADDR</key>
<label>Base Address</label>
<tip></tip>
</widget>
'>
<!ENTITY C_S_AXI_LITE_ADDR_WIDTH '
<widget id="C_S_AXI_LITE_ADDR_WIDTH">
<key>C_S_AXI_LITE_ADDR_WIDTH</key>
<label>AXI Lite Address Width</label>
<tip></tip>
</widget>
'>
<!ENTITY C_S_AXI_LITE_DATA_WIDTH '
<widget id="C_S_AXI_LITE_DATA_WIDTH">
<key>C_S_AXI_LITE_DATA_WIDTH</key>
<label>AXI Lite Data Width</label>
<tip></tip>
</widget>
'>
<!ENTITY C_M_AXI_ADDR_WIDTH '
<widget id="C_M_AXI_ADDR_WIDTH">
<key>C_M_AXI_ADDR_WIDTH</key>
<label>C_M_AXI_ADDR_WIDTH</label>
<tip></tip>
</widget>
'>
<!ENTITY C_M_AXI_DATA_WIDTH '
<widget id="C_M_AXI_DATA_WIDTH">
<key>C_M_AXI_DATA_WIDTH</key>
<label>C_M_AXI_DATA_WIDTH</label>
<tip></tip>
</widget>
'>
<!ENTITY C_M_AXI_PROTOCOL '
<widget id="C_M_AXI_PROTOCOL">
<key>C_M_AXI_PROTOCOL</key>
<label>AXI Master Protocol</label>
<tip></tip>
</widget>
'>
<!ENTITY C_S_AXI_LITE_PROTOCOL '
<widget id="C_S_AXI_LITE_PROTOCOL">
<key>C_S_AXI_LITE_PROTOCOL</key>
<label>AXI Lite Protocol</label>
<tip></tip>
</widget>
'>
<!ENTITY C_USE_ADVANCED_PORTS '
<widget id="C_USE_ADVANCED_PORTS">
<key>C_USE_ADVANCED_PORTS</key>
<label>C_USE_ADVANCED_PORTS</label>
<tip></tip>
</widget>
'>
<!ENTITY C_S_AXI_LITE_SUPPORTS_READ '
<widget id="C_S_AXI_LITE_SUPPORTS_READ">
<key>C_S_AXI_LITE_SUPPORTS_READ</key>
<label>AXI Lite Supports Read Access</label>
<tip></tip>
</widget>
'>
<!ENTITY C_S_AXI_LITE_SUPPORTS_WRITE '
<widget id="C_S_AXI_LITE_SUPPORTS_WRITE">
<key>C_S_AXI_LITE_SUPPORTS_WRITE</key>
<label>AXI Lite Supports Write Access</label>
<tip></tip>
</widget>
'>
<!ENTITY C_M_AXI_SUPPORTS_READ '
<widget id="C_M_AXI_SUPPORTS_READ">
<key>C_M_AXI_SUPPORTS_READ</key>
<label>C_M_AXI_SUPPORTS_READ</label>
<tip></tip>
</widget>
'>
<!ENTITY C_M_AXI_SUPPORTS_WRITE '
<widget id="C_M_AXI_SUPPORTS_WRITE">
<key>C_M_AXI_SUPPORTS_WRITE</key>
<label>C_M_AXI_SUPPORTS_WRITE</label>
<tip></tip>
</widget>
'>
<!ENTITY C_M_AXI_SUPPORTS_USER_SIGNALS '
<widget id="C_M_AXI_SUPPORTS_USER_SIGNALS">
<key>C_M_AXI_SUPPORTS_USER_SIGNALS</key>
<label>C_M_AXI_SUPPORTS_USER_SIGNALS</label>
<tip></tip>
</widget>
'>
<!ENTITY C_M_AXI_AWUSER_WIDTH '
<widget id="C_M_AXI_AWUSER_WIDTH">
<key>C_M_AXI_AWUSER_WIDTH</key>
<label>C_M_AXI_AWUSER_WIDTH</label>
<tip></tip>
</widget>
'>
<!ENTITY C_M_AXI_ARUSER_WIDTH '
<widget id=" C_M_AXI_ARUSER_WIDTH ">
<key>C_M_AXI_ARUSER_WIDTH</key>
<label>C_M_AXI_ARUSER_WIDTH</label>
<tip></tip>
</widget>
'>
<!ENTITY C_M_AXI_WUSER_WIDTH '
<widget id="C_M_AXI_WUSER_WIDTH">
<key>C_M_AXI_WUSER_WIDTH</key>
<label>C_M_AXI_WUSER_WIDTH</label>
<tip></tip>
</widget>
'>
<!ENTITY C_M_AXI_RUSER_WIDTH '
<widget id="C_M_AXI_RUSER_WIDTH">
<key>C_M_AXI_RUSER_WIDTH</key>
<label>C_M_AXI_RUSER_WIDTH</label>
<tip></tip>
</widget>
'>
<!ENTITY C_M_AXI_BUSER_WIDTH '
<widget id="C_M_AXI_BUSER_WIDTH">
<key>C_M_AXI_BUSER_WIDTH</key>
<label>C_M_AXI_BUSER_WIDTH</label>
<tip></tip>
</widget>
'>
<!ENTITY C_M_AXI_SUPPORTS_NARROW_BURST '
<widget id="C_M_AXI_SUPPORTS_NARROW_BURST">
<key>C_M_AXI_SUPPORTS_NARROW_BURST</key>
<label>C_M_AXI_SUPPORTS_NARROW_BURST</label>
<tip></tip>
</widget>
'>
<!ENTITY C_M_AXI_TARGET '
<widget id="C_M_AXI_TARGET">
<key>C_M_AXI_TARGET</key>
<label>C_M_AXI_TARGET</label>
<tip></tip>
</widget>
'>
<!ENTITY C_M_AXI_BURST_LEN '
<widget id="C_M_AXI_BURST_LEN">
<key>C_M_AXI_BURST_LEN</key>
<label>C_M_AXI_BURST_LEN</label>
<tip></tip>
</widget>
'>
<!ENTITY C_MAX_UNREAD_WRITES '
<widget id="C_MAX_UNREAD_WRITES">
<key>C_MAX_UNREAD_WRITES</key>
<label>C_MAX_UNREAD_WRITES</label>
<tip></tip>
</widget>
'>
<!ENTITY C_OFFSET_WIDTH '
<widget id="C_OFFSET_WIDTH">
<key>C_OFFSET_WIDTH</key>
<label>C_OFFSET_WIDTH</label>
<tip></tip>
</widget>
'>
<!ENTITY C_DISPLAY_START_ADDRESS '
<widget id="C_DISPLAY_START_ADDRESS">
<key>C_DISPLAY_START_ADDRESS</key>
<label>C_DISPLAY_START_ADDRESS</label>
<tip></tip>
</widget>
'>
<!ENTITY C_UPSIDE_DOWN '
<widget id="C_UPSIDE_DOWN">
<key>C_UPSIDE_DOWN</key>
<label>C_UPSIDE_DOWN</label>
<tip></tip>
</widget>
'>
]>
<doc>
<view id="User">
<display>User</display>
<group id="Common">
<display>Common</display>
<item>&C_M_AXI_TARGET;</item>
<item>&C_M_AXI_BURST_LEN;</item>
<item>&C_MAX_UNREAD_WRITES;</item>
<item>&C_OFFSET_WIDTH;</item>
<item>&C_DISPLAY_START_ADDRESS;</item>
<item>&C_UPSIDE_DOWN;</item>
</group>
</view>
<view id="System">
<display>System</display>
<group id="Addresses">
<display>Addresses</display>
<item>&C_BASEADDR;</item>
<item>&C_HIGHADDR;</item>
</group>
<group id="AXI">
<display>AXI</display>
<item>&C_S_AXI_LITE_PROTOCOL;</item>
<item>&C_S_AXI_LITE_ADDR_WIDTH;</item>
<item>&C_S_AXI_LITE_DATA_WIDTH;</item>
<item>&C_S_AXI_LITE_SUPPORTS_READ;</item>
<item>&C_S_AXI_LITE_SUPPORTS_WRITE;</item>
<item>&C_M_AXI_PROTOCOL;</item>
<item>&C_M_AXI_ADDR_WIDTH;</item>
<item>&C_M_AXI_DATA_WIDTH;</item>
<item>&C_M_AXI_SUPPORTS_READ;</item>
<item>&C_M_AXI_SUPPORTS_WRITE;</item>
<item>&C_M_AXI_SUPPORTS_THREADS;</item>
<item>&C_M_AXI_THREAD_ID_WIDTH;</item>
<item>&C_M_AXI_SUPPORTS_NARROW_BURST;</item>
<item>&C_M_AXI_SUPPORTS_USER_SIGNALS;</item>
<item>&C_M_AXI_AWUSER_WIDTH;</item>
<item>&C_M_AXI_ARUSER_WIDTH;</item>
<item>&C_M_AXI_WUSER_WIDTH;</item>
<item>&C_M_AXI_RUSER_WIDTH;</item>
<item>&C_M_AXI_BUSER_WIDTH;</item>
</group>
</view>
</doc>
C_S_AXI_LITE_PROTOCOL パラメータに AXI4LITE を指定した。DT (Data Type) は STRING、ASSIGNMENT を CONSTANTにすると下の図のように設定することができなくなる。PARAMETER C_S_AXI_LITE_PROTOCOL = AXI4LITE, DT = STRING, BUS = S_AXI_LITE, ASSIGNMENT = CONSTANT, TYPE = NON_HDL
DT (Data Type) は INTEGER で、RANGE = (0,1) に設定するとチェックボックスになる。RANGE = (0,1) を指定しないと、値を設定できる。PARAMETER C_S_AXI_LITE_SUPPORTS_READ = 1, DT = INTEGER, RANGE = (0,1), BUS = S_AXI_LITE, TYPE = NON_HDL
RANGE = (1:16) だと、1から16まで設定することができる。下に図で16に設定すると、もう値を増やすことが出来ない。よく見ると上向き三角はハイドされている。PARAMETER C_M_AXI_THREAD_ID_WIDTH = 1, DT = integer, RANGE = (1:16), BUS = M_AXI
ISVALID = (C_M_AXI_SUPPORTS_USER_SIGNALS == 1) で、C_M_AXI_SUPPORTS_USER_SIGNALSが1だったら、このパラメータの設定が有効になる。下の図は無効の状態。PARAMETER C_M_AXI_SUPPORTS_USER_SIGNALS = 0, DT = integer, RANGE = (0,1), TYPE = NON_HDL, BUS = M_AXI
PARAMETER C_M_AXI_AWUSER_WIDTH = 1, DT = integer, ISVALID = (C_M_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = M_AXI
PARAMETER C_M_AXI_ARUSER_WIDTH = 1, DT = integer, ISVALID = (C_M_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = M_AXI
PARAMETER C_M_AXI_WUSER_WIDTH = 1, DT = integer, ISVALID = (C_M_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = M_AXI
PARAMETER C_M_AXI_RUSER_WIDTH = 1, DT = integer, ISVALID = (C_M_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = M_AXI
PARAMETER C_M_AXI_BUSER_WIDTH = 1, DT = integer, ISVALID = (C_M_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = M_AXI
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