Other Compiler Options ： -L accellera_ovl_vlog=C:\HDL\Xilinx\14.6\ISE_DS\ISE\verilog\hdp\nt64\accellera_ovl_vlog
Specify Search Directories for 'Include ： D:\HDL\OVL\std_ovl_v2p7
Specify 'define Macro Name and Value ： OVL_VERILOG,OVL_ASSERT_ON,OVL_FINISH_OFF
現在のOVL Ver. 2.7 の入手先は、”License and Statement of Use of Accellera System Initiative's Open Verification Library”です。そのWebページの”Accept agreement and proceed to download OVL.”をクリックするとダウンロード出来ます。
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_always.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_always_on_edge.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_arbiter.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_bits.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_change.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_code_distance.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_coverage.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_decrement.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_crc.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_cycle_sequence.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_delta.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_even_parity.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_fifo.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_fifo_index.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_frame.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_handshake.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_hold_value.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_implication.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_increment.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_memory_async.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_memory_sync.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_multiport_fifo.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_mutex.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_never.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_never_unknown.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_never_unknown_async.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_next.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_next_state.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_no_contention.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_no_overflow.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_no_transition.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_no_underflow.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_odd_parity.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_one_cold.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_one_hot.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_proposition.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_quiescent_state.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_range.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_reg_loaded.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_req_ack_unique.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_req_requires.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_stack.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_time.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_transition.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_unchange.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_valid_id.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_value.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_value_coverage.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_width.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_window.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_win_change.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_win_unchange.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_xproduct_bit_coverage.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_xproduct_value_coverage.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vlogcomp -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v2p7 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v2p7\ovl_zero_one_hot.v
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\std_ovl.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\std_ovl_procs.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\std_ovl_components_vlog.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\std_ovl_clock_gating.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\std_ovl_reset_gating.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_always.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_always_on_edge.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_change.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_cycle_sequence.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_decrement.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_delta.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_even_parity.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_fifo_index.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_frame.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_handshake.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_implication.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_increment.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_never.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_never_unknown.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_never_unknown_async.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_next.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_no_overflow.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_no_transition.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_no_underflow.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_odd_parity.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_one_cold.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_one_hot.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_proposition.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_quiescent_state.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_range.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_time.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_transition.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_unchange.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_width.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_win_change.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_win_unchange.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_window.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\ovl_zero_one_hot.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\vhdl93\ovl_always_rtl.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\vhdl93\ovl_cycle_sequence_rtl.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\vhdl93\ovl_implication_rtl.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\vhdl93\ovl_never_rtl.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\vhdl93\ovl_never_unknown_async_rtl.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\vhdl93\ovl_never_unknown_rtl.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\vhdl93\ovl_next_rtl.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\vhdl93\ovl_one_hot_rtl.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\vhdl93\ovl_range_rtl.vhd
C:\HDL\Xilinx\14.6\ISE_DS\ISE\bin\nt64\vhpcomp -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v2p7\vhdl93\ovl_zero_one_hot_rtl.vhd
accellera_ovl_vlog=$XILINX/verilog/hdp/nt64/accellera_ovl_vlog
accellera_ovl_vhdl=$XILINX/vhdl/hdp/nt64/accellera_ovl_vhdl
// 8bit Memory Module
`default_nettype none
module memory_8bit #(
parameter integer C_S_AXI_ADDR_WIDTH = 32,
parameter integer C_MEMORY_SIZE = 512 // Word (not byte)
)(
input wire clk,
input wire [C_S_AXI_ADDR_WIDTH-1:0] waddr,
input wire [7:0] write_data,
input wire write_enable,
input wire byte_enable,
input wire [C_S_AXI_ADDR_WIDTH-1:0] raddr,
output reg [7:0] read_data
);
// Beyond Circuts, Constant Function in Verilog 2001を参照しました
// http://www.beyond-circuits.com/wordpress/2008/11/constant-functions/
function integer log2;
input integer addr;
begin
addr = addr - 1;
for (log2=0; addr>0; log2=log2+1)
addr = addr >> 1;
end
endfunction
reg [7:0] mem [0:C_MEMORY_SIZE-1];
wire [log2(C_MEMORY_SIZE)-1:0] mem_waddr;
wire [log2(C_MEMORY_SIZE)-1:0] mem_raddr;
// The Address is byte address
assign mem_waddr = waddr[(log2(C_MEMORY_SIZE)+log2((C_S_AXI_ADDR_WIDTH/8)))-1:log2((C_S_AXI_ADDR_WIDTH/8))];
assign mem_raddr = raddr[(log2(C_MEMORY_SIZE)+log2((C_S_AXI_ADDR_WIDTH/8)))-1:log2((C_S_AXI_ADDR_WIDTH/8))];
// Write
always @(posedge clk) begin
if (write_enable & byte_enable)
mem[mem_waddr] <= write_data;
end
// Read
always @(posedge clk) begin
read_data <= mem[mem_raddr];
end
endmodule
`default_nettype wire
1. UCF 制約を含むプロジェクトを開き ます。
2. [Open Synthesized Design] をクリックします。
3. Tcl コンソールに 「write_xdc filename.xdc」 と入力します。
PARAMETER C_S_AXI_NUM_ADDR_RANGES = 1, BUS = S_AXI, DT = INTEGER, ASSIGNMENT = OPTIONAL_UPDATE, TYPE = NON_HDL, RANGE = (1:4)
PARAMETER C_S_AXI_RNG00_BASEADDR = 0xFFFFFFFF, BUS = S_AXI, DT = std_logic_vector, ADDRESS = BASE, PAIR = C_S_AXI_RNG00_HIGHADDR, ISVALID = (C_S_AXI_NUM_ADDR_RANGES >= 1), TYPE = NON_HDL, MIN_SIZE = 0x1000
PARAMETER C_S_AXI_RNG00_HIGHADDR = 0x00000000, BUS = S_AXI, DT = std_logic_vector, ADDRESS = HIGH, PAIR = C_S_AXI_RNG00_BASEADDR, ISVALID = (C_S_AXI_NUM_ADDR_RANGES >= 1), TYPE = NON_HDL
PARAMETER C_S_AXI_RNG01_BASEADDR = 0xFFFFFFFF, BUS = S_AXI, DT = std_logic_vector, ADDRESS = BASE, PAIR = C_S_AXI_RNG01_HIGHADDR, ISVALID = (C_S_AXI_NUM_ADDR_RANGES >= 2), TYPE = NON_HDL, MIN_SIZE = 0x1000
PARAMETER C_S_AXI_RNG01_HIGHADDR = 0x00000000, BUS = S_AXI, DT = std_logic_vector, ADDRESS = HIGH, PAIR = C_S_AXI_RNG01_BASEADDR, ISVALID = (C_S_AXI_NUM_ADDR_RANGES >= 2), TYPE = NON_HDL
PARAMETER C_S_AXI_RNG02_BASEADDR = 0xFFFFFFFF, BUS = S_AXI, DT = std_logic_vector, ADDRESS = BASE, PAIR = C_S_AXI_RNG02_HIGHADDR, ISVALID = (C_S_AXI_NUM_ADDR_RANGES >= 3), TYPE = NON_HDL, MIN_SIZE = 0x1000
PARAMETER C_S_AXI_RNG02_HIGHADDR = 0x00000000, BUS = S_AXI, DT = std_logic_vector, ADDRESS = HIGH, PAIR = C_S_AXI_RNG02_BASEADDR, ISVALID = (C_S_AXI_NUM_ADDR_RANGES >= 3), TYPE = NON_HDL
PARAMETER C_S_AXI_RNG03_BASEADDR = 0xFFFFFFFF, BUS = S_AXI, DT = std_logic_vector, ADDRESS = BASE, PAIR = C_S_AXI_RNG03_HIGHADDR, ISVALID = (C_S_AXI_NUM_ADDR_RANGES >= 4), TYPE = NON_HDL, MIN_SIZE = 0x1000
PARAMETER C_S_AXI_RNG03_HIGHADDR = 0x00000000, BUS = S_AXI, DT = std_logic_vector, ADDRESS = HIGH, PAIR = C_S_AXI_RNG03_BASEADDR, ISVALID = (C_S_AXI_NUM_ADDR_RANGES >= 4), TYPE = NON_HDL
`default_nettype none
`timescale 100ps / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:51:13 06/19/2013
// Design Name: reg_set_axi_lite_master
// Module Name: D:/HDL/FndtnISEWork/Zynq-7000/ZedBoard/test/reg_set_axi_lite_master/reg_set_axi_lite_master_tb.v
// Project Name: reg_set_axi_lite_master
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: reg_set_axi_lite_master
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module reg_set_axi_lite_master_tb;
// Inputs
wire M_AXI_ACLK;
wire M_AXI_ARESETN;
wire M_AXI_AWREADY;
wire M_AXI_WREADY;
wire [1:0] M_AXI_BRESP;
wire M_AXI_BVALID;
wire M_AXI_ARREADY;
wire [31:0] M_AXI_RDATA;
wire [1:0] M_AXI_RRESP;
wire M_AXI_RVALID;
reg init_done;
// Outputs
wire [31:0] M_AXI_AWADDR;
wire [2:0] M_AXI_AWPROT;
wire M_AXI_AWVALID;
wire [31:0] M_AXI_WDATA;
wire [3:0] M_AXI_WSTRB;
wire M_AXI_WVALID;
wire M_AXI_BREADY;
wire [31:0] M_AXI_ARADDR;
wire [2:0] M_AXI_ARPROT;
wire M_AXI_ARVALID;
wire M_AXI_RREADY;
// Instantiate the Unit Under Test (UUT)
reg_set_axi_lite_master uut (
.M_AXI_ACLK(M_AXI_ACLK),
.M_AXI_ARESETN(M_AXI_ARESETN),
.M_AXI_AWADDR(M_AXI_AWADDR),
.M_AXI_AWPROT(M_AXI_AWPROT),
.M_AXI_AWVALID(M_AXI_AWVALID),
.M_AXI_AWREADY(M_AXI_AWREADY),
.M_AXI_WDATA(M_AXI_WDATA),
.M_AXI_WSTRB(M_AXI_WSTRB),
.M_AXI_WVALID(M_AXI_WVALID),
.M_AXI_WREADY(M_AXI_WREADY),
.M_AXI_BRESP(M_AXI_BRESP),
.M_AXI_BVALID(M_AXI_BVALID),
.M_AXI_BREADY(M_AXI_BREADY),
.M_AXI_ARADDR(M_AXI_ARADDR),
.M_AXI_ARPROT(M_AXI_ARPROT),
.M_AXI_ARVALID(M_AXI_ARVALID),
.M_AXI_ARREADY(M_AXI_ARREADY),
.M_AXI_RDATA(M_AXI_RDATA),
.M_AXI_RRESP(M_AXI_RRESP),
.M_AXI_RVALID(M_AXI_RVALID),
.M_AXI_RREADY(M_AXI_RREADY),
.init_done(init_done)
);
axi_lite_slave_BFM axi_lite_slave_BFM_i (
.M_AXI_ACLK(M_AXI_ACLK),
.M_AXI_ARESETN(M_AXI_ARESETN),
.M_AXI_AWADDR(M_AXI_AWADDR),
.M_AXI_AWPROT(M_AXI_AWPROT),
.M_AXI_AWVALID(M_AXI_AWVALID),
.M_AXI_AWREADY(M_AXI_AWREADY),
.M_AXI_WDATA(M_AXI_WDATA),
.M_AXI_WSTRB(M_AXI_WSTRB),
.M_AXI_WVALID(M_AXI_WVALID),
.M_AXI_WREADY(M_AXI_WREADY),
.M_AXI_BRESP(M_AXI_BRESP),
.M_AXI_BVALID(M_AXI_BVALID),
.M_AXI_BREADY(M_AXI_BREADY),
.M_AXI_ARADDR(M_AXI_ARADDR),
.M_AXI_ARPROT(M_AXI_ARPROT),
.M_AXI_ARVALID(M_AXI_ARVALID),
.M_AXI_ARREADY(M_AXI_ARREADY),
.M_AXI_RDATA(M_AXI_RDATA),
.M_AXI_RRESP(M_AXI_RRESP),
.M_AXI_RVALID(M_AXI_RVALID),
.M_AXI_RREADY(M_AXI_RREADY)
);
initial begin
// Initialize Inputs
init_done = 1'b0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
init_done = 1'b1;
end
// ACLK のインスタンス
clk_gen #(
.CLK_PERIOD(100), // 10nsec, 100MHz
.CLK_DUTY_CYCLE(0.5),
.CLK_OFFSET(0),
.START_STATE(1'b0)
) ACLKi (
.clk_out(M_AXI_ACLK)
);
// reset_gen のインスタンス
reset_gen #(
.RESET_STATE(1'b0),
.RESET_TIME(1000) // 100nsec
) RESETi (
.reset_out(M_AXI_ARESETN)
);
endmodule
module clk_gen #(
parameter CLK_PERIOD = 100,
parameter real CLK_DUTY_CYCLE = 0.5,
parameter CLK_OFFSET = 0,
parameter START_STATE = 1'b0 )
(
output reg clk_out
);
begin
initial begin
#CLK_OFFSET;
forever
begin
clk_out = START_STATE;
#(CLK_PERIOD-(CLK_PERIOD*CLK_DUTY_CYCLE)) clk_out = ~START_STATE;
#(CLK_PERIOD*CLK_DUTY_CYCLE);
end
end
end
endmodule
module reset_gen #(
parameter RESET_STATE = 1'b1,
parameter RESET_TIME = 100 )
(
output reg reset_out
);
begin
initial begin
reset_out = RESET_STATE;
#RESET_TIME;
reset_out = ~RESET_STATE;
end
end
endmodule
`default_nettype wire
//
// AXI Lite Master 用 AXI Slave Bus Fuction Model (BFM)
// axi_lite_slave_BFM.v
// AXI Master用 AXI Slave Bus Function Mode (BFM)へのラッパー
//
// 2013/06/19
//
`default_nettype none
module axi_lite_slave_BFM # (
parameter integer C_M_AXI_ADDR_WIDTH = 32,
parameter integer C_M_AXI_DATA_WIDTH = 32,
parameter C_M_AXI_AxSIZE = 3'b010, // 4バイト
parameter integer C_OFFSET_WIDTH = 10, // 割り当てるRAMのアドレスのビット幅
parameter integer WRITE_RANDOM_WAIT = 0, // Write Transaction のデータ転送の時にランダムなWaitを発生させる=1, Waitしない=0
parameter integer WR_BVALID_RANDOM_WAIT = 0, // Write Transaction の時のM_AXI_BVALID をランダムにWaitする=1, Waitしない=0
parameter integer READ_RANDOM_WAIT = 0 // Read Transaction のデータ転送の時にランダムなWaitを発生させる=1, Waitしない=0
) (
// System Signals
input wire M_AXI_ACLK,
input wire M_AXI_ARESETN,
// Master Interface Write Address
input wire [C_M_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
input wire [3-1:0] M_AXI_AWPROT,
input wire M_AXI_AWVALID,
output wire M_AXI_AWREADY,
// Master Interface Write Data
input wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
input wire [C_M_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
input wire M_AXI_WVALID,
output wire M_AXI_WREADY,
// Master Interface Write Response
output wire [2-1:0] M_AXI_BRESP,
output wire M_AXI_BVALID,
input wire M_AXI_BREADY,
// Master Interface Read Address
input wire [C_M_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
input wire [3-1:0] M_AXI_ARPROT,
input wire M_AXI_ARVALID,
output wire M_AXI_ARREADY,
// Master Interface Read Data
input wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY
);
// Instantiate the Unit Under Test (UUT_slave)
axi_slave_bfm #(
.C_M_AXI_ADDR_WIDTH(C_M_AXI_ADDR_WIDTH),
.C_M_AXI_DATA_WIDTH(C_M_AXI_DATA_WIDTH),
.C_OFFSET_WIDTH(C_OFFSET_WIDTH),
.C_M_AXI_BURST_LEN(1),
.WRITE_RANDOM_WAIT(WRITE_RANDOM_WAIT),
.WR_BVALID_RANDOM_WAIT(WR_BVALID_RANDOM_WAIT),
.READ_RANDOM_WAIT(READ_RANDOM_WAIT)
) axi_slave_bfm_i (
.ACLK(M_AXI_ACLK),
.ARESETN(M_AXI_ARESETN),
.M_AXI_AWID(1'b0),
.M_AXI_AWADDR(M_AXI_AWADDR),
.M_AXI_AWLEN(8'd0), // 1 Word
.M_AXI_AWSIZE(C_M_AXI_AxSIZE),
.M_AXI_AWBURST(2'b01), // INCR （アドレスをインクリメント））
.M_AXI_AWLOCK(1'b0), // ノーマル・アクセス
.M_AXI_AWCACHE(4'b0010), // Normal Non-cacheable Non-bufferable
.M_AXI_AWPROT(M_AXI_AWPROT),
.M_AXI_AWQOS(4'b0000), // default
.M_AXI_AWUSER(),
.M_AXI_AWVALID(M_AXI_AWVALID),
.M_AXI_AWREADY(M_AXI_AWREADY),
.M_AXI_WDATA(M_AXI_WDATA),
.M_AXI_WSTRB(M_AXI_WSTRB),
.M_AXI_WLAST(1'b1),
.M_AXI_WUSER(),
.M_AXI_WVALID(M_AXI_WVALID),
.M_AXI_WREADY(M_AXI_WREADY),
.M_AXI_BID(),
.M_AXI_BRESP(M_AXI_BRESP),
.M_AXI_BUSER(),
.M_AXI_BVALID(M_AXI_BVALID),
.M_AXI_BREADY(M_AXI_BREADY),
.M_AXI_ARID(1'b0),
.M_AXI_ARADDR(M_AXI_ARADDR),
.M_AXI_ARLEN(8'd0), // 1 Word
.M_AXI_ARSIZE(C_M_AXI_AxSIZE),
.M_AXI_ARBURST(2'b01), // INCR （アドレスをインクリメント）
.M_AXI_ARLOCK(2'b00), // ノーマル・アクセス
.M_AXI_ARCACHE(4'b0010), // Normal Non-cacheable Non-bufferable
.M_AXI_ARPROT(M_AXI_ARPROT),
.M_AXI_ARQOS(4'b0000), // default
.M_AXI_ARUSER(),
.M_AXI_ARVALID(M_AXI_ARVALID),
.M_AXI_ARREADY(M_AXI_ARREADY),
.M_AXI_RID(),
.M_AXI_RDATA(M_AXI_RDATA),
.M_AXI_RRESP(M_AXI_RRESP),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(M_AXI_RVALID),
.M_AXI_RREADY(M_AXI_RREADY)
);
endmodule
`default_nettype wire
00000010
12345678
00000020
11223344
00000030
55667788
ffffffff
///////////////////////////////////////////////////////////////////////////////
//
// AXI4/Lite Master
//
////////////////////////////////////////////////////////////////////////////
//
// Structure:
// reg_set_axi_lite_master
//
////////////////////////////////////////////////////////////////////////////
`default_nettype none
module reg_set_axi_lite_master # (
parameter integer C_M_AXI_ADDR_WIDTH = 32,
parameter integer C_M_AXI_DATA_WIDTH = 32
)(
// System Signals
input wire M_AXI_ACLK,
input wire M_AXI_ARESETN,
// Master Interface Write Address
output wire [C_M_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [3-1:0] M_AXI_AWPROT,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
// Master Interface Write Data
output wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_M_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
// Master Interface Write Response
input wire [2-1:0] M_AXI_BRESP,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Master Interface Read Address
output wire [C_M_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [3-1:0] M_AXI_ARPROT,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
// Master Interface Read Data
input wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY,
input wire init_done
);
reg [31:0] rom [0:255];
reg [31:0] rom_dout;
initial begin
$readmemh("vdma_reg_set.txt", rom, 0, 255);
end
reg reset_1b, reset;
reg [31:0] reg_addr;
reg [31:0] reg_data;
reg [7:0] rom_addr;
reg awvalid;
reg wvalid;
reg bready;
localparam RESP_OKAY = 2'b00,
RESP_EXOKAY = 2'b01,
RESP_SLVERR = 2'b10,
RESP_DECERR = 2'b11;
localparam IDLE_RRSM = 3'b000,
ADDRESS_READ = 3'b001,
DATA_READ = 3'b011,
REG_SET_DATA_VALID = 3'b010,
END_RRSM = 3'b110;
reg [2:0] rrsm_cs;
localparam IDLE_ADDR = 2'b00,
AWVALID_ASSERT = 2'b01,
AWVALID_HOLD_OFF = 2'b11;
reg [1:0] addr_cs;
localparam IDLE_DATA = 2'b00,
WVALID_ASSERT = 2'b01,
WVALID_HOLD_OFF = 2'b11;
reg [1:0] data_cs;
localparam IDLE_RESP = 1'b0,
BREADY_ASSERT = 1'b1;
reg resp_cs;
reg reg_data_valid;
reg rom_read_done;
// Read is not implement
assign M_AXI_ARADDR = 0;
assign M_AXI_ARPROT = 3'd0;
assign M_AXI_ARVALID = 1'b0;
assign M_AXI_RDATA = 0;
assign M_AXI_RREADY = 1'b1;
assign M_AXI_WSTRB = 4'b1111;
assign M_AXI_AWPROT = 3'b000;
// reset
always @(posedge M_AXI_ACLK) begin
reset_1b <= ~M_AXI_ARESETN | ~init_done;
reset <= reset_1b;
end
// instantiaton of rom
always @(posedge M_AXI_ACLK) begin
rom_dout <= rom[rom_addr];
end
// rom read State Machine
always @(posedge M_AXI_ACLK) begin
if (reset) begin
rrsm_cs <= IDLE_RRSM;
reg_data_valid <= 1'b0;
end else begin
case (rrsm_cs)
IDLE_RRSM :
rrsm_cs <= ADDRESS_READ;
ADDRESS_READ :
rrsm_cs <= DATA_READ;
DATA_READ : begin
if (rom_dout == 32'hFFFF_FFFF) begin // end
rrsm_cs <= END_RRSM;
reg_data_valid <= 1'b0;
end else begin
rrsm_cs <= REG_SET_DATA_VALID;
reg_data_valid <= 1'b1;
end
end
REG_SET_DATA_VALID : begin
if (rom_read_done) begin
rrsm_cs <= ADDRESS_READ;
reg_data_valid <= 1'b0;
end
end
END_RRSM :
rrsm_cs <= END_RRSM;
endcase
end
end
// rom_addr
always @(posedge M_AXI_ACLK) begin
if (reset) begin
rom_addr <= 8'd0;
end else begin
if (rrsm_cs == ADDRESS_READ) // Data
rom_addr <= rom_addr + 8'd1;
else if (rrsm_cs == REG_SET_DATA_VALID && rom_read_done) // Address
rom_addr <= rom_addr + 8'd1;
end
end
// AXI4 Lite Master Address
always @(posedge M_AXI_ACLK) begin
if (reset) begin
reg_addr <= 32'd0;
end else begin
if (rrsm_cs == DATA_READ)
reg_addr <= rom_dout;
end
end
assign M_AXI_AWADDR = reg_addr;
// AXI4 Lite Master WDATA
always @(posedge M_AXI_ACLK) begin
if (reset) begin
reg_data <= 32'd0;
end else begin
if (rrsm_cs == REG_SET_DATA_VALID)
reg_data <= rom_dout;
end
end
assign M_AXI_WDATA = reg_data;
// AXI Lite Master Address State Machine
always @(posedge M_AXI_ACLK) begin
if (reset) begin
addr_cs <= IDLE_ADDR;
awvalid <= 1'b0;
end else begin
case (addr_cs)
IDLE_ADDR :
if (rrsm_cs == REG_SET_DATA_VALID) begin
addr_cs <= AWVALID_ASSERT;
awvalid <= 1'b1;
end
AWVALID_ASSERT :
if (M_AXI_AWREADY) begin
addr_cs <= AWVALID_HOLD_OFF;
awvalid <= 1'b0;
end
AWVALID_HOLD_OFF :
if (rrsm_cs != REG_SET_DATA_VALID)
addr_cs <= IDLE_ADDR;
endcase
end
end
assign M_AXI_AWVALID = awvalid;
// AXI Lite Master Data State Machine
always @(posedge M_AXI_ACLK) begin
if (reset) begin
data_cs <= IDLE_DATA;
wvalid <= 1'b0;
rom_read_done <= 1'b0;
end else begin
case (data_cs)
IDLE_DATA : begin
rom_read_done <= 1'b0;
if (rrsm_cs == REG_SET_DATA_VALID) begin
data_cs <= WVALID_ASSERT;
wvalid <= 1'b1;
end
end
WVALID_ASSERT :
if (M_AXI_WREADY) begin
wvalid <= 1'b0;
rom_read_done <= 1'b1;
data_cs <= WVALID_HOLD_OFF;
end
WVALID_HOLD_OFF : begin
rom_read_done <= 1'b0;
if (addr_cs == AWVALID_HOLD_OFF)
data_cs <= IDLE_DATA;
end
endcase
end
end
assign M_AXI_WVALID = wvalid;
// bready State Machine
always @(posedge M_AXI_ACLK) begin
if (reset) begin
resp_cs <= IDLE_RESP;
bready <= 1'b0;
end else begin
case (resp_cs)
IDLE_RESP :
if (M_AXI_WREADY && data_cs == WVALID_ASSERT) begin
resp_cs <= BREADY_ASSERT;
bready <= 1'b1;
end
BREADY_ASSERT :
if (M_AXI_BVALID) begin
resp_cs <= IDLE_RESP;
bready <= 1'b0;
end
endcase
end
end
assign M_AXI_BREADY = bready;
endmodule
`default_nettype none
#.hexファイルを読んで、命令をidram.vhdの分散RAMの初期値として書き込む
def usage
STDERR.print "usage : #$0 [input .hex file name] [output init_idram.txt file] \n"
exit 1
end
if ARGV.size < 2
usage
else
mem_data = [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0]
file = File.open(ARGV[0], 'r')
while line=file.gets
if line[0, 1] == ':' then # intel hex code
max = line[1,2].hex
address = (line[3,4].hex)/4
if line[7,2] == "00" then # normal data record
for i in 1..max/4 do
mem_data[address] = line[9+(i-1)*8,8].hex
address += 1
end
end
end
end
file.close
## mem_data.each do |i|
## printf("%0.8X", *i)
## print "\n"
# end
init_data_file = File.open(ARGV[1], 'w') # RAMの初期化データファイルを出力でオープン
i = 0
while i < mem_data.size
init_data_file.printf("%.8X\r\n", *mem_data[i])
i += 1
end
init_data_file.close
end
ocra-1.2.0 Documentation
rubyforge.org/projects/ocra
github.com/larsch/ocra
..\Ruby-1.9.1-p378\bin\ruby.exe ocrasa.rb inst_load_hex.rb
inst_load_hex.exe disp_test2.hex init_idram.txt
表面実装用USBコネクタ(ミニB)(2個入)
超高輝度白色LED5mm OSPW5111A-YZ 10個入
ターミナルブロック 2ピン(緑)(縦)小
ターミナルブロック 2ピン(青)(縦)小
RGBイルミネーション・フルカラーLED 5mm乳白色ボディ OST1MK5A32A (10個入)
3. Gerber file requirements:
The following layers are needed:
Top Layer: pcbname.GTL
Bottom Layer: pcbname.GBL
Solder Mask Top: pcbname.GTS
Solder Mask Bottom: pcbname.GBS
Silk Top: pcbname.GTO
Silk Bottom: pcbname.GBO
Drill Drawing: pcbname.TXT
Board Outline:pcbname.GML/GKO
Note:
The Gerber file must be RS-274x format.
06/14/2013 PCB Processing PCB File:D84539_15681_MSC_006.zip passed file examination.
（2013/06/15：修正）
レイヤーとレンダーを一緒に使用している時に、つまり、レイヤーB.Cu、レンダーModule Backのチェックを外して、表面の配線をしてから、レイヤーとレンダーに全てチェックを入れ、レイヤーF.CuとレンダーModule Back のチェックを外して、配線を書くときに表面の同じネットの配線がハイライトされますが、その配線と同じルートで裏面も配線を引くと、そのときは配線が表示されないようです。
ズームしたりレイヤーにチェックを入れたりすると表示されます。実際には配線が書けています。
キャラクタROMをAXI4 Lite Slave として実装する１（AXI4 Lite バスの勉強）
キャラクタROMをAXI4 Lite Slave として実装する２（AXI4 Lite バスの勉強２）
VHDLでのブロックRAMや分散RAMの初期化（外部データファイル）
VHDLでのブロックRAMや分散RAMの初期化（16進数で書かれた外部データファイル）
## -- DISCLAIMER OF LIABILITY
## --
## -- This file contains proprietary and confidential information of
## -- Xilinx, Inc. ("Xilinx"), that is distributed under a license
## -- from Xilinx, and may be used, copied and/or disclosed only
## -- pursuant to the terms of a valid license agreement with Xilinx.
## --
## -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
## -- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
## -- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
## -- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
## -- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
## -- does not warrant that functions included in the Materials will
## -- meet the requirements of Licensee, or that the operation of the
## -- Materials will be uninterrupted or error-free, or that defects
## -- in the Materials will be corrected. Furthermore, Xilinx does
## -- not warrant or make any representations regarding use, or the
## -- results of the use, of the Materials in terms of correctness,
## -- accuracy, reliability or otherwise.
## --
## -- Xilinx products are not designed or intended to be fail-safe,
## -- or for use in any application requiring fail-safe performance,
## -- such as life-support or safety devices or systems, Class III
## -- medical devices, nuclear facilities, applications related to
## -- the deployment of airbags, or any other applications that could
## -- lead to death, personal injury or severe property or
## -- environmental damage (individually and collectively, "critical
## -- applications"). Customer assumes the sole risk and liability
## -- of any use of Xilinx products in critical applications,
## -- subject only to applicable laws and regulations governing
## -- limitations on product liability.
## --
## -- Copyright 2009 Xilinx, Inc.
## -- All rights reserved.
## --
## -- This disclaimer and copyright notice must be retained as part
## -- of this file at all times.
##
###############################################################################
##
## video_out_zed_v1_00_a.pao
##
## Peripheral Analyze Order File
##
##
###############################################################################
lib video_out_zed_v1_00_a conv_rgb2ycbcr.v verilog
lib video_out_zed_v1_00_a conv_hdmi_out.v verilog
lib video_out_zed_v1_00_a video_out_zed.v verilog
#-- DISCLAIMER OF LIABILITY
#--
#-- This file contains proprietary and confidential information of
#-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
#-- from Xilinx, and may be used, copied and/or disclosed only
#-- pursuant to the terms of a valid license agreement with Xilinx.
#--
#-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
#-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
#-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
#-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
#-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
#-- does not warrant that functions included in the Materials will
#-- meet the requirements of Licensee, or that the operation of the
#-- Materials will be uninterrupted or error-free, or that defects
#-- in the Materials will be corrected. Furthermore, Xilinx does
#-- not warrant or make any representations regarding use, or the
#-- results of the use, of the Materials in terms of correctness,
#-- accuracy, reliability or otherwise.
#--
#-- Xilinx products are not designed or intended to be fail-safe,
#-- or for use in any application requiring fail-safe performance,
#-- such as life-support or safety devices or systems, Class III
#-- medical devices, nuclear facilities, applications related to
#-- the deployment of airbags, or any other applications that could
#-- lead to death, personal injury or severe property or
#-- environmental damage (individually and collectively, "critical
#-- applications"). Customer assumes the sole risk and liability
#-- of any use of Xilinx products in critical applications,
#-- subject only to applicable laws and regulations governing
#-- limitations on product liability.
#--
#-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
#--
#-- This disclaimer and copyright notice must be retained as part
#-- of this file at all times.
#--
###################################################################
##
## Name : video_out_zed
## Desc : Microprocessor Peripheral Description
## : Automatically generated by PsfUtility
##
###################################################################
BEGIN video_out_zed
## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION STYLE = HDL
OPTION DESC = video_out_zed
OPTION LONG_DESC = Video Out for ZedBoard
OPTION HDL = VERILOG
OPTION RUN_NGCBUILD = FALSE
## Generics for VHDL or Parameters for Verilog
PARAMETER VIDEO_DATA_WIDTH = 24, DT = INTEGER, RANGE = (8,16,24,32,40,48,56,64,128,256)
## Ports
PORT pixclk = "", DIR = I, SIGIS = CLK
PORT aresetn = "", DIR = I, SIGIS = RST
PORT video_de = "", DIR = I
PORT video_vsync = "", DIR = I
PORT video_hsync = "", DIR = I
PORT video_vblank = "", DIR = I
PORT video_hblank = "", DIR = I
PORT video_data = "", DIR = I, VEC = [(VIDEO_DATA_WIDTH-1):0]
PORT vga_red = "", DIR = O, VEC = [3:0]
PORT vga_green = "", DIR = O, VEC = [3:0]
PORT vga_blue = "", DIR = O, VEC = [3:0]
PORT vga_hsync = "", DIR = O
PORT vga_vsync = "", DIR = O
PORT hdmi_clk = "", DIR = O
PORT hdmi_vsync = "", DIR = O
PORT hdmi_hsync = "", DIR = O
PORT hdmi_data_e = "", DIR = O
PORT hdmi_data = "", DIR = O, VEC = [15:0]
END
<?xml version="1.0" encoding="ISO-8859-1"?>
<!--
###############################################################################
## DISCLAIMER OF LIABILITY
##
## This file contains proprietary and confidential information of
## Xilinx, Inc. ("Xilinx"), that is distributed under a license
## from Xilinx, and may be used, copied and/or disclosed only
## pursuant to the terms of a valid license agreement with Xilinx.
##
## XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
## ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
## EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
## LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
## MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
## does not warrant that functions included in the Materials will
## meet the requirements of Licensee, or that the operation of the
## Materials will be uninterrupted or error-free, or that defects
## in the Materials will be corrected. Furthermore, Xilinx does
## not warrant or make any representations regarding use, or the
## results of the use, of the Materials in terms of correctness,
## accuracy, reliability or otherwise.
##
## Xilinx products are not designed or intended to be fail-safe,
## or for use in any application requiring fail-safe performance,
## such as life-support or safety devices or systems, Class III
## medical devices, nuclear facilities, applications related to
## the deployment of airbags, or any other applications that could
## lead to death, personal injury or severe property or
## environmental damage (individually and collectively, "critical
## applications"). Customer assumes the sole risk and liability
## of any use of Xilinx products in critical applications,
## subject only to applicable laws and regulations governing
## limitations on product liability.
##
## Copyright 2009 Xilinx, Inc.
## All rights reserved.
##
## This disclaimer and copyright notice must be retained as part
## of this file at all times.
##
###############################################################################
-->
<!DOCTYPE doc SYSTEM "../../ipdialog.dtd" [
<!-- -->
<!ENTITY VIDEO_DATA_WIDTH '
<widget id="VIDEO_DATA_WIDTH">
<key>VIDEO_DATA_WIDTH</key>
<label>VIDEO_DATA_WIDTH</label>
<tip></tip>
</widget>
'>
]>
<doc>
<view id="VIDEO">
<display>VIDEO</display>
<group id="VIDEO">
<display>VIDEO</display>
<item>&VIDEO_DATA_WIDTH;</item>
</group>
</view>
</doc>
// XPS のIP、v_axi4s_vid_out のVideo出力を受けてVGAポートとHDMI出力に出力する
// video_out_zed.v
// 2013/06/09
//
`default_nettype none
module video_out_zed # (
parameter VIDEO_DATA_WIDTH = 24
) (
input wire pixclk, // pixel clock
input wire aresetn, // AXI reset
input wire video_de, // data enable
input wire video_hsync,
input wire video_vsync,
input wire video_vblank,
input wire video_hblank,
input wire [VIDEO_DATA_WIDTH-1:0] video_data,
(* IOB = "FORCE" *) output reg [3:0] vga_red,
(* IOB = "FORCE" *) output reg [3:0] vga_green,
(* IOB = "FORCE" *) output reg [3:0] vga_blue,
(* IOB = "FORCE" *) output reg vga_hsync,
(* IOB = "FORCE" *) output reg vga_vsync,
(* IOB = "FORCE" *) output wire hdmi_clk,
(* IOB = "FORCE" *) output wire hdmi_vsync,
(* IOB = "FORCE" *) output wire hdmi_hsync,
(* IOB = "FORCE" *) output wire hdmi_data_e,
(* IOB = "FORCE" *) output wire [15:0] hdmi_data
);
reg reset_1b, reset;
reg [7:0] red, green, blue;
reg hsyncx, vsyncx;
// synchronization of reset_1b
always @(posedge pixclk) begin
reset_1b <= ~aresetn;
reset <= reset_1b;
end
// input FF
always @(posedge pixclk) begin
if (reset) begin
red <= 8'd0;
green <= 8'd0;
blue <= 8'd0;
hsyncx <= 1'b1;
vsyncx <= 1'b1;
end else begin
red <= video_data[23:16];
green <= video_data[15:8];
blue <= video_data[7:0];
hsyncx <= ~video_hsync;
vsyncx <= ~video_vsync;
end
end
// Output VGA Port
always @(posedge pixclk) begin
if (reset) begin
vga_hsync <= 1'b1;
vga_vsync <= 1'b1;
end else begin
vga_hsync <= hsyncx;
vga_vsync <= vsyncx;
end
end
always @(posedge pixclk) begin
if (reset) begin
vga_red <= 4'd0;
vga_green <= 4'd0;
vga_blue <= 4'd0;
end else begin
if (video_de) begin
vga_red <= red[7:4];
vga_green <= green[7:4];
vga_blue <= blue[7:4];
end else begin
vga_red <= 4'd0;
vga_green <= 4'd0;
vga_blue <= 4'd0;
end
end
end
conv_hdmi_out conv_hdmi_out_inst (
.clk_disp(pixclk),
.reset_disp(~aresetn),
.red(red),
.green(green),
.blue(blue),
.hsyncx(hsyncx),
.vsyncx(vsyncx),
.display_enable(video_de),
.hdmi_clk(hdmi_clk),
.hdmi_vsync(hdmi_vsync),
.hdmi_hsync(hdmi_hsync),
.hdmi_data_e(hdmi_data_e),
.hdmi_data(hdmi_data)
);
endmodule
`default_nettype wire
`default_nettype none
`timescale 100ps / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03:40:14 06/11/2013
// Design Name: video_out_zed
// Module Name: D:/HDL/FndtnISEWork/Zynq-7000/ZedBoard/test/video_out_zed/video_out_zed_tb.v
// Project Name: video_out_zed
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: video_out_zed
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module video_out_zed_tb;
// Inputs
wire pclk;
wire aresetn;
wire video_de;
wire video_hsync;
wire video_vsync;
wire video_vblank;
wire video_hblank;
wire [23:0] video_data;
// Outputs
wire [3:0] vga_red;
wire [3:0] vga_green;
wire [3:0] vga_blue;
wire vga_hsync;
wire vga_vsync;
wire hdmi_clk;
wire hdmi_vsync;
wire hdmi_hsync;
wire hdmi_data_e;
wire [15:0] hdmi_data;
// R, G, B 毎に違った生成多項式のM系列を用意した
function [7:0] mseqf8_R (input [7:0] din);
reg xor_result;
begin
xor_result = din[7] ^ din[3] ^ din[2] ^ din[1];
mseqf8_R = {din[6:0], xor_result};
end
endfunction
function [7:0] mseqf8_G (input [7:0] din);
reg xor_result;
begin
xor_result = din[7] ^ din[4] ^ din[2] ^ din[0];
mseqf8_G = {din[6:0], xor_result};
end
endfunction
function [7:0] mseqf8_B (input [7:0] din);
reg xor_result;
begin
xor_result = din[7] ^ din[5] ^ din[2] ^ din[1];
mseqf8_B = {din[6:0], xor_result};
end
endfunction
reg [7:0] mseq8r = 8'd1;
reg [7:0] mseq8g = 8'd1;
reg [7:0] mseq8b = 8'd1;
// Instantiate the Unit Under Test (UUT)
video_out_zed video_out_zed_i (
.pclk(pclk),
.aresetn(aresetn),
.video_de(video_de),
.video_hsync(video_hsync),
.video_vsync(video_vsync),
.video_vblank(video_vblank),
.video_hblank(video_hblank),
.video_data(video_data),
.vga_red(vga_red),
.vga_green(vga_green),
.vga_blue(vga_blue),
.vga_hsync(vga_hsync),
.vga_vsync(vga_vsync),
.hdmi_clk(hdmi_clk),
.hdmi_vsync(hdmi_vsync),
.hdmi_hsync(hdmi_hsync),
.hdmi_data_e(hdmi_data_e),
.hdmi_data(hdmi_data)
);
// Instantiate the Unit Under Test (UUT)
custom_vtc custom_vtc_i (
.vclk(pclk),
.aresetn(aresetn),
.vtc_ce(1'b1),
.vtc_act_vid(video_de),
.vtc_vsync(video_vsync),
.vtc_hsync(video_hsync),
.vtc_vblank(video_vblank),
.vtc_hblank(video_hblank)
);
// Red のM系列符号生成
always @(posedge pclk) begin
// if (mt9d111_cs==ACTIVE_DATA_TIME)
mseq8r <= mseqf8_R(mseq8r);
end
// Green のM系列符号生成
always @(posedge pclk) begin
// if (mt9d111_cs==ACTIVE_DATA_TIME)
mseq8g <= mseqf8_G(mseq8g);
end
// Blue のM系列符号生成
always @(posedge pclk) begin
// if (mt9d111_cs==ACTIVE_DATA_TIME)
mseq8b <= mseqf8_B(mseq8b);
end
assign video_data = {mseq8r, mseq8g, mseq8b};
// pclk generate
clk_gen #(
.CLK_PERIOD(250), // 25.0nsec, 40MHz
.CLK_DUTY_CYCLE(0.5),
.CLK_OFFSET(0),
.START_STATE(1'b0)
) pclk_from_pll_i (
.clk_out(pclk)
);
// aresetn generate
reset_gen #(
.RESET_STATE(1'b0),
.RESET_TIME(1000) // 100nsec
) RESETi (
.reset_out(aresetn)
);
endmodule
module clk_gen #(
parameter CLK_PERIOD = 100,
parameter real CLK_DUTY_CYCLE = 0.5,
parameter CLK_OFFSET = 0,
parameter START_STATE = 1'b0 )
(
output reg clk_out
);
begin
initial begin
#CLK_OFFSET;
forever
begin
clk_out = START_STATE;
#(CLK_PERIOD-(CLK_PERIOD*CLK_DUTY_CYCLE)) clk_out = ~START_STATE;
#(CLK_PERIOD*CLK_DUTY_CYCLE);
end
end
end
endmodule
module reset_gen #(
parameter RESET_STATE = 1'b1,
parameter RESET_TIME = 100 )
(
output reg reset_out
);
begin
initial begin
reset_out = RESET_STATE;
#RESET_TIME;
reset_out = ~RESET_STATE;
end
end
endmodule
`default_nettype wire
module video_out_zed # (
parameter VIDEO_DATA_WIDTH = 24
) (
input wire pclk, // pixel clock
input wire aresetn, // AXI reset
input wire video_de // data enable
input wire video_hsync,
input wire video_vsync,
input wire video_vblank,
input wire video_hblank,
input wire [VIDEO_DATA_WIDTH-1:0] video_data,
(* IOB = "FORCE" *) output reg [3:0] vga_red,
(* IOB = "FORCE" *) output reg [3:0] vga_green,
(* IOB = "FORCE" *) output reg [3:0] vga_blue,
(* IOB = "FORCE" *) output reg vga_hsync,
(* IOB = "FORCE" *) output reg vga_vsync,
(* IOB = "FORCE" *) output wire hdmi_clk,
(* IOB = "FORCE" *) output wire hdmi_vsync,
(* IOB = "FORCE" *) output wire hdmi_hsync,
(* IOB = "FORCE" *) output wire hdmi_data_e,
(* IOB = "FORCE" *) output wire [15:0] hdmi_data
);
## -- DISCLAIMER OF LIABILITY
## --
## -- This file contains proprietary and confidential information of
## -- Xilinx, Inc. ("Xilinx"), that is distributed under a license
## -- from Xilinx, and may be used, copied and/or disclosed only
## -- pursuant to the terms of a valid license agreement with Xilinx.
## --
## -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
## -- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
## -- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
## -- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
## -- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
## -- does not warrant that functions included in the Materials will
## -- meet the requirements of Licensee, or that the operation of the
## -- Materials will be uninterrupted or error-free, or that defects
## -- in the Materials will be corrected. Furthermore, Xilinx does
## -- not warrant or make any representations regarding use, or the
## -- results of the use, of the Materials in terms of correctness,
## -- accuracy, reliability or otherwise.
## --
## -- Xilinx products are not designed or intended to be fail-safe,
## -- or for use in any application requiring fail-safe performance,
## -- such as life-support or safety devices or systems, Class III
## -- medical devices, nuclear facilities, applications related to
## -- the deployment of airbags, or any other applications that could
## -- lead to death, personal injury or severe property or
## -- environmental damage (individually and collectively, "critical
## -- applications"). Customer assumes the sole risk and liability
## -- of any use of Xilinx products in critical applications,
## -- subject only to applicable laws and regulations governing
## -- limitations on product liability.
## --
## -- Copyright 2009 Xilinx, Inc.
## -- All rights reserved.
## --
## -- This disclaimer and copyright notice must be retained as part
## -- of this file at all times.
##
###############################################################################
##
## custom_vtc_v1_00_a.pao
##
## Peripheral Analyze Order File
##
##
###############################################################################
lib custom_vtc_v1_00_a custom_vtc.v verilog
#-- DISCLAIMER OF LIABILITY
#--
#-- This file contains proprietary and confidential information of
#-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
#-- from Xilinx, and may be used, copied and/or disclosed only
#-- pursuant to the terms of a valid license agreement with Xilinx.
#--
#-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
#-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
#-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
#-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
#-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
#-- does not warrant that functions included in the Materials will
#-- meet the requirements of Licensee, or that the operation of the
#-- Materials will be uninterrupted or error-free, or that defects
#-- in the Materials will be corrected. Furthermore, Xilinx does
#-- not warrant or make any representations regarding use, or the
#-- results of the use, of the Materials in terms of correctness,
#-- accuracy, reliability or otherwise.
#--
#-- Xilinx products are not designed or intended to be fail-safe,
#-- or for use in any application requiring fail-safe performance,
#-- such as life-support or safety devices or systems, Class III
#-- medical devices, nuclear facilities, applications related to
#-- the deployment of airbags, or any other applications that could
#-- lead to death, personal injury or severe property or
#-- environmental damage (individually and collectively, "critical
#-- applications"). Customer assumes the sole risk and liability
#-- of any use of Xilinx products in critical applications,
#-- subject only to applicable laws and regulations governing
#-- limitations on product liability.
#--
#-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
#--
#-- This disclaimer and copyright notice must be retained as part
#-- of this file at all times.
#--
###################################################################
##
## Name : custom_vtc
## Desc : Microprocessor Peripheral Description
## : Automatically generated by PsfUtility
##
###################################################################
BEGIN custom_vtc
## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION STYLE = HDL
OPTION DESC = custom_vtc
OPTION LONG_DESC = Custom Video Timing Controller
OPTION HDL = VERILOG
OPTION RUN_NGCBUILD = FALSE
## Bus Interfaces
BUS_INTERFACE BUS = VTIMING_OUT, BUS_TYPE = INITIATOR, BUS_STD = VTIMING
## Generics for VHDL or Parameters for Verilog
PARAMETER H_ACTIVE_VIDEO = 800, DT = integer
PARAMETER H_FRONT_PORCH = 40, DT = integer
PARAMETER H_SYNC_PULSE = 128, DT = integer
PARAMETER H_BACK_PORCH = 88, DT = integer
PARAMETER V_ACTIVE_VIDEO = 600, DT = integer
PARAMETER V_FRONT_PORCH = 1, DT = integer
PARAMETER V_SYNC_PULSE = 4, DT = integer
PARAMETER V_BACK_PORCH = 23, DT = integer
## Ports
PORT vclk = "", DIR = I, SIGIS = CLK
PORT aresetn = "", DIR = I, SIGIS = RST
PORT vtc_ce = "", DIR = I
PORT vtg_act_vid = active_video, DIR = O, BUS = VTIMING_OUT
PORT vtg_vsync = vsync, DIR = O, BUS = VTIMING_OUT
PORT vtg_hsync = hsync, DIR = O, BUS = VTIMING_OUT
PORT vtg_vblank = vblank, DIR = O, BUS = VTIMING_OUT
PORT vtg_hblank = hblank, DIR = O, BUS = VTIMING_OUT
END
<?xml version="1.0" encoding="ISO-8859-1"?>
<!--
###############################################################################
## DISCLAIMER OF LIABILITY
##
## This file contains proprietary and confidential information of
## Xilinx, Inc. ("Xilinx"), that is distributed under a license
## from Xilinx, and may be used, copied and/or disclosed only
## pursuant to the terms of a valid license agreement with Xilinx.
##
## XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
## ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
## EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
## LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
## MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
## does not warrant that functions included in the Materials will
## meet the requirements of Licensee, or that the operation of the
## Materials will be uninterrupted or error-free, or that defects
## in the Materials will be corrected. Furthermore, Xilinx does
## not warrant or make any representations regarding use, or the
## results of the use, of the Materials in terms of correctness,
## accuracy, reliability or otherwise.
##
## Xilinx products are not designed or intended to be fail-safe,
## or for use in any application requiring fail-safe performance,
## such as life-support or safety devices or systems, Class III
## medical devices, nuclear facilities, applications related to
## the deployment of airbags, or any other applications that could
## lead to death, personal injury or severe property or
## environmental damage (individually and collectively, "critical
## applications"). Customer assumes the sole risk and liability
## of any use of Xilinx products in critical applications,
## subject only to applicable laws and regulations governing
## limitations on product liability.
##
## Copyright 2009 Xilinx, Inc.
## All rights reserved.
##
## This disclaimer and copyright notice must be retained as part
## of this file at all times.
##
###############################################################################
-->
<!DOCTYPE doc SYSTEM "../../ipdialog.dtd" [
<!-- -->
<!ENTITY H_ACTIVE_VIDEO '
<widget id="H_ACTIVE_VIDEO">
<key>H_ACTIVE_VIDEO</key>
<label>H_ACTIVE_VIDEO</label>
<tip></tip>
</widget>
'>
<!ENTITY H_FRONT_PORCH '
<widget id="H_FRONT_PORCH">
<key>H_FRONT_PORCH</key>
<label>H_FRONT_PORCH</label>
<tip></tip>
</widget>
'>
<!ENTITY H_SYNC_PULSE '
<widget id="H_SYNC_PULSE">
<key>H_SYNC_PULSE</key>
<label>H_SYNC_PULSE</label>
<tip></tip>
</widget>
'>
<!ENTITY H_BACK_PORCH '
<widget id="H_BACK_PORCH">
<key>H_BACK_PORCH</key>
<label>H_BACK_PORCH</label>
<tip></tip>
</widget>
'>
<!ENTITY V_ACTIVE_VIDEO '
<widget id="V_ACTIVE_VIDEO">
<key>V_ACTIVE_VIDEO</key>
<label>V_ACTIVE_VIDEO</label>
<tip></tip>
</widget>
'>
<!ENTITY V_FRONT_PORCH '
<widget id="V_FRONT_PORCH">
<key>V_FRONT_PORCH</key>
<label>V_FRONT_PORCH</label>
<tip></tip>
</widget>
'>
<!ENTITY V_SYNC_PULSE '
<widget id="V_SYNC_PULSE">
<key>V_SYNC_PULSE</key>
<label>V_SYNC_PULSE</label>
<tip></tip>
</widget>
'>
<!ENTITY C_M_AXI_SUPPORTS_WRITE '
<widget id="C_M_AXI_SUPPORTS_WRITE">
<key>C_M_AXI_SUPPORTS_WRITE</key>
<label>C_M_AXI_SUPPORTS_WRITE</label>
<tip></tip>
</widget>
'>
<!ENTITY V_BACK_PORCH '
<widget id="V_BACK_PORCH">
<key>V_BACK_PORCH</key>
<label>V_BACK_PORCH</label>
<tip></tip>
</widget>
'>
]>
<doc>
<view id="Video Timing">
<display>Video Timing</display>
<group id="Video Timing">
<display>Video Timing</display>
<item>&H_ACTIVE_VIDEO;</item>
<item>&H_FRONT_PORCH;</item>
<item>&H_SYNC_PULSE;</item>
<item>&H_BACK_PORCH;</item>
<item>&V_ACTIVE_VIDEO;</item>
<item>&V_FRONT_PORCH;</item>
<item>&V_SYNC_PULSE;</item>
<item>&V_BACK_PORCH;</item>
</group>
</view>
</doc>
<!DOCTYPE doc SYSTEM "../../ipdialog.dtd" [
<?xml version="1.0" encoding="ISO-8859-1"?>
<!DOCTYPE doc SYSTEM "../../ipdialog.dtd" [
<!-- -->
<!ENTITY H_ACTIVE_VIDEO '
<widget id="H_ACTIVE_VIDEO">
<key>H_ACTIVE_VIDEO</key>
<label>H_ACTIVE_VIDEO</label>
<tip></tip>
</widget>
'>
<!ENTITY H_FRONT_PORCH '
<widget id="H_FRONT_PORCH">
<key>H_FRONT_PORCH</key>
<label>H_FRONT_PORCH</label>
<tip></tip>
</widget>
'>
<!ENTITY H_SYNC_PULSE '
<widget id="H_SYNC_PULSE">
<key>H_SYNC_PULSE</key>
<label>H_SYNC_PULSE</label>
<tip></tip>
</widget>
'>
<!ENTITY H_BACK_PORCH '
<widget id="H_BACK_PORCH">
<key>H_BACK_PORCH</key>
<label>H_BACK_PORCH</label>
<tip></tip>
</widget>
'>
<!ENTITY V_ACTIVE_VIDEO '
<widget id="V_ACTIVE_VIDEO">
<key>V_ACTIVE_VIDEO</key>
<label>V_ACTIVE_VIDEO</label>
<tip></tip>
</widget>
'>
<!ENTITY V_FRONT_PORCH '
<widget id="V_FRONT_PORCH">
<key>V_FRONT_PORCH</key>
<label>V_FRONT_PORCH</label>
<tip></tip>
</widget>
'>
<!ENTITY V_SYNC_PULSE '
<widget id="V_SYNC_PULSE">
<key>V_SYNC_PULSE</key>
<label>V_SYNC_PULSE</label>
<tip></tip>
</widget>
'>
<!ENTITY C_M_AXI_SUPPORTS_WRITE '
<widget id="C_M_AXI_SUPPORTS_WRITE">
<key>C_M_AXI_SUPPORTS_WRITE</key>
<label>C_M_AXI_SUPPORTS_WRITE</label>
<tip></tip>
</widget>
'>
<!ENTITY V_BACK_PORCH '
<widget id="V_BACK_PORCH">
<key>V_BACK_PORCH</key>
<label>V_BACK_PORCH</label>
<tip></tip>
</widget>
'>
]>
<doc>
<view id="Video Timing">
<display>Video Timing1</display>
<group id="Video Timing">
<display>Video Timing2</display>
<item>&H_ACTIVE_VIDEO;</item>
<item>&H_FRONT_PORCH;</item>
<item>&H_SYNC_PULSE;</item>
<item>&H_BACK_PORCH;</item>
<item>&V_ACTIVE_VIDEO;</item>
<item>&V_FRONT_PORCH;</item>
<item>&V_SYNC_PULSE;</item>
<item>&V_BACK_PORCH;</item>
</group>
</view>
</doc>
// Custom Video Timing Controller IP
// custom_vtc.v
// AXI4バス用
`default_nettype none
// synthesis translate_off
// `include "std_ovl_defines.h"
// synthesis translate_on
module custom_vtc # (
parameter integer H_ACTIVE_VIDEO = 800,
parameter integer H_FRONT_PORCH = 40,
parameter integer H_SYNC_PULSE = 128,
parameter integer H_BACK_PORCH = 88,
parameter integer V_ACTIVE_VIDEO = 600,
parameter integer V_FRONT_PORCH = 1,
parameter integer V_SYNC_PULSE = 4,
parameter integer V_BACK_PORCH = 23
)(
input wire vclk, // ディスプレイ表示用クロック
input wire aresetn, // 非同期リセット負論理
input wire vtc_ce, // VTC clock enable.
output wire vtg_act_vid, // VTG active video signal.
output wire vtg_vsync,
output wire vtg_hsync,
output wire vtg_vblank,
output wire vtg_hblank
);
localparam integer H_SUM = H_ACTIVE_VIDEO + H_FRONT_PORCH + H_SYNC_PULSE + H_BACK_PORCH;
localparam integer V_SUM = V_ACTIVE_VIDEO + V_FRONT_PORCH + V_SYNC_PULSE + V_BACK_PORCH;
reg reset_1b, reset;
reg [15:0] h_count;
reg [15:0] v_count;
reg hsyncx_node, vsyncx_node;
reg display_enable;
reg hblank;
reg vblank;
// aresetn をvclk で同期化
always @(posedge vclk) begin
reset_1b <= ~aresetn;
reset <= reset_1b;
end
// h_countの実装（水平カウンタ）
always @(posedge vclk) begin
if (reset)
h_count <= 0;
else if (vtc_ce) begin
if (h_count>=(H_SUM-1)) // h_count がH_SUM-1よりも大きければ0に戻す(mod H_SUM)
h_count <= 0;
else
h_count <= h_count + 1;
end
end
// v_countの実装（垂直カウンタ）
always @(posedge vclk) begin
if (reset)
v_count <= 0;
else if (vtc_ce) begin
if (h_count>=(H_SUM-1)) begin // 水平カウンタがクリアされるとき
if (v_count>=(V_SUM-1)) // v_count がV_SUM-1よりも大きければ0に戻す(mode V_SUM)
v_count <= 0;
else
v_count <= v_count + 1;
end
end
end
// vtg_hsync 出力（水平同期信号）
always @(posedge vclk) begin
if (reset)
hsyncx_node <= 1'b1;
else if (vtc_ce) begin
if (h_count>(H_ACTIVE_VIDEO + H_FRONT_PORCH-1) && h_count<=(H_ACTIVE_VIDEO + H_FRONT_PORCH + H_SYNC_PULSE-1)) // 水平同期期間
hsyncx_node <= 1'b0;
else
hsyncx_node <= 1'b1;
end
end
assign vtg_hsync = ~hsyncx_node;
// vtg_vsync 出力（水平同期信号）
always @(posedge vclk) begin
if (reset)
vsyncx_node <= 1'b1;
else if (vtc_ce) begin
if (v_count>(V_ACTIVE_VIDEO + V_FRONT_PORCH-1) && v_count<=(V_ACTIVE_VIDEO + V_FRONT_PORCH + V_SYNC_PULSE-1)) // 垂直同期期間
vsyncx_node <= 1'b0;
else
vsyncx_node <= 1'b1;
end
end
assign vtg_vsync = ~vsyncx_node;
// vtg_act_vid 出力
always @(posedge vclk) begin
if (reset)
display_enable <= 1'b0;
else if (vtc_ce) begin
if (h_count<H_ACTIVE_VIDEO && v_count<V_ACTIVE_VIDEO)
display_enable <= 1'b1;
else
display_enable <= 1'b0;
end
end
assign vtg_act_vid = display_enable;
// vtg_hblank 出力
always @(posedge vclk) begin
if (reset)
hblank <= 1'b0;
else if (vtc_ce) begin
if (h_count >= H_ACTIVE_VIDEO)
hblank <= 1'b1;
else
hblank <= 1'b0;
end
end
assign vtg_hblank = hblank;
// vtg_vblank 出力
always @(posedge vclk) begin
if (reset)
vblank <= 1'b0;
else if (vtc_ce) begin
if (v_count >= V_ACTIVE_VIDEO)
vblank <= 1'b1;
else
vblank <= 1'b0;
end
end
assign vtg_vblank = vblank;
endmodule
`default_nettype wire
`default_nettype none
`timescale 100ps / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 05:22:59 06/05/2013
// Design Name: custom_vtc
// Module Name: D:/HDL/FndtnISEWork/Zynq-7000/ZedBoard/test/VDMA_test/custom_vtc_tb.v
// Project Name: VDMA_test
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: custom_vtc
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module custom_vtc_tb;
// Inputs
wire vclk;
wire aresetn;
reg vtc_ce;
// Outputs
wire vtg_act_vid;
wire vtg_vsync;
wire vtg_hsync;
wire vtg_vblank;
wire vtg_hblank;
// Instantiate the Unit Under Test (UUT)
custom_vtc uut (
.vclk(vclk),
.aresetn(aresetn),
.vtc_ce(vtc_ce),
.vtg_act_vid(vtg_act_vid),
.vtg_vsync(vtg_vsync),
.vtg_hsync(vtg_hsync),
.vtg_vblank(vtg_vblank),
.vtg_hblank(vtg_hblank)
);
initial begin
// Initialize Inputs
vtc_ce = 1'b0;
// Wait 200 ns for global reset to finish
#2000;
// Add stimulus here
vtc_ce = 1'b1;
end
// vclk generate
clk_gen #(
.CLK_PERIOD(250), // 25.0nsec, 40MHz
.CLK_DUTY_CYCLE(0.5),
.CLK_OFFSET(0),
.START_STATE(1'b0)
) pclk_from_pll_i (
.clk_out(vclk)
);
// aresetn generate
reset_gen #(
.RESET_STATE(1'b0),
.RESET_TIME(1000) // 100nsec
) RESETi (
.reset_out(aresetn)
);
endmodule
module clk_gen #(
parameter CLK_PERIOD = 100,
parameter real CLK_DUTY_CYCLE = 0.5,
parameter CLK_OFFSET = 0,
parameter START_STATE = 1'b0 )
(
output reg clk_out
);
begin
initial begin
#CLK_OFFSET;
forever
begin
clk_out = START_STATE;
#(CLK_PERIOD-(CLK_PERIOD*CLK_DUTY_CYCLE)) clk_out = ~START_STATE;
#(CLK_PERIOD*CLK_DUTY_CYCLE);
end
end
end
endmodule
module reset_gen #(
parameter RESET_STATE = 1'b1,
parameter RESET_TIME = 100 )
(
output reg reset_out
);
begin
initial begin
reset_out = RESET_STATE;
#RESET_TIME;
reset_out = ~RESET_STATE;
end
end
endmodule
`default_nettype wire
module custom_vtc # (
parameter integer H_ACTIVE_VIDEO = 800,
parameter integer H_FRONT_PORCH = 40,
parameter integer H_SYNC_PULSE = 128,
parameter integer H_BACK_PORCH = 88,
parameter integer V_ACTIVE_VIDEO = 600,
parameter integer V_FRONT_PORCH = 1,
parameter integer V_SYNC_PULSE = 4,
parameter integer V_BACK_PORCH = 23
)(
input wire vclk, // ディスプレイ表示用クロック
input wire aresetn, // 非同期リセット負論理
input wire vtc_ce, // VTC clock enable.
output wire vtc_act_vid, // VTC active video signal.
output wire vtc_vsync,
output wire vtc_hsync,
output wire vtc_vblank,
output wire vtc_hblank
);
## AXI Stream Core
lib mt9d111_inf_axi_stream_v1_00_a mt9d111_inf_axi_stream.vhd vhdl
lib mt9d111_inf_axi_stream_v1_00_a pixel_fifo.v verilog
lib mt9d111_inf_axi_stream_v1_00_a mt9d111_cam_conts.v verilog
OPTION DESC = mt9d111_inf_axi_stream
OPTION LONG_DESC = MT9D111 Interface of AXI4-Stream
IO_INTERFACE IO_IF = mt9d111_inf
PARAMETER C_M_AXIS_PROTOCOL = XIL_AXI_STREAM_VID_DATA, DT = STRING, BUS = M_AXIS, ASSIGNMENT = CONSTANT, TYPE = NON_HDL
## Ports
PORT s2mm_aclk = "", DIR = I, SIGIS = CLK
PORT s2mm_prmry_reset = "", DIR = I, SIGIS = RST
PORT s2mm_fsync = "", DIR = O
# IO port for MT9D111
PORT init_done = "", DIR = I, IO_IF = mt9d111_inf, IO_IS = init_done
PORT pclk_from_pll = "", DIR = I, SIGIS = CLK, IO_IF = mt9d111_inf, IO_IS = pclk_from_pll
PORT pclk = "", DIR = I, SIGIS = CLK, IO_IF = mt9d111_inf, IO_IS = pclk
PORT xck = "", DIR =O, SIGIS = CLK, IO_IF = mt9d111_inf, IO_IS = xck
PORT href = "", DIR = I, IO_IF = mt9d111_inf, IO_IS = href
PORT vsync = "", DIR = I, IO_IF = mt9d111_inf, IO_IS = vsync
PORT cam_data = "", DIR = I, VEC = [7:0], IO_IF = mt9d111_inf, IO_IS = cam_data
PORT standby = "", DIR = O, IO_IF = mt9d111_inf, IO_IS = standby
PORT pfifo_overflow = "", DIR = O, IO_IF = mt9d111_inf, IO_IS = pfifo_overflow
PORT pfifo_underflow = "", DIR = O, IO_IF = mt9d111_inf, IO_IS = pfifo_underflow
FILES
pixel_fifo.ngc
-----------------------------------------------------------------------------
--
-- AXI Stream Master用 AXI Stream Slave Bus Function Mode (BFM)
--
-----------------------------------------------------------------------------
-- 2012/02/25 : M_AXI_AWBURST＝1 (INCR) にのみ対応、AWSIZE, ARSIZE = 000 (1byte), 001 (2bytes), 010 (4bytes) のみ対応。
-- 2012/01/15 : BVALID が1になる間隔をランダム変更できるようにした。
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
package m_seq_bfm_pack is
function M_SEQ16_BFM_F(mseq16in : std_logic_vector
)return std_logic_vector;
end package m_seq_bfm_pack;
package body m_seq_bfm_pack is
function M_SEQ16_BFM_F(mseq16in : std_logic_vector
)return std_logic_vector is
variable mseq16 : std_logic_vector(15 downto 0);
variable xor_result : std_logic;
begin
xor_result := mseq16in(15) xor mseq16in(12) xor mseq16in(10) xor mseq16in(8) xor mseq16in(7) xor mseq16in(6) xor mseq16in(3) xor mseq16in(2);
mseq16 := mseq16in(14 downto 0) & xor_result;
return mseq16;
end M_SEQ16_BFM_F;
end m_seq_bfm_pack;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use IEEE.math_real.all;
library work;
use work.m_seq_bfm_pack.all;
--library unisim;
--use unisim.vcomponents.all;
entity axi4s_slave_bfm is
generic (
-- Master AXI Stream Data Width
C_M_AXIS_DATA_WIDTH : integer range 8 to 1024 := 24; C_M_AXI_ID_WIDTH : integer := 1;
TREADY_RANDOM_WAIT : integer := 1 -- m_axis_treadyにランダムなWaitを発生させる=1, Waitしない=0
);
port(
-- System Signals
ACLK : in std_logic;
ARESETN : in std_logic;
-- Master Stream Ports
-- m_axis_aresetn : out std_logic;
m_axis_tdata : in std_logic_vector(C_M_AXIS_DATA_WIDTH-1 downto 0);
m_axis_tstrb : in std_logic_vector((C_M_AXIS_DATA_WIDTH/8)-1 downto 0);
m_axis_tvalid : in std_logic;
m_axis_tready : out std_logic;
m_axis_tlast : in std_logic
);
end axi4s_slave_bfm;
architecture RTL of axi4s_slave_bfm is
signal m_seq16_wr : std_logic_vector(15 downto 0);
signal reset_1d, reset_2d, reset : std_logic := '1';
signal tready : std_logic;
begin
-- ARESETN をACLK で同期化
process (ACLK) begin
if ACLK'event and ACLK='1' then
reset_1d <= not ARESETN;
reset_2d <= reset_1d;
end if;
end process;
reset <= reset_2d;
-- m_seq_wr、16ビットのM系列を計算する
process (ACLK) begin
if ACLK'event and ACLK='1' then
if reset='1' then
m_seq16_wr <= (0 => '1', others => '0');
else
if TREADY_RANDOM_WAIT=1 then -- ランダムなWaitを挿入する
m_seq16_wr <= M_SEQ16_BFM_F(m_seq16_wr);
else -- Wait無し
m_seq16_wr <= (others => '0');
end if;
end if;
end if;
end process;
-- tready のアサート、TREADY_RANDOM_WAIT=1のときはランダムにアサートする
process (ACLK) begin
if ACLK'event and ACLK='1' then
if reset='1' then
tready <= '0';
else
if TREADY_RANDOM_WAIT=1 then -- tready の処理、M系列を計算して128以上だったらWaitする。
if m_seq16_wr(7)='0' then -- tready='1'
tready <= '1';
else -- m_seq16_wr(7)='1' then -- tready='0'
tready <= '0';
end if;
else -- 常時1
tready <= '1';
end if;
end if;
end if;
end process;
m_axis_tready <= tready;
end RTL;
// mt9d111_model.v
// mt9d111 の動作モデル
// RGB565 を出力
`default_nettype none
`timescale 1ns / 1ps
module mt9d111_model # (
parameter integer HORIZONTAL_PIXELS = 800,
parameter integer VERTICAL_LINES = 600,
parameter integer HBLANK_REG = 174, // pixels
parameter integer VBLANK_REG = 16, // rows
parameter integer PCLK_DELAY = 1
)(
input wire xck,
output reg pclk = 1'b1,
output reg href = 1'b0,
output reg vsync = 1'b0,
output reg [7:0] d = 8'd0,
input wire scl,
inout wire sda,
input wire standby
);
parameter [2:0] INITIAL_STATE = 3'b000,
FRAME_START_BLANKING = 3'b001,
ACTIVE_DATA_TIME = 3'b011,
HORIZONTAL_BLANKING = 3'b010,
FRAME_END_BLANKING = 3'b110,
VERTICAL_BLANKING = 3'b111;
reg [2:0] mt9d111_cs = INITIAL_STATE;
reg [2:0] fseb_count = 3'd5;
reg [15:0] adt_count = (HORIZONTAL_PIXELS * 2) - 1;
reg [15:0] hb_count = HBLANK_REG - 1;
reg [15:0] fvt_count = VERTICAL_LINES - 1;
reg [31:0] vb_count = VBLANK_REG * (HORIZONTAL_PIXELS + HBLANK_REG) - 1;
reg [15:0] init_count = 10; // 初期化時間
reg href_node = 1'b0;
reg vsync_node = 1'b0;
reg dout_is_even = 1'b0;
// R, G, B 毎に違った生成多項式のM系列を用意した
function [7:0] mseqf8_R (input [7:0] din);
reg xor_result;
begin
xor_result = din[7] ^ din[3] ^ din[2] ^ din[1];
mseqf8_R = {din[6:0], xor_result};
end
endfunction
function [7:0] mseqf8_G (input [7:0] din);
reg xor_result;
begin
xor_result = din[7] ^ din[4] ^ din[2] ^ din[0];
mseqf8_G = {din[6:0], xor_result};
end
endfunction
function [7:0] mseqf8_B (input [7:0] din);
reg xor_result;
begin
xor_result = din[7] ^ din[5] ^ din[2] ^ din[1];
mseqf8_B = {din[6:0], xor_result};
end
endfunction
reg [7:0] mseq8r = 8'd1;
reg [7:0] mseq8g = 8'd1;
reg [7:0] mseq8b = 8'd1;
// pclk の出力
always @*
pclk <= #PCLK_DELAY xck;
// MT9D111 のステート
always @(posedge pclk) begin
case (mt9d111_cs)
INITIAL_STATE : begin
if (init_count==0) begin
mt9d111_cs <= FRAME_START_BLANKING;
vsync_node <= 1'b1;
end
end
FRAME_START_BLANKING : begin
if (fseb_count==0) begin
mt9d111_cs <= ACTIVE_DATA_TIME;
href_node <= 1'b1;
end
end
ACTIVE_DATA_TIME : begin
if (adt_count==0) begin
if (fvt_count==0) // frame end
mt9d111_cs <= FRAME_END_BLANKING;
else
mt9d111_cs <= HORIZONTAL_BLANKING;
href_node <= 1'b0;
end
end
HORIZONTAL_BLANKING : begin
if (hb_count==0) begin
mt9d111_cs <= ACTIVE_DATA_TIME;
href_node <= 1'b1;
end
end
FRAME_END_BLANKING : begin
if (fseb_count==0) begin
mt9d111_cs <= VERTICAL_BLANKING;
vsync_node <= 1'b0;
end
end
VERTICAL_BLANKING : begin
if (vb_count==0) begin
mt9d111_cs <= FRAME_START_BLANKING;
vsync_node <= 1'b1;
end
end
endcase
end
// vsync, href 出力、レーシングを防ぐためにpclk よりも出力を遅らせる
always @* begin
vsync <= #1 vsync_node;
href <= #1 href_node;
end
// Frame Start/End Blanking Counter (6 pixel clocks)
always @(posedge pclk) begin
if (mt9d111_cs==FRAME_START_BLANKING || mt9d111_cs==FRAME_END_BLANKING) begin
if (fseb_count > 0)
fseb_count <= fseb_count - 3'd1;
end else
fseb_count <= 3'd5;
end
// Initial Counter
always @(posedge pclk) begin
if (mt9d111_cs == INITIAL_STATE) begin
if (init_count != 0)
init_count <= init_count - 1;
end
end
// Active Data Time Counter
always @(posedge pclk) begin
if (mt9d111_cs != INITIAL_STATE) begin
if (mt9d111_cs==ACTIVE_DATA_TIME) begin
if (adt_count > 0)
adt_count <= adt_count - 16'd1;
end else
adt_count <= (HORIZONTAL_PIXELS * 2) - 1;
end
end
// Horizontal Blanking Counter
always @(posedge pclk) begin
if (mt9d111_cs != INITIAL_STATE) begin
if (mt9d111_cs==HORIZONTAL_BLANKING) begin
if (hb_count > 0)
hb_count <= hb_count - 16'd1;
end else
hb_count <= HBLANK_REG - 1;
end
end
// Frame Valid Time Counter
always @(posedge pclk) begin
if (mt9d111_cs != INITIAL_STATE) begin
if (mt9d111_cs==ACTIVE_DATA_TIME && adt_count==0) begin
if (fvt_count > 0)
fvt_count <= fvt_count - 16'd1;
end if (mt9d111_cs == VERTICAL_BLANKING)
fvt_count <= VERTICAL_LINES - 1;
end
end
// Vertical Blanking Counter
always @(posedge pclk) begin
if (mt9d111_cs != INITIAL_STATE) begin
if (mt9d111_cs==VERTICAL_BLANKING) begin
if (vb_count > 0)
vb_count <= vb_count - 32'd1;
end else
vb_count <= VBLANK_REG * (HORIZONTAL_PIXELS + HBLANK_REG) - 1;
end
end
// Red のM系列符号生成
always @(posedge pclk) begin
// if (mt9d111_cs==ACTIVE_DATA_TIME)
mseq8r <= mseqf8_R(mseq8r);
end
// Green のM系列符号生成
always @(posedge pclk) begin
// if (mt9d111_cs==ACTIVE_DATA_TIME)
mseq8g <= mseqf8_G(mseq8g);
end
// Blue のM系列符号生成
always @(posedge pclk) begin
// if (mt9d111_cs==ACTIVE_DATA_TIME)
mseq8b <= mseqf8_B(mseq8b);
end
// d 出力のODD とEVEN を示す
always @(posedge pclk) begin
if (mt9d111_cs==ACTIVE_DATA_TIME)
dout_is_even <= ~dout_is_even;
else
dout_is_even <= 1'b0;
end
// d 出力、レーシングを防ぐためにpclk よりも出力を遅らせる
always @(posedge pclk) begin
if (mt9d111_cs==ACTIVE_DATA_TIME) begin
if (dout_is_even)
d <= #1 {mseq8g[4:2], mseq8b[7:3]};
else
d <= #1 {mseq8r[7:3], mseq8g[7:5]};
end
end
endmodule
`default_nettype wire
`default_nettype none
`timescale 100ps / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:51:18 12/31/2012
// Design Name: mt9d111_inf_axi_master
// Module Name: D:\HDL\FndtnISEWork\Zynq-7000\ZedBoard\test\VDMA_test\mt9d111_inf_axi_stream_tb.v
// Project Name: mt9d111_inf_axi_master
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: mt9d111_inf_axi_master
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module mt9d111_inf_axi_stream_tb;
wire s2mm_aclk;
wire s2mm_prmry_reset;
wire s2mm_fsync;
wire init_done;
wire pclk_from_pll;
wire pclk;
wire href;
wire vsync;
wire [7:0] cam_data;
wire xck;
wire standby;
wire pfifo_overflow;
wire pfifo_underflow;
wire [23:0] m_axis_tdata;
wire [2:0] m_axis_tstrb;
wire m_axis_tvalid;
wire m_axis_tready;
wire m_axis_tlast;
// Instantiate the Unit Under Test (UUT)
mt9d111_inf_axi_stream # (
.C_M_AXIS_DATA_WIDTH(24)
) uut (
.s2mm_aclk(s2mm_aclk),
.s2mm_prmry_reset(s2mm_prmry_reset),
.s2mm_fsync(s2mm_fsync),
.m_axis_tdata(m_axis_tdata),
.m_axis_tstrb(m_axis_tstrb),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.init_done(init_done),
.pclk_from_pll(pclk_from_pll),
.pclk(pclk),
.xck(xck),
.href(href),
.vsync(vsync),
.cam_data(cam_data),
.standby(standby),
.pfifo_overflow(pfifo_overflow),
.pfifo_underflow(pfifo_underflow)
);
assign init_done = 1'b1;
// pclk_from_pll のインスタンス
clk_gen #(
.CLK_PERIOD(278), // 27.8nsec, 約36MHz
.CLK_DUTY_CYCLE(0.5),
.CLK_OFFSET(0),
.START_STATE(1'b0)
) pclk_from_pll_i (
.clk_out(pclk_from_pll)
);
// s2mm_prmry_reset のインスタンス
reset_gen #(
.RESET_STATE(1'b1),
.RESET_TIME(1000) // 100nsec
) RESETi (
.reset_out(s2mm_prmry_reset)
);
// MT9D111 モデル
mt9d111_model #(
.HORIZONTAL_PIXELS(800),
.VERTICAL_LINES(600),
.HBLANK_REG(174),
.VBLANK_REG(16),
.PCLK_DELAY(1)
) mt9d111_model_i (
.xck(xck),
.pclk(pclk),
.href(href),
.vsync(vsync),
.d(cam_data),
.scl(1'b1),
.sda(),
.standby(standby)
);
// Instantiate the Unit Under Test (UUT_slave)
axi4s_slave_bfm #(
.C_M_AXIS_DATA_WIDTH(24),
.TREADY_RANDOM_WAIT(1) // m_axis_treadyにランダムなWaitを発生させる=1, Waitしない=0
) uut_slave (
.ACLK(s2mm_aclk),
.ARESETN(~s2mm_prmry_reset),
.m_axis_tdata(m_axis_tdata),
.m_axis_tstrb(m_axis_tstrb),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast)
);
endmodule
module clk_gen #(
parameter CLK_PERIOD = 100,
parameter real CLK_DUTY_CYCLE = 0.5,
parameter CLK_OFFSET = 0,
parameter START_STATE = 1'b0 )
(
output reg clk_out
);
begin
initial begin
#CLK_OFFSET;
forever
begin
clk_out = START_STATE;
#(CLK_PERIOD-(CLK_PERIOD*CLK_DUTY_CYCLE)) clk_out = ~START_STATE;
#(CLK_PERIOD*CLK_DUTY_CYCLE);
end
end
end
endmodule
module reset_gen #(
parameter RESET_STATE = 1'b1,
parameter RESET_TIME = 100 )
(
output reg reset_out
);
begin
initial begin
reset_out = RESET_STATE;
#RESET_TIME;
reset_out = ~RESET_STATE;
end
end
endmodule
`default_nettype wire
| 日 | 月 | 火 | 水 | 木 | 金 | 土 |
|---|---|---|---|---|---|---|
| - | - | - | - | - | - | 1 |
| 2 | 3 | 4 | 5 | 6 | 7 | 8 |
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| 16 | 17 | 18 | 19 | 20 | 21 | 22 |
| 23 | 24 | 25 | 26 | 27 | 28 | 29 |
| 30 | - | - | - | - | - | - |