・左の Explorer に ip フォルダが増えて、圧縮された xilinx_com_hls_example_1_0.zip もできていた。
・Winodows の Explorer で、ip フォルダを見た。下に示す。
・ip\hdl\verilog フォルダを見た。下に示す。
example_BUS_A_if.v が、AXI4 Lite Slave とのインターフェイスを行うVerilog HDLファイルだ。中を見てみると、AXI4 Lite Slave と ap_hs バスのインターフェイスは、AXI4 Lite Slave にマップされたアドレス経由で行われている。下に Address Info を引用する。
//------------------------Address Info------------------- // 0x00 : Control signals // bit 0 - ap_start (Read/Write/COH) // bit 1 - ap_done (Read/COR) // bit 2 - ap_idle (Read) // bit 3 - ap_ready (Read) // bit 7 - auto_restart (Read/Write) // others - reserved // 0x04 : Global Interrupt Enable Register // bit 0 - Global Interrupt Enable (Read/Write) // others - reserved // 0x08 : IP Interrupt Enable Register (Read/Write) // bit 0 - Channel 0 (ap_done) // bit 1 - Channel 1 (ap_ready) // others - reserved // 0x0c : IP Interrupt Status Register (Read/TOW) // bit 0 - Channel 0 (ap_done) // bit 1 - Channel 1 (ap_ready) // others - reserved // 0x10 : Control signal of a // bit 0 - a_ap_vld (Read/Write/COH) // bit 1 - a_ap_ack (Read) // others - reserved // 0x14 : Data signal of a // bit 7~0 - a[7:0] (Read/Write) // others - reserved // 0x18 : Control signal of b // bit 0 - b_ap_vld (Read/Write/SC) // others - reserved // 0x1c : Data signal of b // bit 7~0 - b[7:0] (Read/Write) // others - reserved // 0x20 : reserved // 0x24 : Data signal of c_i // bit 7~0 - c_i[7:0] (Read/Write) // others - reserved // 0x28 : reserved // 0x2c : Data signal of c_o // bit 7~0 - c_o[7:0] (Read) // others - reserved // (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
この方式では、AXI4 Lite バスに接続されたプロセッサ?などの負担が大きくなる。しかもサンプルドライバが必要なはずだ。探してみると、solution1\impl\drivers\example_top_v1_00_a\src にドライバのCソースコードがあった。下に示す。
Starting C/RTL cosimulation ... C:/HDL/Xilinx/Vivado_HLS/2013.2/Win_x86/bin/vivado_hls_bin.exe C:\Users\Masaaki\Documents\Vivado_HLS\axi_lite\proj_axi_lite\solution1\cosim.tcl @I [LIC-101] Checked out feature [HLS] @I [HLS-10] Running 'C:/HDL/Xilinx/Vivado_HLS/2013.2/Win_x86/bin/vivado_hls_bin.exe' for user 'Masaaki' on host 'masaaki-pc' (Windows NT_intel version 6.1) on Mon Aug 26 04:18:16 +0900 2013 in directory 'C:/Users/Masaaki/Documents/Vivado_HLS/axi_lite' @I [HLS-10] Opening project 'C:/Users/Masaaki/Documents/Vivado_HLS/axi_lite/proj_axi_lite'. @I [HLS-10] Opening solution 'C:/Users/Masaaki/Documents/Vivado_HLS/axi_lite/proj_axi_lite/solution1'. @I [SYN-201] Setting up clock 'default' with a period of 13.3333ns. @I [HLS-10] Setting target device to 'xc7z020clg484-2' @I [SIM-47] Using XSIM for RTL simulation. @I [SIM-14] Instrumenting C test bench ... Build using "C:/HDL/Xilinx/Vivado_HLS/2013.2/msys/bin/g++.exe" Compiling apatb_example.cpp Compiling example.cpp_pre.cpp.tb.cpp Compiling example_test.cpp_pre.cpp.tb.cpp Generating cosim.tv.exe @I [SIM-302] Generating test vectors ... HLS AXI-Lite Example Function c += a + b Initial values a = 5, b = 10, c = 0 HW result = 15 SW result = 15 Success SW and HW results match @I [SIM-333] Generating C post check test bench ... @I [SIM-12] Generating RTL test bench ... @I [SIM-323] Starting verilog simulation. @I [SIM-15] Starting XSIM ...
C:\Users\Masaaki\Documents\Vivado_HLS\axi_lite\proj_axi_lite\solution1\sim\verilog>call xelab apatb_example_top -prj example.prj --lib "ieee_proposed=./ieee_proposed" -s example Vivado Simulator 2013.2 Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. Running: C:/HDL/Xilinx/Vivado/2013.2/bin/unwrapped/win64.o/xelab.exe apatb_example_top -prj example.prj --lib ieee_proposed=./ieee_proposed -s example Determining compilation order of HDL files INFO: [VRFC 10-165] Analyzing Verilog file "example.autotb.v" into library work INFO: [VRFC 10-165] Analyzing Verilog file "example.v" into library work Starting static elaboration Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module work.example Compiling module work.apatb_example_top Built simulation snapshot example
****** xsim v2013.2 (64-bit) **** Build 272601 by xbuild on Sat Jun 15 11:27:26 MDT 2013 ** Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
source xsim.dir/example/xsim_script.tcl # xsim {example} -maxdeltaid 10000 -tclbatch {example.tcl} Vivado Simulator 2013.2 Time resolution is 1 ps source example.tcl ## run all WARNING: File/Multi-channel descriptor (-1) passed to $fclose is not valid. Please compile the design with -debug for source location information. $finish called at time : 180509 ps : File "example.autotb.v" Line 394 ## quit INFO: [Common 17-206] Exiting xsim at Mon Aug 26 04:18:44 2013... @I [SIM-316] Starting C post checking ... HLS AXI-Lite Example Function c += a + b Initial values a = 5, b = 10, c = 0 HW result = 15 SW result = 15 Success SW and HW results match @I [SIM-1000] *** C/RTL co-simulation finished: PASS *** @I [LIC-101] Checked in feature [HLS]
CRITICAL WARNING: [BD 41-968] AXI interface port /m_axis is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. CRITICAL WARNING: [BD 41-967] AXI interface pin /mt9d111_inf_axi_stream_1/m_axis is not associated to any clock pin. It may not work correctly.
[Synth 8-439] module 'mt9d111_inf_axis_test_mt9d111_inf_axi_stream_1_0' not found ["C:/Users/Masaaki/Documents/Vivado/Zynq/Zedboard/mt9d111_inf_axis_test/mt9d111_inf_axis_test.srcs/sources_1/bd/mt9d111_inf_axis_test/hdl/mt9d111_inf_axis_test.v":79]
Flow Navigator のSimulation -> Run Simulation を選択して、Run Behavioral Simulation を選択して、シミュレーションをスタートしたところエラーが発生した。
FIFO GENERATORが見つからないというエラーだ。
ERROR: [VRFC 10-2063] Module not found while processing module instance [C:/HDL/Xilinx/Vivado/2013.2/ids_lite/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_fifo_gen.v:572] ERROR: [VRFC 10-2063] Module not found while processing module instance [C:/Users/Masaaki/Documents/Vivado/Zynq/Zedboard/VDMA_test2_org/VDMA_test2_org.srcs/sources_1/edk/system/pcores/custom_axi4s_video_v1_00_a/hdl/verilog/video_fifo.v:71] ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed
・system_top_tb.v を選択して、ProcessesウインドウからSimulate Behavioral Model をダブルクリックして、シミュレーションをスタートしたところエラーが出てしまった。
エラー内容を下に示す。
ERROR:HDLCompiler:104 - "C:/HDL/Xilinx/14.5/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/dynshreg_f.vhd" Line 328: Cannot find in library . Please ensure that the library was compiled, and that a library and a use clause are present in the VHDL file. ERROR:HDLCompiler:854 - "C:/HDL/Xilinx/14.5/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/dynshreg_f.vhd" Line 158: Unit ignored due to previous errors. -------------------------------------------------------------------------------- ERROR:HWCoSim - Program 'xst' returned with a non-zero exit code 6. Please refer to log file 'D:\HDL\FndtnISEWork\Zynq-7000\ZedBoard\test\VDMA_test2\isim\hwcosim_tmp\jtag\synth_model\xst_system_top.srp' for further details. HDL wrapper and bitstream generation process failed.
前回、シミュレーションが成功したと書いたが、v_axi4s_vid_out IP の video_... の信号が出て無かった。従って、HDMIの信号が出力されていない。 そこで、v_axi4s_vid_out IP と互換(あくまで私が想定する用途ではということです)のカスタムIPを自分で作ることにした。名前は、custom_axi4s_video とした。custom_axi4s_video.v を下に示す。
前回で一応、AXI4 Master, AXI4 Lite Slaveバスを持つプロジェクトをVivado IP Packager でIPにすることは出来たが、XPSと同じというわけではない。それは、MPDファイルのみのパラメータや、パラメータのレンジ、パラメータ同士の依存関係が書けていないことだ。つまりMPDファイルに書いてあるパラメータの属性を設定できていない。それを設定することにしよう。
## Generics for VHDL or Parameters for Verilog PARAMETER C_S_AXI_LITE_ADDR_WIDTH = 9, DT = INTEGER, BUS = S_AXI_LITE PARAMETER C_S_AXI_LITE_DATA_WIDTH = 32, DT = INTEGER, BUS = S_AXI_LITE PARAMETER C_BASEADDR = 0xffffffff, DT = STD_LOGIC_VECTOR(31 downto 0), PAIR = C_HIGHADDR, ADDRESS = BASE, BUS = S_AXI_LITE, MIN_SIZE = 0x1000, ASSIGNMENT = REQUIRE, TYPE = NON_HDL PARAMETER C_HIGHADDR = 0x00000000, DT = STD_LOGIC_VECTOR(31 downto 0), PAIR = C_BASEADDR, ADDRESS = HIGH, BUS = S_AXI_LITE, ASSIGNMENT = REQUIRE, TYPE = NON_HDL PARAMETER C_S_AXI_LITE_PROTOCOL = AXI4LITE, DT = STRING, BUS = S_AXI_LITE, ASSIGNMENT = CONSTANT, TYPE = NON_HDL PARAMETER C_S_AXI_LITE_SUPPORTS_READ = 1, DT = INTEGER, RANGE = (0,1), BUS = S_AXI_LITE, TYPE = NON_HDL PARAMETER C_S_AXI_LITE_SUPPORTS_WRITE = 1, DT = INTEGER, RANGE = (0,1), BUS = S_AXI_LITE, TYPE = NON_HDL
PARAMETER C_M_AXI_SUPPORTS_THREADS = 0, DT = integer, RANGE = (0,1), TYPE = NON_HDL, BUS = M_AXI PARAMETER C_M_AXI_THREAD_ID_WIDTH = 1, DT = integer, RANGE = (1:16), BUS = M_AXI PARAMETER C_M_AXI_ADDR_WIDTH = 32, DT = integer, ASSIGNMENT = CONSTANT, BUS = M_AXI PARAMETER C_M_AXI_DATA_WIDTH = 64, DT = integer, RANGE = (32, 64, 128, 256), BUS = M_AXI PARAMETER C_M_AXI_PROTOCOL = AXI4, DT = string, TYPE = NON_HDL, VALUES = (AXI4 = AXI4, AXI4Lite = AXI4Lite), BUS = M_AXI # Max number of write commands able to be issued without responses # In this example, issued writes + unread writes will throttle write address channel PARAMETER C_INTERCONNECT_M_AXI_WRITE_ISSUING = 8, DT = INTEGER, BUS = M_AXI #Read Issuing in this example HDL will go as high as write issuing parameter PARAMETER C_INTERCONNECT_M_AXI_READ_ISSUING = 8, DT = INTEGER, BUS = M_AXI, TYPE = NON_HDL PARAMETER C_M_AXI_SUPPORTS_READ = 1, DT = integer, RANGE = (0,1), BUS = M_AXI #,TYPE = NON_HDL PARAMETER C_M_AXI_SUPPORTS_WRITE = 1, DT = integer, RANGE = (0,1), BUS = M_AXI #,TYPE = NON_HDL PARAMETER C_M_AXI_SUPPORTS_USER_SIGNALS = 0, DT = integer, RANGE = (0,1), TYPE = NON_HDL, BUS = M_AXI PARAMETER C_M_AXI_AWUSER_WIDTH = 1, DT = integer, ISVALID = (C_M_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = M_AXI PARAMETER C_M_AXI_ARUSER_WIDTH = 1, DT = integer, ISVALID = (C_M_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = M_AXI PARAMETER C_M_AXI_WUSER_WIDTH = 1, DT = integer, ISVALID = (C_M_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = M_AXI PARAMETER C_M_AXI_RUSER_WIDTH = 1, DT = integer, ISVALID = (C_M_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = M_AXI PARAMETER C_M_AXI_BUSER_WIDTH = 1, DT = integer, ISVALID = (C_M_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = M_AXI PARAMETER C_M_AXI_SUPPORTS_NARROW_BURST = 0, DT = integer, RANGE = (0,1), TYPE = NON_HDL, BUS = M_AXI
# Example Parameters # Base address of targeted slave PARAMETER C_M_AXI_TARGET = 0x00000000, DT = std_logic_vector(31 downto 0) # Burst length for transactions, in C_M_AXI_DATA_WIDTHs PARAMETER C_M_AXI_BURST_LEN = 16, DT = integer # Number of address bits to test before wrapping PARAMETER C_OFFSET_WIDTH = 9, DT = integer
CPU : Altera SOCFPGA Platform BOARD : Altera SOCFPGA Cyclone 5 Board DRAM: 1 GiB MMC: DESIGNWARE SD/MMC: 0 *** Warning - bad CRC, using default environment
In: serial Out: serial Err: serial Net: mii0 Warning: failed to set MAC address
Hit any key to stop autoboot: 0 reading uImage
2720256 bytes read reading socfpga.dtb
15658 bytes read ## Booting kernel from Legacy Image at 00007fc0 ... Image Name: Linux-3.8.0 Image Type: ARM Linux Kernel Image (uncompressed) Data Size: 2720192 Bytes = 2.6 MiB Load Address: 00008000 Entry Point: 00008000 ## Flattened Device Tree blob at 00000100 Booting using the fdt blob at 0x00000100 XIP Kernel Image ... OK OK Loading Device Tree to 0fff8000, end 0fffed29 ... OK
Starting kernel ...
Booting Linux on physical CPU 0x0 Initializing cgroup subsys cpuset Linux version 3.8.0 (alterasoc@alterasoc-VirtualBox) (gcc version 4.7.3 20121106 (prerelease) (crosstool-NG linaro-1.13.1-4.7-2012.11-20121123 - Linaro GCC 2012.11) ) #1 SMP Tue May 28 17:43:52 JST 2013 CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=10c5387d CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache Machine: Altera SOCFPGA, model: Altera SOCFPGA Cyclone V Memory policy: ECC disabled, Data cache writealloc PERCPU: Embedded 8 pages/cpu @80d6b000 s10880 r8192 d13696 u32768 Built 1 zonelists in Zone order, mobility grouping on. Total pages: 260096 Kernel command line: console=ttyS0,57600 root=/dev/mmcblk0p2 rw rootwait PID hash table entries: 4096 (order: 2, 16384 bytes) Dentry cache hash table entries: 131072 (order: 7, 524288 bytes) Inode-cache hash table entries: 65536 (order: 6, 262144 bytes) __ex_table already sorted, skipping sort Memory: 1024MB = 1024MB total Memory: 1033952k/1033952k available, 14624k reserved, 0K highmem Virtual kernel memory layout: vector : 0xffff0000 - 0xffff1000 ( 4 kB) fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB) vmalloc : 0xc0800000 - 0xff000000 (1000 MB) lowmem : 0x80000000 - 0xc0000000 (1024 MB) modules : 0x7f000000 - 0x80000000 ( 16 MB) .text : 0x80008000 - 0x804c9350 (4869 kB) .init : 0x804ca000 - 0x804f6a80 ( 179 kB) .data : 0x804f8000 - 0x80527038 ( 189 kB) .bss : 0x80527038 - 0x8055eb2c ( 223 kB) SLUB: Genslabs=11, HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1 Hierarchical RCU implementation. NR_IRQS:16 nr_irqs:16 16 sched_clock: 32 bits at 100MHz, resolution 10ns, wraps every 42949ms Console: colour dummy device 80x30 Calibrating delay loop... 1594.16 BogoMIPS (lpj=7970816) pid_max: default: 32768 minimum: 301 Mount-cache hash table entries: 512 CPU: Testing write buffer coherency: ok CPU0: thread -1, cpu 0, socket 0, mpidr 80000000 Setting up static identity map for 0x395b80 - 0x395bd8 CPU1: Booted secondary processor CPU1: thread -1, cpu 1, socket 0, mpidr 80000001 Brought up 2 CPUs SMP: Total of 2 processors activated (3188.32 BogoMIPS). devtmpfs: initialized NET: Registered protocol family 16 DMA: preallocated 256 KiB pool for atomic coherent allocations L310 cache controller enabled l2x0: 8 ways, CACHE_ID 0x000000c0, AUX_CTRL 0x32460000, Cache size: 524288 B hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers. hw-breakpoint: maximum watchpoint size is 4 bytes. bio: create slab at 0 FPGA Mangager framework driver SCSI subsystem initialized usbcore: registered new interface driver usbfs usbcore: registered new interface driver hub usbcore: registered new device driver usb lcd_load_custom_fonts: i2c_master_send returns -121 lcd_cmd_no_params: i2c_master_send returns -121 lcd_cmd_one_param: i2c_master_send returns -121 lcd_cmd_no_params: i2c_master_send returns -121 lcd-comm 0-0028: LCD driver initialized Switching to clocksource timer0 NET: Registered protocol family 2 TCP established hash table entries: 8192 (order: 4, 65536 bytes) TCP bind hash table entries: 8192 (order: 4, 65536 bytes) TCP: Hash tables configured (established 8192 bind 8192) TCP: reno registered UDP hash table entries: 512 (order: 2, 16384 bytes) UDP-Lite hash table entries: 512 (order: 2, 16384 bytes) NET: Registered protocol family 1 RPC: Registered named UNIX socket transport module. RPC: Registered udp transport module. RPC: Registered tcp transport module. RPC: Registered tcp NFSv4.1 backchannel transport module. hw perfevents: enabled with ARMv7 Cortex-A9 PMU driver, 7 counters available arm-pmu arm-pmu: PMU:CTI successfully enabled NFS: Registering the id_resolver key type Key type id_resolver registered Key type id_legacy registered NTFS driver 2.1.30 [Flags: R/W]. jffs2: version 2.2. (NAND) c 2001-2006 Red Hat, Inc. msgmni has been set to 2019 io scheduler noop registered (default) Serial: 8250/16550 driver, 2 ports, IRQ sharing disabled ffc02000.serial0: ttyS0 at MMIO 0xffc02000 (irq = 194) is a 8250 console [ttyS0] enabled ffc03000.serial1: ttyS1 at MMIO 0xffc03000 (irq = 195) is a 8250 altera_fpga_manager ff706000.fpgamgr: fpga manager [Altera FPGA Manager] registered as minor 0 brd: module loaded at24 0-0051: 4096 byte 24c32 EEPROM, writable, 32 bytes/write cadence-qspi ff705000.spi: master is unqueued, this is deprecated m25p80 spi2.0: unrecognized JEDEC id ffffff cadence-qspi ff705000.spi: Cadence QSPI controller driver dw_spi_mmio fff00000.spi: master is unqueued, this is deprecated dw_spi_mmio fff01000.spi: master is unqueued, this is deprecated stmmac - user ID: 0x10, Synopsys ID: 0x37 DMA HW capability register supported Enhanced/Alternate descriptors RX Checksum Offload Engine supported (type 2) TX Checksum insertion supported Enable RX Mitigation via HW Watchdog Timer libphy: stmmac: probed eth0: PHY ID 00221611 at 4 IRQ 0 (stmmac-0:04) active socfpga_phy_reset_mii writing extended registers to phyaddr 4 Initializing USB Mass Storage driver... usbcore: registered new interface driver usb-storage USB Mass Storage support registered. Using Slave mode dwc_otg ffb40000.usb: DWC OTG Controller dwc_otg ffb40000.usb: new USB bus registered, assigned bus number 1 dwc_otg ffb40000.usb: irq 160, io mem 0xffb40000 Init: Port Power? op_state=b_peripheral hub 1-0:1.0: USB hub found hub 1-0:1.0: 1 port detected mousedev: PS/2 mouse device common for all mice rtc-ds1307 0-0068: rtc core: registered ds1339 as rtc0 i2c /dev entries driver Synopsys Designware Multimedia Card Interface Driver dwmmc_socfpga ff704000.dwmmc0: couldn't determine pwr-en, assuming pwr-en = 0 dwmmc_socfpga ff704000.dwmmc0: Using internal DMA controller. dwmmc_socfpga ff704000.dwmmc0: DW MMC controller at irq 171, 32 bit host data width, 1024 deep fifo mmc_host mmc0: Bus speed (slot 0) = 100000000Hz (slot req 400000Hz, actual 400000HZ div = 125) dwmmc_socfpga ff704000.dwmmc0: 1 slots initialized dwmmc_socfpga ff704000.dwmmc0: Version ID is 240a ledtrig-cpu: registered to indicate activity on CPUs usbcore: registered new interface driver usbhid usbhid: USB HID core driver oprofile: using arm/armv7-ca9 TCP: cubic registered NET: Registered protocol family 17 NET: Registered protocol family 15 Key type dns_resolver registered VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4 ThumbEE CPU extension supported. Registering SWP/SWPB emulation handler Waiting for root device /dev/mmcblk0p2... dwmmc_socfpga ff704000.dwmmc0: data FIFO error (status=00000800) mmc0: problem reading SD Status register. mmc_host mmc0: Bus speed (slot 0) = 100000000Hz (slot req 50000000Hz, actual 50000000HZ div = 1) mmc0: new high speed SDHC card at address b368 mmcblk0: mmc0:b368 43579 7.45 GiB mmcblk0: p1 p2 p3 ++OTG Interrupt: A-Device Timeout Change++ kjournald starting. Commit interval 5 seconds EXT3-fs (mmcblk0p2): using internal journal EXT3-fs (mmcblk0p2): recovery complete EXT3-fs (mmcblk0p2): mounted filesystem with ordered data mode VFS: Mounted root (ext3 filesystem) on device 179:2. devtmpfs: mounted Freeing init memory: 176K INIT: version 2.88 booting Starting Bootlog daemon: bootlogd. Configuring network interfaces... eth0: device MAC address 82:fa:a7:3f:a0:7b udhcpc (v1.20.2) started Sending discover... Sending discover... Sending discover... No lease, failing Starting portmap daemon... INIT: Entering runlevel: 5 Starting OpenBSD Secure Shell server: sshd done. Starting syslogd/klogd: done Starting Lighttpd Web Server: lighttpd. Stopping Bootlog daemon: bootlogd.
26.Add IP Files ダイアログが表示された。Add Files... ボタンをクリックした。
27.Files of types を PDF files(.PDF) に変更して、custom_vtc_manual.pdf を選択した。OKボタンをクリックした。
28.custom_vtc_manual.pdf が、Add IP Files ダイアログに表示された。Copy source into project をチェックして、OKボタンをクリックした。
29.Package IP タブに、custom_vtc_manual.pdf が表示された。
30.Package IP タブの左のペインでReview and Package を選択した。(なお、IP File Groups に!が表示されているが、これはProduct Guide をプロジェクトにコピーしなかったためだ、現在、マニュアルをプロジェクトにコピーしているので解消されている)
31.Tools メニューから Project Settings... を選択した。
32.左のペインで IP を選択し、Pakager タブを選択する。確認したら Cancel ボタンをクリックする。
33.Package IP タブの左のペインでReview and Package を選択して、Package IP ボタンをクリックした。(なお、IP File Groups に!が表示されているが、これはProduct Guide をプロジェクトにコピーしなかったためだ、現在、マニュアルをプロジェクトにコピーしているので解消されている)
34.Package IP が終了後、Flow Navigator の IP Catalog をクリックした。
35.custom_vtc が、Base IP とVideo & Image Processing カテゴリに登録された。