NET "axi_gpio_0_GPIO_IO_pin" LOC = T18;
NET "axi_gpio_0_GPIO_IO_pin" IOSTANDARD = LVCMOS25;
NET "processing_system7_0_GPIO_pin" LOC = R18;
NET "processing_system7_0_GPIO_pin" IOSTANDARD = LVCMOS25;
NET "LED8bit[7]" IOSTANDARD = LVCMOS33;
NET "LED8bit[6]" IOSTANDARD = LVCMOS33;
NET "LED8bit[5]" IOSTANDARD = LVCMOS33;
NET "LED8bit[4]" IOSTANDARD = LVCMOS33;
NET "LED8bit[3]" IOSTANDARD = LVCMOS33;
NET "LED8bit[2]" IOSTANDARD = LVCMOS33;
NET "LED8bit[1]" IOSTANDARD = LVCMOS33;
NET "LED8bit[0]" IOSTANDARD = LVCMOS33;
NET "LED8bit[0]" LOC = T22;
NET "LED8bit[1]" LOC = T21;
NET "LED8bit[2]" LOC = U22;
NET "LED8bit[3]" LOC = U21;
NET "LED8bit[4]" LOC = V22;
NET "LED8bit[5]" LOC = W22;
NET "LED8bit[6]" LOC = U19;
NET "LED8bit[7]" LOC = U14;
-----------------------------------------------------------------------------
--
-- AXI Lite Slave
--
-- led8_axi_lite_slave
--
-- LED 8bitを制御する
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
--library unisim;
--use unisim.vcomponents.all;
entity led8_axi_lite_slave is
generic (
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_DATA_WIDTH : integer := 32
);
port(
-- System Signals
ACLK : in std_logic;
ARESETN : in std_logic;
-- Slave Interface Write Address Ports
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(3-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
-- Slave Interface Write Data Ports
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector(C_S_AXI_DATA_WIDTH/8-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
-- Slave Interface Write Response Ports
S_AXI_BRESP : out std_logic_vector(2-1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
-- Slave Interface Read Address Ports
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(3-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
-- Slave Interface Read Data Ports
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(2-1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- User Signals
LED8bit : out std_logic_vector(7 downto 0)
);
end led8_axi_lite_slave;
architecture implementation of led8_axi_lite_slave is
-- RESP の値の定義
constant RESP_OKAY : std_logic_vector := "00";
constant RESP_EXOKAY : std_logic_vector := "01";
constant RESP_SLVERR : std_logic_vector := "10";
constant RESP_DECERR : std_logic_vector := "11";
-- Write Transaction State Machine
type WRITE_TRAN_SM is (IDLE_WR, DATA_WIRTE_HOLD, BREADY_ASSERT);
signal wrt_cs : WRITE_TRAN_SM;
-- Read Transaction State Machine
type READ_TRAN_SM is (IDLE_RD, RDATA_WAIT);
signal rdt_cs : READ_TRAN_SM;
-- Registers
signal Commannd_Register : std_logic_vector(31 downto 0);
signal Counter_Load_Register : std_logic_vector(31 downto 0);
signal LED_Interval_Resgister : std_logic_vector(31 downto 0);
-- Counters
signal LED_Display_Counter : std_logic_vector(7 downto 0);
signal LED_Interval_Counter : std_logic_vector(31 downto 0);
signal awready : std_logic := '1';
signal bvalid : std_logic := '0';
signal arready : std_logic := '1';
signal rvalid : std_logic := '0';
signal rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal awaddr_hold : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal wready : std_logic;
begin
---- Write Transaction
-- AXI4 Lite Slave Write Transaction State Machine (Address, Response)
proc_Write_Tran_SM : process (ACLK) begin
if ACLK'event and ACLK='1' then
if ARESETN = '0' then
wrt_cs <= IDLE_WR;
awready <= '1';
bvalid <= '0';
awaddr_hold <= (others => '0');
wready <= '0';
else
case wrt_cs is
when IDLE_WR =>
if S_AXI_AWVALID = '1' then -- Write Transaction Start
wrt_cs <= DATA_WIRTE_HOLD;
awready <= '0';
awaddr_hold <= S_AXI_AWADDR;
wready <= '1';
end if;
when DATA_WIRTE_HOLD =>
if S_AXI_WVALID = '1' then -- Write data just valid
wrt_cs <= BREADY_ASSERT;
bvalid <= '1';
wready <= '0';
end if;
when BREADY_ASSERT =>
if S_AXI_BREADY = '1' then -- The write transaction was terminated.
wrt_cs <= IDLE_WR;
bvalid <= '0';
awready <= '1';
end if;
end case;
end if;
end if;
end process proc_Write_Tran_SM;
S_AXI_AWREADY <= awready;
S_AXI_BVALID <= bvalid;
S_AXI_BRESP <= RESP_OKAY;
S_AXI_WREADY <= wready;
---- Read Transaction
-- AXI4 Lite Slave Read Transaction State Machine
proc_Read_Tran_SM : process (ACLK) begin
if ACLK'event and ACLK='1' then
if ARESETN = '0' then
rdt_cs <= IDLE_RD;
arready <= '1';
rvalid <= '0';
else
case rdt_cs is
when IDLE_RD =>
if S_AXI_ARVALID = '1' then
rdt_cs <= RDATA_WAIT;
arready <= '0';
rvalid <= '1';
end if;
when RDATA_WAIT =>
if S_AXI_RREADY = '1' then
rdt_cs <= IDLE_RD;
arready <= '1';
rvalid <= '0';
end if;
end case;
end if;
end if;
end process proc_Read_Tran_SM;
S_AXI_ARREADY <= arready;
S_AXI_RVALID <= rvalid;
S_AXI_RRESP <= RESP_OKAY;
-- S_AXI_RDATA
proc_RDATA : process (ACLK) begin
if ARESETN = '0' then
rdata <= (others => '0');
elsif S_AXI_ARVALID = '1' then
case S_AXI_ARADDR(3 downto 0) is
when x"0" => rdata <= Commannd_Register;
when x"4" => rdata <= Counter_Load_Register;
when x"8" => rdata(31 downto 8) <= x"000000";
rdata(7 downto 0) <= LED_Display_Counter;
when x"c" => rdata <= LED_Interval_Resgister;
when others =>
end case;
end if;
end process proc_RDATA;
S_AXI_RDATA <= rdata;
---- Registeres
-- Commannd_Register
-- オフセット0：Command Register（R/W）
-- ビット0：1 - LEDの値を＋1する 0 - LEDの値はそのまま （デフォルト値は0）
-- ビット31〜1：リザーブ
proc_Commannd_Register : process (ACLK) begin
if ACLK'event and ACLK='1' then
if ARESETN = '0' then
Commannd_Register <= (others => '0');
else
if S_AXI_WVALID='1' and wready='1' and awaddr_hold(3 downto 0)=x"0" then
Commannd_Register(0) <= S_AXI_WDATA(0);
end if;
end if;
end if;
end process proc_Commannd_Register;
-- Counter_Load_Register
-- オフセット4：LED Counter Load Register（R/W）
-- ビット7〜0：8ビット分のLEDの値
-- ビット31〜8：リザーブ（Read時はすべて0）
proc_Counter_Load_Register : process (ACLK) begin
if ACLK'event and ACLK='1' then
if ARESETN = '0' then
Counter_Load_Register <= (others => '0');
else
if S_AXI_WVALID='1' and wready='1' and awaddr_hold(3 downto 0)=x"4" then
Counter_Load_Register(7 downto 0) <= S_AXI_WDATA(7 downto 0);
end if;
end if;
end if;
end process proc_Counter_Load_Register;
-- LED_Interval_Resgister
-- オフセットC：LED Interval Register（R/W）但し、動作クロックは100MHzとする
-- ビット31〜0：LED値を＋1する時のカウント値
proc_LED_Interval_Resgister : process (ACLK) begin
if ACLK'event and ACLK='1' then
if ARESETN = '0' then
LED_Interval_Resgister <= (others => '0');
else
if S_AXI_WVALID='1' and wready='1' and awaddr_hold(3 downto 0)=x"C" then
LED_Interval_Resgister <= S_AXI_WDATA;
end if;
end if;
end if;
end process proc_LED_Interval_Resgister;
---- Conteres
-- LED_Display_Counter
proc_LED_Display_Counter : process (ACLK) begin
if ACLK'event and ACLK='1' then
if ARESETN='0' then
LED_Display_Counter <= (others => '0');
else
if S_AXI_WVALID='1' and wready='1' and awaddr_hold(3 downto 0)=x"4" then -- Counter Load
LED_Display_Counter <= S_AXI_WDATA(7 downto 0);
elsif Commannd_Register(0) = '1' then -- Enable
if LED_Interval_Counter = x"00000000" then
LED_Display_Counter <= std_logic_vector(unsigned(LED_Display_Counter) + 1);
end if;
end if;
end if;
end if;
end process proc_LED_Display_Counter;
LED8bit <= LED_Display_Counter;
-- LED_Interval_Counter
proc_LED_Interval_Counter : process (ACLK) begin
if ACLK'event and ACLK='1' then
if ARESETN='0' then
LED_Interval_Counter <= (others => '0');
else
if Commannd_Register(0) = '1' then -- Enable
if LED_Interval_Counter = x"00000000" then
LED_Interval_Counter <= LED_Interval_Resgister;
else
LED_Interval_Counter <= std_logic_vector(unsigned(LED_Interval_Counter) - 1);
end if;
else
LED_Interval_Counter <= LED_Interval_Resgister;
end if;
end if;
end if;
end process proc_LED_Interval_Counter;
end implementation;
lap_filter_axim_urem_12ns_12ns_12_15.v
/* * led8_axi_lite_slave.c * * Created on: 2013/12/16 * Author: Masaaki */
#include <stdio.h>
#include "xil_types.h"
#include "xtmrctr.h"
#include "xparameters.h"
#include "xil_io.h"
#include "xil_exception.h"
#include "xscugic.h"
#define LED8_AXILS_BASEADDR XPAR_LED8_AXI_LITE_SLAVE_0_S_AXI_RNG00_BASEADDR
extern char inbyte(void);
int main() {
int inbyte_in;
int val;
char str[80];
while(1){
print("********************** LED8 TEST Start ***********************\n\r");
print("TeraTerm: Please Set Local Echo Mode.\n\r");
print("Press '1' to show all registers\n\r");
print("Press '2' to set LED8 Enable or Disable(Toggle, Command Register)\n\r");
print("Press '3' to set LED Counter Load Register (8bits, Please input hexadecimal)\n\r");
print("Press '4' to set LED Interval Register (32bits, Please input decimal)\n\r");
print("Press '5' to exit\n\r");
print("Selection : ");
inbyte_in = inbyte();
print(" \r\n");
print(" \r\n");
switch(inbyte_in) {
case '1' : // Show all registers
val = (int)Xil_In32((u32)LED8_AXILS_BASEADDR);
printf("Command Register is %x\r\n", val);
val = (int)Xil_In32((u32)(LED8_AXILS_BASEADDR+4));
printf("LED Counter Load Register is %x\r\n", val);
val = (int)Xil_In32((u32)(LED8_AXILS_BASEADDR+8));
printf("LED Monitor Register is %x\r\n", val);
val = (int)Xil_In32((u32)(LED8_AXILS_BASEADDR+0xc));
printf("LED Interval Register is %d (decimal)\r\n", val);
break;
case '2' : // Set LED8 Enable or Disable(Toggle, Command Register)
val = (int)Xil_In32((u32)LED8_AXILS_BASEADDR);
if (val & 1) {
Xil_Out32((u32)LED8_AXILS_BASEADDR, (u32)0);
print("LED8 count is Disable\n\r");
} else {
Xil_Out32((u32)LED8_AXILS_BASEADDR, (u32)1);
print("LED8 count is Enable\n\r");
}
break;
case '3' : // Set LED Counter Load Register (8bits, Please input hexadecimal)
print("Please input LED Counter Load Register value (hexadecimal)");
scanf("%x", &val);
Xil_Out32((u32)(LED8_AXILS_BASEADDR+4), (u32)val);
print(" \r\n");
break;
case '4' : // Set LED Interval Register (32bits, Please input hexadecimal)
print("Please input LED Interval Load Register value (decimal) ");
scanf("%d", &val);
Xil_Out32((u32)(LED8_AXILS_BASEADDR+0xc), (u32)val);
print(" \r\n");
break;
case '5' : // exit
print("exit\r\n");
return 0;
}
print(" \r\n");
}
}
#-- DISCLAIMER OF LIABILITY
#--
#-- This file contains proprietary and confidential information of
#-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
#-- from Xilinx, and may be used, copied and/or disclosed only
#-- pursuant to the terms of a valid license agreement with Xilinx.
#--
#-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
#-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
#-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
#-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
#-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
#-- does not warrant that functions included in the Materials will
#-- meet the requirements of Licensee, or that the operation of the
#-- Materials will be uninterrupted or error-free, or that defects
#-- in the Materials will be corrected. Furthermore, Xilinx does
#-- not warrant or make any representations regarding use, or the
#-- results of the use, of the Materials in terms of correctness,
#-- accuracy, reliability or otherwise.
#--
#-- Xilinx products are not designed or intended to be fail-safe,
#-- or for use in any application requiring fail-safe performance,
#-- such as life-support or safety devices or systems, Class III
#-- medical devices, nuclear facilities, applications related to
#-- the deployment of airbags, or any other applications that could
#-- lead to death, personal injury or severe property or
#-- environmental damage (individually and collectively, "critical
#-- applications"). Customer assumes the sole risk and liability
#-- of any use of Xilinx products in critical applications,
#-- subject only to applicable laws and regulations governing
#-- limitations on product liability.
#--
#-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
#--
#-- This disclaimer and copyright notice must be retained as part
#-- of this file at all times.
#--
###################################################################
##
## Name : led8_axi_lite_slave
## Desc : Microprocessor Peripheral Description
## : Automatically generated by PsfUtility
##
###################################################################
BEGIN led8_axi_lite_slave
## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION STYLE = HDL
OPTION DESC = LED8 AXI Lite Slave
OPTION LONG_DESC = LED 8bit AXI4-Lite Slave
OPTION HDL = MIXED
OPTION RUN_NGCBUILD = FALSE
## Bus Interfaces
BUS_INTERFACE BUS = S_AXI, BUS_STD = AXI, BUS_TYPE = SLAVE
## Generics for VHDL or Parameters for Verilog
PARAMETER C_S_AXI_ADDR_WIDTH = 32, DT = integer, ASSIGNMENT = CONSTANT, BUS = S_AXI
PARAMETER C_S_AXI_DATA_WIDTH = 32, DT = integer, ASSIGNMENT = CONSTANT, BUS = S_AXI
PARAMETER C_S_AXI_PROTOCOL = AXI4Lite, DT = string, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, BUS = S_AXI
PARAMETER C_S_AXI_SUPPORTS_READ = 1, DT = integer, RANGE = (0,1), TYPE = NON_HDL, ASSIGNMENT = OPTIONAL_UPDATE, BUS = S_AXI
PARAMETER C_S_AXI_SUPPORTS_WRITE = 1, DT = integer, RANGE = (0,1), TYPE = NON_HDL, ASSIGNMENT = OPTIONAL_UPDATE, BUS = S_AXI
PARAMETER C_S_AXI_NUM_ADDR_RANGES = 1, BUS = S_AXI, DT = INTEGER, ASSIGNMENT = OPTIONAL_UPDATE, TYPE = NON_HDL, RANGE = (1:4)
PARAMETER C_S_AXI_RNG00_BASEADDR = 0xFFFFFFFF, BUS = S_AXI, DT = std_logic_vector, ADDRESS = BASE, PAIR = C_S_AXI_RNG00_HIGHADDR, ISVALID = (C_S_AXI_NUM_ADDR_RANGES >= 1), TYPE = NON_HDL, MIN_SIZE = 0x1000
PARAMETER C_S_AXI_RNG00_HIGHADDR = 0x00000000, BUS = S_AXI, DT = std_logic_vector, ADDRESS = HIGH, PAIR = C_S_AXI_RNG00_BASEADDR, ISVALID = (C_S_AXI_NUM_ADDR_RANGES >= 1), TYPE = NON_HDL
PARAMETER C_S_AXI_RNG01_BASEADDR = 0xFFFFFFFF, BUS = S_AXI, DT = std_logic_vector, ADDRESS = BASE, PAIR = C_S_AXI_RNG01_HIGHADDR, ISVALID = (C_S_AXI_NUM_ADDR_RANGES >= 2), TYPE = NON_HDL, MIN_SIZE = 0x1000
PARAMETER C_S_AXI_RNG01_HIGHADDR = 0x00000000, BUS = S_AXI, DT = std_logic_vector, ADDRESS = HIGH, PAIR = C_S_AXI_RNG01_BASEADDR, ISVALID = (C_S_AXI_NUM_ADDR_RANGES >= 2), TYPE = NON_HDL
PARAMETER C_S_AXI_RNG02_BASEADDR = 0xFFFFFFFF, BUS = S_AXI, DT = std_logic_vector, ADDRESS = BASE, PAIR = C_S_AXI_RNG02_HIGHADDR, ISVALID = (C_S_AXI_NUM_ADDR_RANGES >= 3), TYPE = NON_HDL, MIN_SIZE = 0x1000
PARAMETER C_S_AXI_RNG02_HIGHADDR = 0x00000000, BUS = S_AXI, DT = std_logic_vector, ADDRESS = HIGH, PAIR = C_S_AXI_RNG02_BASEADDR, ISVALID = (C_S_AXI_NUM_ADDR_RANGES >= 3), TYPE = NON_HDL
PARAMETER C_S_AXI_RNG03_BASEADDR = 0xFFFFFFFF, BUS = S_AXI, DT = std_logic_vector, ADDRESS = BASE, PAIR = C_S_AXI_RNG03_HIGHADDR, ISVALID = (C_S_AXI_NUM_ADDR_RANGES >= 4), TYPE = NON_HDL, MIN_SIZE = 0x1000
PARAMETER C_S_AXI_RNG03_HIGHADDR = 0x00000000, BUS = S_AXI, DT = std_logic_vector, ADDRESS = HIGH, PAIR = C_S_AXI_RNG03_BASEADDR, ISVALID = (C_S_AXI_NUM_ADDR_RANGES >= 4), TYPE = NON_HDL
## Ports
PORT ACLK = "", BUS = S_AXI, DIR = I, SIGIS = CLK
PORT ARESETN = ARESETN, BUS = S_AXI, DIR = I, SIGIS = RST
PORT S_AXI_AWADDR = AWADDR, BUS = S_AXI, DIR = I, VEC = [(C_S_AXI_ADDR_WIDTH-1):0]
PORT S_AXI_AWPROT = AWPROT, BUS = S_AXI, DIR = I, VEC = [2:0]
PORT S_AXI_AWVALID = AWVALID, BUS = S_AXI, DIR = I
PORT S_AXI_AWREADY = AWREADY, BUS = S_AXI, DIR = O
PORT S_AXI_WDATA = WDATA, BUS = S_AXI, DIR = I, VEC = [(C_S_AXI_DATA_WIDTH-1):0]
PORT S_AXI_WSTRB = WSTRB, BUS = S_AXI, DIR = I, VEC = [((C_S_AXI_DATA_WIDTH/8) -1):0]
PORT S_AXI_WVALID = WVALID, BUS = S_AXI, DIR = I
PORT S_AXI_WREADY = WREADY, BUS = S_AXI, DIR = O
PORT S_AXI_BRESP = BRESP, BUS = S_AXI, DIR = O, VEC = [1:0]
PORT S_AXI_BVALID = BVALID, BUS = S_AXI, DIR = O
PORT S_AXI_BREADY = BREADY, BUS = S_AXI, DIR = I
PORT S_AXI_ARADDR = ARADDR, BUS = S_AXI, DIR = I, VEC = [(C_S_AXI_ADDR_WIDTH-1):0
PORT S_AXI_ARPROT = ARPROT, BUS = S_AXI, DIR = I, VEC = [2:0]
PORT S_AXI_ARVALID = ARVALID, BUS = S_AXI, DIR = I
PORT S_AXI_ARREADY = ARREADY, BUS = S_AXI, DIR = O
PORT S_AXI_RDATA = RDATA, BUS = S_AXI, DIR = O, VEC = [(C_S_AXI_DATA_WIDTH-1):0]
PORT S_AXI_RRESP = RRESP, BUS = S_AXI, DIR = O, VEC = [1:0]
PORT S_AXI_RVALID = RVALID, BUS = S_AXI, DIR = O
PORT S_AXI_RREADY = RREADY, BUS = S_AXI, DIR = I
PORT LED8bit = "", DIR = O, VEC = [7:0]
END
## -- DISCLAIMER OF LIABILITY
## --
## -- This file contains proprietary and confidential information of
## -- Xilinx, Inc. ("Xilinx"), that is distributed under a license
## -- from Xilinx, and may be used, copied and/or disclosed only
## -- pursuant to the terms of a valid license agreement with Xilinx.
## --
## -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
## -- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
## -- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
## -- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
## -- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
## -- does not warrant that functions included in the Materials will
## -- meet the requirements of Licensee, or that the operation of the
## -- Materials will be uninterrupted or error-free, or that defects
## -- in the Materials will be corrected. Furthermore, Xilinx does
## -- not warrant or make any representations regarding use, or the
## -- results of the use, of the Materials in terms of correctness,
## -- accuracy, reliability or otherwise.
## --
## -- Xilinx products are not designed or intended to be fail-safe,
## -- or for use in any application requiring fail-safe performance,
## -- such as life-support or safety devices or systems, Class III
## -- medical devices, nuclear facilities, applications related to
## -- the deployment of airbags, or any other applications that could
## -- lead to death, personal injury or severe property or
## -- environmental damage (individually and collectively, "critical
## -- applications"). Customer assumes the sole risk and liability
## -- of any use of Xilinx products in critical applications,
## -- subject only to applicable laws and regulations governing
## -- limitations on product liability.
## --
## -- Copyright 2009 Xilinx, Inc.
## -- All rights reserved.
## --
## -- This disclaimer and copyright notice must be retained as part
## -- of this file at all times.
##
###############################################################################
##
## axi_lite_slave_v2_1_0.pao
##
## Peripheral Analyze Order File
##
##
###############################################################################
lib led8_axi_lite_slave_v1_00_a led8_axi_lite_slave.v verilog
//-----------------------------------------------------------------------------
//-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//--
//-- This file contains confidential and proprietary information
//-- of Xilinx, Inc. and is protected under U.S. and
//-- international copyright and other intellectual property
//-- laws.
//--
//-- DISCLAIMER
//-- This disclaimer is not a license and does not grant any
//-- rights to the materials distributed herewith. Except as
//-- otherwise provided in a valid license issued to you by
//-- Xilinx, and to the maximum extent permitted by applicable
//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
//-- (2) Xilinx shall not be liable (whether in contract or tort,
//-- including negligence, or under any other theory of
//-- liability) for any loss or damage of any kind or nature
//-- related to, arising under or in connection with these
//-- materials, including for any direct, or any indirect,
//-- special, incidental, or consequential loss or damage
//-- (including loss of data, profits, goodwill, or any type of
//-- loss or damage suffered as a result of any action brought
//-- by a third party) even if such damage or loss was
//-- reasonably foreseeable or Xilinx had been advised of the
//-- possibility of the same.
//--
//-- CRITICAL APPLICATIONS
//-- Xilinx products are not designed or intended to be fail-
//-- safe, or for use in any application requiring fail-safe
//-- performance, such as life-support or safety devices or
//-- systems, Class III medical devices, nuclear facilities,
//-- applications related to the deployment of airbags, or any
//-- other applications that could lead to death, personal
//-- injury, or severe property or environmental damage
//-- (individually and collectively, "Critical
//-- Applications"). Customer assumes the sole risk and
//-- liability of any use of Xilinx products in Critical
//-- Applications, subject only to applicable laws and
//-- regulations governing limitations on product liability.
//--
//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
//-- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// AXI Lite Slave
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// led8_axi_lite
//
// LED 8bitを制御する
//--------------------------------------------------------------------------
`default_nettype none
module led8_axi_lite_slave #(
parameter integer C_S_AXI_ADDR_WIDTH = 32,
parameter integer C_S_AXI_DATA_WIDTH = 32
)(
// System Signals
input wire ACLK,
input wire ARESETN,
// Slave Interface Write Address Ports
input wire [C_S_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [3-1:0] S_AXI_AWPROT,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_S_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_S_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [2-1:0] S_AXI_BRESP,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_S_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [3-1:0] S_AXI_ARPROT,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_S_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// User Signals
output wire [7:0] LED8bit
);
// RESP の値の定義
parameter RESP_OKAY = 2'b00;
parameter RESP_EXOKAY = 2'b01;
parameter RESP_SLVERR = 2'b10;
parameter RESP_DECERR = 2'b11;
// Write Address Transaction State Machine
parameter IDLE_WR = 2'b00, // for wrt_cs
DATA_WRITE_HOLD = 2'b01,
BREADY_ASSERT = 2'b11;
reg [1:0] wrt_cs = IDLE_WR;
// Read Transaction State Machine
parameter IDLE_RD = 1'b0, // for rdt_cs
RDATA_WAIT = 1'b1;
reg rdt_cs = IDLE_RD;
// Registers
reg [31:0] Commannd_Register;
reg [31:0] Counter_Load_Register;
reg [31:0] LED_Interval_Resgister;
// Counter
reg [7:0] LED_Display_Counter;
reg [31:0] LED_Interval_Counter;
reg awready = 1'b1;
reg bvalid = 1'b0;
reg arready = 1'b1;
reg rvalid = 1'b0;
reg [C_S_AXI_DATA_WIDTH-1:0] rdata;
reg [C_S_AXI_ADDR_WIDTH-1:0] awaddr_hold;
reg wready;
//// Write Transaction
// AXI4 Lite Slave Write Transaction State Machine (Address, Response)
always @(posedge ACLK) begin : proc_Write_Tran_SM
if (~ARESETN) begin
wrt_cs <= IDLE_WR;
awready <= 1'b1;
bvalid <= 1'b0;
awaddr_hold <= 0;
wready <= 1'b0;
end else begin
case (wrt_cs)
IDLE_WR :
if (S_AXI_AWVALID) begin // Write Transaction Start
wrt_cs <= DATA_WRITE_HOLD;
awready <= 1'b0;
awaddr_hold <= S_AXI_AWADDR;
wready <= 1'b1;
end
DATA_WRITE_HOLD :
if (S_AXI_WVALID) begin // Write data just valid
wrt_cs <= BREADY_ASSERT;
bvalid <= 1'b1;
wready <= 1'b0;
end
BREADY_ASSERT :
if (S_AXI_BREADY) begin // The write transaction was terminated.
wrt_cs <= IDLE_WR;
bvalid <= 1'b0;
awready <= 1'b1;
end
endcase
end
end
assign S_AXI_AWREADY = awready;
assign S_AXI_BVALID = bvalid;
assign S_AXI_BRESP = RESP_OKAY;
assign S_AXI_WREADY = wready;
//// Read Transaction
// AXI4 Lite Slave Read Transaction State Machine
always @(posedge ACLK) begin : proc_Read_Tran_SM
if (~ARESETN) begin
rdt_cs <= IDLE_RD;
arready <= 1'b1;
rvalid <= 1'b0;
end else begin
case (rdt_cs)
IDLE_RD :
if (S_AXI_ARVALID) begin
rdt_cs <= RDATA_WAIT;
arready <= 1'b0;
rvalid <= 1'b1;
end
RDATA_WAIT :
if (S_AXI_RREADY) begin
rdt_cs <= IDLE_RD;
arready <= 1'b1;
rvalid <= 1'b0;
end
endcase
end
end
assign S_AXI_ARREADY = arready;
assign S_AXI_RVALID = rvalid;
assign S_AXI_RRESP = RESP_OKAY;
// S_AXI_RDATA
always @(posedge ACLK) begin : proc_RDATA
if(~ARESETN) begin
rdata <= 32'd0;
end else if (S_AXI_ARVALID) begin
case (S_AXI_ARADDR[3:0])
4'h0 : rdata <= Commannd_Register;
4'h4 : rdata <= Counter_Load_Register;
4'h8 : rdata <= {24'd0, LED_Display_Counter};
4'hC : rdata <= LED_Interval_Resgister;
endcase
end
end
assign S_AXI_RDATA = rdata;
//// Registeres
// Commannd_Register
// オフセット0：Command Register（R/W）
// ビット0：1 - LEDの値を＋1する 0 - LEDの値はそのまま （デフォルト値は0）
// ビット31〜1：リザーブ
always @(posedge ACLK) begin : proc_Commannd_Register
if(~ARESETN) begin
Commannd_Register <= 32'd0;
end else begin
if (S_AXI_WVALID==1'b1 && wready==1'b1 && awaddr_hold[3:0]==4'h0)
Commannd_Register[0] <= S_AXI_WDATA[0];
end
end
// Counter_Load_Register
// オフセット4：LED Counter Load Register（R/W）
// ビット7〜0：8ビット分のLEDの値
// ビット31〜8：リザーブ（Read時はすべて0）
always @(posedge ACLK) begin : proc_Counter_Load_Register
if(~ARESETN) begin
Counter_Load_Register <= 32'd0;
end else begin
if (S_AXI_WVALID==1'b1 && wready==1'b1 && awaddr_hold[3:0]==4'h4)
Counter_Load_Register[7:0] <= S_AXI_WDATA[7:0];
end
end
// LED_Interval_Resgister
// オフセットC：LED Interval Register（R/W）但し、動作クロックは100MHzとする
// ビット31〜0：LED値を＋1する時のカウント値
always @(posedge ACLK) begin : proc_LED_Interval_Resgister
if(~ARESETN) begin
LED_Interval_Resgister <= 32'd0;
end else begin
if (S_AXI_WVALID==1'b1 && wready==1'b1 && awaddr_hold[3:0]==4'hC)
LED_Interval_Resgister <= S_AXI_WDATA;
end
end
//// Conteres
// LED_Display_Counter
always @(posedge ACLK) begin : proc_LED_Display_Counter
if(~ARESETN) begin
LED_Display_Counter <= 8'd0;
end else begin
if (S_AXI_WVALID==1'b1 && wready==1'b1 && awaddr_hold[3:0]==4'h4) // Counter Load
LED_Display_Counter <= S_AXI_WDATA[7:0];
else if (Commannd_Register[0]) begin // Enable
if (LED_Interval_Counter == 32'd0)
LED_Display_Counter <= LED_Display_Counter + 8'd1;
end
end
end
assign LED8bit = LED_Display_Counter;
// LED_Interval_Counter
always @(posedge ACLK) begin : proc_LED_Interval_Counter
if(~ARESETN) begin
LED_Interval_Counter <= 32'd0;
end else begin
if (Commannd_Register[0]) begin // Enable
if (LED_Interval_Counter == 32'd0)
LED_Interval_Counter <= LED_Interval_Resgister;
else
LED_Interval_Counter <= LED_Interval_Counter - 32'd1;
end else
LED_Interval_Counter <= LED_Interval_Resgister;
end
end
endmodule
`default_nettype wire
NET "axi_gpio_0_GPIO_IO_pin" LOC = T18;
NET "axi_gpio_0_GPIO_IO_pin" IOSTANDARD = LVCMOS25;
NET "processing_system7_0_GPIO_pin" LOC = R18;
NET "processing_system7_0_GPIO_pin" IOSTANDARD = LVCMOS25;
# PlanAhead Generated IO constraints
NET "LED8bit[7]" IOSTANDARD = LVCMOS33;
NET "LED8bit[6]" IOSTANDARD = LVCMOS33;
NET "LED8bit[5]" IOSTANDARD = LVCMOS33;
NET "LED8bit[4]" IOSTANDARD = LVCMOS33;
NET "LED8bit[3]" IOSTANDARD = LVCMOS33;
NET "LED8bit[2]" IOSTANDARD = LVCMOS33;
NET "LED8bit[1]" IOSTANDARD = LVCMOS33;
NET "LED8bit[0]" IOSTANDARD = LVCMOS33;
# PlanAhead Generated physical constraints
NET "LED8bit[0]" LOC = T22;
NET "LED8bit[1]" LOC = T21;
NET "LED8bit[2]" LOC = U22;
NET "LED8bit[3]" LOC = U21;
NET "LED8bit[4]" LOC = V22;
NET "LED8bit[5]" LOC = W22;
NET "LED8bit[6]" LOC = U19;
NET "LED8bit[7]" LOC = U14;
// S_AXI_RDATA
always @(posedge ACLK) begin : proc_RDATA
if(~ARESETN) begin
rdata <= 32'd0;
end else if (S_AXI_ARVALID) begin
case (S_AXI_ARADDR[3:0])
4'h0 : rdata <= Commannd_Register;
4'h4 : rdata <= Counter_Load_Register;
4'h8 : rdata <= {24'd0, LED_Display_Counter};
4'hC : rdata <= LED_Interval_Resgister;
endcase
end
end
assign S_AXI_RDATA = rdata;
NET "axi_gpio_0_GPIO_IO_pin" LOC = T18;
NET "axi_gpio_0_GPIO_IO_pin" IOSTANDARD = LVCMOS25;
NET "processing_system7_0_GPIO_pin" LOC = R18;
NET "processing_system7_0_GPIO_pin" IOSTANDARD = LVCMOS25;
# PlanAhead Generated IO constraints
NET "LED8bit[7]" IOSTANDARD = LVCMOS33;
NET "LED8bit[6]" IOSTANDARD = LVCMOS33;
NET "LED8bit[5]" IOSTANDARD = LVCMOS33;
NET "LED8bit[4]" IOSTANDARD = LVCMOS33;
NET "LED8bit[3]" IOSTANDARD = LVCMOS33;
NET "LED8bit[2]" IOSTANDARD = LVCMOS33;
NET "LED8bit[1]" IOSTANDARD = LVCMOS33;
NET "LED8bit[0]" IOSTANDARD = LVCMOS33;
# PlanAhead Generated physical constraints
NET "LED8bit[0]" LOC = T22;
NET "LED8bit[1]" LOC = T21;
NET "LED8bit[2]" LOC = U22;
NET "LED8bit[3]" LOC = U21;
NET "LED8bit[4]" LOC = V22;
NET "LED8bit[5]" LOC = W22;
NET "LED8bit[6]" LOC = U19;
NET "LED8bit[7]" LOC = U14;
・AXI_LiteM_1Seq_Write（Write Address, Write Data, Write Response をシーケンシャルにオーバーラップせずに行う）
・AXI_LiteM_WAC（Write Address Channel の Transaction を実行する）
・AXI_LiteM_WDC（Write Data Channel の Transaction を実行する）
・AXI_LiteM_WRC（Write Response Channel の Transaction を実行する）
・AXI_LiteM_1Seq_Read（Read Address, Read Data をシーケンシャルに行う）
・AXI_LiteM_RAC（Read Address Channel の Transaction を実行する）
・AXI_LiteM_RDC（Read Data Channel の Transaction を実行する）
// AXI4 bus Lite Master Bus Fucntion Mode
// 2013/12/14
// AXI4_Master_BFM のラッパー
//
//
`default_nettype none
`timescale 100ps / 1ps
module AXI4_Lite_Master_BFM #(
parameter DELAY = 10 )
(
input wire ACLK,
output wire [31:0] S_AXI_AWADDR,
output wire [2:0] S_AXI_AWPROT,
output wire S_AXI_AWVALID,
output wire [31:0] S_AXI_WDATA,
output wire [3:0] S_AXI_WSTRB,
output wire S_AXI_WVALID,
output wire S_AXI_BREADY,
output wire [31:0] S_AXI_ARADDR,
output wire [2:0] S_AXI_ARPROT,
output wire S_AXI_ARVALID,
output wire S_AXI_RREADY,
input wire S_AXI_AWREADY,
input wire S_AXI_WREADY,
input wire [1:0] S_AXI_BRESP,
input wire S_AXI_BVALID,
input wire S_AXI_ARREADY,
input wire [31:0] S_AXI_RDATA,
input wire [1:0] S_AXI_RRESP,
input wire S_AXI_RVALID
);
parameter ASIZE_BT_4 = 3'd2; // 32 bit width
parameter ASIZE_BT_2 = 3'd1; // 16 bit width
parameter ASIZE_BT_1 = 3'd0; // 8 bit width
parameter ABURST_FIXED = 2'd0;
parameter ABURST_INCR = 2'd1;
parameter ABURST_WRAP = 2'd2;
// RESP の値の定義
parameter RESP_OKAY = 2'b00;
parameter RESP_EXOKAY = 2'b01;
parameter RESP_SLVERR = 2'b10;
parameter RESP_DECERR = 2'b11;
reg [7:0] awlen_hold = 0;
reg [0:0] wid_hold = 0;
reg axi_w_transaction_active = 0;
reg axi_r_transaction_active = 0;
reg [7:0] arlen_hold = 0;
// AXI4_BFM のインスタンス
AXI4_Master_BFM #(.DELAY(DELAY)) MBFMi(
.ACLK(ACLK),
.S_AXI_AWID(),
.S_AXI_AWADDR(S_AXI_AWADDR),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWLOCK(),
.S_AXI_AWCACHE(),
.S_AXI_AWPROT(S_AXI_AWPROT),
.S_AXI_AWREGION(),
.S_AXI_AWQOS(),
.S_AXI_AWUSER(),
.S_AXI_AWVALID(S_AXI_AWVALID),
.S_AXI_AWREADY(S_AXI_AWREADY),
.S_AXI_WID(),
.S_AXI_WDATA(S_AXI_WDATA),
.S_AXI_WSTRB(S_AXI_WSTRB),
.S_AXI_WLAST(),
.S_AXI_WUSER(),
.S_AXI_WVALID(S_AXI_WVALID),
.S_AXI_WREADY(S_AXI_WREADY),
.S_AXI_BID(1'b0),
.S_AXI_BRESP(S_AXI_BRESP),
.S_AXI_BUSER(1'b0),
.S_AXI_BVALID(S_AXI_BVALID),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_ARID(),
.S_AXI_ARADDR(S_AXI_ARADDR),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARLOCK(),
.S_AXI_ARCACHE(),
.S_AXI_ARPROT(S_AXI_ARPROT),
.S_AXI_ARREGION(),
.S_AXI_ARQOS(),
.S_AXI_ARUSER(),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_RID(1'b0),
.S_AXI_RDATA(S_AXI_RDATA),
.S_AXI_RRESP(S_AXI_RRESP),
.S_AXI_RLAST(1'b1),
.S_AXI_RUSER(1'b0),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_RREADY(S_AXI_RREADY)
);
// Write Channel
// wait_clk_bready : 0 - bready の Wait は無し、0以外 - bready の Wait は wait_clk_bready の値の Wait が入る
// wmax_wait : 0 - wvalid の Wait は無し、0以外 - wmax_wait を最大値とするランダムな値の Wait が wvalid に入る
task AXI_LiteM_1Seq_Write; // Write Address, Write Data, Write Response をシーケンシャルにオーバーラップせずに行う。
input [31:0] awaddr;
input [31:0] wdata;
input [7:0] wait_clk_bready;
input [7:0] wmax_wait;
begin
MBFMi.AXI_Master_1Seq_Write(1'b0, awaddr, 8'd0, ASIZE_BT_4, ABURST_INCR, wdata, wait_clk_bready, wmax_wait);
end
endtask
// Write Address Channel
task AXI_LiteM_WAC;
input [31:0] awaddr;
begin
MBFMi.AXI_MASTER_WAC(1'b0, awaddr, 8'd0, ASIZE_BT_4, ABURST_INCR);
end
endtask
// Write Data Channel
// wmax_wait : 0 - wvalid の Wait は無し、0以外 - wmax_wait を最大値とするランダムな値の Wait が wvalid に入る
task AXI_LiteM_WDC; // WDATA は+1する
// とりあえず、WSTRBはオール1にする
input [31:0] wdata;
input [7:0] wmax_wait; // Write時の最大wait数
begin
MBFMi.AXI_MASTER_WDC(wdata, wmax_wait);
end
endtask
// Write Response Channel
// wait_clk_bready : 0 - bready の Wait は無し、0以外 - bready の Wait は wait_clk_bready の値の Wait が入る
task AXI_LiteM_WRC; // wait_clk_bready
input [7:0] wait_clk_bready;
begin
MBFMi.AXI_MASTER_WRC(wait_clk_bready);
end
endtask
// Read Channel
task AXI_LiteM_1Seq_Read; // Read Address, Read Data をシーケンシャルに行う。
input [31:0] araddr;
input [7:0] rmax_wait; // Read時の最大wait数
begin
MBFMi.AXI_Master_1Seq_Read(1'b0, araddr, 8'd0, ASIZE_BT_4, ABURST_INCR);
end
endtask
// Read Address Channel
task AXI_LiteM_RAC;
input [31:0] araddr;
begin
MBFMi.AXI_MASTER_RAC(1'b0, araddr, 8'd0, ASIZE_BT_4, ABURST_INCR);
end
endtask
// Read Data Channel
task AXI_LiteM_RDC; // S_AXI_RLAST がアサートされるまでS_AXI_RREADY をアサートする
input [7:0] rmax_wait; // Read時の最大wait数
begin
MBFMi.AXI_MASTER_RDC(rmax_wait);
end
endtask
endmodule
`default_nettype wire
・オフセット4 (LED Counter Load Register) に 32'hAA を Writeする。
・オフセットC (LED Interval Register) に 32'h8 を Writeする。
・オフセット0 (Command Register) に 1 を Writeする。
`default_nettype none
`timescale 100ps / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 05:08:14 12/14/2013
// Design Name: led8_axi_lite
// Module Name: D:/HDL/FndtnISEWork/Zynq-7000/ZedBoard/AXI4_bus/parctices/PS_PL_Tutorial/system/pcores/led8_axi_lite_v1_00_a/led8_axi_lite_verilog/led8_axi_lite_tb.v
// Project Name: led8_axi_lite_verilog
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: led8_axi_lite
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module led8_axi_lite_slave_tb;
parameter DELAY = 10;
// Inputs
wire ACLK;
wire ARESETN;
wire [31:0] S_AXI_AWADDR;
wire [2:0] S_AXI_AWPROT;
wire S_AXI_AWVALID;
wire [31:0] S_AXI_WDATA;
wire [3:0] S_AXI_WSTRB;
wire S_AXI_WVALID;
wire S_AXI_BREADY;
wire [31:0] S_AXI_ARADDR;
wire [2:0] S_AXI_ARPROT;
wire S_AXI_ARVALID;
wire S_AXI_RREADY;
// Outputs
wire S_AXI_AWREADY;
wire S_AXI_WREADY;
wire [1:0] S_AXI_BRESP;
wire S_AXI_BVALID;
wire S_AXI_ARREADY;
wire [31:0] S_AXI_RDATA;
wire [1:0] S_AXI_RRESP;
wire S_AXI_RVALID;
wire [7:0] LED8bit;
// Instantiate the Unit Under Test (UUT)
led8_axi_lite_slave uut (
.ACLK(ACLK),
.ARESETN(ARESETN),
.S_AXI_AWADDR(S_AXI_AWADDR),
.S_AXI_AWPROT(S_AXI_AWPROT),
.S_AXI_AWVALID(S_AXI_AWVALID),
.S_AXI_AWREADY(S_AXI_AWREADY),
.S_AXI_WDATA(S_AXI_WDATA),
.S_AXI_WSTRB(S_AXI_WSTRB),
.S_AXI_WVALID(S_AXI_WVALID),
.S_AXI_WREADY(S_AXI_WREADY),
.S_AXI_BRESP(S_AXI_BRESP),
.S_AXI_BVALID(S_AXI_BVALID),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_ARADDR(S_AXI_ARADDR),
.S_AXI_ARPROT(S_AXI_ARPROT),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_RDATA(S_AXI_RDATA),
.S_AXI_RRESP(S_AXI_RRESP),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_RREADY(S_AXI_RREADY),
.LED8bit(LED8bit)
);
// AXI4_Lite_Master_BFM
AXI4_Lite_Master_BFM #(.DELAY(DELAY)) LMBFMi(
.ACLK(ACLK),
.S_AXI_AWADDR(S_AXI_AWADDR),
.S_AXI_AWPROT(S_AXI_AWPROT),
.S_AXI_AWVALID(S_AXI_AWVALID),
.S_AXI_AWREADY(S_AXI_AWREADY),
.S_AXI_WDATA(S_AXI_WDATA),
.S_AXI_WSTRB(S_AXI_WSTRB),
.S_AXI_WVALID(S_AXI_WVALID),
.S_AXI_WREADY(S_AXI_WREADY),
.S_AXI_BRESP(S_AXI_BRESP),
.S_AXI_BVALID(S_AXI_BVALID),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_ARADDR(S_AXI_ARADDR),
.S_AXI_ARPROT(S_AXI_ARPROT),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_RDATA(S_AXI_RDATA),
.S_AXI_RRESP(S_AXI_RRESP),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_RREADY(S_AXI_RREADY)
);
// test
initial begin
// Initialize Inputs
// Wait 100 ns for global reset to finish
#1000;
// Add stimulus here
@(posedge ACLK); // 次のクロックへ
#DELAY;
LMBFMi.AXI_LiteM_1Seq_Write(32'h4, 32'hAA, 0, 0); // LED8bit = AA, wait_clk_bready=0, wmax_wait=0
LMBFMi.AXI_LiteM_1Seq_Write(32'hC, 32'h8, 1, 2); // 8クロックでLEDが+1される, wait_clk_bready=1, wmax_wait=2
LMBFMi.AXI_LiteM_1Seq_Write(32'h0, 32'h1, 2, 3); // LED incriment Enable, wait_clk_bready=2, wmax_wait=3
#1000; // Wait 100 ns
@(posedge ACLK); // 次のクロックへ
#DELAY;
LMBFMi.AXI_LiteM_1Seq_Read(32'h0, 0); // Command Register, rmax_wait=0
LMBFMi.AXI_LiteM_1Seq_Read(32'h4, 1); // LED Counter Load Register, rmax_wait=1
LMBFMi.AXI_LiteM_1Seq_Read(32'h8, 2); // LED Monitor Register, rmax_wait=2
LMBFMi.AXI_LiteM_1Seq_Read(32'hC, 3); // LED Interval Register, rmax_wait=3
end
// ACLK
clk_gen #(
.CLK_PERIOD(100), // 10nsec, 100MHz
.CLK_DUTY_CYCLE(0.5),
.CLK_OFFSET(0),
.START_STATE(1'b0)
) ACLKi (
.clk_out(ACLK)
);
// reset_gen
reset_gen #(
.RESET_STATE(1'b0),
.RESET_TIME(1000) // 100nsec
) RESETi (
.reset_out(ARESETN)
);
endmodule
module clk_gen #(
parameter CLK_PERIOD = 100,
parameter real CLK_DUTY_CYCLE = 0.5,
parameter CLK_OFFSET = 0,
parameter START_STATE = 1'b0 )
(
output reg clk_out
);
begin
initial begin
#CLK_OFFSET;
forever
begin
clk_out = START_STATE;
#(CLK_PERIOD-(CLK_PERIOD*CLK_DUTY_CYCLE)) clk_out = ~START_STATE;
#(CLK_PERIOD*CLK_DUTY_CYCLE);
end
end
end
endmodule
module reset_gen #(
parameter RESET_STATE = 1'b1,
parameter RESET_TIME = 100 )
(
output reg reset_out
);
begin
initial begin
reset_out = RESET_STATE;
#RESET_TIME;
reset_out = ~RESET_STATE;
end
end
endmodule
`default_nettype wire
オフセット0：Command Register（R/W）
ビット0：1 - LEDの値を＋1する 0 - LEDの値はそのまま （デフォルト値は0）
ビット31～１：リザーブ
オフセット4：LED Counter Load Register（R/W）
ビット7～0：8ビット分のLEDの値
ビット31～8：リザーブ（Read時はすべて0）
オフセット8：LED Monitor Register（Read Only）
ビット7～0：8ビット分の現在のLEDの値
ビット31～8：すべて0
オフセットC：LED Interval Register（R/W）但し、動作クロックは100MHzとする
ビット31～0：LED値を＋1する時のカウント値
オフセット0：Command Register（R/W）
ビット0：1 - LEDの値を＋1する 0 - LEDの値はそのまま （デフォルト値は0）
ビット31～１：リザーブ
オフセット4：LED Counter Load Register（R/W）
ビット7～0：8ビット分のLEDの値
ビット31～8：リザーブ（Read時はすべて0）
オフセット8：LED Monitor Register（Read Only）
ビット7～0：8ビット分の現在のLEDの値
ビット31～8：すべて0
オフセットC：LED Interval Register（R/W）但し、動作クロックは100MHzとする
ビット31～0：LED値を＋1する時のカウント値
1_Zynq-7000の概要
2_Zynq用ツール概要
3_Zynq用ツールのチュートリアル１
4_Zynq用ツールのチュートリアル２
5_Zynq用ツールのチュートリアル３
6_XPSプロジェクトでカスタムIPを作る方法
7_AXI4 バス説明、AXI4バスを使用したカスタムIPの作成方法
オフセット0：コマンド・レジスタ（R/W）
ビット0：1 - LEDの値を＋1する 0 - LEDの値はそのまま （デフォルト値は0）
ビット31～１：リザーブ
オフセット4：LED値のロード・レジスタ（R/W）
ビット7～0：8ビット分のLEDの値
ビット31～8：リザーブ（Read時はすべて0）
オフセット8：現在のLEDの値のReadレジスタ（Read Only）
ビット7～0：8ビット分の現在のLEDの値
ビット31～8：すべて0
オフセットC：LED値を＋1する時のカウント値（R/W）但し、動作クロックは100MHzとする
ビット31～0：LED値を＋1する時のカウント値
| 日 | 月 | 火 | 水 | 木 | 金 | 土 |
|---|---|---|---|---|---|---|
| 1 | 2 | 3 | 4 | 5 | 6 | 7 |
| 8 | 9 | 10 | 11 | 12 | 13 | 14 |
| 15 | 16 | 17 | 18 | 19 | 20 | 21 |
| 22 | 23 | 24 | 25 | 26 | 27 | 28 |
| 29 | 30 | 31 | - | - | - | - |