set_false_path -from [get_clocks pclk] -to [get_clocks clk_fpga_0]
create_debug_core u_ila_0 labtools_ila_v3
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list CamD_VDMA_i/processing_system7_0/FCLK_CLK0]]
set_property port_width 4 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARCACHE[0]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARCACHE[1]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARCACHE[2]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARCACHE[3]}]]
create_debug_core u_ila_1 labtools_ila_v3
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_1]
set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_1]
set_property C_ADV_TRIGGER true [get_debug_cores u_ila_1]
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_1]
set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_1]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_1]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_1]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_1]
set_property port_width 1 [get_debug_ports u_ila_1/clk]
connect_debug_port u_ila_1/clk [get_nets [list CamD_VDMA_i/processing_system7_0_FCLK_CLK0]]
set_property port_width 32 [get_debug_ports u_ila_1/probe0]
connect_debug_port u_ila_1/probe0 [get_nets [list {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[0]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[1]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[2]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[3]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[4]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[5]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[6]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[7]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[8]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[9]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[10]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[11]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[12]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[13]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[14]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[15]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[16]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[17]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[18]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[19]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[20]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[21]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[22]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[23]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[24]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[25]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[26]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[27]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[28]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[29]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[30]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[31]}]]
create_debug_core u_ila_2 labtools_ila_v3
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_2]
set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_2]
set_property C_ADV_TRIGGER true [get_debug_cores u_ila_2]
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_2]
set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_2]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_2]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_2]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_2]
set_property port_width 1 [get_debug_ports u_ila_2/clk]
connect_debug_port u_ila_2/clk [get_nets [list CamD_VDMA_i/processing_system7_0_FCLK_CLK2]]
set_property port_width 32 [get_debug_ports u_ila_2/probe0]
connect_debug_port u_ila_2/probe0 [get_nets [list {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[0]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[1]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[2]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[3]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[4]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[5]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[6]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[7]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[8]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[9]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[10]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[11]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[12]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[13]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[14]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[15]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[16]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[17]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[18]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[19]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[20]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[21]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[22]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[23]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[24]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[25]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[26]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[27]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[28]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[29]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[30]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[31]}]]
create_debug_core u_ila_3 labtools_ila_v3
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_3]
set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_3]
set_property C_ADV_TRIGGER true [get_debug_cores u_ila_3]
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_3]
set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_3]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_3]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_3]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_3]
set_property port_width 1 [get_debug_ports u_ila_3/clk]
connect_debug_port u_ila_3/clk [get_nets [list mt9d111_pclk_IBUF_BUFG]]
set_property port_width 24 [get_debug_ports u_ila_3/probe0]
connect_debug_port u_ila_3/probe0 [get_nets [list {CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TDATA[0]} {CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TDATA[1]} {CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TDATA[2]} {CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TDATA[3]} {CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TDATA[4]} {CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TDATA[5]} {CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TDATA[6]} {CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TDATA[7]} {CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TDATA[8]} {CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TDATA[9]} {CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TDATA[10]} {CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TDATA[11]} {CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TDATA[12]} {CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TDATA[13]} {CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TDATA[14]} {CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TDATA[15]} {CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TDATA[16]} {CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TDATA[17]} {CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TDATA[18]} {CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TDATA[19]} {CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TDATA[20]} {CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TDATA[21]} {CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TDATA[22]} {CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TDATA[23]}]]
create_debug_port u_ila_0 probe
set_property port_width 3 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARPROT[0]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARPROT[1]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARPROT[2]}]]
create_debug_port u_ila_0 probe
set_property port_width 4 [get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWCACHE[0]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWCACHE[1]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWCACHE[2]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWCACHE[3]}]]
create_debug_port u_ila_0 probe
set_property port_width 3 [get_debug_ports u_ila_0/probe3]
connect_debug_port u_ila_0/probe3 [get_nets [list {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWPROT[0]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWPROT[1]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWPROT[2]}]]
create_debug_port u_ila_0 probe
set_property port_width 2 [get_debug_ports u_ila_0/probe4]
connect_debug_port u_ila_0/probe4 [get_nets [list {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_BRESP[0]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_BRESP[1]}]]
create_debug_port u_ila_0 probe
set_property port_width 2 [get_debug_ports u_ila_0/probe5]
connect_debug_port u_ila_0/probe5 [get_nets [list {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RRESP[0]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RRESP[1]}]]
create_debug_port u_ila_1 probe
set_property port_width 2 [get_debug_ports u_ila_1/probe1]
connect_debug_port u_ila_1/probe1 [get_nets [list {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARBURST[0]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARBURST[1]}]]
create_debug_port u_ila_1 probe
set_property port_width 8 [get_debug_ports u_ila_1/probe2]
connect_debug_port u_ila_1/probe2 [get_nets [list {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARLEN[0]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARLEN[1]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARLEN[2]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARLEN[3]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARLEN[4]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARLEN[5]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARLEN[6]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARLEN[7]}]]
create_debug_port u_ila_1 probe
set_property port_width 3 [get_debug_ports u_ila_1/probe3]
connect_debug_port u_ila_1/probe3 [get_nets [list {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARSIZE[0]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARSIZE[1]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARSIZE[2]}]]
create_debug_port u_ila_1 probe
set_property port_width 64 [get_debug_ports u_ila_1/probe4]
connect_debug_port u_ila_1/probe4 [get_nets [list {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[0]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[1]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[2]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[3]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[4]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[5]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[6]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[7]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[8]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[9]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[10]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[11]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[12]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[13]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[14]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[15]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[16]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[17]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[18]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[19]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[20]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[21]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[22]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[23]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[24]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[25]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[26]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[27]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[28]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[29]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[30]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[31]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[32]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[33]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[34]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[35]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[36]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[37]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[38]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[39]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[40]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[41]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[42]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[43]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[44]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[45]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[46]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[47]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[48]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[49]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[50]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[51]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[52]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[53]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[54]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[55]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[56]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[57]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[58]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[59]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[60]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[61]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[62]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[63]}]]
create_debug_port u_ila_1 probe
set_property port_width 2 [get_debug_ports u_ila_1/probe5]
connect_debug_port u_ila_1/probe5 [get_nets [list {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RRESP[0]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RRESP[1]}]]
create_debug_port u_ila_1 probe
set_property port_width 32 [get_debug_ports u_ila_1/probe6]
connect_debug_port u_ila_1/probe6 [get_nets [list {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[0]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[1]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[2]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[3]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[4]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[5]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[6]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[7]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[8]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[9]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[10]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[11]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[12]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[13]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[14]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[15]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[16]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[17]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[18]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[19]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[20]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[21]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[22]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[23]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[24]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[25]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[26]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[27]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[28]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[29]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[30]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[31]}]]
create_debug_port u_ila_1 probe
set_property port_width 2 [get_debug_ports u_ila_1/probe7]
connect_debug_port u_ila_1/probe7 [get_nets [list {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWBURST[0]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWBURST[1]}]]
create_debug_port u_ila_1 probe
set_property port_width 8 [get_debug_ports u_ila_1/probe8]
connect_debug_port u_ila_1/probe8 [get_nets [list {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWLEN[0]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWLEN[1]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWLEN[2]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWLEN[3]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWLEN[4]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWLEN[5]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWLEN[6]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWLEN[7]}]]
create_debug_port u_ila_1 probe
set_property port_width 3 [get_debug_ports u_ila_1/probe9]
connect_debug_port u_ila_1/probe9 [get_nets [list {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWSIZE[0]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWSIZE[1]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWSIZE[2]}]]
create_debug_port u_ila_1 probe
set_property port_width 2 [get_debug_ports u_ila_1/probe10]
connect_debug_port u_ila_1/probe10 [get_nets [list {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_BRESP[0]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_BRESP[1]}]]
create_debug_port u_ila_1 probe
set_property port_width 32 [get_debug_ports u_ila_1/probe11]
connect_debug_port u_ila_1/probe11 [get_nets [list {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[0]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[1]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[2]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[3]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[4]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[5]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[6]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[7]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[8]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[9]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[10]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[11]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[12]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[13]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[14]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[15]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[16]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[17]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[18]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[19]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[20]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[21]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[22]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[23]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[24]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[25]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[26]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[27]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[28]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[29]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[30]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[31]}]]
create_debug_port u_ila_1 probe
set_property port_width 4 [get_debug_ports u_ila_1/probe12]
connect_debug_port u_ila_1/probe12 [get_nets [list {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WSTRB[0]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WSTRB[1]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WSTRB[2]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WSTRB[3]}]]
create_debug_port u_ila_1 probe
set_property port_width 9 [get_debug_ports u_ila_1/probe13]
connect_debug_port u_ila_1/probe13 [get_nets [list {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_AWADDR[0]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_AWADDR[1]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_AWADDR[2]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_AWADDR[3]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_AWADDR[4]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_AWADDR[5]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_AWADDR[6]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_AWADDR[7]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_AWADDR[8]}]]
create_debug_port u_ila_1 probe
set_property port_width 32 [get_debug_ports u_ila_1/probe14]
connect_debug_port u_ila_1/probe14 [get_nets [list {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[0]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[1]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[2]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[3]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[4]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[5]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[6]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[7]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[8]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[9]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[10]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[11]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[12]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[13]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[14]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[15]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[16]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[17]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[18]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[19]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[20]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[21]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[22]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[23]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[24]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[25]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[26]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[27]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[28]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[29]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[30]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[31]}]]
create_debug_port u_ila_1 probe
set_property port_width 9 [get_debug_ports u_ila_1/probe15]
connect_debug_port u_ila_1/probe15 [get_nets [list {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_ARADDR[0]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_ARADDR[1]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_ARADDR[2]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_ARADDR[3]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_ARADDR[4]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_ARADDR[5]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_ARADDR[6]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_ARADDR[7]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_ARADDR[8]}]]
create_debug_port u_ila_1 probe
set_property port_width 32 [get_debug_ports u_ila_1/probe16]
connect_debug_port u_ila_1/probe16 [get_nets [list {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[0]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[1]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[2]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[3]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[4]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[5]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[6]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[7]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[8]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[9]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[10]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[11]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[12]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[13]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[14]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[15]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[16]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[17]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[18]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[19]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[20]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[21]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[22]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[23]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[24]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[25]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[26]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[27]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[28]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[29]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[30]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[31]}]]
create_debug_port u_ila_1 probe
set_property port_width 1 [get_debug_ports u_ila_1/probe17]
connect_debug_port u_ila_1/probe17 [get_nets [list CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARREADY]]
create_debug_port u_ila_1 probe
set_property port_width 1 [get_debug_ports u_ila_1/probe18]
connect_debug_port u_ila_1/probe18 [get_nets [list CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARVALID]]
create_debug_port u_ila_1 probe
set_property port_width 1 [get_debug_ports u_ila_1/probe19]
connect_debug_port u_ila_1/probe19 [get_nets [list CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RLAST]]
create_debug_port u_ila_1 probe
set_property port_width 1 [get_debug_ports u_ila_1/probe20]
connect_debug_port u_ila_1/probe20 [get_nets [list CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RREADY]]
create_debug_port u_ila_1 probe
set_property port_width 1 [get_debug_ports u_ila_1/probe21]
connect_debug_port u_ila_1/probe21 [get_nets [list CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RVALID]]
create_debug_port u_ila_1 probe
set_property port_width 1 [get_debug_ports u_ila_1/probe22]
connect_debug_port u_ila_1/probe22 [get_nets [list CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWREADY]]
create_debug_port u_ila_1 probe
set_property port_width 1 [get_debug_ports u_ila_1/probe23]
connect_debug_port u_ila_1/probe23 [get_nets [list CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWVALID]]
create_debug_port u_ila_1 probe
set_property port_width 1 [get_debug_ports u_ila_1/probe24]
connect_debug_port u_ila_1/probe24 [get_nets [list CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_BREADY]]
create_debug_port u_ila_1 probe
set_property port_width 1 [get_debug_ports u_ila_1/probe25]
connect_debug_port u_ila_1/probe25 [get_nets [list CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_BVALID]]
create_debug_port u_ila_1 probe
set_property port_width 1 [get_debug_ports u_ila_1/probe26]
connect_debug_port u_ila_1/probe26 [get_nets [list CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WLAST]]
create_debug_port u_ila_1 probe
set_property port_width 1 [get_debug_ports u_ila_1/probe27]
connect_debug_port u_ila_1/probe27 [get_nets [list CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WREADY]]
create_debug_port u_ila_1 probe
set_property port_width 1 [get_debug_ports u_ila_1/probe28]
connect_debug_port u_ila_1/probe28 [get_nets [list CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WVALID]]
create_debug_port u_ila_1 probe
set_property port_width 1 [get_debug_ports u_ila_1/probe29]
connect_debug_port u_ila_1/probe29 [get_nets [list CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_ARREADY]]
create_debug_port u_ila_1 probe
set_property port_width 1 [get_debug_ports u_ila_1/probe30]
connect_debug_port u_ila_1/probe30 [get_nets [list CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_ARVALID]]
create_debug_port u_ila_1 probe
set_property port_width 1 [get_debug_ports u_ila_1/probe31]
connect_debug_port u_ila_1/probe31 [get_nets [list CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_AWREADY]]
create_debug_port u_ila_1 probe
set_property port_width 1 [get_debug_ports u_ila_1/probe32]
connect_debug_port u_ila_1/probe32 [get_nets [list CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_AWVALID]]
create_debug_port u_ila_1 probe
set_property port_width 1 [get_debug_ports u_ila_1/probe33]
connect_debug_port u_ila_1/probe33 [get_nets [list CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_BREADY]]
create_debug_port u_ila_1 probe
set_property port_width 1 [get_debug_ports u_ila_1/probe34]
connect_debug_port u_ila_1/probe34 [get_nets [list CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_BVALID]]
create_debug_port u_ila_1 probe
set_property port_width 1 [get_debug_ports u_ila_1/probe35]
connect_debug_port u_ila_1/probe35 [get_nets [list CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RREADY]]
create_debug_port u_ila_1 probe
set_property port_width 1 [get_debug_ports u_ila_1/probe36]
connect_debug_port u_ila_1/probe36 [get_nets [list CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RVALID]]
create_debug_port u_ila_1 probe
set_property port_width 1 [get_debug_ports u_ila_1/probe37]
connect_debug_port u_ila_1/probe37 [get_nets [list CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WREADY]]
create_debug_port u_ila_1 probe
set_property port_width 1 [get_debug_ports u_ila_1/probe38]
connect_debug_port u_ila_1/probe38 [get_nets [list CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WVALID]]
create_debug_port u_ila_2 probe
set_property port_width 1 [get_debug_ports u_ila_2/probe1]
connect_debug_port u_ila_2/probe1 [get_nets [list CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TLAST]]
create_debug_port u_ila_2 probe
set_property port_width 1 [get_debug_ports u_ila_2/probe2]
connect_debug_port u_ila_2/probe2 [get_nets [list CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TREADY]]
create_debug_port u_ila_2 probe
set_property port_width 1 [get_debug_ports u_ila_2/probe3]
connect_debug_port u_ila_2/probe3 [get_nets [list CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TUSER]]
create_debug_port u_ila_2 probe
set_property port_width 1 [get_debug_ports u_ila_2/probe4]
connect_debug_port u_ila_2/probe4 [get_nets [list CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TVALID]]
create_debug_port u_ila_2 probe
set_property port_width 1 [get_debug_ports u_ila_2/probe5]
connect_debug_port u_ila_2/probe5 [get_nets [list CamD_VDMA_i/custom_vtc_0_vtg_sync]]
create_debug_port u_ila_3 probe
set_property port_width 1 [get_debug_ports u_ila_3/probe1]
connect_debug_port u_ila_3/probe1 [get_nets [list CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TLAST]]
create_debug_port u_ila_3 probe
set_property port_width 1 [get_debug_ports u_ila_3/probe2]
connect_debug_port u_ila_3/probe2 [get_nets [list CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TREADY]]
create_debug_port u_ila_3 probe
set_property port_width 1 [get_debug_ports u_ila_3/probe3]
connect_debug_port u_ila_3/probe3 [get_nets [list CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TVALID]]
create_debug_port u_ila_3 probe
set_property port_width 1 [get_debug_ports u_ila_3/probe4]
connect_debug_port u_ila_3/probe4 [get_nets [list CamD_VDMA_i/mt9d111_inf_axi_stream_0_s2mm_fsync]]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
オフセット0x00 – 0x8B : MM2S_DMACR
GenlockSrc : 1 = Internal Genlockオフセット0x60 – 0x10200000 : MM2S_START_ADDRESS2
GenlockEn : 1 = Genlock or Dynamic Genlock Synchronization enabled. MM2S synchronized to Genlock frame input.
Circular_Park : 1 = Circular Mode – Engine continuously circles through MM2S_FRMSTORE frame buffers.
RS : 1 = Run – Start VDMA operations.
オフセット0x5C – 0x10000000 : MM2S_START_ADDRESS1
オフセット0x64 – 0x10400000 : MM2S_START_ADDRESS3
オフセット0x58 – 0xc80 : MM2S_FRMDLY_STRIDE
Stride(Bytes) : 0xc80 (3200Bytes, 800Words)オフセット0x54 – 0xc80 : MM2S_HSIZEHorizontal Size(Bytes) : 0xc80 (3200Bytes, 800Words)オフセット0x50 – 0x258 : MM2S_VSIZEVertical Size(Lines) : 0x258 (600Lines)オフセット0x30 – 0x3 :Circular_Park : 1 = Circular Mode – Engine continuously circles through MM2S_FRMSTORE frame buffers.オフセット0xac – 0x10000000 : S2MM_START_ADDRESS1
RS : 1 = Run – Start VDMA operations.
オフセット0xb0 – 0x10200000 : S2MM_START_ADDRESS2
オフセット0xb4 – 0x10400000 : S2MM_START_ADDRESS3
オフセット0xa8 – 0xc80 : S2MM_FRMDLY_STRIDEStride(Bytes) : 0xc80 (3200Bytes, 800Words)オフセット0xa4 – 0xc80 : S2MM_HSIZEHorizontal Size(Bytes) : 0xc80 (3200Bytes, 800Words)オフセット0xa0 – 0x258 : S2MM_VSIZEVertical Size(Lines) : 0x258 (600Lines)
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2014/01/18 20:31:13
// Design Name:
// Module Name: iic_3state_buf
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`default_nettype none
module iic_3state_buf(
output wire sda_i,
input wire sda_o,
input wire sda_t,
output wire scl_i,
input wire scl_o,
input wire scl_t,
inout wire sda,
inout wire scl
);
assign sda = (sda_t==1'b1) ? 1'bz : sda_o;
assign sda_i = sda;
assign scl = (scl_t==1'b1) ? 1'bz : scl_o;
assign scl_i = scl;
endmodule
`default_nettype wire
1) Open Block Design で該当するデザインを開く.
2) AXI_IICのインスタンスのIICポートを右クリックして、Make Externalをクリックして IIC を外部端子とする
3)Souces窓の .bd ファイルを右クリックして Create HDL Wrapper...をクリック.
4) Let Vivado manager wrapper and auto-update を選択.
こうして生成したラッパーファイルには IIC の入出力ポートに 双方向のIOBUF が追加されています。
追記)Project Setting で Top module name を生成したラッパーファイルに変更するのを忘れずに.
// XPS のIP、v_axi4s_vid_out のVideo出力を受けてVGAポートとHDMI出力に出力する
// video_out_zed.v
// 2013/06/09
//
`default_nettype none
module video_out_zed # (
parameter VIDEO_DATA_WIDTH = 24
) (
input wire pixclk, // pixel clock
input wire aresetn, // AXI reset
input wire video_de, // data enable
input wire video_hsync,
input wire video_vsync,
input wire video_vblank,
input wire video_hblank,
input wire [VIDEO_DATA_WIDTH-1:0] video_data,
(* IOB = "FORCE" *) output reg [3:0] vga_red,
(* IOB = "FORCE" *) output reg [3:0] vga_green,
(* IOB = "FORCE" *) output reg [3:0] vga_blue,
(* IOB = "FORCE" *) output reg vga_hsync,
(* IOB = "FORCE" *) output reg vga_vsync,
output wire hdmi_clk, // 下のモジュールで ODDR プリミティブを宣言してあるので、wire宣言のままとした
(* IOB = "FORCE" *) output reg hdmi_vsync,
(* IOB = "FORCE" *) output reg hdmi_hsync,
(* IOB = "FORCE" *) output reg hdmi_data_e,
(* IOB = "FORCE" *) output reg [15:0] hdmi_data
);
reg reset_1b, reset;
reg [7:0] red, green, blue;
reg hsyncx, vsyncx;
wire hdmi_vs, hdmi_hs;
wire hdmi_de;
wire [15:0] hdmi_d;
// 途中は略
always @(posedge pixclk) begin
if(reset) begin
hdmi_vsync <= 1'b1;
hdmi_hsync <= 1'b1;
hdmi_data_e <= 1'b0;
hdmi_data <= 16'd0;
end else begin
hdmi_vsync <= hdmi_vs;
hdmi_hsync <= hdmi_hs;
hdmi_data_e <= hdmi_de;
hdmi_data <= hdmi_d;
end
end
endmodule
`default_nettype wire
create_clock -period 28.000 -name pclk -waveform {0.000 14.000} [get_ports mt9d111_pclk]
set_input_delay -clock [get_clocks pclk] -rise 11.000 [get_ports {mt9d111_cam_data[0] mt9d111_cam_data[1] mt9d111_cam_data[2] mt9d111_cam_data[3] mt9d111_cam_data[4] mt9d111_cam_data[5] mt9d111_cam_data[6] mt9d111_cam_data[7] mt9d111_href mt9d111_pclk mt9d111_vsync}]
set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks clk_fpga_2]
set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks pclk]
module video_out_zed # (
parameter VIDEO_DATA_WIDTH = 24
) (
input wire pixclk, // pixel clock
input wire aresetn, // AXI reset
input wire video_de, // data enable
input wire video_hsync,
input wire video_vsync,
input wire video_vblank,
input wire video_hblank,
input wire [VIDEO_DATA_WIDTH-1:0] video_data,
(* IOB = "FORCE" *) output reg [3:0] vga_red,
(* IOB = "FORCE" *) output reg [3:0] vga_green,
(* IOB = "FORCE" *) output reg [3:0] vga_blue,
(* IOB = "FORCE" *) output reg vga_hsync,
(* IOB = "FORCE" *) output reg vga_vsync,
(* IOB = "FORCE" *) output wire hdmi_clk,
(* IOB = "FORCE" *) output wire hdmi_vsync,
(* IOB = "FORCE" *) output wire hdmi_hsync,
(* IOB = "FORCE" *) output wire hdmi_data_e,
(* IOB = "FORCE" *) output wire [15:0] hdmi_data
);
でタイミングが制約と合っていないようだ。[Route 35-39] The design did not meet timing requirements. Please run report_timing_summary for detailed reports.
// synchronization of reset_1b
always @(posedge pixclk) begin
reset_1b <= ~aresetn;
reset <= reset_1b;
end
-- ARESETN をACLK で同期化
process (ACLK) begin
if ACLK'event and ACLK='1' then
reset_1d <= not ARESETN or not init_done;
reset_2d <= reset_1d;
end if;
end process;
reset <= reset_2d;
-- ARESETN をpclk で同期化
process(pclk) begin
if pclk'event and pclk='1' then
preset_1d <= not ARESETN or not init_done;
preset_2d <= preset_1d;
end if;
end process;
preset <= preset_2d;
// video_fifo のインプリメント
video_fifo video_fifo_i (
.rst(~aresetn), // input rst
.wr_clk(aclk), // input wr_clk
.rd_clk(video_clk), // input rd_clk
.din(s_axis_video_tdata), // input [31 : 0] din
.wr_en(s_axis_video_tvalid & s_axis_video_tready), // input wr_en
.rd_en(vtg_act_vid), // input rd_en
.dout(video_data), // output [31 : 0] dout
.full(vfifo_full), // output full
.almost_full(vfifo_almost_full), // output almost_full
.overflow(vfifo_overflow), // output overflow
.empty(vfifo_empty), // output empty
.almost_empty(vfifo_almost_empty), // output almost_empty
.underflow(vfifo_underflow) // output underflow
);
create_clock -period 28.000 -name pclk -waveform {0.000 14.000} [get_ports mt9d111_pclk]
set_input_delay -clock [get_clocks pclk] -rise 11.000 [get_ports {mt9d111_cam_data[0] mt9d111_cam_data[1] mt9d111_cam_data[2] mt9d111_cam_data[3] mt9d111_cam_data[4] mt9d111_cam_data[5] mt9d111_cam_data[6] mt9d111_cam_data[7] mt9d111_href mt9d111_pclk mt9d111_vsync}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_blue[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_blue[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_blue[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_blue[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_green[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_green[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_green[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_green[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_red[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_red[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_red[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_red[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_data[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_data[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_data[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_data[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_data[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_data[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_data[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_data[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_data[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_data[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_data[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_data[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_data[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_data[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_data[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_data[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {mt9d111_cam_data[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {mt9d111_cam_data[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {mt9d111_cam_data[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {mt9d111_cam_data[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {mt9d111_cam_data[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {mt9d111_cam_data[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {mt9d111_cam_data[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {mt9d111_cam_data[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports mt9d111_pclk]
set_property PACKAGE_PIN AA9 [get_ports mt9d111_pclk]
set_property IOSTANDARD LVCMOS33 [get_ports mt9d111_standby]
set_property PACKAGE_PIN Y10 [get_ports mt9d111_standby]
set_property PACKAGE_PIN V13 [get_ports {hdmi_data[15]}]
set_property PACKAGE_PIN V14 [get_ports {hdmi_data[14]}]
set_property PACKAGE_PIN U17 [get_ports {hdmi_data[13]}]
set_property PACKAGE_PIN V15 [get_ports {hdmi_data[12]}]
set_property PACKAGE_PIN W15 [get_ports {hdmi_data[11]}]
set_property PACKAGE_PIN W13 [get_ports {hdmi_data[10]}]
set_property PACKAGE_PIN Y15 [get_ports {hdmi_data[9]}]
set_property PACKAGE_PIN AA17 [get_ports {hdmi_data[8]}]
set_property PACKAGE_PIN AB17 [get_ports {hdmi_data[7]}]
set_property PACKAGE_PIN AA16 [get_ports {hdmi_data[6]}]
set_property PACKAGE_PIN AB16 [get_ports {hdmi_data[5]}]
set_property PACKAGE_PIN AB15 [get_ports {hdmi_data[4]}]
set_property PACKAGE_PIN Y14 [get_ports {hdmi_data[3]}]
set_property PACKAGE_PIN AA14 [get_ports {hdmi_data[2]}]
set_property PACKAGE_PIN AA13 [get_ports {hdmi_data[1]}]
set_property PACKAGE_PIN Y13 [get_ports {hdmi_data[0]}]
set_property SLEW FAST [get_ports {hdmi_data[15]}]
set_property SLEW FAST [get_ports {hdmi_data[14]}]
set_property SLEW FAST [get_ports {hdmi_data[13]}]
set_property SLEW FAST [get_ports {hdmi_data[12]}]
set_property SLEW FAST [get_ports {hdmi_data[11]}]
set_property SLEW FAST [get_ports {hdmi_data[10]}]
set_property SLEW FAST [get_ports {hdmi_data[9]}]
set_property SLEW FAST [get_ports {hdmi_data[8]}]
set_property SLEW FAST [get_ports {hdmi_data[7]}]
set_property SLEW FAST [get_ports {hdmi_data[6]}]
set_property SLEW FAST [get_ports {hdmi_data[5]}]
set_property SLEW FAST [get_ports {hdmi_data[4]}]
set_property SLEW FAST [get_ports {hdmi_data[3]}]
set_property SLEW FAST [get_ports {hdmi_data[2]}]
set_property SLEW FAST [get_ports {hdmi_data[1]}]
set_property SLEW FAST [get_ports {hdmi_data[0]}]
set_property SLEW FAST [get_ports {vga_blue[3]}]
set_property SLEW FAST [get_ports {vga_blue[2]}]
set_property SLEW FAST [get_ports {vga_blue[1]}]
set_property SLEW FAST [get_ports {vga_blue[0]}]
set_property SLEW FAST [get_ports {vga_green[3]}]
set_property SLEW FAST [get_ports {vga_green[2]}]
set_property SLEW FAST [get_ports {vga_green[1]}]
set_property SLEW FAST [get_ports {vga_green[0]}]
set_property PACKAGE_PIN W12 [get_ports {mt9d111_cam_data[7]}]
set_property PACKAGE_PIN V12 [get_ports {mt9d111_cam_data[6]}]
set_property PACKAGE_PIN W11 [get_ports {mt9d111_cam_data[5]}]
set_property PACKAGE_PIN W10 [get_ports {mt9d111_cam_data[4]}]
set_property PACKAGE_PIN V10 [get_ports {mt9d111_cam_data[3]}]
set_property PACKAGE_PIN V9 [get_ports {mt9d111_cam_data[2]}]
set_property PACKAGE_PIN W8 [get_ports {mt9d111_cam_data[1]}]
set_property PACKAGE_PIN V8 [get_ports {mt9d111_cam_data[0]}]
set_property PACKAGE_PIN AB19 [get_ports {vga_blue[3]}]
set_property PACKAGE_PIN AB20 [get_ports {vga_blue[2]}]
set_property PACKAGE_PIN Y20 [get_ports {vga_blue[1]}]
set_property PACKAGE_PIN Y21 [get_ports {vga_blue[0]}]
set_property PACKAGE_PIN AA21 [get_ports {vga_green[3]}]
set_property PACKAGE_PIN AB21 [get_ports {vga_green[2]}]
set_property PACKAGE_PIN AA22 [get_ports {vga_green[1]}]
set_property PACKAGE_PIN AB22 [get_ports {vga_green[0]}]
set_property PACKAGE_PIN V20 [get_ports {vga_red[0]}]
set_property PACKAGE_PIN U20 [get_ports {vga_red[1]}]
set_property PACKAGE_PIN V19 [get_ports {vga_red[2]}]
set_property PACKAGE_PIN V18 [get_ports {vga_red[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports hdmi_clk]
set_property IOSTANDARD LVCMOS33 [get_ports hdmi_data_e]
set_property IOSTANDARD LVCMOS33 [get_ports hdmi_hsync]
set_property IOSTANDARD LVCMOS33 [get_ports hdmi_iic_Scl]
set_property IOSTANDARD LVCMOS33 [get_ports hdmi_iic_Sda]
set_property IOSTANDARD LVCMOS33 [get_ports hdmi_vsync]
set_property IOSTANDARD LVCMOS33 [get_ports mt9d111_href]
set_property IOSTANDARD LVCMOS33 [get_ports mt9d111_Scl]
set_property IOSTANDARD LVCMOS33 [get_ports mt9d111_Sda]
set_property PULLUP true [get_ports mt9d111_Scl]
set_property PULLUP true [get_ports mt9d111_Sda]
set_property PACKAGE_PIN W18 [get_ports hdmi_clk]
set_property PACKAGE_PIN U16 [get_ports hdmi_data_e]
set_property PACKAGE_PIN V17 [get_ports hdmi_hsync]
set_property PACKAGE_PIN AA18 [get_ports hdmi_iic_Scl]
set_property PACKAGE_PIN Y16 [get_ports hdmi_iic_Sda]
set_property PACKAGE_PIN W17 [get_ports hdmi_vsync]
set_property PACKAGE_PIN AB10 [get_ports mt9d111_href]
set_property PACKAGE_PIN Y11 [get_ports mt9d111_Scl]
set_property PACKAGE_PIN AB11 [get_ports mt9d111_Sda]
set_property IOSTANDARD LVCMOS33 [get_ports mt9d111_vsync]
set_property IOSTANDARD LVCMOS33 [get_ports vga_vsync]
set_property IOSTANDARD LVCMOS33 [get_ports vga_hsync]
set_property PACKAGE_PIN AA11 [get_ports mt9d111_vsync]
set_property PACKAGE_PIN Y19 [get_ports vga_vsync]
set_property SLEW FAST [get_ports {vga_red[3]}]
set_property SLEW FAST [get_ports {vga_red[2]}]
set_property SLEW FAST [get_ports {vga_red[1]}]
set_property SLEW FAST [get_ports {vga_red[0]}]
set_property SLEW FAST [get_ports hdmi_clk]
set_property SLEW FAST [get_ports hdmi_data_e]
set_property SLEW FAST [get_ports hdmi_hsync]
set_property SLEW FAST [get_ports hdmi_vsync]
set_property SLEW FAST [get_ports vga_hsync]
set_property SLEW FAST [get_ports vga_vsync]
set_property PACKAGE_PIN AA19 [get_ports vga_hsync]
set_property IOSTANDARD LVTTL [get_ports mt9d111_xck]
set_property PACKAGE_PIN AA8 [get_ports mt9d111_xck]
FAILURE : Behavioral models do not support built-in FIFO configurations. Please use post-synthesis or post-implement simulation in Vivado.
set_property -dict [list CONFIG.Component_Name {axi_vdma_0 } CONFIG.c_enable_debug_all {1}] [get_ips axi_vdma_0]
というエラーだった。[BD 41-237] Bus Interface property FREQ_HZ does not match between /axi_vdma_0/S_AXIS_S2MM(100000000) and /mt9d111_inf_axi_stream_0/m_axis(18000000)
[BD 41-1275] set port parameter, Invalid long/float value '' specified for parameter 'Freq Hz(FREQ_HZ)' for BD Interface 'mt9d111_pclk'.
1.IP integrator net_vcc
2.Connecting signals to ground in Vivado block design
AXI VDMAのレジスタ設定用AXI Lite Master IPの作製1(仕様の検討)
AXI VDMAのレジスタ設定用AXI Lite Master IPの作製2(シミュレーション)
AXI VDMAのレジスタ設定用AXI Lite Master IPの作製3(HDLソースの公開)
AXI VDMAのレジスタ設定用AXI Lite Master IPの作製4(XPSへAdd IP)
initial begin
$readmemh("vdma_reg_set.txt", rom, 0, 255);
end
MI02~MI06:GNDにショート
JP2, JP6:ショート
J18:VADJ SELECT:1V8
日 | 月 | 火 | 水 | 木 | 金 | 土 |
---|---|---|---|---|---|---|
- | - | - | 1 | 2 | 3 | 4 |
5 | 6 | 7 | 8 | 9 | 10 | 11 |
12 | 13 | 14 | 15 | 16 | 17 | 18 |
19 | 20 | 21 | 22 | 23 | 24 | 25 |
26 | 27 | 28 | 29 | 30 | 31 | - |