顔検出の結果を下に示す。./facedetect --cascade="/usr/local/share/OpenCV/haarcascades/haarcascade_frontalface_alt.xml" lena.jpg
sudo apt-get -yV update
sudo apt-get -yV upgrade
sudo reboot
sudo apt-get -yV install build-essential
sudo apt-get -yV install libboost1.46-all-dev
#
cd /tmp; sudo apt-get source opencv
sudo apt-get -yV build-dep opencv
#
sudo apt-get -yV install libqt4-dev
sudo apt-get -yV install libgtk2.0-dev
sudo apt-get -yV install pkg-config
#
sudo apt-get -yV install opencl-headers
#
sudo apt-get -yV install libjpeg-dev
sudo apt-get -yV install libopenjpeg-dev
sudo apt-get -yV install jasper
sudo apt-get -yV install libjasper-dev libjasper-runtime
sudo apt-get -yV install libpng12-dev
sudo apt-get -yV install libpng++-dev libpng3
sudo apt-get -yV install libpnglite-dev libpngwriter0-dev libpngwriter0c2
sudo apt-get -yV install libtiff-dev libtiff-tools pngtools
sudo apt-get -yV install zlib1g-dev zlib1g-dbg
sudo apt-get -yV install v4l2ucp
#
sudo apt-get -yV install python
sudo apt-get -yV install autoconf
sudo apt-get -yV install libtbb2 libtbb-dev
sudo apt-get -yV install libeigen2-dev
sudo apt-get -yV install cmake
sudo apt-get -yV install openexr
sudo apt-get -yV install gstreamer-plugins-*
sudo apt-get -yV install freeglut3-dev
sudo apt-get -yV install libglui-dev
sudo apt-get -yV install libavc1394-dev libdc1394-22-dev libdc1394-utils
# ビデオ関係のパッケージ
sudo apt-get -yV install libxine-dev
sudo apt-get -yV install libxvidcore-dev
sudo apt-get -yV install libva-dev
sudo apt-get -yV install libssl-dev
sudo apt-get -yV install libv4l-dev
sudo apt-get -yV install libvo-aacenc-dev
sudo apt-get -yV install libvo-amrwbenc-dev
sudo apt-get -yV install libvorbis-dev
sudo apt-get -yV install libvpx-dev
wget http://sourceforge.net/projects/opencvlibrary/files/opencv-unix/2.4.6.1/opencv-2.4.6.1.tar.gz
wget ftp://ftp.jp.netbsd.org/pub/pkgsrc/distfiles/opencv-2.4.6.1.tar.gz
tar xvzf opencv-2.4.6.1.tar.gz
cd opencv-2.4.6.1
mkdir build
cd build
cmake ..
make
sudo make install
sudo ldconfig
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_always.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_always_on_edge.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_arbiter.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_bits.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_change.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_code_distance.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_coverage.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_decrement.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_crc.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_cycle_sequence.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_delta.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_even_parity.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_fifo.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_fifo_index.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_frame.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_handshake.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_hold_value.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_implication.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_increment.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_memory_async.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_memory_sync.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_multiport_fifo.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_mutex.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_never.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_never_unknown.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_never_unknown_async.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_next.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_next_state.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_no_contention.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_no_overflow.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_no_transition.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_no_underflow.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_odd_parity.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_one_cold.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_one_hot.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_proposition.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_quiescent_state.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_range.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_reg_loaded.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_req_ack_unique.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_req_requires.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_stack.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_time.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_transition.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_unchange.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_valid_id.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_value.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_value_coverage.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_width.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_window.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_win_change.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_win_unchange.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_xproduct_bit_coverage.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_xproduct_value_coverage.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvlog -d OVL_VERILOG -d OVL_ASSERT_ON -d OVL_FINISH_OFF -i D:\HDL\OVL\std_ovl_v281 -work accellera_ovl_vlog D:\HDL\OVL\std_ovl_v281\ovl_zero_one_hot.v
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvhdl -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v281\std_ovl.vhd
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvhdl -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v281\std_ovl_procs.vhd
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvhdl -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v281\std_ovl_components_vlog.vhd
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvhdl -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v281\std_ovl_clock_gating.vhd
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvhdl -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v281\std_ovl_reset_gating.vhd
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvhdl -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v281\ovl_always.vhd
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvhdl -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v281\ovl_always_on_edge.vhd
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvhdl -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v281\ovl_change.vhd
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvhdl -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v281\ovl_cycle_sequence.vhd
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvhdl -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v281\ovl_decrement.vhd
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvhdl -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v281\ovl_delta.vhd
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvhdl -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v281\ovl_even_parity.vhd
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvhdl -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v281\ovl_fifo_index.vhd
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvhdl -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v281\ovl_frame.vhd
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvhdl -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v281\ovl_handshake.vhd
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvhdl -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v281\ovl_implication.vhd
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvhdl -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v281\ovl_increment.vhd
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvhdl -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v281\ovl_never.vhd
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvhdl -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v281\ovl_never_unknown.vhd
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvhdl -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v281\ovl_never_unknown_async.vhd
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvhdl -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v281\ovl_next.vhd
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvhdl -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v281\ovl_no_overflow.vhd
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvhdl -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v281\ovl_no_transition.vhd
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvhdl -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v281\ovl_no_underflow.vhd
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvhdl -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v281\ovl_odd_parity.vhd
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvhdl -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v281\ovl_one_cold.vhd
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvhdl -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v281\ovl_one_hot.vhd
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvhdl -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v281\ovl_proposition.vhd
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvhdl -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v281\ovl_quiescent_state.vhd
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvhdl -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v281\ovl_range.vhd
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvhdl -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v281\ovl_time.vhd
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvhdl -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v281\ovl_transition.vhd
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvhdl -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v281\ovl_unchange.vhd
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvhdl -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v281\ovl_width.vhd
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvhdl -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v281\ovl_win_change.vhd
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvhdl -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v281\ovl_win_unchange.vhd
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvhdl -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v281\ovl_window.vhd
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvhdl -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v281\ovl_zero_one_hot.vhd
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvhdl -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v281\vhdl93\ovl_always_rtl.vhd
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvhdl -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v281\vhdl93\ovl_cycle_sequence_rtl.vhd
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvhdl -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v281\vhdl93\ovl_implication_rtl.vhd
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvhdl -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v281\vhdl93\ovl_never_rtl.vhd
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvhdl -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v281\vhdl93\ovl_never_unknown_async_rtl.vhd
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvhdl -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v281\vhdl93\ovl_never_unknown_rtl.vhd
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvhdl -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v281\vhdl93\ovl_next_rtl.vhd
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvhdl -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v281\vhdl93\ovl_one_hot_rtl.vhd
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvhdl -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v281\vhdl93\ovl_range_rtl.vhd
call C:\HDL\Xilinx\Vivado\2014.1\bin\xvhdl -work accellera_ovl_vhdl D:\HDL\OVL\std_ovl_v281\vhdl93\ovl_zero_one_hot_rtl.vhd
accellera_ovl_vlog=$RDI_DATADIR/xsim/verilog/accellera_ovl_vlog
accellera_ovl_vhdl=$RDI_DATADIR/xsim/vhdl/accellera_ovl_vhdl
top - 19:57:32 up 17 min, 2 users, load average: 0.14, 1.08, 0.89
Tasks: 130 total, 1 running, 129 sleeping, 0 stopped, 0 zombie
Cpu(s): 0.0%us, 0.7%sy, 0.0%ni, 99.3%id, 0.0%wa, 0.0%hi, 0.0%si, 0.0%st
Mem: 509040k total, 315472k used, 193568k free, 8444k buffers
Swap: 0k total, 0k used, 0k free, 97560k cached
PID USER PR NI VIRT RES SHR S %CPU %MEM TIME+ COMMAND
3004 root 20 0 2156 1036 760 R 1 0.2 0:00.56 top
1 root 20 0 2604 1124 464 S 0 0.2 0:02.33 init
2 root 20 0 0 0 0 S 0 0.0 0:00.00 kthreadd
3 root 20 0 0 0 0 S 0 0.0 0:00.00 ksoftirqd/0
5 root 0 -20 0 0 0 S 0 0.0 0:00.00 kworker/0:0H
6 root 20 0 0 0 0 S 0 0.0 0:00.11 kworker/u:0
7 root 0 -20 0 0 0 S 0 0.0 0:00.00 kworker/u:0H
8 root RT 0 0 0 0 S 0 0.0 0:00.01 migration/0
9 root 20 0 0 0 0 S 0 0.0 0:00.31 rcu_preempt
10 root 20 0 0 0 0 S 0 0.0 0:00.00 rcu_bh
11 root 20 0 0 0 0 S 0 0.0 0:00.00 rcu_sched
12 root 20 0 0 0 0 S 0 0.0 0:00.01 ksoftirqd/1
13 root RT 0 0 0 0 S 0 0.0 0:00.01 migration/1
14 root 20 0 0 0 0 S 0 0.0 0:00.00 kworker/1:0
15 root 0 -20 0 0 0 S 0 0.0 0:00.00 kworker/1:0H
16 root 0 -20 0 0 0 S 0 0.0 0:00.00 khelper
17 root 20 0 0 0 0 S 0 0.0 0:00.00 kdevtmpfs
U-Boot 2012.10-dirty (May 15 2014 - 19:53:53)
DRAM: 512 MiB
WARNING: Caches not enabled
MMC: SDHCI: 0
SF: Detected S25FL256S with page size 64 KiB, total 32 MiB
SF: Warning - Only lower 16MB is accessible in 3 byte addressing mode
*** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
Net: zynq_gem
Hit any key to stop autoboot: 0
Copying Linux from SD to RAM...
Device: SDHCI
Manufacturer ID: 27
OEM: 5048
Name: SD08G
Tran Speed: 50000000
Rd Block Len: 512
SD version 2.0
High Capacity: Yes
Capacity: 7.4 GiB
Bus Width: 4-bit
reading uImage
2907968 bytes read
reading devicetree.dtb
6001 bytes read
## Booting kernel from Legacy Image at 03000000 ...
Image Name: Linux-3.8.0-ga6ab43a
Image Type: ARM Linux Kernel Image (uncompressed)
Data Size: 2907904 Bytes = 2.8 MiB
Load Address: 00008000
Entry Point: 00008000
Verifying Checksum ... OK
## Flattened Device Tree blob at 02a00000
Booting using the fdt blob at 0x02a00000
Loading Kernel Image ... OK
OK
Loading Device Tree to 1fb50000, end 1fb54770 ... OK
Starting kernel ...
Booting Linux on physical CPU 0x0
Linux version 3.8.0-ga6ab43a (masaaki@masaaki-VirtualBox) (gcc version 4.6.3 (Sourcery CodeBench Lite 2012.03-79) ) #4 SMP PREEMPT Thu May 15 20:57:26 JST 2014
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
Machine: Xilinx Zynq Platform, model: Xilinx Zynq ZED
bootconsole [earlycon0] enabled
cma: CMA: reserved 40 MiB at 1d000000
Memory policy: ECC disabled, Data cache writealloc
PERCPU: Embedded 7 pages/cpu @c0e7b000 s8000 r8192 d12480 u32768
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 130048
Kernel command line: console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlyprintk rootfstype=ext4 rootwait devtmpfs.mount=0
PID hash table entries: 2048 (order: 1, 8192 bytes)
Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
__ex_table already sorted, skipping sort
Memory: 512MB = 512MB total
Memory: 467916k/467916k available, 56372k reserved, 0K highmem
Virtual kernel memory layout:
vector : 0xffff0000 - 0xffff1000 ( 4 kB)
fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
vmalloc : 0xe0800000 - 0xff000000 ( 488 MB)
lowmem : 0xc0000000 - 0xe0000000 ( 512 MB)
pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB)
modules : 0xbf000000 - 0xbfe00000 ( 14 MB)
.text : 0xc0008000 - 0xc0501664 (5094 kB)
.init : 0xc0502000 - 0xc052bf40 ( 168 kB)
.data : 0xc052c000 - 0xc0568d20 ( 244 kB)
.bss : 0xc0568d20 - 0xc0a706b8 (5151 kB)
Preemptible hierarchical RCU implementation.
RCU lockdep checking is enabled.
Dump stacks of tasks blocking RCU-preempt GP.
RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
NR_IRQS:16 nr_irqs:16 16
MIO pin 11 not assigned(00001760)
xslcr mapped to e0802000
Zynq clock init
timer #0 at e0804000, irq=43
sched_clock: 32 bits at 100 Hz, resolution 10000000ns, wraps every 4294967286ms
Console: colour dummy device 80x30
Lock dependency validator: Copyright (c) 2006 Red Hat, Inc., Ingo Molnar
... MAX_LOCKDEP_SUBCLASSES: 8
... MAX_LOCK_DEPTH: 48
... MAX_LOCKDEP_KEYS: 8191
... CLASSHASH_SIZE: 4096
... MAX_LOCKDEP_ENTRIES: 16384
... MAX_LOCKDEP_CHAINS: 32768
... CHAINHASH_SIZE: 16384
memory used by lock dependency info: 3695 kB
per task-struct memory footprint: 1152 bytes
Calibrating delay loop... 1332.01 BogoMIPS (lpj=6660096)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 512
CPU: Testing write buffer coherency: ok
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0x37fc68 - 0x37fc9c
L310 cache controller enabled
l2x0: 8 ways, CACHE_ID 0x000000c0, AUX_CTRL 0x72360000, Cache size: 524288 B
CPU1: Booted secondary processor
CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
Brought up 2 CPUs
SMP: Total of 2 processors activated (2664.03 BogoMIPS).
devtmpfs: initialized
NET: Registered protocol family 16
DMA: preallocated 256 KiB pool for atomic coherent allocations
xgpiops e000a000.gpio: gpio at 0xe000a000 mapped to 0xe080c000
hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
hw-breakpoint: maximum watchpoint size is 4 bytes.
bio: create slabat 0
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
Advanced Linux Sound Architecture Driver Initialized.
Switching to clocksource xttcps_clocksource
NET: Registered protocol family 2
TCP established hash table entries: 4096 (order: 3, 32768 bytes)
TCP bind hash table entries: 4096 (order: 5, 147456 bytes)
TCP: Hash tables configured (established 4096 bind 4096)
TCP: reno registered
UDP hash table entries: 256 (order: 2, 20480 bytes)
UDP-Lite hash table entries: 256 (order: 2, 20480 bytes)
NET: Registered protocol family 1
hw perfevents: enabled with ARMv7 Cortex-A9 PMU driver, 7 counters available
msgmni has been set to 993
io scheduler noop registered
io scheduler deadline registered
io scheduler cfq registered (default)
xuartps e0001000.uart: failed to get alias id, errno -19
e0001console [ttyPS0] enabled, bootconsole disabled
console [ttyPS0] enabled, bootconsole disabled
xdevcfg f8007000.devcfg: ioremap f8007000 to e0814000 with size 1000
[drm] Initialized drm 1.1.0 20060810
platform 6c000000.axi_hdmi: Driver axi-hdmi requests probe deferral
brd: module loaded
loop: module loaded
xqspips e000d000.spi: master is unqueued, this is deprecated
xqspips e000d000.spi: at 0xE000D000 mapped to 0xE0816000, irq=51
libphy: XEMACPS mii bus: probed
xemacps e000b000.eth: pdev->id -1, baseaddr 0xe000b000, irq 54
ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
ULPI transceiver vendor/product ID 0x0451/0x1507
Found TI TUSB1210 ULPI transceiver.
ULPI integrity check: passed.
xusbps-ehci xusbps-ehci.0: Xilinx PS USB EHCI Host Controller
xusbps-ehci xusbps-ehci.0: new USB bus registered, assigned bus number 1
xusbps-ehci xusbps-ehci.0: irq 53, io mem 0x00000000
xusbps-ehci xusbps-ehci.0: USB 2.0 started, EHCI 1.00
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 1 port detected
Initializing USB Mass Storage driver...
usbcore: registered new interface driver usb-storage
USB Mass Storage support registered.
mousedev: PS/2 mouse device common for all mice
i2c /dev entries driver
sdhci: Secure Digital Host Controller Interface driver
sdhci: Copyright(c) Pierre Ossman
sdhci-pltfm: SDHCI platform and OF driver helper
mmc0: Invalid maximum block size, assuming 512 bytes
mmc0: SDHCI controller on e0100000.sdhci [e0100000.sdhci] using ADMA
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
mmc0: new high speed SDHC card at address 0007
mmcblk0: mmc0:0007 SD08G 7.42 GiB
mmcblk0: p1 p2
adv7511 0-0039: ASoC: no sink widget found for TMDS
adv7511 0-0039: ASoC: Failed to add route AIFIN -> direct -> TMDS
adv7511-hdmi-snd adv7511_hdmi_snd.3: adv7511 <-> 75c00000.axi-spdif-tx mapping ok
TCP: cubic registered
NET: Registered protocol family 17
VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
Registering SWP/SWPB emulation handler
drivers/rtc/hctosys.c: unable to open rtc device (rtc0)
ALSA device list:
#0: HDMI monitor
axi-hdmi 6c000000.axi_hdmi: No connectors reported connected with modes
[drm] Cannot find any crtc or sizes - going 1024x768
Console: switching to colour frame buffer device 128x48
axi-hdmi 6c000000.axi_hdmi: fb0: frame buffer device
axi-hdmi 6c000000.axi_hdmi: registered panic notifier
[drm] Initialized axi_hdmi_drm 1.0.0 20120930 on minor 0
EXT4-fs (mmcblk0p2): recovery complete
EXT4-fs (mmcblk0p2): mounted filesystem with ordered data mode. Opts: (null)
VFS: Mounted root (ext4 filesystem) on device 179:2.
Freeing init memory: 164K
init: ureadahead main process (741) terminated with status 5
Last login: Thu Jan 1 00:00:13 UTC 1970 on tty1
root@linaro-ubuntu-desktop:~# cd /
root@linaro-ubuntu-desktop:/# ls
bin dev home lost+found mnt proc run selinux sys usr
boot etc lib media opt root sbin srv tmp var
root@linaro-ubuntu-desktop:/# df
Filesystem 1K-blocks Used Available Use% Mounted on
/dev/root 7463628 1485216 5592620 21% /
none 50904 404 50500 1% /run
none 5120 0 5120 0% /run/lock
none 254520 76 254444 1% /run/shm
を実行した。sudo mkfs.msdos -n ZED_BOOT /dev/sdb1
を実行した。sudo mkfs.ext4 -L ROOT_FS /dev/sdb2
コマンドを実行した。export XILINX=/opt/Xilinx/14.4/ISE_DS/ISE
-- pixclk = 25MHz, MMCM VCO Frequency = 600 ~ 1200 MHz
dvi_disp_inst : dvi_disp generic map (
-- MMCM_CLKFBOUT_MULT => 30.0, -- VGA (VCO Freq = 750MHz)
-- MMCM_CLKIN_PERIOD => 40.0,
-- MMCM_CLKOUT0_DIVIDE => 6.0 -- 25MHz x 5 = 125MHz
-- MMCM_CLKFBOUT_MULT => 24.0, -- SVGA (VCO Freq = 600MHz)
-- MMCM_CLKIN_PERIOD => 40.0,
-- MMCM_CLKOUT0_DIVIDE => 3.0 -- 40MHz x 5 = 200MHz
MMCM_CLKFBOUT_MULT => 26.0, -- XGA (VCO Freq = 650MHz)
MMCM_CLKIN_PERIOD => 40.0,
MMCM_CLKOUT0_DIVIDE => 2.0 -- 65MHz x 5 = 325MHz
-- MMCM_CLKFBOUT_MULT => 43.25, -- SXGA (VCO Freq = 1081.25MHz)
-- MMCM_CLKIN_PERIOD => 40.0,
-- MMCM_CLKOUT0_DIVIDE => 2.0 -- 108MHz x 5 = 540MHz(540.625/5=108.125MHz)
-- MMCM_CLKFBOUT_MULT => 29.75, -- HD (VCO Freq = 743.75MHz)
-- MMCM_CLKIN_PERIOD => 40.0,
-- MMCM_CLKOUT0_DIVIDE => 1.0 -- 148.5MHz x 5 = 742.5MHz(743.75/5=148.75MHz)
) port map (
entity MMCME2_BASE is
generic (
BANDWIDTH : string := "OPTIMIZED";
CLKFBOUT_MULT_F : real := 5.000;
CLKFBOUT_PHASE : real := 0.000;
CLKIN1_PERIOD : real := 0.000;
CLKOUT0_DIVIDE_F : real := 1.000;
CLKOUT0_DUTY_CYCLE : real := 0.500;
CLKOUT0_PHASE : real := 0.000;
CLKOUT1_DIVIDE : integer := 1;
CLKOUT1_DUTY_CYCLE : real := 0.500;
CLKOUT1_PHASE : real := 0.000;
CLKOUT2_DIVIDE : integer := 1;
CLKOUT2_DUTY_CYCLE : real := 0.500;
CLKOUT2_PHASE : real := 0.000;
CLKOUT3_DIVIDE : integer := 1;
CLKOUT3_DUTY_CYCLE : real := 0.500;
CLKOUT3_PHASE : real := 0.000;
CLKOUT4_CASCADE : boolean := FALSE;
CLKOUT4_DIVIDE : integer := 1;
CLKOUT4_DUTY_CYCLE : real := 0.500;
CLKOUT4_PHASE : real := 0.000;
CLKOUT5_DIVIDE : integer := 1;
CLKOUT5_DUTY_CYCLE : real := 0.500;
CLKOUT5_PHASE : real := 0.000;
CLKOUT6_DIVIDE : integer := 1;
CLKOUT6_DUTY_CYCLE : real := 0.500;
CLKOUT6_PHASE : real := 0.000;
DIVCLK_DIVIDE : integer := 1;
REF_JITTER1 : real := 0.010;
STARTUP_WAIT : boolean := FALSE
);
port (
CLKFBOUT : out std_ulogic;
CLKFBOUTB : out std_ulogic;
CLKOUT0 : out std_ulogic;
CLKOUT0B : out std_ulogic;
CLKOUT1 : out std_ulogic;
CLKOUT1B : out std_ulogic;
CLKOUT2 : out std_ulogic;
CLKOUT2B : out std_ulogic;
CLKOUT3 : out std_ulogic;
CLKOUT3B : out std_ulogic;
CLKOUT4 : out std_ulogic;
CLKOUT5 : out std_ulogic;
CLKOUT6 : out std_ulogic;
LOCKED : out std_ulogic;
CLKFBIN : in std_ulogic;
CLKIN1 : in std_ulogic;
PWRDWN : in std_ulogic;
RST : in std_ulogic
);
process (PCLK_I, RST_I) begin -- by Digilent ZYBO Base System Design
if RST_I='1' then
async_sync_rst <= '1';
elsif (PCLK_I'event and PCLK_I='1') then
async_sync_rst <= '0';
end if;
end process;
INST "system_i/cdc_axi_slave_0/cdc_axi_slave_0/dvi_disp_inst/MMCM_BASE_PIXEL" LOC = MMCME2_ADV_X0Y1;
PLLE2_ADVからBUFIO に行く配線はないそうだ。PhysDesignRules:2309 - The PLLE2_ADV block
is using an output pin that does not use dedicated connectivity. Routing from the pin to a BUFIO buffer type is not supported.
MMCMを X0Y1 に配置していた。PLLも X0Y1 に制約することにした。INST "*/USER_LOGIC_I/USE_BUFR_DIV5.Inst_mmcme2_drp/mmcm_adv_inst" LOC = "MMCME2_ADV_X0Y1";
INST "system_i/cdc_axi_slave_0/cdc_axi_slave_0/dvi_disp_inst/PLL_BASE_PIXEL" LOC = PLLE2_ADV_X0Y1;
日 | 月 | 火 | 水 | 木 | 金 | 土 |
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11 | 12 | 13 | 14 | 15 | 16 | 17 |
18 | 19 | 20 | 21 | 22 | 23 | 24 |
25 | 26 | 27 | 28 | 29 | 30 | 31 |