と書いてあった。”root:*:15835:0:99999:7:::”
// 0x1c : Control signal of cam_addr
// bit 0 - cam_addr_ap_vld (Read/Write/COH)
// bit 1 - cam_addr_ap_ack (Read)
// others - reserved
// 0x24 : Control signal of lap_addr
// bit 0 - lap_addr_ap_vld (Read/Write/SC)
// others - reserved
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
// BUS_AXI4LS
// 0x00 : Control signals
// bit 0 - ap_start (Read/Write/COH)
// bit 1 - ap_done (Read/COR)
// bit 2 - ap_idle (Read)
// bit 3 - ap_ready (Read)
// bit 7 - auto_restart (Read/Write)
// others - reserved
// 0x04 : Global Interrupt Enable Register
// bit 0 - Global Interrupt Enable (Read/Write)
// others - reserved
// 0x08 : IP Interrupt Enable Register (Read/Write)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// 0x0c : IP Interrupt Status Register (Read/TOW)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// 0x10 : Data signal of ap_return
// bit 31~0 - ap_return[31:0] (Read)
// 0x18 : Data signal of cam_addr
// bit 31~0 - cam_addr[31:0] (Read/Write)
// 0x1c : Control signal of cam_addr
// bit 0 - cam_addr_ap_vld (Read/Write/COH)
// bit 1 - cam_addr_ap_ack (Read)
// others - reserved
// 0x20 : Data signal of lap_addr
// bit 31~0 - lap_addr[31:0] (Read/Write)
// 0x24 : Control signal of lap_addr
// bit 0 - lap_addr_ap_vld (Read/Write/SC)
// others - reserved
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.1
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
// LiteS
// 0x00 : Control signals
// bit 0 - ap_start (Read/Write/COH)
// bit 1 - ap_done (Read/COR)
// bit 2 - ap_idle (Read)
// bit 3 - ap_ready (Read)
// bit 7 - auto_restart (Read/Write)
// others - reserved
// 0x04 : Global Interrupt Enable Register
// bit 0 - Global Interrupt Enable (Read/Write)
// others - reserved
// 0x08 : IP Interrupt Enable Register (Read/Write)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// 0x0c : IP Interrupt Status Register (Read/TOW)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// 0x10 : reserved
// 0x14 : Data signal of cam_addr
// bit 31~0 - cam_addr[31:0] (Read/Write)
// 0x18 : reserved
// 0x1c : Data signal of lap_addr
// bit 31~0 - lap_addr[31:0] (Read/Write)
// 0x20 : Data signal of ap_return
// bit 31~0 - ap_return[31:0] (Read)
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
#pragma HLS INTERFACE ap_none port=cam_addr
#pragma HLS INTERFACE ap_none port=lap_addr
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
// BUS_AXI4LS
// 0x00 : Control signals
// bit 0 - ap_start (Read/Write/COH)
// bit 1 - ap_done (Read/COR)
// bit 2 - ap_idle (Read)
// bit 3 - ap_ready (Read)
// bit 7 - auto_restart (Read/Write)
// others - reserved
// 0x04 : Global Interrupt Enable Register
// bit 0 - Global Interrupt Enable (Read/Write)
// others - reserved
// 0x08 : IP Interrupt Enable Register (Read/Write)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// 0x0c : IP Interrupt Status Register (Read/TOW)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// 0x10 : Data signal of ap_return
// bit 31~0 - ap_return[31:0] (Read)
// 0x18 : Data signal of cam_addr
// bit 31~0 - cam_addr[31:0] (Read/Write)
// 0x1c : reserved
// 0x20 : Data signal of lap_addr
// bit 31~0 - lap_addr[31:0] (Read/Write)
// 0x24 : reserved
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
// laplacian_filter.c
// lap_filter_axim()
#include <stdio.h>
#include <string.h>
#define HORIZONTAL_PIXEL_WIDTH 800
#define VERTICAL_PIXEL_WIDTH 600
#define ALL_PIXEL_VALUE (HORIZONTAL_PIXEL_WIDTH*VERTICAL_PIXEL_WIDTH)
int laplacian_fil(int x0y0, int x1y0, int x2y0, int x0y1, int x1y1, int x2y1, int x0y2, int x1y2, int x2y2);
int conv_rgb2y(int rgb);
int lap_filter_axim(int *cam_addr, int *lap_addr, volatile int *cam_fb, volatile int *lap_fb)
{
#pragma HLS INTERFACE s_axilite port=cam_addr bundle=BUS_AXI4LS
#pragma HLS INTERFACE s_axilite port=lap_addr bundle=BUS_AXI4LS
#pragma HLS INTERFACE s_axilite port=return bundle=BUS_AXI4LS
#pragma HLS INTERFACE ap_none port=cam_addr
#pragma HLS INTERFACE ap_none port=lap_addr
#pragma HLS INTERFACE m_axi port=cam_fb depth=480000
#pragma HLS INTERFACE m_axi port=lap_fb depth=480000
unsigned int line_buf[3][HORIZONTAL_PIXEL_WIDTH];
unsigned int lap_buf[HORIZONTAL_PIXEL_WIDTH];
int x, y;
int lap_fil_val;
int a, b;
int fl, sl, tl;
unsigned int offset;
// RGB値をY(輝度成分)のみに変換し、ラプラシアンフィルタを掛けた。
for (y=0; y<VERTICAL_PIXEL_WIDTH; y++){
for (x=0; x<HORIZONTAL_PIXEL_WIDTH; x++){
if (y==0 || y==VERTICAL_PIXEL_WIDTH-1){ // 縦の境界の時の値は0とする
lap_fil_val = 0;
}else if (x==0 || x==HORIZONTAL_PIXEL_WIDTH-1){ // 横の境界の時も値は0とする
lap_fil_val = 0;
}else{
if (x == 1){ // ラインの最初でラインの画素を読み出す
if (y == 1){ // 最初のラインでは3ライン分の画素を読み出す
for (a=0; a<3; a++){ // 3ライン分
offset = *cam_addr/sizeof(int);
memcpy(line_buf[a], (const int*)(cam_fb+offset+(a*HORIZONTAL_PIXEL_WIDTH)), HORIZONTAL_PIXEL_WIDTH*sizeof(int));
for (b=0; b<HORIZONTAL_PIXEL_WIDTH; b++){ // ライン
line_buf[a][b] = conv_rgb2y(line_buf[a][b]); // カラーから白黒へ
}
}
}
} else { // 最初のラインではないので、1ラインだけ読み込む。すでに他の2ラインは読み込まれている
offset = *cam_addr/sizeof(int);
memcpy(line_buf[(y+1)%3], (const int*)(cam_fb+offset+((y+1)*HORIZONTAL_PIXEL_WIDTH)), HORIZONTAL_PIXEL_WIDTH*sizeof(int));
for (b=0; b<HORIZONTAL_PIXEL_WIDTH; b++){ // ライン
line_buf[(y+1)%3][b] = conv_rgb2y(line_buf[(y+1)%3][b]); // カラーから白黒へ
}
}
fl = (y-1)%3; // 最初のライン, y=1 012, y=2 120, y=3 201, y=4 012
sl = y%3; // 2番めのライン
tl = (y+1)%3; // 3番目のライン
lap_fil_val = laplacian_fil(line_buf[fl][x-1], line_buf[fl][x], line_buf[fl][x+1], line_buf[sl][x-1], line_buf[sl][x], line_buf[sl][x+1], line_buf[tl][x-1], line_buf[tl][x], line_buf[tl][x+1]);
}
lap_buf[x] = (lap_fil_val<<16)+(lap_fil_val<<8)+lap_fil_val; // RGB同じ値を入れる
}
offset = *lap_addr/sizeof(int);
memcpy((int *)(lap_fb+offset+(y*HORIZONTAL_PIXEL_WIDTH)), (const int*)lap_buf, HORIZONTAL_PIXEL_WIDTH*sizeof(int));
}
return(1);
}
// RGBからYへの変換
// RGBのフォーマットは、{8'd0, R(8bits), G(8bits), B(8bits)}, 1pixel = 32bits
// 輝度信号Yのみに変換する。変換式は、Y = 0.299R + 0.587G + 0.114B
// "YUVフォーマット及び YUV<->RGB変換"を参考にした。http://vision.kuee.kyoto-u.ac.jp/~hiroaki/firewire/yuv.html
// 2013/09/27 : float を止めて、すべてint にした
int conv_rgb2y(int rgb){
int r, g, b, y_f;
int y;
b = rgb & 0xff;
g = (rgb>>8) & 0xff;
r = (rgb>>16) & 0xff;
y_f = 77*r + 150*g + 29*b; //y_f = 0.299*r + 0.587*g + 0.114*b;の係数に256倍した
y = y_f >> 8; // 256で割る
return(y);
}
// ラプラシアンフィルタ
// x0y0 x1y0 x2y0 -1 -1 -1
// x0y1 x1y1 x2y1 -1 8 -1
// x0y2 x1y2 x2y2 -1 -1 -1
int laplacian_fil(int x0y0, int x1y0, int x2y0, int x0y1, int x1y1, int x2y1, int x0y2, int x1y2, int x2y2)
{
int y;
y = -x0y0 -x1y0 -x2y0 -x0y1 +8*x1y1 -x2y1 -x0y2 -x1y2 -x2y2;
if (y<0)
y = 0;
else if (y>255)
y = 255;
return(y);
}
@W [HLS-41] Resource core 'AXI4LiteS' on port 'cam_addr' is deprecated. Please use the interface directive to specify the AXI interface.
@W [HLS-41] Resource core 'AXI4LiteS' on port 'lap_addr' is deprecated. Please use the interface directive to specify the AXI interface.
@W [HLS-41] Resource core 'AXI4LiteS' on port 'return' is deprecated. Please use the interface directive to specify the AXI interface.
@W [HLS-41] Resource core 'AXI4M' on port 'cam_fb' is deprecated. Please use the interface directive to specify the AXI interface.
@W [HLS-41] Resource core 'AXI4M' on port 'lap_fb' is deprecated. Please use the interface directive to specify the AXI interface.
#pragma HLS INTERFACE ap_hs port=cam_addr
#pragma HLS INTERFACE ap_vld port=lap_addr
#pragma HLS RESOURCE variable=cam_addr core=AXI4LiteS metadata="-bus_bundle LiteS"
#pragma HLS RESOURCE variable=lap_addr core=AXI4LiteS metadata="-bus_bundle LiteS"
#pragma HLS RESOURCE variable=return core=AXI4LiteS metadata="-bus_bundle LiteS"
#pragma HLS INTERFACE ap_bus port=cam_fb depth=480000
#pragma HLS INTERFACE ap_bus port=lap_fb depth=480000
#pragma HLS RESOURCE variable=cam_fb core=AXI4M
#pragma HLS RESOURCE variable=lap_fb core=AXI4M
void example(char *a, char *b, char *c)
{
#pragma HLS INTERFACE s_axilite port=return bundle=BUS_A
#pragma HLS INTERFACE s_axilite port=a bundle=BUS_A
#pragma HLS INTERFACE s_axilite port=b bundle=BUS_A
#pragma HLS INTERFACE s_axilite port=c bundle=BUS_A offset=0x0400
#pragma HLS INTERFACE ap_vld port=b
*c += *a + *b;
}
#pragma HLS INTERFACE s_axilite port=cam_addr bundle=BUS_AXI4LS
#pragma HLS INTERFACE s_axilite port=lap_addr bundle=BUS_AXI4LS
#pragma HLS INTERFACE s_axilite port=return bundle=BUS_AXI4LS
#pragma HLS INTERFACE ap_hs port=cam_addr
#pragma HLS INTERFACE ap_vld port=lap_addr
#pragma HLS INTERFACE m_axi port=cam_fb depth=480000
#pragma HLS INTERFACE m_axi port=lap_fb depth=480000
0
Device: zynq_sdhci
Manufacturer ID: 74
OEM: 4a45
Name: USD
Tran Speed: 50000000
Rd Block Len: 512
SD version 3.0
High Capacity: Yes
Capacity: 7.5 GiB
Bus Width: 4-bit
reading uEnv.txt
117 bytes read in 8 ms (13.7 KiB/s)
Loaded environment from uEnv.txt
Importing environment from SD ...
Running uenvcmd ...
reading uImage
3987160 bytes read in 351 ms (10.8 MiB/s)
reading devicetree.dtb
7762 bytes read in 16 ms (473.6 KiB/s)
## Booting kernel from Legacy Image at 03000000 ...
Image Name: Linux-3.14.0-xilinx-13567-g906a2
Image Type: ARM Linux Kernel Image (uncompressed)
Data Size: 3987096 Bytes = 3.8 MiB
Load Address: 00008000
Entry Point: 00008000
Verifying Checksum ... OK
## Flattened Device Tree blob at 02a00000
Booting using the fdt blob at 0x2a00000
Loading Kernel Image ... OK
Loading Device Tree to 1fb29000, end 1fb2de51 ... OK
Starting kernel ...
Uncompressing Linux... done, booting the kernel.
[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 3.14.0-xilinx-13567-g906a2c9-dirty (masaaki@masaaki-VirtualBox) (gcc version 4.6.3 (Sourcery CodeBench Lite 2012.03-79) ) #9 SMP PREEMPT Sun Oct 5 04:32:36 JST 2014
[ 0.000000] CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
[ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
[ 0.000000] Machine model: Xilinx Zynq
[ 0.000000] bootconsole [earlycon0] enabled
[ 0.000000] cma: CMA: reserved 128 MiB at 17800000
[ 0.000000] Memory policy: Data cache writealloc
[ 0.000000] PERCPU: Embedded 8 pages/cpu @dfb9e000 s10752 r8192 d13824 u32768
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 130048
[ 0.000000] Kernel command line: console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlyprintk rootfstype=ext4 rootwait devtmpfs.mount=1 coherent_pool=16M
[ 0.000000] PID hash table entries: 2048 (order: 1, 8192 bytes)
[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
[ 0.000000] Memory: 375388K/524288K available (5144K kernel code, 319K rwdata, 1900K rodata, 202K init, 5339K bss, 148900K reserved, 0K highmem)
[ 0.000000] Virtual kernel memory layout:
[ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB)
[ 0.000000] fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
[ 0.000000] vmalloc : 0xe0800000 - 0xff000000 ( 488 MB)
[ 0.000000] lowmem : 0xc0000000 - 0xe0000000 ( 512 MB)
[ 0.000000] pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB)
[ 0.000000] modules : 0xbf000000 - 0xbfe00000 ( 14 MB)
[ 0.000000] .text : 0xc0008000 - 0xc06e9600 (7046 kB)
[ 0.000000] .init : 0xc06ea000 - 0xc071ca00 ( 203 kB)
[ 0.000000] .data : 0xc071e000 - 0xc076dde0 ( 320 kB)
[ 0.000000] .bss : 0xc076ddec - 0xc0ca4c88 (5340 kB)
[ 0.000000] Preemptible hierarchical RCU implementation.
[ 0.000000] RCU lockdep checking is enabled.
[ 0.000000] Dump stacks of tasks blocking RCU-preempt GP.
[ 0.000000] RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
[ 0.000000] NR_IRQS:16 nr_irqs:16 16
[ 0.000000] ps7-slcr mapped to e0802000
[ 0.000000] zynq_clock_init: clkc starts at e0802100
[ 0.000000] Zynq clock init
[ 0.000016] sched_clock: 64 bits at 325MHz, resolution 3ns, wraps every 3383112499200ns
[ 0.008493] ps7-ttc #0 at e0804000, irq=43
[ 0.013537] Console: colour dummy device 80x30
[ 0.017880] Lock dependency validator: Copyright (c) 2006 Red Hat, Inc., Ingo Molnar
[ 0.025929] ... MAX_LOCKDEP_SUBCLASSES: 8
[ 0.029952] ... MAX_LOCK_DEPTH: 48
[ 0.034124] ... MAX_LOCKDEP_KEYS: 8191
[ 0.038543] ... CLASSHASH_SIZE: 4096
[ 0.042895] ... MAX_LOCKDEP_ENTRIES: 16384
[ 0.047366] ... MAX_LOCKDEP_CHAINS: 32768
[ 0.051871] ... CHAINHASH_SIZE: 16384
[ 0.056312] memory used by lock dependency info: 3695 kB
[ 0.061761] per task-struct memory footprint: 1152 bytes
[ 0.067203] Calibrating delay loop... 1292.69 BogoMIPS (lpj=6463488)
[ 0.110951] pid_max: default: 32768 minimum: 301
[ 0.116258] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
[ 0.122798] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
[ 0.137372] CPU: Testing write buffer coherency: ok
[ 0.143614] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[ 0.149250] Setting up static identity map for 0x4de8d0 - 0x4de928
[ 0.155623] L310 cache controller enabled
[ 0.159581] l2x0: 8 ways, CACHE_ID 0x410000c8, AUX_CTRL 0x72760000, Cache size: 512 kB
[ 0.240406] CPU1: Booted secondary processor
[ 0.328276] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
[ 0.329397] Brought up 2 CPUs
[ 0.342265] SMP: Total of 2 processors activated.
[ 0.346967] CPU: All CPU(s) started in SVC mode.
[ 0.354966] devtmpfs: initialized
[ 0.365666] VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
[ 0.379811] regulator-dummy: no parameters
[ 0.392657] NET: Registered protocol family 16
[ 0.429380] DMA: preallocated 16384 KiB pool for atomic coherent allocations
[ 0.443160] cpuidle: using governor ladder
[ 0.447142] cpuidle: using governor menu
[ 0.474344] syscon f8000000.ps7-slcr: regmap [mem 0xf8000000-0xf8000fff] registered
[ 0.488598] hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
[ 0.496700] hw-breakpoint: maximum watchpoint size is 4 bytes.
[ 0.502964] zynq-ocm f800c000.ps7-ocmc: ZYNQ OCM pool: 256 KiB @ 0xe0880000
[ 0.575116] bio: create slabat 0
[ 0.584089] vgaarb: loaded
[ 0.588644] SCSI subsystem initialized
[ 0.594799] usbcore: registered new interface driver usbfs
[ 0.601466] usbcore: registered new interface driver hub
[ 0.607204] usbcore: registered new device driver usb
[ 0.613761] media: Linux media interface: v0.10
[ 0.618757] Linux video capture interface: v2.00
[ 0.624034] pps_core: LinuxPPS API ver. 1 registered
[ 0.628874] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti
[ 0.638486] PTP clock support registered
[ 0.643335] EDAC MC: Ver: 3.0.0
[ 0.649611] Advanced Linux Sound Architecture Driver Initialized.
[ 0.665144] DMA-API: preallocated 4096 debug entries
[ 0.670185] DMA-API: debugging enabled by kernel config
[ 0.675923] Switched to clocksource arm_global_timer
[ 0.738658] NET: Registered protocol family 2
[ 0.745600] TCP established hash table entries: 4096 (order: 2, 16384 bytes)
[ 0.753592] TCP bind hash table entries: 4096 (order: 5, 147456 bytes)
[ 0.761803] TCP: Hash tables configured (established 4096 bind 4096)
[ 0.768287] TCP: reno registered
[ 0.771420] UDP hash table entries: 256 (order: 2, 20480 bytes)
[ 0.777804] UDP-Lite hash table entries: 256 (order: 2, 20480 bytes)
[ 0.785277] NET: Registered protocol family 1
[ 0.791203] RPC: Registered named UNIX socket transport module.
[ 0.797056] RPC: Registered udp transport module.
[ 0.801717] RPC: Registered tcp transport module.
[ 0.806496] RPC: Registered tcp NFSv4.1 backchannel transport module.
[ 0.814383] hw perfevents: enabled with ARMv7 Cortex-A9 PMU driver, 7 counters available
[ 0.828266] futex hash table entries: 512 (order: 3, 32768 bytes)
[ 0.841827] jffs2: version 2.2. (NAND) (SUMMARY) c 2001-2006 Red Hat, Inc.
[ 0.849398] msgmni has been set to 989
[ 0.854655] io scheduler noop registered
[ 0.858617] io scheduler deadline registered
[ 0.862868] io scheduler cfq registered (default)
[ 0.887625] dma-pl330 f8003000.ps7-dma: Loaded driver for PL330 DMAC-2364208
[ 0.894535] dma-pl330 f8003000.ps7-dma: DBUFF-128x8bytes Num_Chans-8 Num_Peri-4 Num_Events-16
[ 0.906786] e0001000.serial: ttyPS0 at MMIO 0xe0001000 (irq = 82, base_baud = 3125000) is a xuartps
[ 0.916208] console [ttyPS0] enabled
[ 0.916208] console [ttyPS0] enabled
[ 0.923261] bootconsole [earlycon0] disabled
[ 0.923261] bootconsole [earlycon0] disabled
[ 0.934678] xdevcfg f8007000.ps7-dev-cfg: ioremap 0xf8007000 to e0866000
[ 0.944496] [drm] Initialized drm 1.1.0 20060810
[ 0.982856] brd: module loaded
[ 1.005097] loop: module loaded
[ 1.021051] m25p80 spi0.0: found s25fl128s1, expected n25q128
[ 1.026984] m25p80 spi0.0: s25fl128s1 (16384 Kbytes)
[ 1.032008] 4 ofpart partitions found on MTD device spi0.0
[ 1.037468] Creating 4 MTD partitions on "spi0.0":
[ 1.042194] 0x000000000000-0x000000400000 : "qspi-fsbl-uboot"
[ 1.056411] 0x000000400000-0x000000900000 : "qspi-linux"
[ 1.066853] 0x000000900000-0x000000920000 : "qspi-device-tree"
[ 1.077593] 0x000000920000-0x000001000000 : "qspi-user"
[ 1.097217] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
[ 1.102969] e1000e: Copyright(c) 1999 - 2013 Intel Corporation.
[ 1.114771] libphy: XEMACPS mii bus: probed
[ 1.121070] xemacps e000b000.ps7-ethernet: invalid address, use assigned
[ 1.128174] xemacps e000b000.ps7-ethernet: MAC updated 4e:96:07:9c:de:93
[ 1.135325] xemacps e000b000.ps7-ethernet: pdev->id -1, baseaddr 0xe000b000, irq 54
[ 1.150692] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[ 1.157754] ehci-pci: EHCI PCI platform driver
[ 1.162833] ULPI transceiver vendor/product ID 0x0424/0x0007
[ 1.168540] Found SMSC USB3320 ULPI transceiver.
[ 1.173098] ULPI integrity check: passed.
[ 1.178048] zynq-ehci zynq-ehci.0: Xilinx Zynq USB EHCI Host Controller
[ 1.185306] zynq-ehci zynq-ehci.0: new USB bus registered, assigned bus number 1
[ 1.215917] zynq-ehci zynq-ehci.0: irq 53, io mem 0x00000000
[ 1.235904] zynq-ehci zynq-ehci.0: USB 2.0 started, EHCI 1.00
[ 1.248654] hub 1-0:1.0: USB hub found
[ 1.252650] hub 1-0:1.0: 1 port detected
[ 1.260595] usbcore: registered new interface driver usb-storage
[ 1.269440] mousedev: PS/2 mouse device common for all mice
[ 1.277130] i2c /dev entries driver
[ 1.289800] zynq-edac f8006000.ps7-ddrc: ecc not enabled
[ 1.296053] cpufreq_cpu0: failed to get cpu0 regulator: -19
[ 1.304439] Xilinx Zynq CpuIdle Driver started
[ 1.310838] sdhci: Secure Digital Host Controller Interface driver
[ 1.317162] sdhci: Copyright(c) Pierre Ossman
[ 1.321437] sdhci-pltfm: SDHCI platform and OF driver helper
[ 1.328663] mmc0: no vqmmc regulator found
[ 1.332686] mmc0: no vmmc regulator found
[ 1.375838] mmc0: SDHCI controller on e0100000.ps7-sdio [e0100000.ps7-sdio] using ADMA
[ 1.391260] usbcore: registered new interface driver usbhid
[ 1.396870] usbhid: USB HID core driver
[ 1.412478] TCP: cubic registered
[ 1.415882] NET: Registered protocol family 17
[ 1.420853] Registering SWP/SWPB emulation handler
[ 1.428183] regulator-dummy: disabling
[ 1.432429] drivers/rtc/hctosys.c: unable to open rtc device (rtc0)
[ 1.448882] mmc0: new high speed SDHC card at address b368
[ 1.457326] mmcblk0: mmc0:b368 USD 7.45 GiB
[ 1.467669] mmcblk0: p1 p2
[ 1.467686] ALSA device list:
[ 1.467690] No soundcards found.
[ 1.512785] EXT4-fs (mmcblk0p2): mounted filesystem with ordered data mode. Opts: (null)
[ 1.520978] VFS: Mounted root (ext4 filesystem) on device 179:2.
[ 1.529301] devtmpfs: mounted
[ 1.532581] Freeing unused kernel memory: 200K (c06ea000 - c071c000)
INIT: version 2.88 booting
[info] Using makefile-style concurrent boot in runlevel S.
[....] Starting the hotplug events dispatcher: udevd[ 3.223839] udevd[701]: starting version 175
. ok
[ ok ] Synthesizing the initial hotplug events...done.
[ ok ] Waiting for /dev to be fully populated...done.
[....] Setting preliminary keymap...[ 5.308635] random: mktemp urandom read with 92 bits of entropy available
[ 8.727210] random: nonblocking pool is initialized
done.
[ ok ] Activating swap...done.
[ 11.596128] EXT4-fs (mmcblk0p2): re-mounted. Opts: (null)
[ ok ] Cleaning up temporary files....
[ ok ] Activating lvm and md swap...done.
[....] Checking file systems...fsck from util-linux 2.20.1
done.
[ ok ] Mounting local filesystems...done.
[ ok ] Activating swapfile swap...done.
[ ok ] Cleaning up temporary files....
[ ok ] Setting kernel variables ...done.
[....] Setting up resolvconf.../etc/resolvconf/update.d/libc: Warning: /etc/resolv.conf is not a symbolic link to /etc/resolvconf/run/resolv.conf
done.
[....] Configuring network interfaces...Internet Systems Consortium DHCP Client 4.2.2
Copyright 2004-2011 Internet Systems Consortium.
All rights reserved.
For info, please visit https://www.isc.org/software/dhcp/
Listening on LPF/eth0/4e:96:07:9c:de:93
Sending on LPF/eth0/4e:96:07:9c:de:93
Sending on Socket/fallback
DHCPREQUEST on eth0 to 255.255.255.255 port 67
[ 22.376773] xemacps e000b000.ps7-ethernet: Set clk to 25000000 Hz
[ 22.382921] xemacps e000b000.ps7-ethernet: link up (100/FULL)
DHCPREQUEST on eth0 to 255.255.255.255 port 67
DHCPNAK from 192.168.3.1
DHCPDISCOVER on eth0 to 255.255.255.255 port 67 interval 6
DHCPREQUEST on eth0 to 255.255.255.255 port 67
DHCPOFFER from 192.168.3.1
DHCPACK from 192.168.3.1
/etc/resolvconf/update.d/libc: Warning: /etc/resolv.conf is not a symbolic link to /etc/resolvconf/run/resolv.conf
bound to 192.168.3.2 -- renewal in 37814 seconds.
done.
[ ok ] Cleaning up temporary files....
[info] Setting console screen modes.
setterm: cannot (un)set powersave mode: Inappropriate ioctl for device
[info] Skipping font and keymap setup (handled by console-setup).
[ ok ] Setting up console font and keymap...done.
INIT: Entering runlevel: 2
[info] Using makefile-style concurrent boot in runlevel 2.
[ ok ] Starting enhanced syslogd: rsyslogd.
[ ok ] Starting periodic command scheduler: cron.
[ ok ] Starting system message bus: dbus.
[ ok ] Starting OpenBSD Secure Shell server: sshd.
create_clock -period 2.500 -name ap_clk -waveform {0.000 1.250} [get_ports ap_clk]
create_clock -period 4.000 -name ap_clk -waveform {0.000 2.000} [get_ports ap_clk]
`default_nettype none
module laplcian_filter_top #(
parameter integer INPUT_FF_NUMBER = 1,
parameter integer OUTPUT_FF_NUMBER = 1
)(
input wire ap_clk,
input wire ap_rst,
input wire ap_start,
output wire ap_done,
output wire ap_idle,
output wire ap_ready,
input wire [31:0] xy,
output wire [31:0] ap_return
);
wire [31:0] x0y0;
wire [31:0] x1y0;
wire [31:0] x2y0;
wire [31:0] x0y1;
wire [31:0] x1y1;
wire [31:0] x2y1;
wire [31:0] x0y2;
wire [31:0] x1y2;
wire [31:0] x2y2;
reg [31:0] xy_d[8:0];
wire ap_done_node;
wire ap_idle_node;
wire ap_ready_node;
wire [31:0] ap_return_node;
reg [31:0] x0y0_d [INPUT_FF_NUMBER-1:0];
reg [31:0] x1y0_d [INPUT_FF_NUMBER-1:0];
reg [31:0] x2y0_d [INPUT_FF_NUMBER-1:0];
reg [31:0] x0y1_d [INPUT_FF_NUMBER-1:0];
reg [31:0] x1y1_d [INPUT_FF_NUMBER-1:0];
reg [31:0] x2y1_d [INPUT_FF_NUMBER-1:0];
reg [31:0] x0y2_d [INPUT_FF_NUMBER-1:0];
reg [31:0] x1y2_d [INPUT_FF_NUMBER-1:0];
reg [31:0] x2y2_d [INPUT_FF_NUMBER-1:0];
reg [31:0] ap_return_d [OUTPUT_FF_NUMBER-1:0];
reg [INPUT_FF_NUMBER-1:0] ap_start_d;
reg [OUTPUT_FF_NUMBER-1:0] ap_done_d;
reg [OUTPUT_FF_NUMBER-1:0] ap_idle_d;
reg [OUTPUT_FF_NUMBER-1:0] ap_ready_d;
laplacian_filter lap_filter_inst (
.ap_clk(ap_clk),
.ap_rst(ap_rst),
.ap_start(ap_start_d[0]),
.ap_done(ap_done_node),
.ap_idle(ap_idle_node),
.ap_ready(ap_ready_node),
.x0y0(x0y0_d[0]),
.x1y0(x1y0_d[0]),
.x2y0(x2y0_d[0]),
.x0y1(x0y1_d[0]),
.x1y1(x1y1_d[0]),
.x2y1(x2y1_d[0]),
.x0y2(x0y2_d[0]),
.x1y2(x1y2_d[0]),
.x2y2(x2y2_d[0]),
.ap_return(ap_return_node)
);
always @(posedge ap_clk) begin : AP_XY_DELAY
integer i;
for(i=8; i>=0; i=i-1) begin
if (ap_rst) begin
xy_d[i] <= 32'd0;
end else begin
if (i == 8) begin
xy_d[i] <= xy;
end else begin
xy_d[i] <= xy_d[i+1];
end
end
end
end
assign x0y0 = xy_d[0];
assign x1y0 = xy_d[1];
assign x2y0 = xy_d[2];
assign x0y1 = xy_d[3];
assign x1y1 = xy_d[4];
assign x2y1 = xy_d[5];
assign x0y2 = xy_d[6];
assign x1y2 = xy_d[7];
assign x2y2 = xy_d[8];
always @(posedge ap_clk) begin : AP_START_DELAY
integer i;
for(i=INPUT_FF_NUMBER-1; i>=0; i=i-1) begin
if (ap_rst) begin
ap_start_d[i] <= 1'b0;
end else begin
if (i == (INPUT_FF_NUMBER-1)) begin
ap_start_d[i] <= ap_start;
end else begin
ap_start_d[i] <= ap_start_d[i+1];
end
end
end
end
always @(posedge ap_clk) begin : AP_DONE_DELAY
integer i;
for(i=OUTPUT_FF_NUMBER-1; i>=0; i=i-1) begin
if (ap_rst) begin
ap_done_d[i] <= 1'b0;
end else begin
if (i == (OUTPUT_FF_NUMBER-1)) begin
ap_done_d[i] <= ap_done_node;
end else begin
ap_done_d[i] <= ap_done_d[i+1];
end
end
end
end
assign ap_done = ap_done_d[0];
always @(posedge ap_clk) begin : AP_IDLE_DELAY
integer i;
for(i=OUTPUT_FF_NUMBER-1; i>=0; i=i-1) begin
if (ap_rst) begin
ap_idle_d[i] <= 1'b0;
end else begin
if (i == (OUTPUT_FF_NUMBER-1)) begin
ap_idle_d[i] <= ap_idle_node;
end else begin
ap_idle_d[i] <= ap_idle_d[i+1];
end
end
end
end
assign ap_idle = ap_idle_d[0];
always @(posedge ap_clk) begin : AP_READY_DELAY
integer i;
for(i=OUTPUT_FF_NUMBER-1; i>=0; i=i-1) begin
if (ap_rst) begin
ap_ready_d[i] <= 1'b0;
end else begin
if (i == (OUTPUT_FF_NUMBER-1)) begin
ap_ready_d[i] <= ap_ready_node;
end else begin
ap_ready_d[i] <= ap_ready_d[i+1];
end
end
end
end
assign ap_ready = ap_ready_d[0];
always @(posedge ap_clk) begin : AP_X0Y0_DELAY
integer i;
for(i=INPUT_FF_NUMBER-1; i>=0; i=i-1) begin
if (ap_rst) begin
x0y0_d[i] <= 32'd0;
end else begin
if (i == (INPUT_FF_NUMBER-1)) begin
x0y0_d[i] <= x0y0;
end else begin
x0y0_d[i] <= x0y0_d[i+1];
end
end
end
end
always @(posedge ap_clk) begin : AP_X1Y0_DELAY
integer i;
for(i=INPUT_FF_NUMBER-1; i>=0; i=i-1) begin
if (ap_rst) begin
x1y0_d[i] <= 32'd0;
end else begin
if (i == (INPUT_FF_NUMBER-1)) begin
x1y0_d[i] <= x1y0;
end else begin
x1y0_d[i] <= x1y0_d[i+1];
end
end
end
end
always @(posedge ap_clk) begin : AP_X2Y0_DELAY
integer i;
for(i=INPUT_FF_NUMBER-1; i>=0; i=i-1) begin
if (ap_rst) begin
x2y0_d[i] <= 32'd0;
end else begin
if (i == (INPUT_FF_NUMBER-1)) begin
x2y0_d[i] <= x2y0;
end else begin
x2y0_d[i] <= x2y0_d[i+1];
end
end
end
end
always @(posedge ap_clk) begin : AP_X0Y1_DELAY
integer i;
for(i=INPUT_FF_NUMBER-1; i>=0; i=i-1) begin
if (ap_rst) begin
x0y1_d[i] <= 32'd0;
end else begin
if (i == (INPUT_FF_NUMBER-1)) begin
x0y1_d[i] <= x0y1;
end else begin
x0y1_d[i] <= x0y1_d[i+1];
end
end
end
end
always @(posedge ap_clk) begin : AP_X1Y1_DELAY
integer i;
for(i=INPUT_FF_NUMBER-1; i>=0; i=i-1) begin
if (ap_rst) begin
x1y1_d[i] <= 32'd0;
end else begin
if (i == (INPUT_FF_NUMBER-1)) begin
x1y1_d[i] <= x1y1;
end else begin
x1y1_d[i] <= x1y1_d[i+1];
end
end
end
end
always @(posedge ap_clk) begin : AP_X2Y1_DELAY
integer i;
for(i=INPUT_FF_NUMBER-1; i>=0; i=i-1) begin
if (ap_rst) begin
x2y1_d[i] <= 32'd0;
end else begin
if (i == (INPUT_FF_NUMBER-1)) begin
x2y1_d[i] <= x2y1;
end else begin
x2y1_d[i] <= x2y1_d[i+1];
end
end
end
end
always @(posedge ap_clk) begin : AP_X0Y2_DELAY
integer i;
for(i=INPUT_FF_NUMBER-1; i>=0; i=i-1) begin
if (ap_rst) begin
x0y2_d[i] <= 32'd0;
end else begin
if (i == (INPUT_FF_NUMBER-1)) begin
x0y2_d[i] <= x0y2;
end else begin
x0y2_d[i] <= x0y2_d[i+1];
end
end
end
end
always @(posedge ap_clk) begin : AP_X1Y2_DELAY
integer i;
for(i=INPUT_FF_NUMBER-1; i>=0; i=i-1) begin
if (ap_rst) begin
x1y2_d[i] <= 32'd0;
end else begin
if (i == (INPUT_FF_NUMBER-1)) begin
x1y2_d[i] <= x1y2;
end else begin
x1y2_d[i] <= x1y2_d[i+1];
end
end
end
end
always @(posedge ap_clk) begin : AP_X2Y2_DELAY
integer i;
for(i=INPUT_FF_NUMBER-1; i>=0; i=i-1) begin
if (ap_rst) begin
x2y2_d[i] <= 32'd0;
end else begin
if (i == (INPUT_FF_NUMBER-1)) begin
x2y2_d[i] <= x2y2;
end else begin
x2y2_d[i] <= x2y2_d[i+1];
end
end
end
end
always @(posedge ap_clk) begin : AP_RETURN_DELAY
integer i;
for(i=OUTPUT_FF_NUMBER-1; i>=0; i=i-1) begin
if (ap_rst) begin
ap_return_d[i] <= 32'd0;
end else begin
if (i == (OUTPUT_FF_NUMBER-1)) begin
ap_return_d[i] <= ap_return_node;
end else begin
ap_return_d[i] <= ap_return_d[i+1];
end
end
end
end
assign ap_return = ap_return_d[0];
endmodule
`default_nettype wire
// clk_gen のインスタンス(ap_clk)
clk_gen #(
.CLK_PERIOD(40), // 4nsec, 250MHz
.CLK_DUTY_CYCLE(0.5),
.CLK_OFFSET(0),
.START_STATE(1'b0)
) ACLKi (
.clk_out(ap_clk)
);
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="laplacian_filter,hls_ip_2014_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z010clg400-1,HLS_INPUT_CLOCK=4.000000,HLS_INPUT_ARCH=pipeline,HLS_SYN_CLOCK=3.940000,HLS_SYN_LAT=7,HLS_SYN_TPT=1,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=485,HLS_SYN_LUT=393}" *)
module laplacian_filter (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
ap_ready,
x0y0,
x1y0,
x2y0,
x0y1,
x1y1,
x2y1,
x0y2,
x1y2,
x2y2,
ap_return
);
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_pp0_stg0_fsm_0 = 1'b1;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv1_1 = 1'b1;
parameter ap_const_lv32_3 = 32'b11;
parameter ap_const_lv32_1F = 32'b11111;
parameter ap_const_lv32_8 = 32'b1000;
parameter ap_const_lv24_0 = 24'b000000000000000000000000;
parameter ap_const_lv7_0 = 7'b0000000;
parameter ap_const_lv10_FF = 10'b11111111;
parameter ap_true = 1'b1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output ap_ready;
input [31:0] x0y0;
input [31:0] x1y0;
input [31:0] x2y0;
input [31:0] x0y1;
input [31:0] x1y1;
input [31:0] x2y1;
input [31:0] x0y2;
input [31:0] x1y2;
input [31:0] x2y2;
output [31:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
(* fsm_encoding = "none" *) reg [0:0] ap_CS_fsm = 1'b1;
reg ap_sig_cseq_ST_pp0_stg0_fsm_0;
reg ap_sig_bdd_17;
wire ap_reg_ppiten_pp0_it0;
reg ap_reg_ppiten_pp0_it1 = 1'b0;
reg ap_reg_ppiten_pp0_it2 = 1'b0;
reg ap_reg_ppiten_pp0_it3 = 1'b0;
reg ap_reg_ppiten_pp0_it4 = 1'b0;
reg ap_reg_ppiten_pp0_it5 = 1'b0;
reg ap_reg_ppiten_pp0_it6 = 1'b0;
reg ap_reg_ppiten_pp0_it7 = 1'b0;
reg [31:0] x2y2_read_reg_214;
reg [31:0] ap_reg_ppstg_x2y2_read_reg_214_pp0_it1;
reg [31:0] ap_reg_ppstg_x2y2_read_reg_214_pp0_it2;
reg [31:0] ap_reg_ppstg_x2y2_read_reg_214_pp0_it3;
reg [31:0] ap_reg_ppstg_x2y2_read_reg_214_pp0_it4;
reg [31:0] x1y2_read_reg_219;
reg [31:0] ap_reg_ppstg_x1y2_read_reg_219_pp0_it1;
reg [31:0] ap_reg_ppstg_x1y2_read_reg_219_pp0_it2;
reg [31:0] ap_reg_ppstg_x1y2_read_reg_219_pp0_it3;
reg [31:0] x0y2_read_reg_224;
reg [31:0] ap_reg_ppstg_x0y2_read_reg_224_pp0_it1;
reg [31:0] ap_reg_ppstg_x0y2_read_reg_224_pp0_it2;
reg [31:0] x2y1_read_reg_229;
reg [31:0] ap_reg_ppstg_x2y1_read_reg_229_pp0_it1;
reg [31:0] x1y1_read_reg_234;
wire [31:0] tmp1_fu_107_p2;
reg [31:0] tmp1_reg_239;
wire [31:0] tmp2_fu_113_p2;
reg [31:0] tmp2_reg_244;
wire [31:0] sum3_neg_fu_128_p2;
reg [31:0] sum3_neg_reg_249;
wire [31:0] tmp_1_fu_134_p2;
reg [31:0] tmp_1_reg_254;
wire [31:0] tmp_2_fu_138_p2;
reg [31:0] tmp_2_reg_259;
wire [31:0] tmp_3_fu_142_p2;
reg [31:0] tmp_3_reg_264;
wire [31:0] y_fu_146_p2;
reg [31:0] y_reg_269;
reg [31:0] ap_reg_ppstg_y_reg_269_pp0_it6;
reg [0:0] tmp_4_reg_274;
reg [0:0] ap_reg_ppstg_tmp_4_reg_274_pp0_it6;
reg [23:0] tmp_5_reg_279;
reg [0:0] tmp_6_reg_284;
reg [0:0] ap_reg_ppstg_tmp_6_reg_284_pp0_it6;
wire [0:0] icmp_fu_176_p2;
reg [0:0] icmp_reg_290;
wire [31:0] tmp_fu_119_p2;
wire [31:0] sum2_fu_124_p2;
wire [8:0] tmp_s_fu_181_p4;
wire signed [9:0] tmp_7_cast_fu_189_p1;
wire signed [9:0] tmp_8_fu_193_p2;
wire [0:0] tmp_9_fu_203_p2;
wire signed [31:0] tmp_8_cast_fu_199_p1;
reg [0:0] ap_NS_fsm;
reg ap_sig_pprstidle_pp0;
/// the current state (ap_CS_fsm) of the state machine. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_reg_ppiten_pp0_it1 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_0) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)))) begin
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end
end
end
/// ap_reg_ppiten_pp0_it2 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
end else begin
if (~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0))) begin
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end
end
end
/// ap_reg_ppiten_pp0_it3 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it3
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
end else begin
if (~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0))) begin
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end
end
end
/// ap_reg_ppiten_pp0_it4 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it4
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
end else begin
if (~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0))) begin
ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3;
end
end
end
/// ap_reg_ppiten_pp0_it5 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it5
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it5 <= ap_const_logic_0;
end else begin
if (~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0))) begin
ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4;
end
end
end
/// ap_reg_ppiten_pp0_it6 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it6
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it6 <= ap_const_logic_0;
end else begin
if (~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0))) begin
ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5;
end
end
end
/// ap_reg_ppiten_pp0_it7 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it7
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it7 <= ap_const_logic_0;
end else begin
if (~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0))) begin
ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0))) begin
ap_reg_ppstg_tmp_4_reg_274_pp0_it6 <= tmp_4_reg_274;
ap_reg_ppstg_tmp_6_reg_284_pp0_it6 <= tmp_6_reg_284;
ap_reg_ppstg_x0y2_read_reg_224_pp0_it2 <= ap_reg_ppstg_x0y2_read_reg_224_pp0_it1;
ap_reg_ppstg_x1y2_read_reg_219_pp0_it2 <= ap_reg_ppstg_x1y2_read_reg_219_pp0_it1;
ap_reg_ppstg_x1y2_read_reg_219_pp0_it3 <= ap_reg_ppstg_x1y2_read_reg_219_pp0_it2;
ap_reg_ppstg_x2y2_read_reg_214_pp0_it2 <= ap_reg_ppstg_x2y2_read_reg_214_pp0_it1;
ap_reg_ppstg_x2y2_read_reg_214_pp0_it3 <= ap_reg_ppstg_x2y2_read_reg_214_pp0_it2;
ap_reg_ppstg_x2y2_read_reg_214_pp0_it4 <= ap_reg_ppstg_x2y2_read_reg_214_pp0_it3;
ap_reg_ppstg_y_reg_269_pp0_it6 <= y_reg_269;
icmp_reg_290 <= icmp_fu_176_p2;
tmp_1_reg_254 <= tmp_1_fu_134_p2;
tmp_2_reg_259 <= tmp_2_fu_138_p2;
tmp_3_reg_264 <= tmp_3_fu_142_p2;
tmp_4_reg_274 <= y_fu_146_p2[ap_const_lv32_1F];
tmp_5_reg_279 <= {{y_fu_146_p2[ap_const_lv32_1F : ap_const_lv32_8]}};
tmp_6_reg_284 <= y_fu_146_p2[ap_const_lv32_1F];
y_reg_269 <= y_fu_146_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_0) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)))) begin
ap_reg_ppstg_x0y2_read_reg_224_pp0_it1 <= x0y2_read_reg_224;
ap_reg_ppstg_x1y2_read_reg_219_pp0_it1 <= x1y2_read_reg_219;
ap_reg_ppstg_x2y1_read_reg_229_pp0_it1 <= x2y1_read_reg_229;
ap_reg_ppstg_x2y2_read_reg_214_pp0_it1 <= x2y2_read_reg_214;
sum3_neg_reg_249 <= sum3_neg_fu_128_p2;
tmp1_reg_239 <= tmp1_fu_107_p2;
tmp2_reg_244 <= tmp2_fu_113_p2;
x0y2_read_reg_224 <= x0y2;
x1y1_read_reg_234 <= x1y1;
x1y2_read_reg_219 <= x1y2;
x2y1_read_reg_229 <= x2y1;
x2y2_read_reg_214 <= x2y2;
end
end
/// ap_done assign process. ///
always @ (ap_start or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it7)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_start or ap_sig_cseq_ST_pp0_stg0_fsm_0 or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppiten_pp0_it3 or ap_reg_ppiten_pp0_it4 or ap_reg_ppiten_pp0_it5 or ap_reg_ppiten_pp0_it6 or ap_reg_ppiten_pp0_it7)
begin
if ((~(ap_const_logic_1 == ap_start) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_0) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it0) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it1) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it2) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it3) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it4) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it5) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it6) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it7))) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// ap_ready assign process. ///
always @ (ap_start or ap_sig_cseq_ST_pp0_stg0_fsm_0 or ap_reg_ppiten_pp0_it0)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)))) begin
ap_ready = ap_const_logic_1;
end else begin
ap_ready = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_pp0_stg0_fsm_0 assign process. ///
always @ (ap_sig_bdd_17)
begin
if (ap_sig_bdd_17) begin
ap_sig_cseq_ST_pp0_stg0_fsm_0 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_pp0_stg0_fsm_0 = ap_const_logic_0;
end
end
/// ap_sig_pprstidle_pp0 assign process. ///
always @ (ap_start or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppiten_pp0_it3 or ap_reg_ppiten_pp0_it4 or ap_reg_ppiten_pp0_it5 or ap_reg_ppiten_pp0_it6)
begin
if (((ap_const_logic_0 == ap_reg_ppiten_pp0_it0) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it1) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it2) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it3) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it4) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it5) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it6) & (ap_const_logic_0 == ap_start))) begin
ap_sig_pprstidle_pp0 = ap_const_logic_1;
end else begin
ap_sig_pprstidle_pp0 = ap_const_logic_0;
end
end
/// the next state (ap_NS_fsm) of the state machine. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_sig_pprstidle_pp0)
begin
case (ap_CS_fsm)
ap_ST_pp0_stg0_fsm_0 :
begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_0;
end
default :
begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_reg_ppiten_pp0_it0 = ap_start;
assign ap_return = ((tmp_9_fu_203_p2)? tmp_8_cast_fu_199_p1: ap_reg_ppstg_y_reg_269_pp0_it6);
/// ap_sig_bdd_17 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_17 = (ap_CS_fsm[ap_const_lv32_0] == ap_const_lv1_1);
end
assign icmp_fu_176_p2 = ($signed(tmp_5_reg_279) > $signed(24'b000000000000000000000000)? 1'b1: 1'b0);
assign sum2_fu_124_p2 = (tmp2_reg_244 + tmp1_reg_239);
assign sum3_neg_fu_128_p2 = (tmp_fu_119_p2 - sum2_fu_124_p2);
assign tmp1_fu_107_p2 = (x1y0 + x0y0);
assign tmp2_fu_113_p2 = (x2y0 + x0y1);
assign tmp_1_fu_134_p2 = (sum3_neg_reg_249 - ap_reg_ppstg_x2y1_read_reg_229_pp0_it1);
assign tmp_2_fu_138_p2 = (tmp_1_reg_254 - ap_reg_ppstg_x0y2_read_reg_224_pp0_it2);
assign tmp_3_fu_142_p2 = (tmp_2_reg_259 - ap_reg_ppstg_x1y2_read_reg_219_pp0_it3);
assign tmp_7_cast_fu_189_p1 = $signed(tmp_s_fu_181_p4);
assign tmp_8_cast_fu_199_p1 = tmp_8_fu_193_p2;
assign tmp_8_fu_193_p2 = ($signed(tmp_7_cast_fu_189_p1) + $signed(ap_const_lv10_FF));
assign tmp_9_fu_203_p2 = (ap_reg_ppstg_tmp_4_reg_274_pp0_it6 | icmp_reg_290);
assign tmp_fu_119_p2 = x1y1_read_reg_234 << ap_const_lv32_3;
assign tmp_s_fu_181_p4 = {{{{ap_reg_ppstg_tmp_6_reg_284_pp0_it6}, {ap_const_lv7_0}}}, {ap_reg_ppstg_tmp_6_reg_284_pp0_it6}};
assign y_fu_146_p2 = (tmp_3_reg_264 - ap_reg_ppstg_x2y2_read_reg_214_pp0_it4);
endmodule //laplacian_filter
しかし、このリッチな構成でハードのHello World のLチカはできるのでしょうか?質問してみたところ、Verilog 部でやって下さいとのことでした。質問したのは、構成がリッチすぎて、ツールを使いはじめるための初心者用チュートリアルが思いつかなかったからです。メモリ抽象化フレームワークPyCoRAMを用いたソフトプロセッサ混載FPGAアクセラレータの開発
PyCoRAM: Python-Verilog高位合成とメモリ抽象化によるFPGAアクセラレータ向けIPコア開発フレームワーク (FPGAX #05)
PyCoRAMを用いたグラフ処理FPGAアクセラレータ
・User Logic は、カウンタを作ってLチカ用にクロックをカウントし、その1, 0 の出力をCoRAM Memory か CoRAM Stream でDRAM にWrite します。これがDMA Write 側です。
・カウンタのカウント値は変えられるようにして、最初は0.5秒間隔、次は、1秒間間隔とか、Lチカの点滅の間隔を変更します。
・次の間隔のLチカ点滅データは、前のLチカ点滅データとは別のメモリ領域にDMA します。前のLチカ点滅データのメモリ領域は現在のLチカのためにDMA Readされて使っているからです。(ダブル・バッファ)
・前にDMA Write されたLチカ点滅データのメモリ領域からDMA Read してLチカのLED出力とします。
・Pythonで書かれた制御部はダブル・バッファの管理やDMAの制御などの全体の制御を行います。
sudo: /usr/bin/sudo must be owned by uid 0 and have the setuid bit set
set_directive_pipeline "laplacian_filter"
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="laplacian_filter,hls_ip_2014_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z010clg400-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=pipeline,HLS_SYN_CLOCK=7.581000,HLS_SYN_LAT=2,HLS_SYN_TPT=1,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=227,HLS_SYN_LUT=297}" *)
module laplacian_filter (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
ap_ready,
x0y0,
x1y0,
x2y0,
x0y1,
x1y1,
x2y1,
x0y2,
x1y2,
x2y2,
ap_return
);
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_pp0_stg0_fsm_0 = 1'b1;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv1_1 = 1'b1;
parameter ap_const_lv32_3 = 32'b11;
parameter ap_const_lv32_1F = 32'b11111;
parameter ap_const_lv32_8 = 32'b1000;
parameter ap_const_lv24_0 = 24'b000000000000000000000000;
parameter ap_const_lv7_0 = 7'b0000000;
parameter ap_const_lv10_FF = 10'b11111111;
parameter ap_true = 1'b1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output ap_ready;
input [31:0] x0y0;
input [31:0] x1y0;
input [31:0] x2y0;
input [31:0] x0y1;
input [31:0] x1y1;
input [31:0] x2y1;
input [31:0] x0y2;
input [31:0] x1y2;
input [31:0] x2y2;
output [31:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
(* fsm_encoding = "none" *) reg [0:0] ap_CS_fsm = 1'b1;
reg ap_sig_cseq_ST_pp0_stg0_fsm_0;
reg ap_sig_bdd_17;
wire ap_reg_ppiten_pp0_it0;
reg ap_reg_ppiten_pp0_it1 = 1'b0;
reg ap_reg_ppiten_pp0_it2 = 1'b0;
reg [31:0] x2y2_read_reg_225;
reg [31:0] ap_reg_ppstg_x2y2_read_reg_225_pp0_it1;
reg [31:0] x1y2_read_reg_230;
reg [31:0] x0y2_read_reg_235;
reg [31:0] x2y1_read_reg_240;
wire [31:0] sum3_neg_fu_131_p2;
reg [31:0] sum3_neg_reg_245;
wire [31:0] tmp_3_fu_146_p2;
reg [31:0] tmp_3_reg_250;
wire [31:0] tmp2_fu_119_p2;
wire [31:0] tmp1_fu_113_p2;
wire [31:0] tmp_fu_107_p2;
wire [31:0] sum2_fu_125_p2;
wire [31:0] tmp_1_fu_137_p2;
wire [31:0] tmp_2_fu_141_p2;
wire [31:0] y_fu_151_p2;
wire [23:0] tmp_5_fu_163_p4;
wire [0:0] tmp_6_fu_179_p3;
wire [8:0] tmp_s_fu_187_p4;
wire signed [9:0] tmp_7_cast_fu_197_p1;
wire signed [9:0] tmp_8_fu_201_p2;
wire [0:0] tmp_4_fu_155_p3;
wire [0:0] icmp_fu_173_p2;
wire [0:0] tmp_9_fu_211_p2;
wire signed [31:0] tmp_8_cast_fu_207_p1;
reg [0:0] ap_NS_fsm;
reg ap_sig_pprstidle_pp0;
/// the current state (ap_CS_fsm) of the state machine. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_reg_ppiten_pp0_it1 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_0) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)))) begin
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end
end
end
/// ap_reg_ppiten_pp0_it2 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
end else begin
if (~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0))) begin
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_0) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)))) begin
ap_reg_ppstg_x2y2_read_reg_225_pp0_it1 <= x2y2_read_reg_225;
sum3_neg_reg_245 <= sum3_neg_fu_131_p2;
tmp_3_reg_250 <= tmp_3_fu_146_p2;
x0y2_read_reg_235 <= x0y2;
x1y2_read_reg_230 <= x1y2;
x2y1_read_reg_240 <= x2y1;
x2y2_read_reg_225 <= x2y2;
end
end
/// ap_done assign process. ///
always @ (ap_start or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it2)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_start or ap_sig_cseq_ST_pp0_stg0_fsm_0 or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2)
begin
if ((~(ap_const_logic_1 == ap_start) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_0) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it0) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it1) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it2))) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// ap_ready assign process. ///
always @ (ap_start or ap_sig_cseq_ST_pp0_stg0_fsm_0 or ap_reg_ppiten_pp0_it0)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)))) begin
ap_ready = ap_const_logic_1;
end else begin
ap_ready = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_pp0_stg0_fsm_0 assign process. ///
always @ (ap_sig_bdd_17)
begin
if (ap_sig_bdd_17) begin
ap_sig_cseq_ST_pp0_stg0_fsm_0 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_pp0_stg0_fsm_0 = ap_const_logic_0;
end
end
/// ap_sig_pprstidle_pp0 assign process. ///
always @ (ap_start or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1)
begin
if (((ap_const_logic_0 == ap_reg_ppiten_pp0_it0) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it1) & (ap_const_logic_0 == ap_start))) begin
ap_sig_pprstidle_pp0 = ap_const_logic_1;
end else begin
ap_sig_pprstidle_pp0 = ap_const_logic_0;
end
end
/// the next state (ap_NS_fsm) of the state machine. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_sig_pprstidle_pp0)
begin
case (ap_CS_fsm)
ap_ST_pp0_stg0_fsm_0 :
begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_0;
end
default :
begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_reg_ppiten_pp0_it0 = ap_start;
assign ap_return = ((tmp_9_fu_211_p2)? tmp_8_cast_fu_207_p1: y_fu_151_p2);
/// ap_sig_bdd_17 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_17 = (ap_CS_fsm[ap_const_lv32_0] == ap_const_lv1_1);
end
assign icmp_fu_173_p2 = ($signed(tmp_5_fu_163_p4) > $signed(24'b000000000000000000000000)? 1'b1: 1'b0);
assign sum2_fu_125_p2 = (tmp2_fu_119_p2 + tmp1_fu_113_p2);
assign sum3_neg_fu_131_p2 = (tmp_fu_107_p2 - sum2_fu_125_p2);
assign tmp1_fu_113_p2 = (x1y0 + x0y0);
assign tmp2_fu_119_p2 = (x2y0 + x0y1);
assign tmp_1_fu_137_p2 = (sum3_neg_reg_245 - x2y1_read_reg_240);
assign tmp_2_fu_141_p2 = (tmp_1_fu_137_p2 - x0y2_read_reg_235);
assign tmp_3_fu_146_p2 = (tmp_2_fu_141_p2 - x1y2_read_reg_230);
assign tmp_4_fu_155_p3 = y_fu_151_p2[ap_const_lv32_1F];
assign tmp_5_fu_163_p4 = {{y_fu_151_p2[ap_const_lv32_1F : ap_const_lv32_8]}};
assign tmp_6_fu_179_p3 = y_fu_151_p2[ap_const_lv32_1F];
assign tmp_7_cast_fu_197_p1 = $signed(tmp_s_fu_187_p4);
assign tmp_8_cast_fu_207_p1 = tmp_8_fu_201_p2;
assign tmp_8_fu_201_p2 = ($signed(tmp_7_cast_fu_197_p1) + $signed(ap_const_lv10_FF));
assign tmp_9_fu_211_p2 = (tmp_4_fu_155_p3 | icmp_fu_173_p2);
assign tmp_fu_107_p2 = x1y1 << ap_const_lv32_3;
assign tmp_s_fu_187_p4 = {{{{tmp_6_fu_179_p3}, {ap_const_lv7_0}}}, {tmp_6_fu_179_p3}};
assign y_fu_151_p2 = (tmp_3_reg_250 - ap_reg_ppstg_x2y2_read_reg_225_pp0_it1);
endmodule //laplacian_filter
set_directive_latency -min 1 -max 1 "laplacian_filter"
/ ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="laplacian_filter,hls_ip_2014_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z010clg400-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=12.461000,HLS_SYN_LAT=1,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=34,HLS_SYN_LUT=298}" *)
module laplacian_filter (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
ap_ready,
x0y0,
x1y0,
x2y0,
x0y1,
x1y1,
x2y1,
x0y2,
x1y2,
x2y2,
ap_return
);
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st1_fsm_0 = 2'b1;
parameter ap_ST_st2_fsm_1 = 2'b10;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv1_1 = 1'b1;
parameter ap_const_lv32_1 = 32'b1;
parameter ap_const_lv32_3 = 32'b11;
parameter ap_const_lv32_1F = 32'b11111;
parameter ap_const_lv32_8 = 32'b1000;
parameter ap_const_lv24_0 = 24'b000000000000000000000000;
parameter ap_const_lv7_0 = 7'b0000000;
parameter ap_const_lv10_FF = 10'b11111111;
parameter ap_true = 1'b1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output ap_ready;
input [31:0] x0y0;
input [31:0] x1y0;
input [31:0] x2y0;
input [31:0] x0y1;
input [31:0] x1y1;
input [31:0] x2y1;
input [31:0] x0y2;
input [31:0] x1y2;
input [31:0] x2y2;
output [31:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
(* fsm_encoding = "none" *) reg [1:0] ap_CS_fsm = 2'b1;
reg ap_sig_cseq_ST_st1_fsm_0;
reg ap_sig_bdd_18;
wire [31:0] tmp_1_fu_137_p2;
reg [31:0] tmp_1_reg_230;
reg ap_sig_cseq_ST_st2_fsm_1;
reg ap_sig_bdd_52;
wire [31:0] tmp2_fu_119_p2;
wire [31:0] tmp1_fu_113_p2;
wire [31:0] tmp_fu_107_p2;
wire [31:0] sum2_fu_125_p2;
wire [31:0] sum3_neg_fu_131_p2;
wire [31:0] tmp_2_fu_143_p2;
wire [31:0] tmp_3_fu_148_p2;
wire [31:0] y_fu_154_p2;
wire [23:0] tmp_5_fu_168_p4;
wire [0:0] tmp_6_fu_184_p3;
wire [8:0] tmp_s_fu_192_p4;
wire signed [9:0] tmp_7_cast_fu_202_p1;
wire signed [9:0] tmp_8_fu_206_p2;
wire [0:0] tmp_4_fu_160_p3;
wire [0:0] icmp_fu_178_p2;
wire [0:0] tmp_9_fu_216_p2;
wire signed [31:0] tmp_8_cast_fu_212_p1;
reg [1:0] ap_NS_fsm;
/// the current state (ap_CS_fsm) of the state machine. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st1_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~(ap_start == ap_const_logic_0))) begin
tmp_1_reg_230 <= tmp_1_fu_137_p2;
end
end
/// ap_done assign process. ///
always @ (ap_sig_cseq_ST_st2_fsm_1)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1)) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_start or ap_sig_cseq_ST_st1_fsm_0)
begin
if ((~(ap_const_logic_1 == ap_start) & (ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0))) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// ap_ready assign process. ///
always @ (ap_sig_cseq_ST_st2_fsm_1)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1)) begin
ap_ready = ap_const_logic_1;
end else begin
ap_ready = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st1_fsm_0 assign process. ///
always @ (ap_sig_bdd_18)
begin
if (ap_sig_bdd_18) begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st2_fsm_1 assign process. ///
always @ (ap_sig_bdd_52)
begin
if (ap_sig_bdd_52) begin
ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_0;
end
end
/// the next state (ap_NS_fsm) of the state machine. ///
always @ (ap_start or ap_CS_fsm)
begin
case (ap_CS_fsm)
ap_ST_st1_fsm_0 :
begin
if (~(ap_start == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end else begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end
end
ap_ST_st2_fsm_1 :
begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end
default :
begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_return = ((tmp_9_fu_216_p2)? tmp_8_cast_fu_212_p1: y_fu_154_p2);
/// ap_sig_bdd_18 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_18 = (ap_CS_fsm[ap_const_lv32_0] == ap_const_lv1_1);
end
/// ap_sig_bdd_52 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_52 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_1]);
end
assign icmp_fu_178_p2 = ($signed(tmp_5_fu_168_p4) > $signed(24'b000000000000000000000000)? 1'b1: 1'b0);
assign sum2_fu_125_p2 = (tmp2_fu_119_p2 + tmp1_fu_113_p2);
assign sum3_neg_fu_131_p2 = (tmp_fu_107_p2 - sum2_fu_125_p2);
assign tmp1_fu_113_p2 = (x1y0 + x0y0);
assign tmp2_fu_119_p2 = (x2y0 + x0y1);
assign tmp_1_fu_137_p2 = (sum3_neg_fu_131_p2 - x2y1);
assign tmp_2_fu_143_p2 = (tmp_1_reg_230 - x0y2);
assign tmp_3_fu_148_p2 = (tmp_2_fu_143_p2 - x1y2);
assign tmp_4_fu_160_p3 = y_fu_154_p2[ap_const_lv32_1F];
assign tmp_5_fu_168_p4 = {{y_fu_154_p2[ap_const_lv32_1F : ap_const_lv32_8]}};
assign tmp_6_fu_184_p3 = y_fu_154_p2[ap_const_lv32_1F];
assign tmp_7_cast_fu_202_p1 = $signed(tmp_s_fu_192_p4);
assign tmp_8_cast_fu_212_p1 = tmp_8_fu_206_p2;
assign tmp_8_fu_206_p2 = ($signed(tmp_7_cast_fu_202_p1) + $signed(ap_const_lv10_FF));
assign tmp_9_fu_216_p2 = (tmp_4_fu_160_p3 | icmp_fu_178_p2);
assign tmp_fu_107_p2 = x1y1 << ap_const_lv32_3;
assign tmp_s_fu_192_p4 = {{{{tmp_6_fu_184_p3}, {ap_const_lv7_0}}}, {tmp_6_fu_184_p3}};
assign y_fu_154_p2 = (tmp_3_fu_148_p2 - x2y2);
endmodule //laplacian_filter
と記述されていた。assign tmp2_fu_113_p2 = (x2y0 + x0y1);
`default_nettype none
`timescale 100ps / 1ps
//
// laplacian_filter_tb.v
// 2015/01/13
//
module laplacian_filter_tb;
parameter DELAY = 1;
parameter LAP_FILTER_END_COUNT = 3;
wire ap_clk; // input
wire ap_rst; // input
reg ap_start; // input
wire ap_done;
wire ap_idle;
wire ap_ready;
reg [31:0] x0y0;
reg [31:0] x1y0;
reg [31:0] x2y0;
reg [31:0] x0y1;
reg [31:0] x1y1;
reg [31:0] x2y1;
reg [31:0] x0y2;
reg [31:0] x1y2;
reg [31:0] x2y2;
wire [31:0] ap_return;
integer i;
laplacian_filter uut (
.ap_clk(ap_clk),
.ap_rst(ap_rst),
.ap_start(ap_start),
.ap_done(ap_done),
.ap_idle(ap_idle),
.ap_ready(ap_ready),
.x0y0(x0y0),
.x1y0(x1y0),
.x2y0(x2y0),
.x0y1(x0y1),
.x1y1(x1y1),
.x2y1(x2y1),
.x0y2(x0y2),
.x1y2(x1y2),
.x2y2(x2y2),
.ap_return(ap_return)
);
// clk_gen のインスタンス(ap_clk)
clk_gen #(
.CLK_PERIOD(100), // 10nsec, 100MHz
.CLK_DUTY_CYCLE(0.5),
.CLK_OFFSET(0),
.START_STATE(1'b0)
) ACLKi (
.clk_out(ap_clk)
);
// reset_gen のインスタンス
reset_gen #(
.RESET_STATE(1'b1),
.RESET_TIME(1000) // 100nsec
) RESET_ARESETN (
.reset_out(ap_rst),
.init_done()
);
initial begin
// Initialize Inputs
ap_start = 1'b0;
x0y0 = 32'd0;
x1y0 = 32'd0;
x2y0 = 32'd0;
x0y1 = 32'd0;
x1y1 = 32'd0;
x2y1 = 32'd0;
x0y2 = 32'd0;
x1y2 = 32'd0;
x2y2 = 32'd0;
// Wait until Reset falling edge
@(negedge ap_rst);
#1000; // 100 ns Wait
@(posedge ap_clk); // 次のクロックへ
#DELAY;
ap_start = 1'b1;
x0y0 = 32'd127;
x1y0 = 32'd127;
x2y0 = 32'd127;
x0y1 = 32'd127;
x1y1 = 32'd127;
x2y1 = 32'd127;
x0y2 = 32'd0;
x1y2 = 32'd0;
x2y2 = 32'd0;
@(posedge ap_clk); // 次のクロックへ
#DELAY;
ap_start = 1'b0;
for (i=0; i<LAP_FILTER_END_COUNT; i=i+1) begin // laplacian_filter の終了を待つ
@(posedge ap_clk); // 次のクロックへ
#DELAY;
end
ap_start = 1'b1;
x0y0 = 32'd127;
x1y0 = 32'd127;
x2y0 = 32'd127;
x0y1 = 32'd127;
x1y1 = 32'd81;
x2y1 = 32'd127;
x0y2 = 32'd0;
x1y2 = 32'd0;
x2y2 = 32'd0;
@(posedge ap_clk); // 次のクロックへ
#DELAY;
ap_start = 1'b0;
for (i=0; i<LAP_FILTER_END_COUNT; i=i+1) begin // laplacian_filter の終了を待つ
@(posedge ap_clk); // 次のクロックへ
#DELAY;
end
end
endmodule
module clk_gen #(
parameter CLK_PERIOD = 100,
parameter real CLK_DUTY_CYCLE = 0.5,
parameter CLK_OFFSET = 0,
parameter START_STATE = 1'b0 )
(
output reg clk_out
);
begin
initial begin
#CLK_OFFSET;
forever
begin
clk_out = START_STATE;
#(CLK_PERIOD-(CLK_PERIOD*CLK_DUTY_CYCLE)) clk_out = ~START_STATE;
#(CLK_PERIOD*CLK_DUTY_CYCLE);
end
end
end
endmodule
module reset_gen #(
parameter RESET_STATE = 1'b1,
parameter RESET_TIME = 100 )
(
output reg reset_out,
output reg init_done
);
begin
initial begin
reset_out = RESET_STATE;
init_done = 1'b0;
#RESET_TIME;
reset_out = ~RESET_STATE;
init_done = 1'b1;
end
end
endmodule
`default_nettype wire
// ラプラシアンフィルタ
// x0y0 x1y0 x2y0 -1 -1 -1
// x0y1 x1y1 x2y1 -1 8 -1
// x0y2 x1y2 x2y2 -1 -1 -1
int laplacian_filter(int x0y0, int x1y0, int x2y0, int x0y1, int x1y1, int x2y1, int x0y2, int x1y2, int x2y2)
{
int y;
y = -x0y0 -x1y0 -x2y0 -x0y1 +8*x1y1 -x2y1 -x0y2 -x1y2 -x2y2;
if (y<0)
y = 0;
else if (y>255)
y = 255;
return(y);
}
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="laplacian_filter,hls_ip_2014_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z010clg400-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=7.581000,HLS_SYN_LAT=2,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=67,HLS_SYN_LUT=298}" *)
module laplacian_filter (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
ap_ready,
x0y0,
x1y0,
x2y0,
x0y1,
x1y1,
x2y1,
x0y2,
x1y2,
x2y2,
ap_return
);
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st1_fsm_0 = 3'b1;
parameter ap_ST_st2_fsm_1 = 3'b10;
parameter ap_ST_st3_fsm_2 = 3'b100;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv1_1 = 1'b1;
parameter ap_const_lv32_1 = 32'b1;
parameter ap_const_lv32_2 = 32'b10;
parameter ap_const_lv32_3 = 32'b11;
parameter ap_const_lv32_1F = 32'b11111;
parameter ap_const_lv32_8 = 32'b1000;
parameter ap_const_lv24_0 = 24'b000000000000000000000000;
parameter ap_const_lv7_0 = 7'b0000000;
parameter ap_const_lv10_FF = 10'b11111111;
parameter ap_true = 1'b1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output ap_ready;
input [31:0] x0y0;
input [31:0] x1y0;
input [31:0] x2y0;
input [31:0] x0y1;
input [31:0] x1y1;
input [31:0] x2y1;
input [31:0] x0y2;
input [31:0] x1y2;
input [31:0] x2y2;
output [31:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
(* fsm_encoding = "none" *) reg [2:0] ap_CS_fsm = 3'b1;
reg ap_sig_cseq_ST_st1_fsm_0;
reg ap_sig_bdd_19;
wire [31:0] sum3_neg_fu_125_p2;
reg [31:0] sum3_neg_reg_223;
wire [31:0] tmp_3_fu_142_p2;
reg [31:0] tmp_3_reg_228;
reg ap_sig_cseq_ST_st2_fsm_1;
reg ap_sig_bdd_48;
reg ap_sig_cseq_ST_st3_fsm_2;
reg ap_sig_bdd_64;
wire [31:0] tmp2_fu_113_p2;
wire [31:0] tmp1_fu_107_p2;
wire [31:0] tmp_fu_101_p2;
wire [31:0] sum2_fu_119_p2;
wire [31:0] tmp_1_fu_131_p2;
wire [31:0] tmp_2_fu_136_p2;
wire [31:0] y_fu_148_p2;
wire [23:0] tmp_5_fu_161_p4;
wire [0:0] tmp_6_fu_177_p3;
wire [8:0] tmp_s_fu_185_p4;
wire signed [9:0] tmp_7_cast_fu_195_p1;
wire signed [9:0] tmp_8_fu_199_p2;
wire [0:0] tmp_4_fu_153_p3;
wire [0:0] icmp_fu_171_p2;
wire [0:0] tmp_9_fu_209_p2;
wire signed [31:0] tmp_8_cast_fu_205_p1;
reg [2:0] ap_NS_fsm;
/// the current state (ap_CS_fsm) of the state machine. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st1_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~(ap_start == ap_const_logic_0))) begin
sum3_neg_reg_223 <= sum3_neg_fu_125_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1)) begin
tmp_3_reg_228 <= tmp_3_fu_142_p2;
end
end
/// ap_done assign process. ///
always @ (ap_sig_cseq_ST_st3_fsm_2)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2)) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_start or ap_sig_cseq_ST_st1_fsm_0)
begin
if ((~(ap_const_logic_1 == ap_start) & (ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0))) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// ap_ready assign process. ///
always @ (ap_sig_cseq_ST_st3_fsm_2)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2)) begin
ap_ready = ap_const_logic_1;
end else begin
ap_ready = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st1_fsm_0 assign process. ///
always @ (ap_sig_bdd_19)
begin
if (ap_sig_bdd_19) begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st2_fsm_1 assign process. ///
always @ (ap_sig_bdd_48)
begin
if (ap_sig_bdd_48) begin
ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st3_fsm_2 assign process. ///
always @ (ap_sig_bdd_64)
begin
if (ap_sig_bdd_64) begin
ap_sig_cseq_ST_st3_fsm_2 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st3_fsm_2 = ap_const_logic_0;
end
end
/// the next state (ap_NS_fsm) of the state machine. ///
always @ (ap_start or ap_CS_fsm)
begin
case (ap_CS_fsm)
ap_ST_st1_fsm_0 :
begin
if (~(ap_start == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end else begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end
end
ap_ST_st2_fsm_1 :
begin
ap_NS_fsm = ap_ST_st3_fsm_2;
end
ap_ST_st3_fsm_2 :
begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end
default :
begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_return = ((tmp_9_fu_209_p2)? tmp_8_cast_fu_205_p1: y_fu_148_p2);
/// ap_sig_bdd_19 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_19 = (ap_CS_fsm[ap_const_lv32_0] == ap_const_lv1_1);
end
/// ap_sig_bdd_48 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_48 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_1]);
end
/// ap_sig_bdd_64 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_64 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_2]);
end
assign icmp_fu_171_p2 = ($signed(tmp_5_fu_161_p4) > $signed(24'b000000000000000000000000)? 1'b1: 1'b0);
assign sum2_fu_119_p2 = (tmp2_fu_113_p2 + tmp1_fu_107_p2);
assign sum3_neg_fu_125_p2 = (tmp_fu_101_p2 - sum2_fu_119_p2);
assign tmp1_fu_107_p2 = (x1y0 + x0y0);
assign tmp2_fu_113_p2 = (x2y0 + x0y1);
assign tmp_1_fu_131_p2 = (sum3_neg_reg_223 - x2y1);
assign tmp_2_fu_136_p2 = (tmp_1_fu_131_p2 - x0y2);
assign tmp_3_fu_142_p2 = (tmp_2_fu_136_p2 - x1y2);
assign tmp_4_fu_153_p3 = y_fu_148_p2[ap_const_lv32_1F];
assign tmp_5_fu_161_p4 = {{y_fu_148_p2[ap_const_lv32_1F : ap_const_lv32_8]}};
assign tmp_6_fu_177_p3 = y_fu_148_p2[ap_const_lv32_1F];
assign tmp_7_cast_fu_195_p1 = $signed(tmp_s_fu_185_p4);
assign tmp_8_cast_fu_205_p1 = tmp_8_fu_199_p2;
assign tmp_8_fu_199_p2 = ($signed(tmp_7_cast_fu_195_p1) + $signed(ap_const_lv10_FF));
assign tmp_9_fu_209_p2 = (tmp_4_fu_153_p3 | icmp_fu_171_p2);
assign tmp_fu_101_p2 = x1y1 << ap_const_lv32_3;
assign tmp_s_fu_185_p4 = {{{{tmp_6_fu_177_p3}, {ap_const_lv7_0}}}, {tmp_6_fu_177_p3}};
assign y_fu_148_p2 = (tmp_3_reg_228 - x2y2);
endmodule //laplacian_filter
void foo(int in[3], char a, char b, char c, int out[3]) {
int x,y;
for(int i = 0; i < 3; i++) {
x = in[i];
y = a*x + b + c;
out[i] = y;
}
}
`default_nettype none
`timescale 100ps / 1ps
//
// foo_tb.v
// 2015/01/10
//
module foo_tb;
parameter DELAY = 1;
wire ap_clk; // input
wire ap_rst; // input
reg ap_start; // input
wire ap_done;
wire ap_idle;
wire ap_ready;
wire [1:0] in_r_address0;
wire in_r_ce0;
wire [31:0] in_r_q0; // input
reg [7:0] a; // input
reg [7:0] b; // input
reg [7:0] c; // input
wire [1:0] out_r_address0;
wire out_r_ce0;
wire out_r_we0;
wire [31:0] out_r_d0;
foo uut (
.ap_clk(ap_clk),
.ap_rst(ap_rst),
.ap_start(ap_start),
.ap_done(ap_done),
.ap_idle(ap_idle),
.ap_ready(ap_ready),
.in_r_address0(in_r_address0),
.in_r_ce0(in_r_ce0),
.in_r_q0(in_r_q0),
.a(a),
.b(b),
.c(c),
.out_r_address0(out_r_address0),
.out_r_ce0(out_r_ce0),
.out_r_we0(out_r_we0),
.out_r_d0(out_r_d0)
);
Single_Prot_BRAM_Model #(
.C_MEMORY_SIZE(4), // Word (not byte), 2^n
.DATA_BUS_WIDTH(32) // RAM Data Width
) spbm_read (
.clk(ap_clk),
.rst(ap_rst),
.addr(in_r_address0),
.ce(in_r_ce0),
.we(1'b0),
.din(0),
.dout(in_r_q0)
);
Single_Prot_BRAM_Model #(
.C_MEMORY_SIZE(4), // Word (not byte), 2^n
.DATA_BUS_WIDTH(32) // RAM Data Width
) spbm_write (
.clk(ap_clk),
.rst(ap_rst),
.addr(out_r_address0),
.ce(out_r_ce0),
.we(out_r_we0),
.din(out_r_d0),
.dout()
);
// clk_gen のインスタンス(ap_clk)
clk_gen #(
.CLK_PERIOD(100), // 10nsec, 100MHz
.CLK_DUTY_CYCLE(0.5),
.CLK_OFFSET(0),
.START_STATE(1'b0)
) ACLKi (
.clk_out(ap_clk)
);
// reset_gen のインスタンス
reset_gen #(
.RESET_STATE(1'b1),
.RESET_TIME(1000) // 100nsec
) RESET_ARESETN (
.reset_out(ap_rst),
.init_done()
);
initial begin
// Initialize Inputs
ap_start = 1'b0;
a = 8'd0;
b = 8'd0;
c = 8'd0;
// Wait until Reset falling edge
@(negedge ap_rst);
#1000; // 100 ns Wait
@(posedge ap_clk); // 次のクロックへ
#DELAY;
ap_start = 1'b1;
a = 8'd2;
b = 8'd3;
c = 8'd4;
@(posedge ap_clk); // 次のクロックへ
#DELAY;
ap_start = 1'b0;
end
endmodule
module clk_gen #(
parameter CLK_PERIOD = 100,
parameter real CLK_DUTY_CYCLE = 0.5,
parameter CLK_OFFSET = 0,
parameter START_STATE = 1'b0 )
(
output reg clk_out
);
begin
initial begin
#CLK_OFFSET;
forever
begin
clk_out = START_STATE;
#(CLK_PERIOD-(CLK_PERIOD*CLK_DUTY_CYCLE)) clk_out = ~START_STATE;
#(CLK_PERIOD*CLK_DUTY_CYCLE);
end
end
end
endmodule
module reset_gen #(
parameter RESET_STATE = 1'b1,
parameter RESET_TIME = 100 )
(
output reg reset_out,
output reg init_done
);
begin
initial begin
reset_out = RESET_STATE;
init_done = 1'b0;
#RESET_TIME;
reset_out = ~RESET_STATE;
init_done = 1'b1;
end
end
endmodule
`default_nettype wire
//
// Initializing Single Port BlockRAM from internal data file
// Single_port_BRAM_Model.v
// 2015/01/10
//
`default_nettype none
module Single_Prot_BRAM_Model # (
parameter integer C_MEMORY_SIZE = 4, // Word (not byte), 2^n
parameter integer DATA_BUS_WIDTH = 32 // RAM Data Width
)(
input wire clk,
input wire rst,
input wire [log2(C_MEMORY_SIZE)-1 : 0] addr,
input wire ce,
input wire we,
input wire [DATA_BUS_WIDTH-1 : 0] din,
output reg [DATA_BUS_WIDTH-1 : 0] dout
);
// Beyond Circuts, Constant Function in Verilog 2001を参照しました
// http://www.beyond-circuits.com/wordpress/2008/11/constant-functions/
function integer log2;
input integer addr;
begin
addr = addr - 1;
for (log2=0; addr>0; log2=log2+1)
addr = addr >> 1;
end
endfunction
reg [DATA_BUS_WIDTH-1:0] mem [0:C_MEMORY_SIZE-1];
integer i;
initial begin
for (i=0; i<C_MEMORY_SIZE; i=i+1)
mem[i] = i;
end
always @(posedge clk) begin
if (rst) begin
dout <= 0;
end else begin
if (we & ce)
mem[addr] <= din;
if (ce)
dout <= mem[addr];
end
end
endmodule
`default_nettype wire
void foo(int in[3], char a, char b, char c, int out[3]) {
int x,y;
for(int i = 0; i < 3; i++) {
x = in[i];
y = a*x + b + c;
out[i] = y;
}
}
int foo(char x, char a, char b, char c) {
char y;
y = x*a+b+c;
return y;
}
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="foo,hls_ip_2014_4,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z010clg400-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=6.380000,HLS_SYN_LAT=0,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=1,HLS_SYN_FF=0,HLS_SYN_LUT=8}" *)
module foo (
ap_start,
ap_done,
ap_idle,
ap_ready,
x,
a,
b,
c,
ap_return
);
parameter ap_const_logic_1 = 1'b1;
parameter ap_true = 1'b1;
parameter ap_const_logic_0 = 1'b0;
input ap_start;
output ap_done;
output ap_idle;
output ap_ready;
input [7:0] x;
input [7:0] a;
input [7:0] b;
input [7:0] c;
output [31:0] ap_return;
wire signed [7:0] tmp_fu_43_p0;
wire signed [7:0] tmp_fu_43_p1;
(* use_dsp48 = "no" *) wire [7:0] tmp1_fu_49_p2;
wire signed [7:0] tmp_fu_43_p2;
wire signed [7:0] y_fu_55_p2;
assign ap_done = ap_start;
assign ap_idle = ap_const_logic_1;
assign ap_ready = ap_start;
assign ap_return = $signed(y_fu_55_p2);
assign tmp1_fu_49_p2 = (b + c);
assign tmp_fu_43_p0 = a;
assign tmp_fu_43_p1 = x;
assign tmp_fu_43_p2 = ($signed(tmp_fu_43_p0) * $signed(tmp_fu_43_p1));
assign y_fu_55_p2 = ($signed(tmp1_fu_49_p2) + $signed(tmp_fu_43_p2));
endmodule //foo
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity foo is
port (
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
x : IN STD_LOGIC_VECTOR (7 downto 0);
a : IN STD_LOGIC_VECTOR (7 downto 0);
b : IN STD_LOGIC_VECTOR (7 downto 0);
c : IN STD_LOGIC_VECTOR (7 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of foo is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"foo,hls_ip_2014_4,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z010clg400-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=6.380000,HLS_SYN_LAT=0,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=1,HLS_SYN_FF=0,HLS_SYN_LUT=8}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_true : BOOLEAN := true;
constant ap_const_logic_0 : STD_LOGIC := '0';
signal tmp_fu_43_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_fu_43_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp1_fu_49_p2 : STD_LOGIC_VECTOR (7 downto 0);
attribute use_dsp48 : string;
attribute use_dsp48 of tmp1_fu_49_p2 : signal is "no";
signal tmp_fu_43_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal y_fu_55_p2 : STD_LOGIC_VECTOR (7 downto 0);
begin
ap_done <= ap_start;
ap_idle <= ap_const_logic_1;
ap_ready <= ap_start;
ap_return <= std_logic_vector(resize(signed(y_fu_55_p2),32));
tmp1_fu_49_p2 <= std_logic_vector(unsigned(b) + unsigned(c));
tmp_fu_43_p0 <= a;
tmp_fu_43_p1 <= x;
tmp_fu_43_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed(tmp_fu_43_p0) * signed(tmp_fu_43_p1))), 8));
y_fu_55_p2 <= std_logic_vector(unsigned(tmp1_fu_49_p2) + unsigned(tmp_fu_43_p2));
end behav;
int foo(char x, char a, char b, char c) {
char y;
y = x*a+b+c;
return y;
}
void foo(int in[3], char a, char b, char c, int out[3]) {
int x,y;
for(int i = 0; i < 3; i++) {
x = in[i];
y = a*x + b + c;
out[i] = y;
}
}
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