mt9d111_axi_iic@0x41600000 {compatible = "generic-uio";reg = < 0x41600000 0x10000>;};axi_vdma_0@43000000 {compatible = "generic-uio";reg = < 0x43000000 0x10000 >;};axis_switch_0@0x43c10000 {compatible = "generic-uio";reg = < 0x43c10000 0x10000 >;};axis_switch_1@0x43c20000 {compatible = "generic-uio";reg = < 0x43c20000 0x10000 >;};lap_filter_axis_0@0x43c30000 {compatible = "generic-uio";reg = < 0x43c30000 0x10000>;};mt9d111_inf_axis_0@0x43C40000 {compatible = "generic-uio";reg = < 0x43C40000 0x10000>;};bitmap_disp_cntrler_axi_master_0@0x43c00000 {compatible = "generic-uio";reg = < 0x43c00000 0x10000>;};bitmap_disp_cntrler_axi_master_1@0x43c50000 {compatible = "generic-uio";reg = < 0x43c50000 0x10000>;};axi_gpio_0@0x41200000 {compatible = "generic-uio";reg = < 0x41200000 0x10000>;};frame_buffer_bmdc@0x17800000 {compatible = "generic-uio";reg = < 0x17800000 0x1000000>;};
Vivado® Design Suite 2015.4 リ リ ースか ら、高位合成ツールであ る Vivado HLS が無償で提供 される よ う にな り 、Vivado のすべてのエデ ィ シ ョ ンに含まれる よ う にな り ま し た。 この変更を示すため、 エデ ィ シ ョ ンの名前は Vivado Design Suite HLx Edition に変更 されています。HLx Edition には、HL System Edition、HL Design Edition、および HL WebPACK™ Edition があ り ます。 これ らのエデ ィ シ ョ ンでは、 All Programmable FPGA、 SoC、 および再利用可能なプ ラ ッ ト フ ォーム を高い生産性で設計する ための新しい手法が イ ネーブルになっています。 すべての HLx エデ ィ シ ョ ンには Vivado 高位合成 (HLS)、 Vivado IP イ ンテグ レーター、 LogicCore IP サブシステム、 および Vivado インプ リ メ ンテーシ ョ ン ツール ス イー ト すべてが含まれてお り 、 生産性が高 く 、 高度な C および IP ベースのデザイ ン フ ローを即座に導入でき る よ う になっています。
// cam_lap_disp.c
// 2015/11/25 by marsee
//
// Refered to Xilinx\SDK\2015.1\data\embeddedsw\XilinxProcessorIPLib\drivers\axivdma_v5_1\doc\html\api
// Refered to https://github.com/elitezhe/Atyls-VDMA-one-in-one-out/blob/master/SDK/colorbar/src/helloworld.c
// Refered to http://www.xilinx.com/support/documentation/ip_documentation/axi_vdma/v6_2/pg020_axi_vdma.pdf
// Refered to http://forums.xilinx.com/t5/Embedded-Processor-System-Design/Axi-VDMA-on-Digilent-Atlys/td-p/297019/page/2
//
// if sw0 is 0 level then normal camera out else laplacian filter out
//
#include <stdio.h>
#include <stdlib.h>
#include "xaxivdma.h"
#include "xil_io.h"
#include "xparameters.h"
#include "sleep.h"
#include "xgpio.h"
#include "xlap_filter_axis.h"
#define NUMBER_OF_WRITE_FRAMES 3 // Note: If not at least 3 or more, the image is not displayed in succession.
#define HORIZONTAL_PIXELS 800
#define VERTICAL_LINES 600
#define PIXEL_NUM_OF_BYTES 4
#define FRAME_BUFFER_ADDRESS 0x10000000
static XAxiVdma_DmaSetup Vdma0_WriteCfg;
void camera_out(XLap_filter_axis Xlap_fil_axis);
void lap_fil_out(XLap_filter_axis Xlap_fil_axis);
void cam_i2c_init(volatile unsigned *mt9d111_i2c_axi_lites) {
mt9d111_i2c_axi_lites[64] = 0x2; // reset tx fifo ,address is 0x100, i2c_control_reg
mt9d111_i2c_axi_lites[64] = 0x1; // enable i2c
}
void cam_i2x_write_sync(void) {
// unsigned c;
// c = *cam_i2c_rx_fifo;
// while ((c & 0x84) != 0x80)
// c = *cam_i2c_rx_fifo; // No Bus Busy and TX_FIFO_Empty = 1
usleep(1000);
}
void cam_i2c_write(volatile unsigned *mt9d111_i2c_axi_lites, unsigned int device_addr, unsigned int write_addr, unsigned int write_data){
mt9d111_i2c_axi_lites[66] = 0x100 | (device_addr & 0xfe); // Slave IIC Write Address, address is 0x108, i2c_tx_fifo
mt9d111_i2c_axi_lites[66] = write_addr;
mt9d111_i2c_axi_lites[66] = (write_data >> 8)|0xff; // first data
mt9d111_i2c_axi_lites[66] = 0x200 | (write_data & 0xff); // second data
cam_i2x_write_sync();
}
int main(){
// malloc frame buffer
// unsigned int *frame_buffer = (unsigned int *)malloc(HORIZONTAL_PIXELS * VERTICAL_LINES * PIXEL_NUM_OF_BYTES * NUMBER_OF_WRITE_FRAMES);
// AXI VDMA Initialization sequence
XAxiVdma_Config *XAxiVdma0_Config;
XAxiVdma XAxiVdma0;
int XAxiVdma0_Status;
static XGpio GPIOInstance_Ptr;
int XGpio_Status;
XLap_filter_axis Xlap_fil_axis;
XLap_filter_axis_Config *Xlap_fil_axisPtr;
int sw0_status, sw0_status_old;
XAxiVdma0_Config = XAxiVdma_LookupConfig(XPAR_CAMERA_INTERFACE_AXI_VDMA_0_DEVICE_ID); // Look up the hardware configuration for a device instance
if (XAxiVdma0_Config == NULL){
fprintf(stderr, "No AXI VDMA found\n");
return(-1);
}
XAxiVdma0_Status = XAxiVdma_CfgInitialize(&XAxiVdma0, XAxiVdma0_Config, XAxiVdma0_Config->BaseAddress); // Initialize the driver with hardware configuration
if (XAxiVdma0_Status != XST_SUCCESS){
fprintf(stderr, "XAxiVdma_CfgInitialize() failed\n");
return(-1);
}
XAxiVdma_Reset(&XAxiVdma0, XAXIVDMA_WRITE);
while(XAxiVdma_ResetNotDone(&XAxiVdma0, XAXIVDMA_WRITE)) ;
XAxiVdma0_Status = XAxiVdma_SetFrmStore(&XAxiVdma0, NUMBER_OF_WRITE_FRAMES, XAXIVDMA_WRITE); // Set the number of frame store buffers to use.
Vdma0_WriteCfg.VertSizeInput = VERTICAL_LINES;
Vdma0_WriteCfg.HoriSizeInput = HORIZONTAL_PIXELS * PIXEL_NUM_OF_BYTES;
Vdma0_WriteCfg.Stride = HORIZONTAL_PIXELS * PIXEL_NUM_OF_BYTES; // Indicates the number of address bytes between the first pixels of each video line.
Vdma0_WriteCfg.FrameDelay = 0; // Indicates the minimum number of frame buffers the Genlock slave is to be behind the locked master. This field is only used if the channel is enabled for Genlock Slave operations. This field has no meaning in other Genlock modes.
Vdma0_WriteCfg.EnableCircularBuf = 1; // Indicates frame buffer Circular mode or frame buffer Park mode. 1 = Circular Mode Engine continuously circles through frame buffers.
Vdma0_WriteCfg.EnableSync = 0; // Enables Genlock or Dynamic Genlock Synchronization. 0 = Genlock or Dynamic Genlock Synchronization disabled.
Vdma0_WriteCfg.PointNum = 0; // No Gen-Lock
Vdma0_WriteCfg.EnableFrameCounter = 0; // Endless transfers
Vdma0_WriteCfg.FixedFrameStoreAddr = 0; // We are not doing parking
XAxiVdma0_Status = XAxiVdma_DmaConfig(&XAxiVdma0, XAXIVDMA_WRITE, &Vdma0_WriteCfg);
if (XAxiVdma0_Status != XST_SUCCESS){
fprintf(stderr, "XAxiVdma_DmaConfig() failed\n");
return(-1);
}
// Frame buffer address set
unsigned int frame_addr = (unsigned int)FRAME_BUFFER_ADDRESS;
int i;
for (i=0; i<NUMBER_OF_WRITE_FRAMES; i++){
Vdma0_WriteCfg.FrameStoreStartAddr[i] = frame_addr;
frame_addr += HORIZONTAL_PIXELS * PIXEL_NUM_OF_BYTES * VERTICAL_LINES;
}
XAxiVdma0_Status = XAxiVdma_DmaSetBufferAddr(&XAxiVdma0, XAXIVDMA_WRITE, Vdma0_WriteCfg.FrameStoreStartAddr);
if (XAxiVdma0_Status != XST_SUCCESS){
fprintf(stderr, "XAxiVdma_DmaSetBufferAddr() failed\n");
return(-1);
}
// axis_switch_1, 1to2 ,Select M00_AXIS
// Refer to http://marsee101.blog19.fc2.com/blog-entry-3177.html
Xil_Out32((XPAR_CAMERA_INTERFACE_AXIS_SWITCH_1_BASEADDR+0x40), 0x0);
Xil_Out32((XPAR_CAMERA_INTERFACE_AXIS_SWITCH_1_BASEADDR+0x44), 0x80000000); // disable
Xil_Out32((XPAR_CAMERA_INTERFACE_AXIS_SWITCH_1_BASEADDR), 0x2); // Commit registers
// axis_switch_0, 2to1, Select S00_AXIS
// Refer to http://marsee101.blog19.fc2.com/blog-entry-3177.html
Xil_Out32((XPAR_CAMERA_INTERFACE_AXIS_SWITCH_0_BASEADDR+0x40), 0x0);
Xil_Out32((XPAR_CAMERA_INTERFACE_AXIS_SWITCH_0_BASEADDR), 0x2); // Commit registers
// VDMA start
XAxiVdma0_Status = XAxiVdma_DmaStart(&XAxiVdma0, XAXIVDMA_WRITE);
if (XAxiVdma0_Status != XST_SUCCESS){
fprintf(stderr, "XAxiVdma_DmaStart() failed\n");
return(-1);
}
// mt9d111_inf_axis_0, axi_iic_0, bitmap_disp_cntrler_axi_master_0
volatile unsigned int *bmdc0_axi_lites;
volatile unsigned int *bmdc1_axi_lites;
volatile unsigned int *mt9d111_axi_lites;
volatile unsigned int *mt9d111_i2c_axi_lites;
bmdc0_axi_lites = (volatile unsigned *)XPAR_BITMAP_DISP_CNTRLER_AXI_MASTER_0_BASEADDR;
bmdc1_axi_lites = (volatile unsigned *)XPAR_BITMAP_DISP_CNTRLER_AXI_MASTER_1_BASEADDR;
mt9d111_axi_lites = (volatile unsigned *)XPAR_CAMERA_INTERFACE_MT9D111_INF_AXIS_0_BASEADDR;
mt9d111_i2c_axi_lites = (volatile unsigned *)XPAR_CAMERA_INTERFACE_AXI_IIC_0_BASEADDR;
bmdc0_axi_lites[0] = (volatile unsigned int)FRAME_BUFFER_ADDRESS; // Bitmap Display Controller 0 start
bmdc1_axi_lites[0] = (volatile unsigned int)FRAME_BUFFER_ADDRESS; // Bitmap Display Controller 1 start
mt9d111_axi_lites[0] = (volatile unsigned int)FRAME_BUFFER_ADDRESS; // Camera Interface start (Address is dummy)
// CMOS Camera initialize, MT9D111
cam_i2c_init(mt9d111_i2c_axi_lites);
cam_i2c_write(mt9d111_i2c_axi_lites, 0xba, 0xf0, 0x1); // Changed regster map to IFP page 1
cam_i2c_write(mt9d111_i2c_axi_lites, 0xba, 0x97, 0x20); // RGB Mode, RGB565
mt9d111_axi_lites[1] = 0; // One_shot_mode is disabled
// AXI GPIO Initialization
XGpio_Status = XGpio_Initialize(&GPIOInstance_Ptr,XPAR_AXI_GPIO_0_DEVICE_ID);
if(XST_SUCCESS != XGpio_Status)
print("GPIO INIT FAILED\n\r");
// AXI GPIO Set the Direction(input setting)
XGpio_SetDataDirection(&GPIOInstance_Ptr, 1, 1);
// Look Up the device configuration
Xlap_fil_axisPtr = XLap_filter_axis_LookupConfig(0);
if (!Xlap_fil_axisPtr){
fprintf(stderr, "XLap_filter_axis configuration failed.\n");
return(-1);
}
// Initialize the Device
int Xlap_status = XLap_filter_axis_CfgInitialize(&Xlap_fil_axis, Xlap_fil_axisPtr);
if (Xlap_status != XST_SUCCESS){
fprintf(stderr, "Could not Initialize XLap_filter_axis\n");
return(-1);
}
sw0_status_old = XGpio_DiscreteRead(&GPIOInstance_Ptr, 1) & 1;
usleep(5000); // wait 5ms
while(1){
sw0_status = XGpio_DiscreteRead(&GPIOInstance_Ptr, 1) & 1;
if (sw0_status_old != sw0_status){ // sw0 status changed
if (sw0_status == 0) // camera output
camera_out(Xlap_fil_axis);
else // laplacian filter output
lap_fil_out(Xlap_fil_axis);
sw0_status_old = sw0_status;
}
usleep(5000); // wait 5ms
}
return(0);
}
void camera_out(XLap_filter_axis Xlap_fil_axis){
// axis_switch_1, 1to2 ,Select M00_AXIS
// Refer to http://marsee101.blog19.fc2.com/blog-entry-3177.html
Xil_Out32((XPAR_CAMERA_INTERFACE_AXIS_SWITCH_1_BASEADDR+0x40), 0x0);
Xil_Out32((XPAR_CAMERA_INTERFACE_AXIS_SWITCH_1_BASEADDR+0x44), 0x80000000); // disable
Xil_Out32((XPAR_CAMERA_INTERFACE_AXIS_SWITCH_1_BASEADDR), 0x2); // Commit registers
// laplacian filter AXIS AutoRestart disable
XLap_filter_axis_DisableAutoRestart(&Xlap_fil_axis);
// axis_switch_0, 2to1, Select S00_AXIS
// Refer to http://marsee101.blog19.fc2.com/blog-entry-3177.html
Xil_Out32((XPAR_CAMERA_INTERFACE_AXIS_SWITCH_0_BASEADDR+0x40), 0x0);
Xil_Out32((XPAR_CAMERA_INTERFACE_AXIS_SWITCH_0_BASEADDR), 0x2); // Commit registers
}
void lap_fil_out(XLap_filter_axis Xlap_fil_axis){
// axis_switch_1, 1to2 ,Select M01_AXIS
// Refer to http://marsee101.blog19.fc2.com/blog-entry-3177.html
Xil_Out32((XPAR_CAMERA_INTERFACE_AXIS_SWITCH_1_BASEADDR+0x40), 0x80000000); // disable
Xil_Out32((XPAR_CAMERA_INTERFACE_AXIS_SWITCH_1_BASEADDR+0x44), 0);
Xil_Out32((XPAR_CAMERA_INTERFACE_AXIS_SWITCH_1_BASEADDR), 0x2); // Commit registers
// laplacian filter AXIS Start
XLap_filter_axis_Start(&Xlap_fil_axis);
XLap_filter_axis_EnableAutoRestart(&Xlap_fil_axis);
// axis_switch_0, 2to1, Select S01_AXIS
// Refer to http://marsee101.blog19.fc2.com/blog-entry-3177.html
Xil_Out32((XPAR_CAMERA_INTERFACE_AXIS_SWITCH_0_BASEADDR+0x40), 0x1);
Xil_Out32((XPAR_CAMERA_INTERFACE_AXIS_SWITCH_0_BASEADDR), 0x2); // Commit registers
}
set_false_path -from [get_clocks ZYBO_0_i/bitmap_disp_cntrler_axi_master_1/inst/dvi_disp_i/pixclk] -to [get_clocks clk_fpga_0]
set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks ZYBO_0_i/bitmap_disp_cntrler_axi_master_1/inst/dvi_disp_i/pixclk]
MMCM_BASE_PIXEL : MMCME2_BASE generic map (BANDWIDTH => "OPTIMIZED",CLKOUT4_CASCADE => FALSE,STARTUP_WAIT => FALSE,CLKFBOUT_MULT_F => MMCM_CLKFBOUT_MULT,CLKIN1_PERIOD => MMCM_CLKIN_PERIOD,CLKOUT0_DIVIDE_F => MMCM_CLKOUT0_DIVIDE,DIVCLK_DIVIDE => 1) port map (CLKFBOUT => mmc_fb_out,CLKOUT0 => pixel_clkx5,LOCKED => mmcm_locked,CLKFBIN => mmc_fb_in,CLKIN1 => clk25,PWRDWN => '0',RST => '0');mmcm_locked_n <= not mmcm_locked;mmc_fb_in <= mmc_fb_out;-- BUF_FB : BUFG port map(-- I => mmc_fb_out,-- O => mmc_fb_in-- );BUFIO_pixel_clkx5 : BUFIO port map (O => pclkx5_buf,I => pixel_clkx5);BUFR_pixel_clk_io : BUFR generic map(BUFR_DIVIDE => "5",SIM_DEVICE => "7SERIES") port map (O => pclk_buf,CE => '1',CLR => mmcm_locked_n,I => pixel_clkx5);CLK_OUT_BUFG : bufg port map (O => pclk_buf_out,I => pclk_buf);pclk_out <= pclk_buf_out;pclk_locked <= mmcm_locked;
create_generated_clock -source [get_pins ZYBO_0_i/bitmap_disp_cntrler_axi_master_1/inst/dvi_disp_i/hdmi_tx_i/pclkx5_buf] -divide_by 5 [get_pins ZYBO_0_i/bitmap_disp_cntrler_axi_master_0/inst/dvi_disp_i/pixclk]
// cam_disp_axis.c// 2015/11/19 by marsee//// Refered to Xilinx\SDK\2015.1\data\embeddedsw\XilinxProcessorIPLib\drivers\axivdma_v5_1\doc\html\api// Refered to https://github.com/elitezhe/Atyls-VDMA-one-in-one-out/blob/master/SDK/colorbar/src/helloworld.c// Refered to http://www.xilinx.com/support/documentation/ip_documentation/axi_vdma/v6_2/pg020_axi_vdma.pdf// Refered to http://forums.xilinx.com/t5/Embedded-Processor-System-Design/Axi-VDMA-on-Digilent-Atlys/td-p/297019/page/2//// normal camera out//#include <stdio.h>#include <stdlib.h>#include "xaxivdma.h"#include "xil_io.h"#include "xparameters.h"#include "sleep.h"#define NUMBER_OF_WRITE_FRAMES 3 // Note: If not at least 3 or more, the image is not displayed in succession.#define HORIZONTAL_PIXELS 800#define VERTICAL_LINES 600#define PIXEL_NUM_OF_BYTES 4#define FRAME_BUFFER_ADDRESS 0x10000000static XAxiVdma_DmaSetup Vdma0_WriteCfg;void cam_i2c_init(volatile unsigned *mt9d111_i2c_axi_lites) {mt9d111_i2c_axi_lites[64] = 0x2; // reset tx fifo ,address is 0x100, i2c_control_regmt9d111_i2c_axi_lites[64] = 0x1; // enable i2c}void cam_i2x_write_sync(void) {// unsigned c;// c = *cam_i2c_rx_fifo;// while ((c & 0x84) != 0x80)// c = *cam_i2c_rx_fifo; // No Bus Busy and TX_FIFO_Empty = 1usleep(1000);}void cam_i2c_write(volatile unsigned *mt9d111_i2c_axi_lites, unsigned int device_addr, unsigned int write_addr, unsigned int write_data){mt9d111_i2c_axi_lites[66] = 0x100 | (device_addr & 0xfe); // Slave IIC Write Address, address is 0x108, i2c_tx_fifomt9d111_i2c_axi_lites[66] = write_addr;mt9d111_i2c_axi_lites[66] = (write_data >> 8)|0xff; // first datamt9d111_i2c_axi_lites[66] = 0x200 | (write_data & 0xff); // second datacam_i2x_write_sync();}int main(){// malloc frame buffer// unsigned int *frame_buffer = (unsigned int *)malloc(HORIZONTAL_PIXELS * VERTICAL_LINES * PIXEL_NUM_OF_BYTES * NUMBER_OF_WRITE_FRAMES);// AXI VDMA Initialization sequenceXAxiVdma_Config *XAxiVdma0_Config;XAxiVdma XAxiVdma0;int XAxiVdma0_Status;XAxiVdma0_Config = XAxiVdma_LookupConfig(XPAR_CAMERA_INTERFACE_AXI_VDMA_0_DEVICE_ID); // Look up the hardware configuration for a device instanceif (XAxiVdma0_Config == NULL){fprintf(stderr, "No AXI VDMA found\n");return(-1);}XAxiVdma0_Status = XAxiVdma_CfgInitialize(&XAxiVdma0, XAxiVdma0_Config, XAxiVdma0_Config->BaseAddress); // Initialize the driver with hardware configurationif (XAxiVdma0_Status != XST_SUCCESS){fprintf(stderr, "XAxiVdma_CfgInitialize() failed\n");return(-1);}XAxiVdma_Reset(&XAxiVdma0, XAXIVDMA_WRITE);while(XAxiVdma_ResetNotDone(&XAxiVdma0, XAXIVDMA_WRITE)) ;XAxiVdma0_Status = XAxiVdma_SetFrmStore(&XAxiVdma0, NUMBER_OF_WRITE_FRAMES, XAXIVDMA_WRITE); // Set the number of frame store buffers to use.Vdma0_WriteCfg.VertSizeInput = VERTICAL_LINES;Vdma0_WriteCfg.HoriSizeInput = HORIZONTAL_PIXELS * PIXEL_NUM_OF_BYTES;Vdma0_WriteCfg.Stride = HORIZONTAL_PIXELS * PIXEL_NUM_OF_BYTES; // Indicates the number of address bytes between the first pixels of each video line.Vdma0_WriteCfg.FrameDelay = 0; // Indicates the minimum number of frame buffers the Genlock slave is to be behind the locked master. This field is only used if the channel is enabled for Genlock Slave operations. This field has no meaning in other Genlock modes.Vdma0_WriteCfg.EnableCircularBuf = 1; // Indicates frame buffer Circular mode or frame buffer Park mode. 1 = Circular Mode Engine continuously circles through frame buffers.Vdma0_WriteCfg.EnableSync = 0; // Enables Genlock or Dynamic Genlock Synchronization. 0 = Genlock or Dynamic Genlock Synchronization disabled.Vdma0_WriteCfg.PointNum = 0; // No Gen-LockVdma0_WriteCfg.EnableFrameCounter = 0; // Endless transfersVdma0_WriteCfg.FixedFrameStoreAddr = 0; // We are not doing parkingXAxiVdma0_Status = XAxiVdma_DmaConfig(&XAxiVdma0, XAXIVDMA_WRITE, &Vdma0_WriteCfg);if (XAxiVdma0_Status != XST_SUCCESS){fprintf(stderr, "XAxiVdma_DmaConfig() failed\n");return(-1);}// Frame buffer address setunsigned int frame_addr = (unsigned int)FRAME_BUFFER_ADDRESS;int i;for (i=0; i<NUMBER_OF_WRITE_FRAMES; i++){Vdma0_WriteCfg.FrameStoreStartAddr[i] = frame_addr;frame_addr += HORIZONTAL_PIXELS * PIXEL_NUM_OF_BYTES * VERTICAL_LINES;}XAxiVdma0_Status = XAxiVdma_DmaSetBufferAddr(&XAxiVdma0, XAXIVDMA_WRITE, Vdma0_WriteCfg.FrameStoreStartAddr);if (XAxiVdma0_Status != XST_SUCCESS){fprintf(stderr, "XAxiVdma_DmaSetBufferAddr() failed\n");return(-1);}// axis_switch_1, 1to2 ,Select M00_AXIS// Refer to http://marsee101.blog19.fc2.com/blog-entry-3177.htmlXil_Out32((XPAR_CAMERA_INTERFACE_AXIS_SWITCH_1_BASEADDR+0x40), 0x0);Xil_Out32((XPAR_CAMERA_INTERFACE_AXIS_SWITCH_1_BASEADDR+0x44), 0x80000000); // disableXil_Out32((XPAR_CAMERA_INTERFACE_AXIS_SWITCH_1_BASEADDR), 0x2); // Commit registers// axis_switch_0, 2to1, Select S00_AXIS// Refer to http://marsee101.blog19.fc2.com/blog-entry-3177.htmlXil_Out32((XPAR_CAMERA_INTERFACE_AXIS_SWITCH_0_BASEADDR+0x40), 0x0);Xil_Out32((XPAR_CAMERA_INTERFACE_AXIS_SWITCH_0_BASEADDR), 0x2); // Commit registers// VDMA startXAxiVdma0_Status = XAxiVdma_DmaStart(&XAxiVdma0, XAXIVDMA_WRITE);if (XAxiVdma0_Status != XST_SUCCESS){fprintf(stderr, "XAxiVdma_DmaStart() failed\n");return(-1);}// mt9d111_inf_axis_0, axi_iic_0, bitmap_disp_cntrler_axi_master_0volatile unsigned int *bmdc0_axi_lites;volatile unsigned int *bmdc1_axi_lites;volatile unsigned int *mt9d111_axi_lites;volatile unsigned int *mt9d111_i2c_axi_lites;bmdc0_axi_lites = (volatile unsigned *)XPAR_BITMAP_DISP_CNTRLER_AXI_MASTER_0_BASEADDR;bmdc1_axi_lites = (volatile unsigned *)XPAR_BITMAP_DISP_CNTRLER_AXI_MASTER_1_BASEADDR;mt9d111_axi_lites = (volatile unsigned *)XPAR_CAMERA_INTERFACE_MT9D111_INF_AXIS_0_BASEADDR;mt9d111_i2c_axi_lites = (volatile unsigned *)XPAR_CAMERA_INTERFACE_AXI_IIC_0_BASEADDR;bmdc0_axi_lites[0] = (volatile unsigned int)FRAME_BUFFER_ADDRESS; // Bitmap Display Controller 0 startbmdc1_axi_lites[0] = (volatile unsigned int)FRAME_BUFFER_ADDRESS; // Bitmap Display Controller 1 startmt9d111_axi_lites[0] = (volatile unsigned int)FRAME_BUFFER_ADDRESS; // Camera Interface start (Address is dummy)// CMOS Camera initialize, MT9D111cam_i2c_init(mt9d111_i2c_axi_lites);cam_i2c_write(mt9d111_i2c_axi_lites, 0xba, 0xf0, 0x1); // Changed regster map to IFP page 1cam_i2c_write(mt9d111_i2c_axi_lites, 0xba, 0x97, 0x20); // RGB Mode, RGB565mt9d111_axi_lites[1] = 0; // One_shot_mode is disabledreturn(0);}
set_false_path -from [get_clocks [list [get_clocks -of_objects [get_pins ZYBO_0_i/bitmap_disp_cntrler_axi_master_0/inst/dvi_disp_i/BUFR_pixel_clk_io/O]]]] -to [get_clocks clk_fpga_0]
set_false_path -from [get_clocks [list [get_clocks -of_objects [get_pins ZYBO_0_i/bitmap_disp_cntrler_axi_master_1/inst/dvi_disp_i/BUFR_pixel_clk_io/O]]]] -to [get_clocks clk_fpga_0]
set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks [list [get_clocks -of_objects [get_pins ZYBO_0_i/bitmap_disp_cntrler_axi_master_0/inst/dvi_disp_i/BUFR_pixel_clk_io/O]]]]
set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks [list [get_clocks -of_objects [get_pins ZYBO_0_i/bitmap_disp_cntrler_axi_master_1/inst/dvi_disp_i/BUFR_pixel_clk_io/O]]]]
lap_fil_hdl_axim
devicetree
MAJOR=247
MINOR=5
DEVNAME=uio5
これを、 marsee_example1 ディレクトリ上で ../../synverll marsee_example1.c mar_ex_top コマンドでC言語からの高位合成を行った。// marsee_example1.c// 掛け算サンプル//#define ARRAY_LIMIT 10int marsee_example1(int multi_in0[ARRAY_LIMIT], int multi_in1[ARRAY_LIMIT], int multi_out[ARRAY_LIMIT]){int i;for (i=0; i<ARRAY_LIMIT; i++){multi_out[i] = multi_in0[i] * multi_in1[i];}return 0;}
/** Copyright (C)2005-2015 AQUAXIS TECHNOLOGY.* Don't remove this header.* When you use this source, there is a need to inherit this header.** This software is released under the MIT License.* http://opensource.org/licenses/mit-license.php** For further information please contact.* URI: http://www.aquaxis.com/* E-Mail: info(at)aquaxis.com*/module mar_ex_top(input system_clock,input system_reset,input __func_start,output __func_done,output __func_ready,output __gm_req,output __gm_rnw,input __gm_done,output [31:0] __gm_adrs,output [1:0] __gm_leng,input [31:0] __gm_di,output [31:0] __gm_do,// global signalinput __args_multi_in0,input __args_multi_in1,input __args_multi_out,output dummy);// wirewire marsee_example1__func_start;wire marsee_example1__func_done;wire marsee_example1__func_ready;wire marsee_example1__gm_req;wire marsee_example1__gm_rnw;wire marsee_example1__gm_done;wire [31:0] marsee_example1__gm_adrs;wire [1:0] marsee_example1__gm_leng;wire [31:0] marsee_example1__gm_di;wire [31:0] marsee_example1__gm_do;wire marsee_example1__args_multi_in0;wire marsee_example1__args_multi_in1;wire marsee_example1__args_multi_out;// connectionassign marsee_example1__gm_done = __gm_done;assign marsee_example1__gm_di = __gm_di;// Global Memoryassign __gm_req = marsee_example1__gm_req ;assign __gm_adrs = marsee_example1__gm_adrs ;assign __gm_rnw = marsee_example1__gm_rnw ;assign __gm_do = marsee_example1__gm_do ;assign __gm_leng = marsee_example1__gm_leng ;// system signalassign marsee_example1__func_start = __func_start;assign __func_done = marsee_example1__func_done;assign __func_ready = marsee_example1__func_ready;assign marsee_example1__args_multi_in0 = __args_multi_in0;assign marsee_example1__args_multi_in1 = __args_multi_in1;assign marsee_example1__args_multi_out = __args_multi_out;// modulesmarsee_example1 u_marsee_example1(// system signals.__func_clock(system_clock),.__func_reset(system_reset),.__func_start(marsee_example1__func_start),.__func_done(marsee_example1__func_done),.__func_ready(marsee_example1__func_ready),// memory bus.__gm_req(marsee_example1__gm_req),.__gm_rnw(marsee_example1__gm_rnw),.__gm_done(marsee_example1__gm_done),.__gm_adrs(marsee_example1__gm_adrs),.__gm_leng(marsee_example1__gm_leng),.__gm_di(marsee_example1__gm_di),.__gm_do(marsee_example1__gm_do),// base address// arguments.__args_multi_in0(marsee_example1__args_multi_in0),.__args_multi_in1(marsee_example1__args_multi_in1),.__args_multi_out(marsee_example1__args_multi_out),// call instruction.__dummy());endmodule
/** Copyright (C)2005-2015 AQUAXIS TECHNOLOGY.* Don't remove this header.* When you use this source, there is a need to inherit this header.** This software is released under the MIT License.* http://opensource.org/licenses/mit-license.php** For further information please contact.* URI: http://www.aquaxis.com/* E-Mail: info(at)aquaxis.com*/module marsee_example1(input __func_clock,input __func_reset,input __func_start,output reg __func_done,output reg __func_ready,output reg __gm_req,output reg __gm_rnw,input __gm_done,output reg [31:0] __gm_adrs,output reg [1:0] __gm_leng,input [31:0] __gm_di,output reg [31:0] __gm_do,// Memory Singalinput [31:0] __args_multi_in0,input [31:0] __args_multi_in1,input [31:0] __args_multi_out,// Call Singaloutput reg __dummy);reg [31:0] __sig_0;reg [31:0] __sig_1;reg [31:0] __sig_mul;wire [31:0] __sig_arrayidx_1;reg [31:0] __sig_2;wire [31:0] __sig_arrayidx1_1;reg [31:0] __sig_3;reg [31:0] __sig_mul_1;wire [31:0] __sig_arrayidx2_1;wire [31:0] __sig_arrayidx_2;reg [31:0] __sig_4;wire [31:0] __sig_arrayidx1_2;reg [31:0] __sig_5;reg [31:0] __sig_mul_2;wire [31:0] __sig_arrayidx2_2;wire [31:0] __sig_arrayidx_3;reg [31:0] __sig_6;wire [31:0] __sig_arrayidx1_3;reg [31:0] __sig_7;reg [31:0] __sig_mul_3;wire [31:0] __sig_arrayidx2_3;wire [31:0] __sig_arrayidx_4;reg [31:0] __sig_8;wire [31:0] __sig_arrayidx1_4;reg [31:0] __sig_9;reg [31:0] __sig_mul_4;wire [31:0] __sig_arrayidx2_4;wire [31:0] __sig_arrayidx_5;reg [31:0] __sig_10;wire [31:0] __sig_arrayidx1_5;reg [31:0] __sig_11;reg [31:0] __sig_mul_5;wire [31:0] __sig_arrayidx2_5;wire [31:0] __sig_arrayidx_6;reg [31:0] __sig_12;wire [31:0] __sig_arrayidx1_6;reg [31:0] __sig_13;reg [31:0] __sig_mul_6;wire [31:0] __sig_arrayidx2_6;wire [31:0] __sig_arrayidx_7;reg [31:0] __sig_14;wire [31:0] __sig_arrayidx1_7;reg [31:0] __sig_15;reg [31:0] __sig_mul_7;wire [31:0] __sig_arrayidx2_7;wire [31:0] __sig_arrayidx_8;reg [31:0] __sig_16;wire [31:0] __sig_arrayidx1_8;reg [31:0] __sig_17;reg [31:0] __sig_mul_8;wire [31:0] __sig_arrayidx2_8;wire [31:0] __sig_arrayidx_9;reg [31:0] __sig_18;wire [31:0] __sig_arrayidx1_9;reg [31:0] __sig_19;reg [31:0] __sig_mul_9;wire [31:0] __sig_arrayidx2_9;assign __sig_arrayidx_1 = (__sig_multi_in0 + (1));assign __sig_arrayidx1_1 = (__sig_multi_in1 + (1));assign __sig_arrayidx2_1 = (__sig_multi_out + (1));assign __sig_arrayidx_2 = (__sig_multi_in0 + (2));assign __sig_arrayidx1_2 = (__sig_multi_in1 + (2));assign __sig_arrayidx2_2 = (__sig_multi_out + (2));assign __sig_arrayidx_3 = (__sig_multi_in0 + (3));assign __sig_arrayidx1_3 = (__sig_multi_in1 + (3));assign __sig_arrayidx2_3 = (__sig_multi_out + (3));assign __sig_arrayidx_4 = (__sig_multi_in0 + (4));assign __sig_arrayidx1_4 = (__sig_multi_in1 + (4));assign __sig_arrayidx2_4 = (__sig_multi_out + (4));assign __sig_arrayidx_5 = (__sig_multi_in0 + (5));assign __sig_arrayidx1_5 = (__sig_multi_in1 + (5));assign __sig_arrayidx2_5 = (__sig_multi_out + (5));assign __sig_arrayidx_6 = (__sig_multi_in0 + (6));assign __sig_arrayidx1_6 = (__sig_multi_in1 + (6));assign __sig_arrayidx2_6 = (__sig_multi_out + (6));assign __sig_arrayidx_7 = (__sig_multi_in0 + (7));assign __sig_arrayidx1_7 = (__sig_multi_in1 + (7));assign __sig_arrayidx2_7 = (__sig_multi_out + (7));assign __sig_arrayidx_8 = (__sig_multi_in0 + (8));assign __sig_arrayidx1_8 = (__sig_multi_in1 + (8));assign __sig_arrayidx2_8 = (__sig_multi_out + (8));assign __sig_arrayidx_9 = (__sig_multi_in0 + (9));assign __sig_arrayidx1_9 = (__sig_multi_in1 + (9));assign __sig_arrayidx2_9 = (__sig_multi_out + (9));reg [31:0] __sig_multi_in0;reg [31:0] __sig_multi_in1;reg [31:0] __sig_multi_out;localparam __state_fin_exec = 0;localparam __state_start_req = 1;localparam __state_start_wait = 2;localparam __state_start_exec = 3;localparam __state_1_exec = 4;localparam __state_2_exec = 5;localparam __state_3_req = 6;localparam __state_3_wait = 7;localparam __state_3_exec = 8;localparam __state_4_req = 9;localparam __state_4_wait = 10;localparam __state_4_exec = 11;localparam __state_5_exec = 12;localparam __state_6_req = 13;localparam __state_6_wait = 14;localparam __state_6_exec = 15;localparam __state_7_req = 16;localparam __state_7_wait = 17;localparam __state_7_exec = 18;localparam __state_8_req = 19;localparam __state_8_wait = 20;localparam __state_8_exec = 21;localparam __state_9_exec = 22;localparam __state_10_req = 23;localparam __state_10_wait = 24;localparam __state_10_exec = 25;localparam __state_11_req = 26;localparam __state_11_wait = 27;localparam __state_11_exec = 28;localparam __state_12_req = 29;localparam __state_12_wait = 30;localparam __state_12_exec = 31;localparam __state_13_exec = 32;localparam __state_14_req = 33;localparam __state_14_wait = 34;localparam __state_14_exec = 35;localparam __state_15_req = 36;localparam __state_15_wait = 37;localparam __state_15_exec = 38;localparam __state_16_req = 39;localparam __state_16_wait = 40;localparam __state_16_exec = 41;localparam __state_17_exec = 42;localparam __state_18_req = 43;localparam __state_18_wait = 44;localparam __state_18_exec = 45;localparam __state_19_req = 46;localparam __state_19_wait = 47;localparam __state_19_exec = 48;localparam __state_20_req = 49;localparam __state_20_wait = 50;localparam __state_20_exec = 51;localparam __state_21_exec = 52;localparam __state_22_req = 53;localparam __state_22_wait = 54;localparam __state_22_exec = 55;localparam __state_23_req = 56;localparam __state_23_wait = 57;localparam __state_23_exec = 58;localparam __state_24_req = 59;localparam __state_24_wait = 60;localparam __state_24_exec = 61;localparam __state_25_exec = 62;localparam __state_26_req = 63;localparam __state_26_wait = 64;localparam __state_26_exec = 65;localparam __state_27_req = 66;localparam __state_27_wait = 67;localparam __state_27_exec = 68;localparam __state_28_req = 69;localparam __state_28_wait = 70;localparam __state_28_exec = 71;localparam __state_29_exec = 72;localparam __state_30_req = 73;localparam __state_30_wait = 74;localparam __state_30_exec = 75;localparam __state_31_req = 76;localparam __state_31_wait = 77;localparam __state_31_exec = 78;localparam __state_32_req = 79;localparam __state_32_wait = 80;localparam __state_32_exec = 81;localparam __state_33_exec = 82;localparam __state_34_req = 83;localparam __state_34_wait = 84;localparam __state_34_exec = 85;localparam __state_35_req = 86;localparam __state_35_wait = 87;localparam __state_35_exec = 88;localparam __state_36_req = 89;localparam __state_36_wait = 90;localparam __state_36_exec = 91;localparam __state_37_exec = 92;localparam __state_38_req = 93;localparam __state_38_wait = 94;localparam __state_38_exec = 95;localparam __state_39_req = 96;localparam __state_39_wait = 97;localparam __state_39_exec = 98;localparam __state_40_req = 99;localparam __state_40_wait = 100;localparam __state_40_exec = 101;localparam __state_41_exec = 102;localparam __state_42_req = 103;localparam __state_42_wait = 104;localparam __state_42_exec = 105;localparam __state_43_exec = 106;localparam __state_44_exec = 107;integer __state;localparam __label_0 = 0;localparam __label_entry = 2;integer __label;always @(posedge __func_clock or negedge __func_reset) beginif(!__func_reset) begin__state <= __state_start_req;__func_ready <= 0;__func_done <= 0;end else begincase(__state)__state_start_req: begin__state <= __state_start_wait;end__state_start_wait: beginif(__func_start) begin__state <= __state_start_exec;__func_ready <= 0;__func_done <= 0;__sig_multi_in0 <= __args_multi_in0;__sig_multi_in1 <= __args_multi_in1;__sig_multi_out <= __args_multi_out;endend__state_start_exec: begin__state <= __state_1_exec;end__state_1_exec: begin__state <= __state_2_exec;end__state_2_exec: begin__state <= __state_3_req;__label <= __label_entry;end__state_3_req: begin__state <= __state_3_wait;__gm_req <= 1;__gm_rnw <= 1;__gm_adrs <= (__sig_multi_in0);__gm_leng <= 3;end__state_3_wait: beginif((__gm_done == 1)) begin__state <= __state_3_exec;end__gm_req <= 0;end__state_3_exec: begin__state <= __state_4_req;__sig_0 <= __gm_di;end__state_4_req: begin__state <= __state_4_wait;__gm_req <= 1;__gm_rnw <= 1;__gm_adrs <= (__sig_multi_in1);__gm_leng <= 3;end__state_4_wait: beginif((__gm_done == 1)) begin__state <= __state_4_exec;end__gm_req <= 0;end__state_4_exec: begin__state <= __state_5_exec;__sig_1 <= __gm_di;end__state_5_exec: begin__state <= __state_6_req;__sig_mul <= __sig_1 * __sig_0;end__state_6_req: begin__state <= __state_6_wait;__gm_req <= 1;__gm_rnw <= 0;__gm_adrs <= (__sig_multi_out);__gm_leng <= 3;__gm_do <= __sig_mul;end__state_6_wait: beginif((__gm_done == 1)) begin__state <= __state_6_exec;end__gm_req <= 0;end__state_6_exec: begin__state <= __state_7_req;end__state_7_req: begin__state <= __state_7_wait;__gm_req <= 1;__gm_rnw <= 1;__gm_adrs <= (__sig_arrayidx_1);__gm_leng <= 3;end__state_7_wait: beginif((__gm_done == 1)) begin__state <= __state_7_exec;end__gm_req <= 0;end__state_7_exec: begin__state <= __state_8_req;__sig_2 <= __gm_di;end__state_8_req: begin__state <= __state_8_wait;__gm_req <= 1;__gm_rnw <= 1;__gm_adrs <= (__sig_arrayidx1_1);__gm_leng <= 3;end__state_8_wait: beginif((__gm_done == 1)) begin__state <= __state_8_exec;end__gm_req <= 0;end__state_8_exec: begin__state <= __state_9_exec;__sig_3 <= __gm_di;end__state_9_exec: begin__state <= __state_10_req;__sig_mul_1 <= __sig_3 * __sig_2;end__state_10_req: begin__state <= __state_10_wait;__gm_req <= 1;__gm_rnw <= 0;__gm_adrs <= (__sig_arrayidx2_1);__gm_leng <= 3;__gm_do <= __sig_mul_1;end__state_10_wait: beginif((__gm_done == 1)) begin__state <= __state_10_exec;end__gm_req <= 0;end__state_10_exec: begin__state <= __state_11_req;end__state_11_req: begin__state <= __state_11_wait;__gm_req <= 1;__gm_rnw <= 1;__gm_adrs <= (__sig_arrayidx_2);__gm_leng <= 3;end__state_11_wait: beginif((__gm_done == 1)) begin__state <= __state_11_exec;end__gm_req <= 0;end__state_11_exec: begin__state <= __state_12_req;__sig_4 <= __gm_di;end__state_12_req: begin__state <= __state_12_wait;__gm_req <= 1;__gm_rnw <= 1;__gm_adrs <= (__sig_arrayidx1_2);__gm_leng <= 3;end__state_12_wait: beginif((__gm_done == 1)) begin__state <= __state_12_exec;end__gm_req <= 0;end__state_12_exec: begin__state <= __state_13_exec;__sig_5 <= __gm_di;end__state_13_exec: begin__state <= __state_14_req;__sig_mul_2 <= __sig_5 * __sig_4;end__state_14_req: begin__state <= __state_14_wait;__gm_req <= 1;__gm_rnw <= 0;__gm_adrs <= (__sig_arrayidx2_2);__gm_leng <= 3;__gm_do <= __sig_mul_2;end__state_14_wait: beginif((__gm_done == 1)) begin__state <= __state_14_exec;end__gm_req <= 0;end__state_14_exec: begin__state <= __state_15_req;end__state_15_req: begin__state <= __state_15_wait;__gm_req <= 1;__gm_rnw <= 1;__gm_adrs <= (__sig_arrayidx_3);__gm_leng <= 3;end__state_15_wait: beginif((__gm_done == 1)) begin__state <= __state_15_exec;end__gm_req <= 0;end__state_15_exec: begin__state <= __state_16_req;__sig_6 <= __gm_di;end__state_16_req: begin__state <= __state_16_wait;__gm_req <= 1;__gm_rnw <= 1;__gm_adrs <= (__sig_arrayidx1_3);__gm_leng <= 3;end__state_16_wait: beginif((__gm_done == 1)) begin__state <= __state_16_exec;end__gm_req <= 0;end__state_16_exec: begin__state <= __state_17_exec;__sig_7 <= __gm_di;end__state_17_exec: begin__state <= __state_18_req;__sig_mul_3 <= __sig_7 * __sig_6;end__state_18_req: begin__state <= __state_18_wait;__gm_req <= 1;__gm_rnw <= 0;__gm_adrs <= (__sig_arrayidx2_3);__gm_leng <= 3;__gm_do <= __sig_mul_3;end__state_18_wait: beginif((__gm_done == 1)) begin__state <= __state_18_exec;end__gm_req <= 0;end__state_18_exec: begin__state <= __state_19_req;end__state_19_req: begin__state <= __state_19_wait;__gm_req <= 1;__gm_rnw <= 1;__gm_adrs <= (__sig_arrayidx_4);__gm_leng <= 3;end__state_19_wait: beginif((__gm_done == 1)) begin__state <= __state_19_exec;end__gm_req <= 0;end__state_19_exec: begin__state <= __state_20_req;__sig_8 <= __gm_di;end__state_20_req: begin__state <= __state_20_wait;__gm_req <= 1;__gm_rnw <= 1;__gm_adrs <= (__sig_arrayidx1_4);__gm_leng <= 3;end__state_20_wait: beginif((__gm_done == 1)) begin__state <= __state_20_exec;end__gm_req <= 0;end__state_20_exec: begin__state <= __state_21_exec;__sig_9 <= __gm_di;end__state_21_exec: begin__state <= __state_22_req;__sig_mul_4 <= __sig_9 * __sig_8;end__state_22_req: begin__state <= __state_22_wait;__gm_req <= 1;__gm_rnw <= 0;__gm_adrs <= (__sig_arrayidx2_4);__gm_leng <= 3;__gm_do <= __sig_mul_4;end__state_22_wait: beginif((__gm_done == 1)) begin__state <= __state_22_exec;end__gm_req <= 0;end__state_22_exec: begin__state <= __state_23_req;end__state_23_req: begin__state <= __state_23_wait;__gm_req <= 1;__gm_rnw <= 1;__gm_adrs <= (__sig_arrayidx_5);__gm_leng <= 3;end__state_23_wait: beginif((__gm_done == 1)) begin__state <= __state_23_exec;end__gm_req <= 0;end__state_23_exec: begin__state <= __state_24_req;__sig_10 <= __gm_di;end__state_24_req: begin__state <= __state_24_wait;__gm_req <= 1;__gm_rnw <= 1;__gm_adrs <= (__sig_arrayidx1_5);__gm_leng <= 3;end__state_24_wait: beginif((__gm_done == 1)) begin__state <= __state_24_exec;end__gm_req <= 0;end__state_24_exec: begin__state <= __state_25_exec;__sig_11 <= __gm_di;end__state_25_exec: begin__state <= __state_26_req;__sig_mul_5 <= __sig_11 * __sig_10;end__state_26_req: begin__state <= __state_26_wait;__gm_req <= 1;__gm_rnw <= 0;__gm_adrs <= (__sig_arrayidx2_5);__gm_leng <= 3;__gm_do <= __sig_mul_5;end__state_26_wait: beginif((__gm_done == 1)) begin__state <= __state_26_exec;end__gm_req <= 0;end__state_26_exec: begin__state <= __state_27_req;end__state_27_req: begin__state <= __state_27_wait;__gm_req <= 1;__gm_rnw <= 1;__gm_adrs <= (__sig_arrayidx_6);__gm_leng <= 3;end__state_27_wait: beginif((__gm_done == 1)) begin__state <= __state_27_exec;end__gm_req <= 0;end__state_27_exec: begin__state <= __state_28_req;__sig_12 <= __gm_di;end__state_28_req: begin__state <= __state_28_wait;__gm_req <= 1;__gm_rnw <= 1;__gm_adrs <= (__sig_arrayidx1_6);__gm_leng <= 3;end__state_28_wait: beginif((__gm_done == 1)) begin__state <= __state_28_exec;end__gm_req <= 0;end__state_28_exec: begin__state <= __state_29_exec;__sig_13 <= __gm_di;end__state_29_exec: begin__state <= __state_30_req;__sig_mul_6 <= __sig_13 * __sig_12;end__state_30_req: begin__state <= __state_30_wait;__gm_req <= 1;__gm_rnw <= 0;__gm_adrs <= (__sig_arrayidx2_6);__gm_leng <= 3;__gm_do <= __sig_mul_6;end__state_30_wait: beginif((__gm_done == 1)) begin__state <= __state_30_exec;end__gm_req <= 0;end__state_30_exec: begin__state <= __state_31_req;end__state_31_req: begin__state <= __state_31_wait;__gm_req <= 1;__gm_rnw <= 1;__gm_adrs <= (__sig_arrayidx_7);__gm_leng <= 3;end__state_31_wait: beginif((__gm_done == 1)) begin__state <= __state_31_exec;end__gm_req <= 0;end__state_31_exec: begin__state <= __state_32_req;__sig_14 <= __gm_di;end__state_32_req: begin__state <= __state_32_wait;__gm_req <= 1;__gm_rnw <= 1;__gm_adrs <= (__sig_arrayidx1_7);__gm_leng <= 3;end__state_32_wait: beginif((__gm_done == 1)) begin__state <= __state_32_exec;end__gm_req <= 0;end__state_32_exec: begin__state <= __state_33_exec;__sig_15 <= __gm_di;end__state_33_exec: begin__state <= __state_34_req;__sig_mul_7 <= __sig_15 * __sig_14;end__state_34_req: begin__state <= __state_34_wait;__gm_req <= 1;__gm_rnw <= 0;__gm_adrs <= (__sig_arrayidx2_7);__gm_leng <= 3;__gm_do <= __sig_mul_7;end__state_34_wait: beginif((__gm_done == 1)) begin__state <= __state_34_exec;end__gm_req <= 0;end__state_34_exec: begin__state <= __state_35_req;end__state_35_req: begin__state <= __state_35_wait;__gm_req <= 1;__gm_rnw <= 1;__gm_adrs <= (__sig_arrayidx_8);__gm_leng <= 3;end__state_35_wait: beginif((__gm_done == 1)) begin__state <= __state_35_exec;end__gm_req <= 0;end__state_35_exec: begin__state <= __state_36_req;__sig_16 <= __gm_di;end__state_36_req: begin__state <= __state_36_wait;__gm_req <= 1;__gm_rnw <= 1;__gm_adrs <= (__sig_arrayidx1_8);__gm_leng <= 3;end__state_36_wait: beginif((__gm_done == 1)) begin__state <= __state_36_exec;end__gm_req <= 0;end__state_36_exec: begin__state <= __state_37_exec;__sig_17 <= __gm_di;end__state_37_exec: begin__state <= __state_38_req;__sig_mul_8 <= __sig_17 * __sig_16;end__state_38_req: begin__state <= __state_38_wait;__gm_req <= 1;__gm_rnw <= 0;__gm_adrs <= (__sig_arrayidx2_8);__gm_leng <= 3;__gm_do <= __sig_mul_8;end__state_38_wait: beginif((__gm_done == 1)) begin__state <= __state_38_exec;end__gm_req <= 0;end__state_38_exec: begin__state <= __state_39_req;end__state_39_req: begin__state <= __state_39_wait;__gm_req <= 1;__gm_rnw <= 1;__gm_adrs <= (__sig_arrayidx_9);__gm_leng <= 3;end__state_39_wait: beginif((__gm_done == 1)) begin__state <= __state_39_exec;end__gm_req <= 0;end__state_39_exec: begin__state <= __state_40_req;__sig_18 <= __gm_di;end__state_40_req: begin__state <= __state_40_wait;__gm_req <= 1;__gm_rnw <= 1;__gm_adrs <= (__sig_arrayidx1_9);__gm_leng <= 3;end__state_40_wait: beginif((__gm_done == 1)) begin__state <= __state_40_exec;end__gm_req <= 0;end__state_40_exec: begin__state <= __state_41_exec;__sig_19 <= __gm_di;end__state_41_exec: begin__state <= __state_42_req;__sig_mul_9 <= __sig_19 * __sig_18;end__state_42_req: begin__state <= __state_42_wait;__gm_req <= 1;__gm_rnw <= 0;__gm_adrs <= (__sig_arrayidx2_9);__gm_leng <= 3;__gm_do <= __sig_mul_9;end__state_42_wait: beginif((__gm_done == 1)) begin__state <= __state_42_exec;end__gm_req <= 0;end__state_42_exec: begin__state <= __state_43_exec;end__state_43_exec: begin__state <= __state_fin_exec;end__state_44_exec: begin__state <= __state_fin_exec;end__state_fin_exec: begin__state <= __state_start_req;__func_ready <= 1;__func_done <= 1;endendcaseendendendmodule
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