で design_name を StereoCamTest に設定した。set design_name StereoCamTest
camera_interface 階層を生成するブロックデザインを選択する必要があるだろうから。。。current_bd_design $design_name
を記述した。create_hier_cell_camera_interface [current_bd_instance .] camera_interface
コマンドを起動して、camera_interface 階層を生成する。source CreateCameraInterface.tcl
# CreateCameraInterface.tcl
#
################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2015.4
set current_vivado_version [version -short]
# CHANGE DESIGN NAME HERE
set design_name StereoCamTest
# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
# create_bd_design $design_name
# Creating design if needed
set errMsg ""
set nRet 0
set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]
puts "INFO: Making design <$design_name> as current_bd_design."
current_bd_design $design_name
# Hierarchical cell: camera_interface
proc create_hier_cell_camera_interface { parentCell nameHier } {
if { $parentCell eq "" || $nameHier eq "" } {
puts "ERROR: create_hier_cell_camera_interface() - Empty argument(s)!"
return
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
puts "ERROR: Unable to find parent cell <$parentCell>!"
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create cell and set as current instance
set hier_obj [create_bd_cell -type hier $nameHier]
current_bd_instance $hier_obj
# Create interface pins
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 IIC
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_S2MM
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI_CTRL
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI_CTRL1
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI_LITE
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_AXILiteS
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_lite1
# Create pins
create_bd_pin -dir I -from 0 -to 0 -type rst aresetn
create_bd_pin -dir I -from 7 -to 0 cam_data
create_bd_pin -dir I href
create_bd_pin -dir I pclk
create_bd_pin -dir I pclk_from_pll
create_bd_pin -dir I -type clk s_axi_aclk
create_bd_pin -dir I -from 0 -to 0 -type rst s_axi_aresetn
create_bd_pin -dir O standby
create_bd_pin -dir I vsync
create_bd_pin -dir O xck
# Create instance: axi_iic_0, and set properties
set axi_iic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_0 ]
# Create instance: axi_vdma_0, and set properties
set axi_vdma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.2 axi_vdma_0 ]
set_property -dict [ list \
CONFIG.c_include_mm2s {0} \
CONFIG.c_m_axi_mm2s_data_width {64} \
CONFIG.c_mm2s_genlock_mode {0} \
CONFIG.c_mm2s_max_burst_length {8} \
] $axi_vdma_0
# Create instance: axis_switch_0, and set properties
set axis_switch_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_0 ]
set_property -dict [ list \
CONFIG.DECODER_REG {0} \
CONFIG.NUM_MI {1} \
CONFIG.NUM_SI {2} \
CONFIG.ROUTING_MODE {1} \
] $axis_switch_0
# Create instance: axis_switch_1, and set properties
set axis_switch_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_1 ]
set_property -dict [ list \
CONFIG.DECODER_REG {1} \
CONFIG.NUM_MI {2} \
CONFIG.NUM_SI {1} \
CONFIG.ROUTING_MODE {1} \
] $axis_switch_1
# Create instance: lap_filter_axis_0, and set properties
set lap_filter_axis_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:lap_filter_axis:1.0 lap_filter_axis_0 ]
# Create instance: mt9d111_inf_axis_0, and set properties
set mt9d111_inf_axis_0 [ create_bd_cell -type ip -vlnv marsee:user:mt9d111_inf_axis:1.0 mt9d111_inf_axis_0 ]
# Create interface connections
connect_bd_intf_net -intf_net axi_iic_0_IIC [get_bd_intf_pins IIC] [get_bd_intf_pins axi_iic_0/IIC]
connect_bd_intf_net -intf_net axi_vdma_0_M_AXI_S2MM [get_bd_intf_pins M_AXI_S2MM] [get_bd_intf_pins axi_vdma_0/M_AXI_S2MM]
connect_bd_intf_net -intf_net axis_switch_0_M00_AXIS [get_bd_intf_pins axi_vdma_0/S_AXIS_S2MM] [get_bd_intf_pins axis_switch_0/M00_AXIS]
connect_bd_intf_net -intf_net axis_switch_1_M00_AXIS [get_bd_intf_pins axis_switch_0/S00_AXIS] [get_bd_intf_pins axis_switch_1/M00_AXIS]
connect_bd_intf_net -intf_net axis_switch_1_M01_AXIS [get_bd_intf_pins axis_switch_1/M01_AXIS] [get_bd_intf_pins lap_filter_axis_0/ins]
connect_bd_intf_net -intf_net lap_filter_axis_0_outs [get_bd_intf_pins axis_switch_0/S01_AXIS] [get_bd_intf_pins lap_filter_axis_0/outs]
connect_bd_intf_net -intf_net mt9d111_inf_axis_0_m_axis [get_bd_intf_pins axis_switch_1/S00_AXIS] [get_bd_intf_pins mt9d111_inf_axis_0/m_axis]
connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M00_AXI [get_bd_intf_pins s_axi_lite1] [get_bd_intf_pins mt9d111_inf_axis_0/s_axi_lite]
connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M01_AXI [get_bd_intf_pins S_AXI] [get_bd_intf_pins axi_iic_0/S_AXI]
connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M02_AXI [get_bd_intf_pins s_axi_AXILiteS] [get_bd_intf_pins lap_filter_axis_0/s_axi_AXILiteS]
connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M04_AXI [get_bd_intf_pins S_AXI_LITE] [get_bd_intf_pins axi_vdma_0/S_AXI_LITE]
connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M05_AXI [get_bd_intf_pins S_AXI_CTRL] [get_bd_intf_pins axis_switch_0/S_AXI_CTRL]
connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M06_AXI [get_bd_intf_pins S_AXI_CTRL1] [get_bd_intf_pins axis_switch_1/S_AXI_CTRL]
# Create port connections
connect_bd_net -net cam_data_1 [get_bd_pins cam_data] [get_bd_pins mt9d111_inf_axis_0/cam_data]
connect_bd_net -net href_1 [get_bd_pins href] [get_bd_pins mt9d111_inf_axis_0/href]
connect_bd_net -net mt9d111_inf_axis_0_standby [get_bd_pins standby] [get_bd_pins mt9d111_inf_axis_0/standby]
connect_bd_net -net mt9d111_inf_axis_0_xck [get_bd_pins xck] [get_bd_pins mt9d111_inf_axis_0/xck]
connect_bd_net -net pclk_1 [get_bd_pins pclk] [get_bd_pins mt9d111_inf_axis_0/pclk]
connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins s_axi_aclk] [get_bd_pins axi_iic_0/s_axi_aclk] [get_bd_pins axi_vdma_0/m_axi_s2mm_aclk] [get_bd_pins axi_vdma_0/s_axi_lite_aclk] [get_bd_pins axi_vdma_0/s_axis_s2mm_aclk] [get_bd_pins axis_switch_0/aclk] [get_bd_pins axis_switch_0/s_axi_ctrl_aclk] [get_bd_pins axis_switch_1/aclk] [get_bd_pins axis_switch_1/s_axi_ctrl_aclk] [get_bd_pins lap_filter_axis_0/ap_clk] [get_bd_pins mt9d111_inf_axis_0/m_axis_aclk] [get_bd_pins mt9d111_inf_axis_0/s_axi_lite_aclk]
connect_bd_net -net processing_system7_0_FCLK_CLK2 [get_bd_pins pclk_from_pll] [get_bd_pins mt9d111_inf_axis_0/pclk_from_pll]
connect_bd_net -net rst_processing_system7_0_100M_interconnect_aresetn [get_bd_pins aresetn] [get_bd_pins axis_switch_0/aresetn] [get_bd_pins axis_switch_1/aresetn]
connect_bd_net -net rst_processing_system7_0_100M_peripheral_aresetn [get_bd_pins s_axi_aresetn] [get_bd_pins axi_iic_0/s_axi_aresetn] [get_bd_pins axi_vdma_0/axi_resetn] [get_bd_pins axis_switch_0/s_axi_ctrl_aresetn] [get_bd_pins axis_switch_1/s_axi_ctrl_aresetn] [get_bd_pins lap_filter_axis_0/ap_rst_n] [get_bd_pins mt9d111_inf_axis_0/axi_resetn]
connect_bd_net -net vsync_1 [get_bd_pins vsync] [get_bd_pins mt9d111_inf_axis_0/vsync]
# Restore current instance
current_bd_instance $oldCurInst
}
# Create instance: camera_interface
create_hier_cell_camera_interface [current_bd_instance .] camera_interface
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