// vflip_dma_write2.h
// 2019/01/28 by marsee
//
#ifndef __VFLIP_DMA_WRITE2_H__
#define __VFLIP_DMA_WRITE2_H__
#include "ap_axi_sdata.h"
#include "hls_video.h"
#define SVGA_WIDTH 800
#define SVGA_HEIGHT 600
#define SVGA_START_OFFSET 0
#define XGA_WIDTH 1024
#define XGA_HEIGHT 768
#define XGA_START_OFFSET (((XGA_HEIGHT-SVGA_HEIGHT)/2)*XGA_WIDTH+(XGA_WIDTH-SVGA_WIDTH)/2)
#define XGA_STRIDE (XGA_WIDHT-SVGA_WIDTH)
#define HD_WIDTH 1920
#define HD_HEIGHT 1080
#define HD_START_OFFSET (((HD_HEIGHT-SVGA_HEIGHT)/2)*HD_WIDTH+(HD_WIDTH-SVGA_WIDTH)/2)
#define HD_STRIDE (HD_WIDHT-SVGA_WIDTH)
#define RESO_SVGA 0
#define RESO_XGA 1
#define RESO_HD 2
typedef hls::stream<ap_axiu<32,1,1,1> > AXI_STREAM;
typedef ap_axiu<32,1,1,1> AP_AXIU32;
typedef hls::Scalar<3, unsigned char> RGB_PIXEL;
typedef hls::Mat<HD_HEIGHT, HD_WIDTH, HLS_8UC3> RGB_IMAGE;
typedef hls::Mat<HD_HEIGHT, HD_WIDTH, HLS_8UC1> GRAY_IMAGE;
#endif
// vflip_dma_write2.cpp
// 2019/01/28 by marsee
//
#include <ap_int.h>
#include <hls_stream.h>
#include <ap_axi_sdata.h>
#include "vflip_dma_write2.h"
int vflip_dma_write2(AXI_STREAM & ins,
volatile ap_int<32> *fb0, volatile ap_int<32> *fb1, volatile ap_int<32> *fb2,
ap_uint<32> &resolution, volatile ap_uint<2> &active_frame){
#pragma HLS INTERFACE s_axilite port=resolution
#pragma HLS INTERFACE ap_none port=active_frame
#pragma HLS INTERFACE m_axi depth=480000 port=fb0 offset=slave
#pragma HLS INTERFACE m_axi depth=480000 port=fb1 offset=slave
#pragma HLS INTERFACE m_axi depth=480000 port=fb2 offset=slave
#pragma HLS INTERFACE axis register both port=ins
#pragma HLS INTERFACE s_axilite port=return
AP_AXIU32 pix;
int max_fb_chk;
int max_width, max_height;
int start_offset;
int stride;
active_frame = 0;
switch((int)resolution){
case 0: // SVGA
start_offset = SVGA_START_OFFSET;
max_width = SVGA_WIDTH;
max_height = SVGA_HEIGHT;
break;
case 1: // XGA
start_offset = XGA_START_OFFSET;
max_width = XGA_WIDTH;
max_height = XGA_HEIGHT;
break;
default: // HD
start_offset = HD_START_OFFSET;
max_width = HD_WIDTH;
max_height = HD_HEIGHT;
break;
}
LOOP_WAIT0: do { // user が 1になった時にフレームがスタートする
#pragma HLS LOOP_TRIPCOUNT min=1 max=1 avg=1
ins >> pix;
} while(pix.user == 0);
LOOP_Y0: for (int y=SVGA_HEIGHT-1; y>=0; y--){ // vflip
LOOP_X0: for (int x=0; x<SVGA_WIDTH; x++){
#pragma HLS PIPELINE II=1
if (!(x==0 && y==0)) // 最初の入力はすでに入力されている
ins >> pix; // AXI4-Stream からの入力
fb0[start_offset + (y*max_width)+x] = pix.data;
}
}
active_frame = 1;
LOOP_WAIT1: do { // user が 1になった時にフレームがスタートする
#pragma HLS LOOP_TRIPCOUNT min=1 max=1 avg=1
ins >> pix;
} while(pix.user == 0);
LOOP_Y1: for (int y=SVGA_HEIGHT-1; y>=0; y--){ // vflip
LOOP_X1: for (int x=0; x<SVGA_WIDTH; x++){
#pragma HLS PIPELINE II=1
if (!(x==0 && y==0)) // 最初の入力はすでに入力されている
ins >> pix; // AXI4-Stream からの入力
fb1[start_offset + (y*max_width)+x] = pix.data;
}
}
active_frame = 2;
LOOP_WAIT2: do { // user が 1になった時にフレームがスタートする
#pragma HLS LOOP_TRIPCOUNT min=1 max=1 avg=1
ins >> pix;
} while(pix.user == 0);
LOOP_Y2: for (int y=SVGA_HEIGHT-1; y>=0; y--){ // vflip
LOOP_X2: for (int x=0; x<SVGA_WIDTH; x++){
#pragma HLS PIPELINE II=1
if (!(x==0 && y==0)) // 最初の入力はすでに入力されている
ins >> pix; // AXI4-Stream からの入力
fb2[start_offset + (y*max_width)+x] = pix.data;
}
}
end:
return(0);
}
// vflip_dma_write2_tb.cpp
// 2019/01/28 by marsee
//
#include <ap_int.h>
#include <hls_stream.h>
#include <iostream>
#include <fstream>
#include "hls_opencv.h"
#include "vflip_dma_write2.h"
int vflip_dma_write2(AXI_STREAM & ins,
volatile ap_int<32> *fb0, volatile ap_int<32> *fb1, volatile ap_int<32> *fb2,
ap_uint<32> &resolution, volatile ap_uint<2> &active_frame);
int vflip_dmaw(AXI_STREAM &ins, int width, int height, ap_uint<32> resolution,
char *output_file0, char *output_file1, char *output_file2);
#define NUM_FRAME_BUFFER 3
int main()
{
using namespace cv;
AXI_STREAM ins0, ins1;
AP_AXIU32 pix;
ap_uint<32> resolution;
// OpenCV で 画像を読み込む
Mat src = imread("bmp_file0_vflip.bmp");
AXI_STREAM src_axi, dst_axi;
// Mat フォーマットから AXI4 Stream へ変換、3画面分
for(int i=0; i<NUM_FRAME_BUFFER; i++){
cvMat2AXIvideo(src, src_axi);
for (int y=0; y<SVGA_HEIGHT; y++){
for (int x=0; x<SVGA_WIDTH; x++){
src_axi >> pix;
ins0 << pix;
ins1 << pix;
}
}
}
char output_file0[] = "xga_result0.bmp";
char output_file1[] = "xga_result1.bmp";
char output_file2[] = "xga_result2.bmp";
resolution = RESO_XGA;
vflip_dmaw(ins0, XGA_WIDTH, XGA_HEIGHT, resolution, output_file0, output_file1, output_file2);
char output_file3[] = "hd_result0.bmp";
char output_file4[] = "hd_result1.bmp";
char output_file5[] = "hd_result2.bmp";
resolution = RESO_HD;
vflip_dmaw(ins1, HD_WIDTH, HD_HEIGHT, resolution, output_file3, output_file4, output_file5);
return(0);
}
int vflip_dmaw(AXI_STREAM &ins, int width, int height, ap_uint<32> resolution,
char *output_file0, char *output_file1, char *output_file2){
using namespace cv;
ap_uint<2> active_frame;
ap_uint<32> *frame_buffer;
// frame buffer をアロケートする、3倍の領域を取ってそれを3つに分ける
if ((frame_buffer =(ap_uint<32> *)malloc(NUM_FRAME_BUFFER * sizeof(ap_int<32>) * (width * height))) == NULL){
fprintf(stderr, "Can't allocate frame_buffer0 ~ 2\n");
exit(1);
}
for(int i=0; i<NUM_FRAME_BUFFER; i++){ // 0 clear
for (int y=0; y<height; y++){
for (int x=0; x<width; x++){
frame_buffer[i*(width * height)+y*width+x] = 0;
}
}
}
vflip_dma_write2(ins, (volatile ap_int<32> *)frame_buffer,
(volatile ap_int<32> *)&frame_buffer[width * height],
(volatile ap_int<32> *)&frame_buffer[2 * (width * height)],
resolution, active_frame);
// AXI4 Stream から Mat フォーマットへ変換
// dst は宣言時にサイズとカラー・フォーマットを定義する必要がある
Mat dst[3];
for(int i=0; i<NUM_FRAME_BUFFER; i++){
dst[i] = Mat(height, width, CV_8UC3);
}
// dst[i] にframe_bufferから画像データをロード
for(int i=0; i<NUM_FRAME_BUFFER; i++){
Mat_<Vec3b> dst_vec3b = Mat_<Vec3b>(dst[i]);
for(int y=0; y<dst[i].rows; y++){
for(int x=0; x<dst[i].cols; x++){
Vec3b pixel;
int rgb = frame_buffer[i*(width * height)+y*width+x];
pixel[0] = (rgb & 0xff); // blue
pixel[1] = (rgb & 0xff00) >> 8; // green
pixel[2] = (rgb & 0xff0000) >> 16; // red
dst_vec3b(y,x) = pixel;
}
}
}
// DMAされたデータをBMPフィルに書き込む
char output_file[100];
for (int i=0; i<NUM_FRAME_BUFFER; i++){
switch (i){
case 0:
strcpy(output_file, output_file0);
break;
case 1:
strcpy(output_file, output_file1);
break;
case 2:
strcpy(output_file, output_file2);
break;
}
// Mat フォーマットからファイルに書き込み
imwrite(output_file, dst[i]);
}
free(frame_buffer);
return(0);
}
1. SVGA解像度のカメラ画像を黒枠付けて異なる解像度に表示
2. SVGA解像度のカメラ画像を拡大して異なる解像度に表示
3. カメラ画像をカメラのI2C設定で設定を変更し、その解像度で出力
create_clock -period 6.734 -name disp_clk -waveform {0.000 3.367} [get_pins displayport_test_i/zynq_ultra_ps_e_0/dp_video_ref_clk]
#set_property PACKAGE_PIN D7 [get_ports {red[0]}]
#set_property PACKAGE_PIN F8 [get_ports {red[1]}]
#set_property PACKAGE_PIN F7 [get_ports {red[2]}]
#set_property PACKAGE_PIN G7 [get_ports {red[3]}]
#set_property PACKAGE_PIN F6 [get_ports {blue[0]}]
#set_property PACKAGE_PIN G5 [get_ports {blue[1]}]
#set_property PACKAGE_PIN A6 [get_ports {blue[2]}]
#set_property PACKAGE_PIN A7 [get_ports {blue[3]}]
#set_property PACKAGE_PIN G6 [get_ports {green[0]}]
#set_property PACKAGE_PIN E6 [get_ports {green[1]}]
#set_property PACKAGE_PIN E5 [get_ports {green[2]}]
#set_property PACKAGE_PIN D6 [get_ports {green[3]}]
#set_property PACKAGE_PIN D5 [get_ports {hsyncx[0]}]
#set_property PACKAGE_PIN C7 [get_ports {vsyncx[0]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {blue[3]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {blue[2]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {blue[1]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {blue[0]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {hsyncx[0]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {vsyncx[0]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {green[3]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {green[2]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {green[1]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {green[0]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {red[3]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {red[2]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {red[1]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {red[0]}]
set_false_path -from [get_clocks clk_pl_0] -to [get_clocks disp_clk]
set_false_path -from [get_clocks disp_clk] -to [get_clocks clk_pl_0]
/dts-v1/;/plugin/;
/ {
fragment@0 {
target-path = "/amba";
__overlay__ {
fclk0 {
compatible = "ikwzm,fclkcfg-0.10.a";
clocks = <&clk 0x47>;
insert-rate = "200000000";
insert-enable = <1>;
remove-rate = "1000000";
remove-enable = <0>;
};
};
};
};
#!/bin/bash
dtc -I dts -O dtb -o fpga-load.dtb fpga-load.dts
dtc -I dts -O dtb -o fclk0-zynqmp.dtb fclk0-zynqmp.dts
dtc -I dts -O dtb -o pattern_gen_axis.dtb pattern_gen_axis.dts
// pattern_gen_axis.c
// 2019/01/18 by marsee
//
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <unistd.h>
#include <assert.h>
#include <sys/mman.h>
#include <fcntl.h>
#include <unistd.h>
int main(){
int fd1;
volatile unsigned *pga;
int i, val;
// uio initialize (uio1)
fd1 = open("/dev/uio1", O_RDWR|O_SYNC); // pattern_gen_axis IP
if (fd1 < 1){
fprintf(stderr, "/dev/uio1 (pattern_gen_axis) open error\n");
exit(1);
}
pga = (volatile unsigned *)mmap(NULL, 0x10000, PROT_READ|PROT_WRITE, MAP_SHARED, fd1, 0);
if (!pga){
fprintf(stderr, "pattern_gen_axis mmap error\n");
exit(1);
}
pga[8] = 0x1; // init_done = 1
while(1){
printf("h_size = ");
scanf("%d", &val);
if(val == 9999)
break;
pga[6] = val; // h_size
printf("v_size = ");
scanf("%d", &val);
pga[4] = val;
printf("v_size = %d, h_size = %d\n\n", pga[4], pga[6]);
}
munmap((void *)pga, 0x10000);
close(fd1);
return(0);
}
// IP start State Machine
always @(posedge axi_clk) begin
if (!axi_rst_n) begin
cs_start <= IDLE_START;
ip_start <= 1'b0;
end else begin
case (cs_start)
IDLE_START : begin
ip_start <= 1'b0;
if (vsync_falling_edge_axi)
cs_start <= IP_START_1;
end
IP_START_1 : begin
ip_start <= 1'b1;
if (ip_done)
cs_start <= IDLE_START;
end
endcase
end
end
// IP start State Machine
always @(posedge axi_clk) begin
if (!axi_rst_n) begin
cs_start <= IDLE_START;
ip_start <= 1'b0;
end else begin
case (cs_start)
IDLE_START : begin
ip_start <= 1'b0;
if (vsync_falling_edge_axi) begin
cs_start <= IP_START_1;
ip_start <= 1'b1;
end
end
IP_START_1 : begin
if (ip_done) begin
cs_start <= IDLE_START;
ip_start <= 1'b0;
end
end
endcase
end
end
// axis2video_out.v
// 2019/01/14 by marsee
// 2019/01/23 : Fixed IP start state machine bug
//
`default_nettype none
module axis2video_out
(
// Clock and Reset
input wire disp_clk,
input wire axi_clk,
input wire axi_rst_n,
input wire init_done,
// AXI4-Stream
input wire [31:0] axis_tdata,
input wire axis_tvalid,
output wire axis_tready,
input wire [3:0] axis_tkeep,
input wire [3:0] axis_tstrb,
input wire axis_tuser,
input wire axis_tlast,
input wire axis_tid,
input wire axis_tdest,
// IP
output reg ip_start,
input wire ip_done,
// video in
input wire de_in,
input wire vsync_in,
input wire hsync_in,
// video_out
output wire [35:0] disp_pixel,
output wire de_out,
output wire vsync_out,
output wire hsync_out
);
parameter IDLE_START = 1'b0,
IP_START_1 = 1'b1;
reg reset_disp_2b = 1'b1, reset_disp_1b = 1'b1;
wire reset_disp;
reg fifo_reset_axi_2b = 1'b0, fifo_reset_axi_1b = 1'b0;
wire fifo_reset_axi;
reg fifo_reset_disp_2b = 1'b0, fifo_reset_disp_1b = 1'b0;
wire fifo_reset_disp;
reg de_1d, vsync_1d, hsync_1d;
reg vsync_axi_1b, vsync_axi_2b;
wire vsync_axi;
reg vsync_axi_1d, vsync_axi_2d;
reg cs_start;
wire pfifo_empty, pfifo_full;
wire [33:0] pfifo_dout;
reg vsync_rising_edge_axi, vsync_falling_edge_axi;
always @(posedge disp_clk) begin
if(reset_disp) begin
de_1d <= 1'b0;
vsync_1d <= 1'b0;
hsync_1d <= 1'b0;
end else begin
de_1d <= de_in;
vsync_1d <= vsync_in;
hsync_1d <= hsync_in;
end
end
// reset signals
always @(posedge axi_clk) begin
fifo_reset_axi_2b <= ~init_done | ~axi_rst_n | vsync_1d;
fifo_reset_axi_1b <= fifo_reset_axi_2b;
end
assign fifo_reset_axi = fifo_reset_axi_1b;
always @(posedge disp_clk) begin
fifo_reset_disp_2b <= ~init_done | ~axi_rst_n | vsync_1d;
fifo_reset_disp_1b <= fifo_reset_disp_2b;
end
assign fifo_reset_disp = fifo_reset_disp_1b;
always @(posedge disp_clk) begin
reset_disp_2b <= ~init_done | ~axi_rst_n;
reset_disp_1b <= reset_disp_2b;
end
assign reset_disp = reset_disp_1b;
// vsync_rising_edge, vsync_falling_edge
always @(posedge axi_clk) begin
if (!axi_rst_n) begin
vsync_axi_2b <= 1'b1;
vsync_axi_1b <= 1'b1;
end else begin
vsync_axi_2b <= vsync_1d;
vsync_axi_1b <= vsync_axi_2b;
end
end
assign vsync_axi = vsync_axi_1b;
always @(posedge axi_clk) begin
if (!axi_rst_n) begin
vsync_axi_1d <= 1'b1;
vsync_axi_2d <= 1'b1;
end else begin
vsync_axi_1d <= vsync_axi;
vsync_axi_2d <= vsync_axi_1d;
end
end
always @(posedge axi_clk) begin
if (!axi_rst_n) begin
vsync_rising_edge_axi = 1'b0;
vsync_falling_edge_axi = 1'b0;
end else begin
vsync_rising_edge_axi <= ~vsync_axi_2d & vsync_axi_1d;
vsync_falling_edge_axi <= vsync_axi_2d & ~vsync_axi_1d;
end
end
// IP start State Machine
always @(posedge axi_clk) begin
if (!axi_rst_n) begin
cs_start <= IDLE_START;
ip_start <= 1'b0;
end else begin
case (cs_start)
IDLE_START : begin
ip_start <= 1'b0;
if (vsync_falling_edge_axi) begin
cs_start <= IP_START_1;
ip_start <= 1'b1;
end
end
IP_START_1 : begin
if (ip_done) begin
cs_start <= IDLE_START;
ip_start <= 1'b0;
end
end
endcase
end
end
// data width 34 bits, 512 depth
pixel_fifo pixel_fifo_i (
.wr_rst(fifo_reset_axi),
.wr_clk(axi_clk),
.rd_rst(fifo_reset_disp),
.rd_clk(disp_clk),
.din({axis_tuser, axis_tlast, axis_tdata}),
.dout(pfifo_dout),
.wr_en(~pfifo_full & axis_tvalid),
.full(pfifo_full),
.rd_en(de_1d),
.empty(pfifo_empty)
);
assign axis_tready = ~pfifo_full;
assign disp_pixel = {pfifo_dout[7:0], 4'd0, pfifo_dout[23:16], 4'd0, pfifo_dout[15:8], 4'd0}; //BRG
assign de_out = de_1d;
assign vsync_out = vsync_1d;
assign hsync_out = hsync_1d;
endmodule
`default_nettype wire
#!/bin/bash
sudo mkdir /config/device-tree/overlays/fpga
sudo cp fpga-load.dtb /config/device-tree/overlays/fpga/dtbo
sudo mkdir /config/device-tree/overlays/fclk0
sudo cp fclk0-zynqmp.dtb /config/device-tree/overlays/fclk0/dtbo
sudo mkdir /config/device-tree/overlays/pattern_gen_axis
sudo cp pattern_gen_axis.dtb /config/device-tree/overlays/pattern_gen_axis/dtbo
sleep 0.5
sudo chmod 666 /dev/uio*
#!/bin/bash
sudo rmdir /config/device-tree/overlays/pattern_gen_axis/
sudo rmdir /config/device-tree/overlays/fclk0
sudo rmdir /config/device-tree/overlays/fpga/
/dts-v1/;
/ {
fragment@0 {
target-path = "/fpga-full";
__overlay__ {
firmware-name = "displayport_test_xga1_sync.bin";
};
};
};
/dts-v1/;/plugin/;
/ {
fragment@0 {
target-path = "/amba";
__overlay__ {
fclk0 {
compatible = "ikwzm,fclkcfg-0.10.a";
clocks = <&clk 0x47>;
insert-rate = "100000000";
insert-enable = <1>;
remove-rate = "1000000";
remove-enable = <0>;
};
};
};
};
/dts-v1/;/plugin/;
/ {
fragment@0 {
target-path = "/amba_pl@0";
#address-cells = <2>;
#size-cells = <2>;
__overlay__ {
#address-cells = <2>;
#size-cells = <2>;
pattern_gen_axis-uio {
compatible = "generic-uio";
reg = <0x0 0xA0000000 0x0 0x10000>;
};
};
};
};
// pattern_gen_axis.c
// 2019/01/18 by marsee
//
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <unistd.h>
#include <assert.h>
#include <sys/mman.h>
#include <fcntl.h>
#include <unistd.h>
int main(){
int fd1;
volatile unsigned *pga;
int i;
// uio initialize (uio1)
fd1 = open("/dev/uio1", O_RDWR|O_SYNC); // pattern_gen_axis IP
if (fd1 < 1){
fprintf(stderr, "/dev/uio1 (pattern_gen_axis) open error\n");
exit(1);
}
pga = (volatile unsigned *)mmap(NULL, 0x10000, PROT_READ|PROT_WRITE, MAP_SHARED, fd1, 0);
if (!pga){
fprintf(stderr, "pattern_gen_axis mmap error\n");
exit(1);
}
pga[4] = 768; // v_size
pga[6] = 1024; // h_size
pga[8] = 0x1; // init_done = 1
printf("sizeof volatile unsigned = %d\n", sizeof(volatile unsigned));
printf("v_size = %d, h_size = %d, init_done = %d\n", pga[4], pga[6], pga[8]);
munmap((void *)pga, 0x10000);
close(fd1);
return(0);
}
#!/bin/bash
sudo ./memwrite fd4ab070 54
sudo ./memwrite fd4aa00c ff
#!/bin/bash
bootgen -image displayport_test_wrapper.bif -arch zynqmp -w -o displayport_test_xga1_sync.bin
all:
{
[destination_device = pl] displayport_test_wrapper.bit
}
// XGA_sync_gen.cpp
// 2019/01/20 by marsee
//
#include <stdio.h>
#include <string.h>
#include <ap_int.h>
#include "ap_utils.h"
// XGA 解像度 65 MHz
#define H_ACTIVE_VIDEO 1024
#define H_FRONT_PORCH 24
#define H_SYNC_PULSE 136
#define H_BACK_PORCH 160
#define H_SUM (H_ACTIVE_VIDEO + H_FRONT_PORCH + H_SYNC_PULSE + H_BACK_PORCH)
#define V_ACTIVE_VIDEO 768
#define V_FRONT_PORCH 2
#define V_SYNC_PULSE 6
#define V_BACK_PORCH 29
#define V_SUM (V_ACTIVE_VIDEO + V_FRONT_PORCH + V_SYNC_PULSE + V_BACK_PORCH)
void XGA_sync_gen(ap_uint<1> &de, ap_uint<1> &hsync, ap_uint<1> &vsync){
#pragma HLS INTERFACE ap_none port=vsyncx
#pragma HLS INTERFACE ap_none port=hsyncx
#pragma HLS INTERFACE ap_none port=de
#pragma HLS INTERFACE ap_ctrl_hs port=return
ap_uint<16> h_count, v_set, v_count;
static int flag = 0;
if(flag == 0){
v_set = 768;
flag = 1;
}else{
v_set = 0;
}
for (v_count=v_set; v_count<V_SUM; v_count++){
for (h_count=0; h_count<H_SUM; h_count++){
#pragma HLS PIPELINE II=1 rewind
if (h_count >= (H_ACTIVE_VIDEO +H_FRONT_PORCH) && h_count < (H_ACTIVE_VIDEO + H_FRONT_PORCH + H_SYNC_PULSE))
hsync = 1;
else
hsync = 0;
if (v_count >= (V_ACTIVE_VIDEO + V_FRONT_PORCH) && v_count < (V_ACTIVE_VIDEO + V_FRONT_PORCH + V_SYNC_PULSE))
vsync = 1;
else
vsync = 0;
if (h_count < H_ACTIVE_VIDEO && v_count < V_ACTIVE_VIDEO)
de = 1;
else
de = 0;
}
}
}
// XGA_sync_gen.cpp
// 2019/01/20 by marsee
//
#include <stdio.h>
#include <string.h>
#include <ap_int.h>
void XGA_sync_gen(ap_uint<1> &de, ap_uint<1> &hsyncx, ap_uint<1> &vsyncx);
int main(){
ap_uint<1> de;
ap_uint<1> hsyncx;
ap_uint<1> vsyncx;
XGA_sync_gen(de, hsyncx, vsyncx);
XGA_sync_gen(de, hsyncx, vsyncx);
return 0;
}
`default_nettype none
`timescale 100ps / 1ps
// axis2video_out_tb.v
// 2019/01/17 by marsee
//
module axis2video_out_tb;
reg axi_clk;
reg axi_rst_n;
wire ip_start;
wire ip_done;
wire [31:0] TDATA;
wire TVALID;
wire TREADY;
wire [3:0] TKEEP;
wire [3:0] TSTRB;
wire TUSER;
wire TLAST;
wire TID;
wire TDEST;
reg init_done;
wire init_done_out;
reg disp_clk;
wire de_in;
wire vsync_in;
wire hsync_in;
wire [35:0] disp_pixel;
wire de_out;
wire vsync_out;
wire hsync_out;
reg ap_start;
// pattern_gen_axis instance
pattern_gen_axis pga_inst(
.ap_clk(axi_clk),
.ap_rst_n(axi_rst_n),
.ap_start(ip_start),
.ap_done(ip_done),
.ap_idle(),
.ap_ready(),
.outs_TDATA(TDATA),
.outs_TVALID(TVALID),
.outs_TREADY(TREADY),
.outs_TKEEP(TKEEP),
.outs_TSTRB(TSTRB),
.outs_TUSER(TUSER),
.outs_TLAST(TLAST),
.outs_TID(TID),
.outs_TDEST(TDEST),
.init_done_V(init_done),
.init_done_out_V(init_done_out),
.ap_return()
);
XGA_sync_gen xgasg (
.ap_clk(disp_clk),
.ap_rst(!axi_rst_n),
.ap_start(ap_start),
.ap_done(),
.ap_idle(),
.ap_ready(),
.de_V(de_in),
.hsync_V(hsync_in),
.vsync_V(vsync_in)
);
// axis2video_out instance
axis2video_out axis2vo_inst(
.disp_clk(disp_clk),
.axi_clk(axi_clk),
.axi_rst_n(axi_rst_n),
.init_done(init_done),
.axis_tdata(TDATA),
.axis_tvalid(TVALID),
.axis_tready(TREADY),
.axis_tkeep(TKEEP),
.axis_tstrb(TSTRB),
.axis_tuser(TUSER),
.axis_tlast(TLAST),
.axis_tid(TID),
.axis_tdest(TDEST),
.ip_start(ip_start),
.ip_done(ip_done),
.de_in(de_in),
.vsync_in(vsync_in),
.hsync_in(hsync_in),
.disp_pixel(disp_pixel),
.de_out(de_out),
.vsync_out(vsync_out),
.hsync_out(hsync_out)
);
// axi_clk = 200 MHz (5 ns)
always #25
axi_clk = ~axi_clk;
// disp_clk = 65 MHz (13.4 ns)
always #77
disp_clk = ~disp_clk;
initial begin
axi_clk = 1'b1;
disp_clk = 1'b1;
axi_rst_n = 1'b0;
init_done = 1'b0;
ap_start = 1'b0;
// Wait 100 ns for global reset to finish
#1000;
axi_rst_n = 1'b1;
#1000;
init_done = 1'b1;
ap_start = 1'b1;
end
endmodule
`default_nettype wire
// axis2video_out.v
// 2019/01/14 by marsee
//
`default_nettype none
module axis2video_out
(
// Clock and Reset
input wire disp_clk,
input wire axi_clk,
input wire axi_rst_n,
input wire init_done,
// AXI4-Stream
input wire [31:0] axis_tdata,
input wire axis_tvalid,
output wire axis_tready,
input wire [3:0] axis_tkeep,
input wire [3:0] axis_tstrb,
input wire axis_tuser,
input wire axis_tlast,
input wire axis_tid,
input wire axis_tdest,
// IP
output reg ip_start,
input wire ip_done,
// video in
input wire de_in,
input wire vsync_in,
input wire hsync_in,
// video_out
output wire [35:0] disp_pixel,
output wire de_out,
output wire vsync_out,
output wire hsync_out
);
parameter IDLE_START = 1'b0,
IP_START_1 = 1'b1;
reg reset_disp_2b = 1'b1, reset_disp_1b = 1'b1;
wire reset_disp;
reg fifo_reset_axi_2b = 1'b0, fifo_reset_axi_1b = 1'b0;
wire fifo_reset_axi;
reg fifo_reset_disp_2b = 1'b0, fifo_reset_disp_1b = 1'b0;
wire fifo_reset_disp;
reg de_1d, vsync_1d, hsync_1d;
reg vsync_axi_1b, vsync_axi_2b;
wire vsync_axi;
reg vsync_axi_1d, vsync_axi_2d;
reg cs_start;
wire pfifo_empty, pfifo_full;
wire [33:0] pfifo_dout;
reg vsync_rising_edge_axi, vsync_falling_edge_axi;
always @(posedge disp_clk) begin
if(reset_disp) begin
de_1d <= 1'b0;
vsync_1d <= 1'b0;
hsync_1d <= 1'b0;
end else begin
de_1d <= de_in;
vsync_1d <= vsync_in;
hsync_1d <= hsync_in;
end
end
// reset signals
always @(posedge axi_clk) begin
fifo_reset_axi_2b <= ~init_done | ~axi_rst_n | vsync_1d;
fifo_reset_axi_1b <= fifo_reset_axi_2b;
end
assign fifo_reset_axi = fifo_reset_axi_1b;
always @(posedge disp_clk) begin
fifo_reset_disp_2b <= ~init_done | ~axi_rst_n | vsync_1d;
fifo_reset_disp_1b <= fifo_reset_disp_2b;
end
assign fifo_reset_disp = fifo_reset_disp_1b;
always @(posedge disp_clk) begin
reset_disp_2b <= ~init_done | ~axi_rst_n;
reset_disp_1b <= reset_disp_2b;
end
assign reset_disp = reset_disp_1b;
// vsync_rising_edge, vsync_falling_edge
always @(posedge axi_clk) begin
if (!axi_rst_n) begin
vsync_axi_2b <= 1'b1;
vsync_axi_1b <= 1'b1;
end else begin
vsync_axi_2b <= vsync_1d;
vsync_axi_1b <= vsync_axi_2b;
end
end
assign vsync_axi = vsync_axi_1b;
always @(posedge axi_clk) begin
if (!axi_rst_n) begin
vsync_axi_1d <= 1'b1;
vsync_axi_2d <= 1'b1;
end else begin
vsync_axi_1d <= vsync_axi;
vsync_axi_2d <= vsync_axi_1d;
end
end
always @(posedge axi_clk) begin
if (!axi_rst_n) begin
vsync_rising_edge_axi = 1'b0;
vsync_falling_edge_axi = 1'b0;
end else begin
vsync_rising_edge_axi <= ~vsync_axi_2d & vsync_axi_1d;
vsync_falling_edge_axi <= vsync_axi_2d & ~vsync_axi_1d;
end
end
// IP start State Machine
always @(posedge axi_clk) begin
if (!axi_rst_n) begin
cs_start <= IDLE_START;
ip_start <= 1'b0;
end else begin
case (cs_start)
IDLE_START : begin
ip_start <= 1'b0;
if (vsync_falling_edge_axi)
cs_start <= IP_START_1;
end
IP_START_1 : begin
ip_start <= 1'b1;
if (ip_done)
cs_start <= IDLE_START;
end
endcase
end
end
// data width 34 bits, 512 depth
pixel_fifo pixel_fifo_i (
.wr_rst(fifo_reset_axi),
.wr_clk(axi_clk),
.rd_rst(fifo_reset_disp),
.rd_clk(disp_clk),
.din({axis_tuser, axis_tlast, axis_tdata}),
.dout(pfifo_dout),
.wr_en(~pfifo_full & axis_tvalid),
.full(pfifo_full),
.rd_en(de_1d),
.empty(pfifo_empty)
);
assign axis_tready = ~pfifo_full;
assign disp_pixel = {pfifo_dout[23:16], 4'd0, pfifo_dout[15:8], 4'd0, pfifo_dout[7:0], 4'd0};
assign de_out = de_1d;
assign vsync_out = vsync_1d;
assign hsync_out = hsync_1d;
endmodule
`default_nettype wire
// axis2video_out.v
// 2019/01/14 by marsee
//
`default_nettype none
module axis2video_out
(
// Clock and Reset
input wire disp_clk,
input wire axi_clk,
input wire axi_rst_n,
input wire init_done,
// AXI4-Stream
input wire [31:0] axis_tdata,
input wire axis_tvalid,
output wire axis_tready,
input wire [3:0] axis_tkeep,
input wire [3:0] axis_tstrb,
input wire axis_tuser,
input wire axis_tlast,
input wire axis_tid,
input wire axis_tdest,
// IP
output reg ip_start,
input wire ip_done,
// video in
input wire de_in,
input wire vsync_in,
input wire hsync_in,
// video_out
output wire [35:0] disp_pixel,
output wire de_out,
output wire vsync_out,
output wire hsync_out
);
parameter IDLE_START = 1'b0,
IP_START_1 = 1'b1;
reg reset_disp_2b = 1'b1, reset_disp_1b = 1'b1;
wire reset_disp;
reg fifo_reset_axi_2b = 1'b0, fifo_reset_axi_1b = 1'b0;
wire fifo_reset_axi;
reg fifo_reset_disp_2b = 1'b0, fifo_reset_disp_1b = 1'b0;
wire fifo_reset_disp;
reg de_1d, vsync_1d, hsync_1d;
reg vsync_axi_1b, vsync_axi_2b;
wire vsync_axi;
reg vsync_axi_1d, vsync_axi_2d;
reg cs_start;
wire pfifo_empty, pfifo_full;
wire [31:0] pfifo_dout;
reg vsync_rising_edge_axi, vsync_falling_edge_axi;
always @(posedge disp_clk) begin
if(reset_disp) begin
de_1d <= 1'b0;
vsync_1d <= 1'b1;
hsync_1d <= 1'b1;
end else begin
de_1d <= de_in;
vsync_1d <= vsync_in;
hsync_1d <= hsync_in;
end
end
// reset signals
always @(posedge axi_clk) begin
fifo_reset_axi_2b <= ~init_done | ~axi_rst_n | ~vsync_1d;
fifo_reset_axi_1b <= fifo_reset_axi_2b;
end
assign fifo_reset_axi = fifo_reset_axi_1b;
always @(posedge disp_clk) begin
fifo_reset_disp_2b <= ~init_done | ~axi_rst_n | ~vsync_1d;
fifo_reset_disp_1b <= fifo_reset_disp_2b;
end
assign fifo_reset_disp = fifo_reset_disp_1b;
always @(posedge disp_clk) begin
reset_disp_2b <= ~init_done | ~axi_rst_n;
reset_disp_1b <= reset_disp_2b;
end
assign reset_disp = reset_disp_1b;
// vsync_rising_edge, vsync_falling_edge
always @(posedge axi_clk) begin
if (!axi_rst_n) begin
vsync_axi_2b <= 1'b1;
vsync_axi_1b <= 1'b1;
end else begin
vsync_axi_2b <= vsync_1d;
vsync_axi_1b <= vsync_axi_2b;
end
end
assign vsync_axi = vsync_axi_1b;
always @(posedge axi_clk) begin
if (!axi_rst_n) begin
vsync_axi_1d <= 1'b1;
vsync_axi_2d <= 1'b1;
end else begin
vsync_axi_1d <= vsync_axi;
vsync_axi_2d <= vsync_axi_1d;
end
end
always @(posedge axi_clk) begin
if (!axi_rst_n) begin
vsync_rising_edge_axi = 1'b0;
vsync_falling_edge_axi = 1'b0;
end else begin
vsync_rising_edge_axi <= ~vsync_axi_2d & vsync_axi_1d;
vsync_falling_edge_axi <= vsync_axi_2d & ~vsync_axi_1d;
end
end
// IP start State Machine
always @(posedge axi_clk) begin
if (!axi_rst_n) begin
cs_start <= IDLE_START;
ip_start <= 1'b0;
end else begin
case (cs_start)
IDLE_START : begin
ip_start <= 1'b0;
if (vsync_rising_edge_axi)
cs_start <= IP_START_1;
end
IP_START_1 : begin
ip_start <= 1'b1;
if (ip_done)
cs_start <= IDLE_START;
end
endcase
end
end
// data width 34 bits, 512 depth
pixel_fifo pixel_fifo_i (
.wr_rst(fifo_reset_axi),
.wr_clk(axi_clk),
.rd_rst(fifo_reset_disp),
.rd_clk(disp_clk),
.din({axis_tuser, axis_tlast, axis_tdata}),
.dout(pfifo_dout),
.wr_en(~pfifo_full & axis_tvalid),
.full(pfifo_full),
.rd_en(de_1d),
.empty(pfifo_empty)
);
assign axis_tready = ~pfifo_full;
assign disp_pixel = {pfifo_dout[23:16], 4'd0, pfifo_dout[15:8], 4'd0, pfifo_dout[7:0], 4'd0};
assign de_out = de_1d;
assign vsync_out = vsync_1d;
assign hsync_out = hsync_1d;
endmodule
`default_nettype wire
`default_nettype none
`timescale 100ps / 1ps
// axis2video_out_tb.v
// 2019/01/17 by marsee
//
module axis2video_out_tb;
reg axi_clk;
reg axi_rst_n;
wire ip_start;
wire ip_done;
wire [31:0] TDATA;
wire TVALID;
wire TREADY;
wire [3:0] TKEEP;
wire [3:0] TSTRB;
wire TUSER;
wire TLAST;
wire TID;
wire TDEST;
reg init_done;
wire init_done_out;
reg disp_clk;
reg de_in;
reg vsync_in;
reg hsync_in;
wire [35:0] disp_pixel;
wire de_out;
wire vsync_out;
wire hsync_out;
// pattern_gen_axis instance
pattern_gen_axis pga_inst(
.ap_clk(axi_clk),
.ap_rst_n(axi_rst_n),
.ap_start(ip_start),
.ap_done(ip_done),
.ap_idle(),
.ap_ready(),
.outs_TDATA(TDATA),
.outs_TVALID(TVALID),
.outs_TREADY(TREADY),
.outs_TKEEP(TKEEP),
.outs_TSTRB(TSTRB),
.outs_TUSER(TUSER),
.outs_TLAST(TLAST),
.outs_TID(TID),
.outs_TDEST(TDEST),
.init_done_V(init_done),
.init_done_out_V(init_done_out),
.ap_return()
);
// axis2video_out instance
axis2video_out axis2vo_inst(
.disp_clk(disp_clk),
.axi_clk(axi_clk),
.axi_rst_n(axi_rst_n),
.init_done(init_done),
.axis_tdata(TDATA),
.axis_tvalid(TVALID),
.axis_tready(TREADY),
.axis_tkeep(TKEEP),
.axis_tstrb(TSTRB),
.axis_tuser(TUSER),
.axis_tlast(TLAST),
.axis_tid(TID),
.axis_tdest(TDEST),
.ip_start(ip_start),
.ip_done(ip_done),
.de_in(de_in),
.vsync_in(vsync_in),
.hsync_in(hsync_in),
.disp_pixel(disp_pixel),
.de_out(de_out),
.vsync_out(vsync_out),
.hsync_out(hsync_out)
);
// axi_clk = 200 MHz (5 ns)
always #25
axi_clk = ~axi_clk;
// disp_clk = 65 MHz (13.4 ns)
always #77
disp_clk = ~disp_clk;
initial begin
axi_clk = 1'b1;
disp_clk = 1'b1;
axi_rst_n = 1'b0;
init_done = 1'b0;
de_in = 1'b0;
vsync_in = 1'b1;
hsync_in = 1'b1;
// Wait 100 ns for global reset to finish
#1000;
axi_rst_n = 1'b1;
#500;
init_done = 1'b1;
#1000;
vsync_in = 1'b0;
#1000;
vsync_in = 1'b1;
#1000;
de_in = 1'b1;
#5000;
de_in = 1'b0;
#1000;
hsync_in = 1'b0;
#1000;
hsync_in = 1'b1;
end
endmodule
`default_nettype wire
// pattern_gen_axis.cpp
// 2019/01/13 by marsee
//
#include <ap_int.h>
#include <hls_stream.h>
#include <ap_axi_sdata.h>
#define V_SIZE 60
#define H_SIZE 80
int pattern_gen_axis(hls::stream<ap_axis<32,1,1,1> >& outs,
ap_uint<1> &init_done, ap_uint<1> &init_done_out
){
#pragma HLS INTERFACE ap_none register port=init_done_out
#pragma HLS INTERFACE ap_none port=init_done
#pragma HLS INTERFACE axis register both port=outs
#pragma HLS INTERFACE ap_ctrl_hs port=return
ap_axis<32,1,1,1> out_val;
init_done_out = init_done;
LOOP_Y: for(int y=0; y<V_SIZE; y++){
#pragma HLS LOOP_TRIPCOUNT min=768 max=768 avg=768
LOOP_X: for(int x=0; x<H_SIZE; x++){
#pragma HLS LOOP_TRIPCOUNT min=1024 max=1024 avg=1024
#pragma HLS PIPELINE II=1
if (y < V_SIZE/2){
if (x < H_SIZE/2){
out_val.data = 0xff0000; // *red=0xff; *green=0; *blue=0;
} else if (x < H_SIZE){
out_val.data = 0x00ff00; // *red=0; *green=0xff; *blue=0;
} else {
out_val.data = 0x000000; // *red=0; *green=0; *blue=0;
}
} else if (y < V_SIZE){
if (x < H_SIZE/2){
out_val.data = 0x0000ff; // *red=0; *green=0; *blue=0xff;
} else if (x < H_SIZE){
out_val.data = 0xffffff; // *red=0xff; *green=0xff; *blue=0xff;
} else {
out_val.data = 0x000000; // *red=0; *green=0; *blue=0;
}
} else {
out_val.data = 0x000000; // *red=0; *green=0; *blue=0;
}
if(x==0 && y==0)
out_val.user = 1;
else
out_val.user = 0;
if(x == H_SIZE-1)
out_val.last = 1;
else
out_val.last = 0;
outs << out_val;
}
}
return(0);
}
// pattern_gen_axis.cpp
// 2019/01/13 by marsee
//
#include <ap_int.h>
#include <hls_stream.h>
#include <ap_axi_sdata.h>
int pattern_gen_axis(hls::stream<ap_axis<32,1,1,1> >& outs,
ap_uint<11> v_size, ap_uint<11> h_size,
ap_uint<1> &init_done, ap_uint<1> &init_done_out
){
#pragma HLS INTERFACE ap_none register port=init_done_out
#pragma HLS INTERFACE s_axilite port=init_done
#pragma HLS INTERFACE s_axilite port=v_size
#pragma HLS INTERFACE s_axilite port=h_size
#pragma HLS INTERFACE axis register both port=outs
#pragma HLS INTERFACE ap_ctrl_hs port=return
ap_axis<32,1,1,1> out_val;
init_done_out = init_done;
LOOP_Y: for(int y=0; y<v_size; y++){
#pragma HLS LOOP_TRIPCOUNT min=768 max=768 avg=768
LOOP_X: for(int x=0; x<h_size; x++){
#pragma HLS LOOP_TRIPCOUNT min=1024 max=1024 avg=1024
#pragma HLS PIPELINE II=1
if (y < v_size/2){
if (x < h_size/2){
out_val.data = 0xff0000; // *red=0xff; *green=0; *blue=0;
} else if (x < h_size){
out_val.data = 0x00ff00; // *red=0; *green=0xff; *blue=0;
} else {
out_val.data = 0x000000; // *red=0; *green=0; *blue=0;
}
} else if (y < v_size){
if (x < h_size/2){
out_val.data = 0x0000ff; // *red=0; *green=0; *blue=0xff;
} else if (x < h_size){
out_val.data = 0xffffff; // *red=0xff; *green=0xff; *blue=0xff;
} else {
out_val.data = 0x000000; // *red=0; *green=0; *blue=0;
}
} else {
out_val.data = 0x000000; // *red=0; *green=0; *blue=0;
}
if(x==0 && y==0)
out_val.user = 1;
else
out_val.user = 0;
if(x == h_size-1)
out_val.last = 1;
else
out_val.last = 0;
outs << out_val;
}
}
return(0);
}
//------------------------Address Info-------------------
// 0x00 : reserved
// 0x04 : reserved
// 0x08 : reserved
// 0x0c : reserved
// 0x10 : Data signal of v_size_V
// bit 10~0 - v_size_V[10:0] (Read/Write)
// others - reserved
// 0x14 : reserved
// 0x18 : Data signal of h_size_V
// bit 10~0 - h_size_V[10:0] (Read/Write)
// others - reserved
// 0x1c : reserved
// 0x20 : Data signal of init_done_V
// bit 0 - init_done_V[0] (Read/Write)
// others - reserved
// 0x24 : reserved
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
// pattern_gen_axis.cpp
// 2019/01/13 by marsee
//
#include <ap_int.h>
#include <hls_stream.h>
#include <ap_axi_sdata.h>
int pattern_gen_axis(hls::stream<ap_axis<32,1,1,1> >& outs,
int v_size, int h_size,
ap_uint<1> &init_done, ap_uint<1> &init_done_out
){
#pragma HLS INTERFACE ap_none register port=init_done_out
#pragma HLS INTERFACE s_axilite port=init_done
#pragma HLS INTERFACE s_axilite port=v_size
#pragma HLS INTERFACE s_axilite port=h_size
#pragma HLS INTERFACE axis register both port=outs
#pragma HLS INTERFACE s_axilite port=return
ap_axis<32,1,1,1> out_val;
init_done_out = init_done;
LOOP_Y: for(int y=0; y<v_size; y++){
#pragma HLS LOOP_TRIPCOUNT min=768 max=768 avg=768
LOOP_X: for(int x=0; x<h_size; x++){
#pragma HLS LOOP_TRIPCOUNT min=1024 max=1024 avg=1024
#pragma HLS PIPELINE II=1
if (y < v_size/2){
if (x < h_size/2){
out_val.data = 0xff0000; // *red=0xff; *green=0; *blue=0;
} else if (x < h_size){
out_val.data = 0x00ff00; // *red=0; *green=0xff; *blue=0;
} else {
out_val.data = 0x000000; // *red=0; *green=0; *blue=0;
}
} else if (y < v_size){
if (x < h_size/2){
out_val.data = 0x0000ff; // *red=0; *green=0; *blue=0xff;
} else if (x < h_size){
out_val.data = 0xffffff; // *red=0xff; *green=0xff; *blue=0xff;
} else {
out_val.data = 0x000000; // *red=0; *green=0; *blue=0;
}
} else {
out_val.data = 0x000000; // *red=0; *green=0; *blue=0;
}
if(x==0 && y==0)
out_val.user = 1;
else
out_val.user = 0;
if(x == h_size-1)
out_val.last = 1;
else
out_val.last = 0;
outs << out_val;
}
}
return(0);
}
// pattern_gen_axis_tb.cpp
// 2019/01/13 by marsee
//
#include <ap_int.h>
#include <hls_stream.h>
#include <iostream>
#include <fstream>
#include "hls_opencv.h"
#include "ap_axi_sdata.h"
#include "hls_video.h"
int pattern_gen_axis(hls::stream<ap_axis<32,1,1,1> >& outs,
int v_size, int h_size,
ap_uint<1> &init_done, ap_uint<1> &init_done_out
);
#define V_SIZE 60
#define H_SIZE 80
int main(){
using namespace cv;
hls::stream<ap_axis<32,1,1,1> > outs;
ap_axis<32,1,1,1> pix;
ap_uint<1> init_done = 1;
ap_uint<1> init_done_out = 0;
pattern_gen_axis(outs, V_SIZE, H_SIZE, init_done, init_done_out);
Mat dst = Mat(V_SIZE, H_SIZE, CV_8UC3);
Mat_<Vec3b> dst_vec3b = Mat_<Vec3b>(dst);
for(int y=0; y<dst.rows; y++){
for(int x=0; x<dst.cols; x++){
Vec3b pixel;
outs >> pix;
ap_int<32> rgb = pix.data;
pixel[0] = (rgb & 0xff); // blue
pixel[1] = (rgb & 0xff00) >> 8; // green
pixel[2] = (rgb & 0xff0000) >> 16; // red
dst_vec3b(y,x) = pixel;
}
}
imwrite("pattern_out.bmp", dst);
return(0);
}
// init_done_axils.cpp
// 2019/01/12 by marsee
//
#include "ap_int.h"
int init_done_axi4ls(ap_uint<1> &init_done, ap_uint<1> &init_done_out){
#pragma HLS INTERFACE ap_none register port=init_done_out
#pragma HLS INTERFACE s_axilite port=init_done
#pragma HLS INTERFACE s_axilite port=return
init_done_out = init_done;
return(0);
}
// XGA 解像度 65 MHz
#define H_ACTIVE_VIDEO 1024
#define H_FRONT_PORCH 24
#define H_SYNC_PULSE 136
#define H_BACK_PORCH 160
#define H_SUM (H_ACTIVE_VIDEO + H_FRONT_PORCH + H_SYNC_PULSE + H_BACK_PORCH)
#define V_ACTIVE_VIDEO 768
#define V_FRONT_PORCH 2
#define V_SYNC_PULSE 6
#define V_BACK_PORCH 29
#define V_SUM (V_ACTIVE_VIDEO + V_FRONT_PORCH + V_SYNC_PULSE + V_BACK_PORCH)
// memwrite.c
// 2018/01/07 : by marsee
// I referred to http://independence-sys.net/main/?p=2209
//
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <fcntl.h>
#include <sys/mman.h>
#include <unistd.h>
#define BLOCK_SIZE 4096
volatile uint32_t *reg;
int main(int argc, char **argv){
int fd;
void *memp;
uint32_t phy_addr;
uint32_t phy_addr_base;
int addr, wd;
uint32_t write_data;
if (argc != 3){
fprintf(stderr, "Usage : ./memwrite <address(hex)> <write data(hex)>\n");
exit(-1);
}
fd = open("/dev/mem", O_RDWR | O_SYNC);
if (fd == -1){
fprintf(stderr, "/dev/mem open error\n");
exit(-1);
}
sscanf(argv[1], "%x", &addr);
phy_addr = (uint32_t)addr;
phy_addr_base = phy_addr & 0xfffff000; // 4k byte boundary
memp = mmap(NULL, BLOCK_SIZE,
PROT_READ | PROT_WRITE, MAP_SHARED,
fd, phy_addr_base );
if ((int64_t)memp == -1){
fprintf(stderr,"/dev/mem map error\n");
exit(-1);
}
close(fd);
reg = (uint32_t *)memp;
int index = (phy_addr & 0xfff)/sizeof(uint32_t);
sscanf(argv[2], "%x", &wd);
write_data = (uint32_t)wd;
reg[index] = write_data;
munmap((void *)memp, BLOCK_SIZE);
return(0);
}
all:
{
[destination_device = pl] displayport_test_wrapper.bit
}
/dts-v1/;
/ {
fragment@0 {
target-path = "/fpga-full";
__overlay__ {
firmware-name = "displayport_test_wrapper.bin";
};
};
};
/dts-v1/;/plugin/;
/ {
fragment@0 {
target-path = "/amba";
__overlay__ {
fclk0 {
compatible = "ikwzm,fclkcfg-0.10.a";
clocks = <&clk 0x47>;
insert-rate = "40000000";
insert-enable = <1>;
remove-rate = "1000000";
remove-enable = <0>;
};
};
};
};
#!/bin/bash
sudo mkdir /config/device-tree/overlays/fpga
sudo cp fpga-load.dtb /config/device-tree/overlays/fpga/dtbo
sudo mkdir /config/device-tree/overlays/fclk0
sudo cp fclk0-zynqmp.dtb /config/device-tree/overlays/fclk0/dtbo
#!/bin/bash
sudo rmdir /config/device-tree/overlays/fclk0
sudo rmdir /config/device-tree/overlays/fpga/
/*
* mnist_conv_soft_vflip.c (for ZYBO Z7-20, for OV5642)
*
* Created on: 2019/01/03
* Author: marsee
*/
#include <stdio.h>
#include <stdlib.h>
#include "xil_io.h"
#include "xparameters.h"
#include "sleep.h"
#include "xtime_l.h"
#include "xvflip_dma_write.h"
#include "xmnist_conv_nn.h"
#include "xsquare_frame_gen.h"
#include "af1_bias_float.h"
#include "af1_weight_float.h"
#include "af2_bias_float.h"
#include "af2_weight_float.h"
#include "conv1_bias_float.h"
#include "conv1_weight_float.h"
#define FRAME_BUFFER_ADDRESS 0x10000000
#define NUMBER_OF_WRITE_FRAMES 3 // Note: If not at least 3 or more, the image is not displayed in succession.
#define HORIZONTAL_PIXELS 800
#define VERTICAL_LINES 600
#define PIXEL_NUM_OF_BYTES 4
int max_int(int out[10]);
int max_float(float out[10]);
int mnist_conv_nn_float(int in[22400], int addr_offset, float out[10]);
float conv_rgb2y_soft(int rgb);
float buf[28][28];
float conv_out[10][24][24];
float pool_out[10][12][12];
float dot1[100];
float dot2[10];
void cam_i2c_init(volatile unsigned *ov5642_i2c_axi_lites) {
ov5642_i2c_axi_lites[64] = 0x2; // reset tx fifo ,address is 0x100, i2c_control_reg
ov5642_i2c_axi_lites[64] = 0x1; // enable i2c
}
void cam_i2x_write_sync(void) {
// unsigned c;
// c = *cam_i2c_rx_fifo;
// while ((c & 0x84) != 0x80)
// c = *cam_i2c_rx_fifo; // No Bus Busy and TX_FIFO_Empty = 1
usleep(1000);
}
void cam_i2c_write(volatile unsigned *ov5642_axi_iic, unsigned int device_addr, unsigned int write_addr, unsigned int write_data){
ov5642_axi_iic[66] = 0x100 | (device_addr & 0xfe); // Slave IIC Write Address, address is 0x108, i2c_tx_fifo
ov5642_axi_iic[66] = (write_addr >> 8) & 0xff; // address upper byte
ov5642_axi_iic[66] = write_addr & 0xff; // address lower byte
ov5642_axi_iic[66] = 0x200 | (write_data & 0xff); // data
cam_i2x_write_sync();
}
int cam_reg_set(volatile unsigned *axi_iic, unsigned int device_addr);
int main(){
XMnist_conv_nn mcnn;
XSquare_frame_gen sf_gen;
XVflip_dma_write vfdma;
int inbyte_in;
int xval, yval;
int i, res;
int result[10];
float result_float[10];
int max_id;
int result_disp = 0;
int conv_addr;
int max_id_float;
XTime start_time, end_time;
// vflip_dma_write Initialization sequence
XVflip_dma_write_Initialize(&vfdma, 0);
// Frame buffer address set
XVflip_dma_write_Set_fb0_V(&vfdma, FRAME_BUFFER_ADDRESS);
XVflip_dma_write_Set_fb1_V(&vfdma, FRAME_BUFFER_ADDRESS);
XVflip_dma_write_Set_fb2_V(&vfdma, FRAME_BUFFER_ADDRESS);
// Mnist_conv_nn, Square_frame_gen Initialize
XMnist_conv_nn_Initialize(&mcnn, 0);
XSquare_frame_gen_Initialize(&sf_gen, 0);
// square_frame_gen initialize
XSquare_frame_gen_Set_x_pos(&sf_gen, HORIZONTAL_PIXELS/2);
xval = HORIZONTAL_PIXELS/2;
XSquare_frame_gen_Set_y_pos(&sf_gen, VERTICAL_LINES/2);
yval = VERTICAL_LINES/2;
XSquare_frame_gen_Set_width(&sf_gen, 28);
XSquare_frame_gen_Set_height(&sf_gen, 28);
XSquare_frame_gen_Set_off_on(&sf_gen, 1); // on
// XSquare_frame_gen start
XSquare_frame_gen_DisableAutoRestart(&sf_gen);
while(!XSquare_frame_gen_IsIdle(&sf_gen)) ;
XSquare_frame_gen_Start(&sf_gen);
XSquare_frame_gen_EnableAutoRestart(&sf_gen);
// mnist_conv_nn initialize
XMnist_conv_nn_Set_addr_offset(&mcnn, HORIZONTAL_PIXELS/2);
XMnist_conv_nn_Set_in_r(&mcnn, FRAME_BUFFER_ADDRESS+HORIZONTAL_PIXELS*(VERTICAL_LINES/2)*sizeof(int));
// axis_switch_1, 1to2 ,Select M00_AXIS
// Refer to http://marsee101.blog19.fc2.com/blog-entry-3177.html
Xil_Out32((XPAR_CAMERA_INTERFACE_AXIS_SWITCH_1_BASEADDR+0x40), 0x80000000); // disable
Xil_Out32((XPAR_CAMERA_INTERFACE_AXIS_SWITCH_1_BASEADDR+0x44), 0x0); // square_frame_gen enable
Xil_Out32((XPAR_CAMERA_INTERFACE_AXIS_SWITCH_1_BASEADDR), 0x2); // Commit registers
// axis_switch_0, 2to1, Select S00_AXIS
// Refer to http://marsee101.blog19.fc2.com/blog-entry-3177.html
Xil_Out32((XPAR_CAMERA_INTERFACE_AXIS_SWITCH_0_BASEADDR+0x40), 0x1);
Xil_Out32((XPAR_CAMERA_INTERFACE_AXIS_SWITCH_0_BASEADDR), 0x2); // Commit registers
// vflip_dma_write start
XVflip_dma_write_Start(&vfdma);
XVflip_dma_write_EnableAutoRestart(&vfdma);
// ov5642_inf_axis_0, axi_iic_0, bitmap_disp_cntrler_axi_master_0
volatile unsigned int *bmdc_axi_lites;
volatile unsigned int *ov5642_axi_lites;
volatile unsigned int *ov5642_i2c_axi_lites;
bmdc_axi_lites = (volatile unsigned *)XPAR_BMD_CONTROLLER_AXIM_0_BASEADDR;
ov5642_axi_lites = (volatile unsigned *)XPAR_CAMERA_INTERFACE_MT9D111_INF_AXIS_0_BASEADDR;
ov5642_i2c_axi_lites = (volatile unsigned *)XPAR_CAMERA_INTERFACE_AXI_IIC_0_BASEADDR;
bmdc_axi_lites[0] = (volatile unsigned int)FRAME_BUFFER_ADDRESS; // Bitmap Display Controller start
//ov5642_axi_lites[0] = (volatile unsigned int)FRAME_BUFFER_ADDRESS; // Camera Interface start (Address is dummy)
// CMOS Camera initialize, MT9D111
cam_i2c_init(ov5642_i2c_axi_lites);
cam_reg_set(ov5642_i2c_axi_lites, 0x78); // OV5642 register set
ov5642_axi_lites[0] = (volatile unsigned int)FRAME_BUFFER_ADDRESS; // Camera Interface start (Address is dummy)
ov5642_axi_lites[1] = 0; // One_shot_mode is disabled
while(1){
printf("mnist_conv_nn_test, <h> : left, <k> : up, <j> : down, <l> : right, <q> : exit\n");
inbyte_in = inbyte();
switch(inbyte_in) {
case 'h' : // left
case 'H' : // left -5
if(inbyte_in == 'h' && xval > 0)
--xval;
else if(inbyte_in == 'H' && xval >= 5)
xval -= 5;
XSquare_frame_gen_Set_x_pos(&sf_gen, xval);
XMnist_conv_nn_Set_addr_offset(&mcnn, xval);
printf("X_POS = %d, Y_POS = %d\n", xval, yval);
break;
case 'l' : // right
case 'L' : // right +5
if(inbyte_in == 'l' && xval < HORIZONTAL_PIXELS-28)
xval++;
else if(inbyte_in == 'L' && xval <= HORIZONTAL_PIXELS-28-5)
xval += 5;
XSquare_frame_gen_Set_x_pos(&sf_gen, xval);
XMnist_conv_nn_Set_addr_offset(&mcnn, xval);
printf("X_POS = %d, Y_POS = %d\n", xval, yval);
break;
case 'k' : // up
case 'K' : // up +5 (vflip)
if(inbyte_in == 'k' && yval > 0)
yval++;
else if(inbyte_in == 'K' && yval >= 5)
yval += 5;
XSquare_frame_gen_Set_y_pos(&sf_gen, yval);
XMnist_conv_nn_Set_in_r(&mcnn, FRAME_BUFFER_ADDRESS+HORIZONTAL_PIXELS*(VERTICAL_LINES-1-yval-28)*sizeof(int));
printf("X_POS = %d, Y_POS = %d\n", xval, yval);
break;
case 'j' : // down
case 'J' : // down -5 (vflip)
if(inbyte_in == 'j' && yval < VERTICAL_LINES-28)
--yval;
else if(inbyte_in == 'J' && yval <= VERTICAL_LINES-28-5)
yval -= 5;
XSquare_frame_gen_Set_y_pos(&sf_gen, yval);
XMnist_conv_nn_Set_in_r(&mcnn, FRAME_BUFFER_ADDRESS+HORIZONTAL_PIXELS*(VERTICAL_LINES-1-yval-28)*sizeof(int));
printf("X_POS = %d, Y_POS = %d\n", xval, yval);
break;
case 'r' : // result check
result_disp = 1;
break;
case 'q' : // exit
return(0);
}
if(result_disp){
printf("\nHardware\n");
// XMnist_conv_nn start
XMnist_conv_nn_DisableAutoRestart(&mcnn);
while(!XMnist_conv_nn_IsIdle(&mcnn));
XTime_GetTime(&start_time);
XMnist_conv_nn_Start(&mcnn);
while(!XMnist_conv_nn_IsIdle(&mcnn));
XTime_GetTime(&end_time);
printf("conv_time = %f ms\n", (float)((long)end_time-(long)start_time)/325000.0);
// mnist cnn result check
for(i=0; i<5; i++){
XMnist_conv_nn_Read_out_V_Words(&mcnn, i, &res, 1);
result[i*2] = res & 0x0fff;
if(result[i*2] & 0x800) // minus
result[i*2] = 0xfffff000 | result[i*2]; // Sign extension
result[i*2+1] = (res & 0x0fff0000) >> 16;
if(result[i*2+1] & 0x800) // minus
result[i*2+1] = 0xfffff000 | result[i*2+1]; // Sign extension
}
max_id = max_int(result);
for(i=0; i<10; i++){
printf("result[%d] = %x\n", i, result[i]);
}
printf("max_id = %d\n", max_id);
printf("\nSoftware\n");
conv_addr = FRAME_BUFFER_ADDRESS+HORIZONTAL_PIXELS*(VERTICAL_LINES-1-yval-28)*sizeof(int);
XTime_GetTime(&start_time);
mnist_conv_nn_float((int *)conv_addr, xval, result_float);
XTime_GetTime(&end_time);
max_id_float = max_float(result_float);
printf("conv_time = %f ms\n", (float)((long)end_time-(long)start_time)/325000.0);
for(i=0; i<10; i++){
printf("result_float[%d] = %f\n", i, result_float[i]);
}
printf("max_id_float = %d\n", max_id_float);
result_disp = 0;
}
}
}
int max_int(int out[10]){
int max_id;
int max, i;
for(i=0; i<10; i++){
if(i == 0){
max = out[0];
max_id = 0;
}else if(out[i]>max){
max = out[i];
max_id = i;
}
}
return(max_id);
}
int mnist_conv_nn_float(int in[22400], int addr_offset, float out[10]){
// 手書き数字の値を表示
/*for (int i=0; i<28; i++){
for (int j=0; j<800; j++){
if (j>=addr_offset && j<addr_offset+28)
printf("%2x, ", (int)(conv_rgb2y_soft(in[i*800+j])*256.0));
}
printf("\n");
} */
buf_copy1: for(int i=0; i<28; i++){
buf_copy2: for(int j=0; j<800; j++){
if (j>=addr_offset && j<addr_offset+28)
buf[i][j-addr_offset] = (float)0.99609375 - (float)conv_rgb2y_soft(in[i*800+j]);
}
}
// Convolutional Neural Network 5x5 kernel, Stride = 1, Padding = 0
// + ReLU
CONV1: for(int i=0; i<10; i++){ // カーネルの個数
CONV2: for(int j=0; j<24; j++){
CONV3: for(int k=0; k<24; k++){
conv_out[i][j][k] = 0;
CONV4: for(int m=0; m<5; m++){
CONV5: for(int n=0; n<5; n++){
conv_out[i][j][k] += buf[j+m][k+n] * conv1_fweight[i][0][m][n];
}
}
conv_out[i][j][k] += conv1_fbias[i];
if(conv_out[i][j][k]<0) // ReLU
conv_out[i][j][k] = 0;
}
}
}
// Pooling Kernel = 2 x 2, Stride = 2
POOL1: for(int i=0; i<10; i++){
POOL2: for(int j=0; j<24; j += 2){
POOL3: for(int k=0; k<24; k += 2){
POOL4: for(int m=0; m<2; m++){
POOL5: for(int n=0; n<2; n++){
if(m==0 && n==0){
pool_out[i][j/2][k/2] = conv_out[i][j][k];
} else if(pool_out[i][j/2][k/2] < conv_out[i][j+m][k+n]){
pool_out[i][j/2][k/2] = conv_out[i][j+m][k+n];
}
}
}
}
}
}
af1_dot1: for(int col=0; col<100; col++){
dot1[col] = 0;
af1_dot2: for(int i=0; i<10; i++){
af1_dot3: for(int j=0; j<12; j++){
af1_dot4: for(int k=0; k<12; k++){
dot1[col] += pool_out[i][j][k]*af1_fweight[i*12*12+j*12+k][col];
}
}
}
dot1[col] += af1_fbias[col];
if(dot1[col] < 0) // ReLU
dot1[col] = 0;
}
af2_dot1: for(int col=0; col<10; col++){
dot2[col] = 0;
af2_dot2: for(int row=0; row<100; row++){
dot2[col] += dot1[row]*af2_fweight[row][col];
}
dot2[col] += af2_fbias[col];
out[col] = dot2[col];
}
return(0);
}
int max_float(float out[10]){
int max_id;
float max;
for(int i=0; i<10; i++){
if(i == 0){
max = out[0];
max_id = 0;
}else if(out[i]>max){
max = out[i];
max_id = i;
}
}
return(max_id);
}
// RGBからYへの変換
// RGBのフォーマットは、{8'd0, R(8bits), G(8bits), B(8bits)}, 1pixel = 32bits
// 輝度信号Yのみに変換する。変換式は、Y = 0.299R + 0.587G + 0.114B
// "YUVフォーマット及び YUV<->RGB変換"を参考にした。http://vision.kuee.kyoto-u.ac.jp/~hiroaki/firewire/yuv.html
// 2013/09/27 : float を止めて、すべてint にした
// 2017/06/30 : retval を float にした
float conv_rgb2y_soft(int rgb){
int r, g, b, y_f;
int y;
float y_float;
b = rgb & 0xff;
g = (rgb>>8) & 0xff;
r = (rgb>>16) & 0xff;
y_f = 77*r + 150*g + 29*b; //y_f = 0.299*r + 0.587*g + 0.114*b;の係数に256倍した
y = y_f >> 8; // 256で割る
if (y >= 256)
y = 255;
y_float = (float)y/256.0;
return(y_float);
}
int cam_reg_set(volatile unsigned *axi_iic, unsigned int device_addr){
cam_i2c_write(axi_iic, device_addr, 0x3103, 0x93);
cam_i2c_write(axi_iic, device_addr, 0x3008, 0x82);
cam_i2c_write(axi_iic, device_addr, 0x3017, 0x7f);
cam_i2c_write(axi_iic, device_addr, 0x3018, 0xfc);
cam_i2c_write(axi_iic, device_addr, 0x3810, 0xc2);
cam_i2c_write(axi_iic, device_addr, 0x3615, 0xf0);
cam_i2c_write(axi_iic, device_addr, 0x3000, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x3001, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x3002, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x3003, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x3000, 0xf8);
cam_i2c_write(axi_iic, device_addr, 0x3001, 0x48);
cam_i2c_write(axi_iic, device_addr, 0x3002, 0x5c);
cam_i2c_write(axi_iic, device_addr, 0x3003, 0x02);
cam_i2c_write(axi_iic, device_addr, 0x3004, 0x07);
cam_i2c_write(axi_iic, device_addr, 0x3005, 0xb7);
cam_i2c_write(axi_iic, device_addr, 0x3006, 0x43);
cam_i2c_write(axi_iic, device_addr, 0x3007, 0x37);
cam_i2c_write(axi_iic, device_addr, 0x3011, 0x08); // 0x08 - 15fps, 0x10 - 30fps
cam_i2c_write(axi_iic, device_addr, 0x3010, 0x10);
cam_i2c_write(axi_iic, device_addr, 0x460c, 0x22);
cam_i2c_write(axi_iic, device_addr, 0x3815, 0x04);
cam_i2c_write(axi_iic, device_addr, 0x370d, 0x06);
cam_i2c_write(axi_iic, device_addr, 0x370c, 0xa0);
cam_i2c_write(axi_iic, device_addr, 0x3602, 0xfc);
cam_i2c_write(axi_iic, device_addr, 0x3612, 0xff);
cam_i2c_write(axi_iic, device_addr, 0x3634, 0xc0);
cam_i2c_write(axi_iic, device_addr, 0x3613, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x3605, 0x7c);
cam_i2c_write(axi_iic, device_addr, 0x3621, 0x09);
cam_i2c_write(axi_iic, device_addr, 0x3622, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x3604, 0x40);
cam_i2c_write(axi_iic, device_addr, 0x3603, 0xa7);
cam_i2c_write(axi_iic, device_addr, 0x3603, 0x27);
cam_i2c_write(axi_iic, device_addr, 0x4000, 0x21);
cam_i2c_write(axi_iic, device_addr, 0x401d, 0x02);
cam_i2c_write(axi_iic, device_addr, 0x3600, 0x54);
cam_i2c_write(axi_iic, device_addr, 0x3605, 0x04);
cam_i2c_write(axi_iic, device_addr, 0x3606, 0x3f);
cam_i2c_write(axi_iic, device_addr, 0x3c01, 0x80);
cam_i2c_write(axi_iic, device_addr, 0x5000, 0x4f);
cam_i2c_write(axi_iic, device_addr, 0x5020, 0x04);
cam_i2c_write(axi_iic, device_addr, 0x5181, 0x79);
cam_i2c_write(axi_iic, device_addr, 0x5182, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5185, 0x22);
cam_i2c_write(axi_iic, device_addr, 0x5197, 0x01);
cam_i2c_write(axi_iic, device_addr, 0x5001, 0xff);
cam_i2c_write(axi_iic, device_addr, 0x5500, 0x0a);
cam_i2c_write(axi_iic, device_addr, 0x5504, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5505, 0x7f);
cam_i2c_write(axi_iic, device_addr, 0x5080, 0x08);
cam_i2c_write(axi_iic, device_addr, 0x300e, 0x18);
cam_i2c_write(axi_iic, device_addr, 0x4610, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x471d, 0x05);
cam_i2c_write(axi_iic, device_addr, 0x4708, 0x06);
cam_i2c_write(axi_iic, device_addr, 0x3710, 0x10);
cam_i2c_write(axi_iic, device_addr, 0x3632, 0x41);
cam_i2c_write(axi_iic, device_addr, 0x3702, 0x40);
cam_i2c_write(axi_iic, device_addr, 0x3620, 0x37);
cam_i2c_write(axi_iic, device_addr, 0x3631, 0x01);
cam_i2c_write(axi_iic, device_addr, 0x3808, 0x02);
cam_i2c_write(axi_iic, device_addr, 0x3809, 0x80);
cam_i2c_write(axi_iic, device_addr, 0x380a, 0x01);
cam_i2c_write(axi_iic, device_addr, 0x380b, 0xe0);
cam_i2c_write(axi_iic, device_addr, 0x380e, 0x07);
cam_i2c_write(axi_iic, device_addr, 0x380f, 0xd0);
cam_i2c_write(axi_iic, device_addr, 0x501f, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5000, 0x4f);
cam_i2c_write(axi_iic, device_addr, 0x4300, 0x61); // RGB565
cam_i2c_write(axi_iic, device_addr, 0x3503, 0x07);
cam_i2c_write(axi_iic, device_addr, 0x3501, 0x73);
cam_i2c_write(axi_iic, device_addr, 0x3502, 0x80);
cam_i2c_write(axi_iic, device_addr, 0x350b, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x3503, 0x07);
cam_i2c_write(axi_iic, device_addr, 0x3824, 0x11);
cam_i2c_write(axi_iic, device_addr, 0x3501, 0x1e);
cam_i2c_write(axi_iic, device_addr, 0x3502, 0x80);
cam_i2c_write(axi_iic, device_addr, 0x350b, 0x7f);
cam_i2c_write(axi_iic, device_addr, 0x380c, 0x0c);
cam_i2c_write(axi_iic, device_addr, 0x380d, 0x80);
cam_i2c_write(axi_iic, device_addr, 0x380e, 0x03);
cam_i2c_write(axi_iic, device_addr, 0x380f, 0xe8);
cam_i2c_write(axi_iic, device_addr, 0x3a0d, 0x04);
cam_i2c_write(axi_iic, device_addr, 0x3a0e, 0x03);
cam_i2c_write(axi_iic, device_addr, 0x3818, 0xc1);
cam_i2c_write(axi_iic, device_addr, 0x3705, 0xdb);
cam_i2c_write(axi_iic, device_addr, 0x370a, 0x81);
cam_i2c_write(axi_iic, device_addr, 0x3801, 0x80);
cam_i2c_write(axi_iic, device_addr, 0x3621, 0xc7);
cam_i2c_write(axi_iic, device_addr, 0x3801, 0x50);
cam_i2c_write(axi_iic, device_addr, 0x3803, 0x08);
cam_i2c_write(axi_iic, device_addr, 0x3827, 0x08);
cam_i2c_write(axi_iic, device_addr, 0x3810, 0xc0);
cam_i2c_write(axi_iic, device_addr, 0x3804, 0x05);
cam_i2c_write(axi_iic, device_addr, 0x3805, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5682, 0x05);
cam_i2c_write(axi_iic, device_addr, 0x5683, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x3806, 0x03);
cam_i2c_write(axi_iic, device_addr, 0x3807, 0xc0);
cam_i2c_write(axi_iic, device_addr, 0x5686, 0x03);
cam_i2c_write(axi_iic, device_addr, 0x5687, 0xc0);
cam_i2c_write(axi_iic, device_addr, 0x3a00, 0x78);
cam_i2c_write(axi_iic, device_addr, 0x3a1a, 0x04);
cam_i2c_write(axi_iic, device_addr, 0x3a13, 0x30);
cam_i2c_write(axi_iic, device_addr, 0x3a18, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x3a19, 0x7c);
cam_i2c_write(axi_iic, device_addr, 0x3a08, 0x12);
cam_i2c_write(axi_iic, device_addr, 0x3a09, 0xc0);
cam_i2c_write(axi_iic, device_addr, 0x3a0a, 0x0f);
cam_i2c_write(axi_iic, device_addr, 0x3a0b, 0xa0);
cam_i2c_write(axi_iic, device_addr, 0x3004, 0xff);
cam_i2c_write(axi_iic, device_addr, 0x350c, 0x07);
cam_i2c_write(axi_iic, device_addr, 0x350d, 0xd0);
cam_i2c_write(axi_iic, device_addr, 0x3500, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x3501, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x3502, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x350a, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x350b, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x3503, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x528a, 0x02);
cam_i2c_write(axi_iic, device_addr, 0x528b, 0x04);
cam_i2c_write(axi_iic, device_addr, 0x528c, 0x08);
cam_i2c_write(axi_iic, device_addr, 0x528d, 0x08);
cam_i2c_write(axi_iic, device_addr, 0x528e, 0x08);
cam_i2c_write(axi_iic, device_addr, 0x528f, 0x10);
cam_i2c_write(axi_iic, device_addr, 0x5290, 0x10);
cam_i2c_write(axi_iic, device_addr, 0x5292, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5293, 0x02);
cam_i2c_write(axi_iic, device_addr, 0x5294, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5295, 0x02);
cam_i2c_write(axi_iic, device_addr, 0x5296, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5297, 0x02);
cam_i2c_write(axi_iic, device_addr, 0x5298, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5299, 0x02);
cam_i2c_write(axi_iic, device_addr, 0x529a, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x529b, 0x02);
cam_i2c_write(axi_iic, device_addr, 0x529c, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x529d, 0x02);
cam_i2c_write(axi_iic, device_addr, 0x529e, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x529f, 0x02);
cam_i2c_write(axi_iic, device_addr, 0x3a0f, 0x3c);
cam_i2c_write(axi_iic, device_addr, 0x3a10, 0x30);
cam_i2c_write(axi_iic, device_addr, 0x3a1b, 0x3c);
cam_i2c_write(axi_iic, device_addr, 0x3a1e, 0x30);
cam_i2c_write(axi_iic, device_addr, 0x3a11, 0x70);
cam_i2c_write(axi_iic, device_addr, 0x3a1f, 0x10);
cam_i2c_write(axi_iic, device_addr, 0x3030, 0x0b);
cam_i2c_write(axi_iic, device_addr, 0x3a02, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x3a03, 0x7d);
cam_i2c_write(axi_iic, device_addr, 0x3a04, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x3a14, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x3a15, 0x7d);
cam_i2c_write(axi_iic, device_addr, 0x3a16, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x3a00, 0x78);
cam_i2c_write(axi_iic, device_addr, 0x3a08, 0x09);
cam_i2c_write(axi_iic, device_addr, 0x3a09, 0x60);
cam_i2c_write(axi_iic, device_addr, 0x3a0a, 0x07);
cam_i2c_write(axi_iic, device_addr, 0x3a0b, 0xd0);
cam_i2c_write(axi_iic, device_addr, 0x3a0d, 0x08);
cam_i2c_write(axi_iic, device_addr, 0x3a0e, 0x06);
cam_i2c_write(axi_iic, device_addr, 0x5193, 0x70);
cam_i2c_write(axi_iic, device_addr, 0x3620, 0x57);
cam_i2c_write(axi_iic, device_addr, 0x3703, 0x98);
cam_i2c_write(axi_iic, device_addr, 0x3704, 0x1c);
cam_i2c_write(axi_iic, device_addr, 0x589b, 0x04);
cam_i2c_write(axi_iic, device_addr, 0x589a, 0xc5);
cam_i2c_write(axi_iic, device_addr, 0x528a, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x528b, 0x02);
cam_i2c_write(axi_iic, device_addr, 0x528c, 0x08);
cam_i2c_write(axi_iic, device_addr, 0x528d, 0x10);
cam_i2c_write(axi_iic, device_addr, 0x528e, 0x20);
cam_i2c_write(axi_iic, device_addr, 0x528f, 0x28);
cam_i2c_write(axi_iic, device_addr, 0x5290, 0x30);
cam_i2c_write(axi_iic, device_addr, 0x5292, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5293, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5294, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5295, 0x02);
cam_i2c_write(axi_iic, device_addr, 0x5296, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5297, 0x08);
cam_i2c_write(axi_iic, device_addr, 0x5298, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5299, 0x10);
cam_i2c_write(axi_iic, device_addr, 0x529a, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x529b, 0x20);
cam_i2c_write(axi_iic, device_addr, 0x529c, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x529d, 0x28);
cam_i2c_write(axi_iic, device_addr, 0x529e, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x529f, 0x30);
cam_i2c_write(axi_iic, device_addr, 0x5282, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5300, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5301, 0x20);
cam_i2c_write(axi_iic, device_addr, 0x5302, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5303, 0x7c);
cam_i2c_write(axi_iic, device_addr, 0x530c, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x530d, 0x0c);
cam_i2c_write(axi_iic, device_addr, 0x530e, 0x20);
cam_i2c_write(axi_iic, device_addr, 0x530f, 0x80);
cam_i2c_write(axi_iic, device_addr, 0x5310, 0x20);
cam_i2c_write(axi_iic, device_addr, 0x5311, 0x80);
cam_i2c_write(axi_iic, device_addr, 0x5308, 0x20);
cam_i2c_write(axi_iic, device_addr, 0x5309, 0x40);
cam_i2c_write(axi_iic, device_addr, 0x5304, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5305, 0x30);
cam_i2c_write(axi_iic, device_addr, 0x5306, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5307, 0x80);
cam_i2c_write(axi_iic, device_addr, 0x5314, 0x08);
cam_i2c_write(axi_iic, device_addr, 0x5315, 0x20);
cam_i2c_write(axi_iic, device_addr, 0x5319, 0x30);
cam_i2c_write(axi_iic, device_addr, 0x5316, 0x10);
cam_i2c_write(axi_iic, device_addr, 0x5317, 0x08);
cam_i2c_write(axi_iic, device_addr, 0x5318, 0x02);
cam_i2c_write(axi_iic, device_addr, 0x5380, 0x01);
cam_i2c_write(axi_iic, device_addr, 0x5381, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5382, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5383, 0x4e);
cam_i2c_write(axi_iic, device_addr, 0x5384, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5385, 0x0f);
cam_i2c_write(axi_iic, device_addr, 0x5386, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5387, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5388, 0x01);
cam_i2c_write(axi_iic, device_addr, 0x5389, 0x15);
cam_i2c_write(axi_iic, device_addr, 0x538a, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x538b, 0x31);
cam_i2c_write(axi_iic, device_addr, 0x538c, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x538d, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x538e, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x538f, 0x0f);
cam_i2c_write(axi_iic, device_addr, 0x5390, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5391, 0xab);
cam_i2c_write(axi_iic, device_addr, 0x5392, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5393, 0xa2);
cam_i2c_write(axi_iic, device_addr, 0x5394, 0x08);
cam_i2c_write(axi_iic, device_addr, 0x5480, 0x14);
cam_i2c_write(axi_iic, device_addr, 0x5481, 0x21);
cam_i2c_write(axi_iic, device_addr, 0x5482, 0x36);
cam_i2c_write(axi_iic, device_addr, 0x5483, 0x57);
cam_i2c_write(axi_iic, device_addr, 0x5484, 0x65);
cam_i2c_write(axi_iic, device_addr, 0x5485, 0x71);
cam_i2c_write(axi_iic, device_addr, 0x5486, 0x7d);
cam_i2c_write(axi_iic, device_addr, 0x5487, 0x87);
cam_i2c_write(axi_iic, device_addr, 0x5488, 0x91);
cam_i2c_write(axi_iic, device_addr, 0x5489, 0x9a);
cam_i2c_write(axi_iic, device_addr, 0x548a, 0xaa);
cam_i2c_write(axi_iic, device_addr, 0x548b, 0xb8);
cam_i2c_write(axi_iic, device_addr, 0x548c, 0xcd);
cam_i2c_write(axi_iic, device_addr, 0x548d, 0xdd);
cam_i2c_write(axi_iic, device_addr, 0x548e, 0xea);
cam_i2c_write(axi_iic, device_addr, 0x548f, 0x10);
cam_i2c_write(axi_iic, device_addr, 0x5490, 0x05);
cam_i2c_write(axi_iic, device_addr, 0x5491, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5492, 0x04);
cam_i2c_write(axi_iic, device_addr, 0x5493, 0x20);
cam_i2c_write(axi_iic, device_addr, 0x5494, 0x03);
cam_i2c_write(axi_iic, device_addr, 0x5495, 0x60);
cam_i2c_write(axi_iic, device_addr, 0x5496, 0x02);
cam_i2c_write(axi_iic, device_addr, 0x5497, 0xb8);
cam_i2c_write(axi_iic, device_addr, 0x5498, 0x02);
cam_i2c_write(axi_iic, device_addr, 0x5499, 0x86);
cam_i2c_write(axi_iic, device_addr, 0x549a, 0x02);
cam_i2c_write(axi_iic, device_addr, 0x549b, 0x5b);
cam_i2c_write(axi_iic, device_addr, 0x549c, 0x02);
cam_i2c_write(axi_iic, device_addr, 0x549d, 0x3b);
cam_i2c_write(axi_iic, device_addr, 0x549e, 0x02);
cam_i2c_write(axi_iic, device_addr, 0x549f, 0x1c);
cam_i2c_write(axi_iic, device_addr, 0x54a0, 0x02);
cam_i2c_write(axi_iic, device_addr, 0x54a1, 0x04);
cam_i2c_write(axi_iic, device_addr, 0x54a2, 0x01);
cam_i2c_write(axi_iic, device_addr, 0x54a3, 0xed);
cam_i2c_write(axi_iic, device_addr, 0x54a4, 0x01);
cam_i2c_write(axi_iic, device_addr, 0x54a5, 0xc5);
cam_i2c_write(axi_iic, device_addr, 0x54a6, 0x01);
cam_i2c_write(axi_iic, device_addr, 0x54a7, 0xa5);
cam_i2c_write(axi_iic, device_addr, 0x54a8, 0x01);
cam_i2c_write(axi_iic, device_addr, 0x54a9, 0x6c);
cam_i2c_write(axi_iic, device_addr, 0x54aa, 0x01);
cam_i2c_write(axi_iic, device_addr, 0x54ab, 0x41);
cam_i2c_write(axi_iic, device_addr, 0x54ac, 0x01);
cam_i2c_write(axi_iic, device_addr, 0x54ad, 0x20);
cam_i2c_write(axi_iic, device_addr, 0x54ae, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x54af, 0x16);
cam_i2c_write(axi_iic, device_addr, 0x3406, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5192, 0x04); // 0x04
cam_i2c_write(axi_iic, device_addr, 0x5191, 0xf8); // 0xf8
cam_i2c_write(axi_iic, device_addr, 0x5193, 0x70);
cam_i2c_write(axi_iic, device_addr, 0x5194, 0xf0);
cam_i2c_write(axi_iic, device_addr, 0x5195, 0xf0);
cam_i2c_write(axi_iic, device_addr, 0x518d, 0x3d);
cam_i2c_write(axi_iic, device_addr, 0x518f, 0x54);
cam_i2c_write(axi_iic, device_addr, 0x518e, 0x3d);
cam_i2c_write(axi_iic, device_addr, 0x5190, 0x54);
cam_i2c_write(axi_iic, device_addr, 0x518b, 0xc0);
cam_i2c_write(axi_iic, device_addr, 0x518c, 0xbd);
cam_i2c_write(axi_iic, device_addr, 0x5187, 0x18);
cam_i2c_write(axi_iic, device_addr, 0x5188, 0x18);
cam_i2c_write(axi_iic, device_addr, 0x5189, 0x6e);
cam_i2c_write(axi_iic, device_addr, 0x518a, 0x68);
cam_i2c_write(axi_iic, device_addr, 0x5186, 0x1c);
cam_i2c_write(axi_iic, device_addr, 0x5181, 0x50);
cam_i2c_write(axi_iic, device_addr, 0x5184, 0x25);
cam_i2c_write(axi_iic, device_addr, 0x5182, 0x11);
cam_i2c_write(axi_iic, device_addr, 0x5183, 0x14);
cam_i2c_write(axi_iic, device_addr, 0x5184, 0x25);
cam_i2c_write(axi_iic, device_addr, 0x5185, 0x24);
cam_i2c_write(axi_iic, device_addr, 0x5025, 0x82);
cam_i2c_write(axi_iic, device_addr, 0x5583, 0x40);
cam_i2c_write(axi_iic, device_addr, 0x5584, 0x40);
cam_i2c_write(axi_iic, device_addr, 0x5580, 0x02); // 0x02
cam_i2c_write(axi_iic, device_addr, 0x3633, 0x07);
cam_i2c_write(axi_iic, device_addr, 0x3702, 0x10);
cam_i2c_write(axi_iic, device_addr, 0x3703, 0xb2);
cam_i2c_write(axi_iic, device_addr, 0x3704, 0x18);
cam_i2c_write(axi_iic, device_addr, 0x370b, 0x40);
cam_i2c_write(axi_iic, device_addr, 0x370d, 0x02);
cam_i2c_write(axi_iic, device_addr, 0x3620, 0x52);
cam_i2c_write(axi_iic, device_addr, 0x3c00, 0x04);
cam_i2c_write(axi_iic, device_addr, 0x5001, 0xFF);
cam_i2c_write(axi_iic, device_addr, 0x5282, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5300, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5301, 0x20);
cam_i2c_write(axi_iic, device_addr, 0x5302, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5303, 0x7c);
cam_i2c_write(axi_iic, device_addr, 0x530c, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x530d, 0x10);
cam_i2c_write(axi_iic, device_addr, 0x530e, 0x20);
cam_i2c_write(axi_iic, device_addr, 0x530f, 0x80);
cam_i2c_write(axi_iic, device_addr, 0x5310, 0x20);
cam_i2c_write(axi_iic, device_addr, 0x5311, 0x80);
cam_i2c_write(axi_iic, device_addr, 0x5308, 0x20);
cam_i2c_write(axi_iic, device_addr, 0x5309, 0x40);
cam_i2c_write(axi_iic, device_addr, 0x5304, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5305, 0x30);
cam_i2c_write(axi_iic, device_addr, 0x5306, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5307, 0x80);
cam_i2c_write(axi_iic, device_addr, 0x5314, 0x08);
cam_i2c_write(axi_iic, device_addr, 0x5315, 0x20);
cam_i2c_write(axi_iic, device_addr, 0x5319, 0x30);
cam_i2c_write(axi_iic, device_addr, 0x5316, 0x10);
cam_i2c_write(axi_iic, device_addr, 0x5317, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5318, 0x02);
cam_i2c_write(axi_iic, device_addr, 0x5500, 0x10);
cam_i2c_write(axi_iic, device_addr, 0x5502, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5503, 0x06);
cam_i2c_write(axi_iic, device_addr, 0x5504, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5505, 0x7f);
cam_i2c_write(axi_iic, device_addr, 0x5025, 0x80);
cam_i2c_write(axi_iic, device_addr, 0x5300, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5301, 0x20);
cam_i2c_write(axi_iic, device_addr, 0x5302, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5303, 0x7c);
cam_i2c_write(axi_iic, device_addr, 0x530c, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x530d, 0x0c);
cam_i2c_write(axi_iic, device_addr, 0x530e, 0x20);
cam_i2c_write(axi_iic, device_addr, 0x530f, 0x80);
cam_i2c_write(axi_iic, device_addr, 0x5310, 0x20);
cam_i2c_write(axi_iic, device_addr, 0x5311, 0x80);
cam_i2c_write(axi_iic, device_addr, 0x5308, 0x20);
cam_i2c_write(axi_iic, device_addr, 0x5309, 0x40);
cam_i2c_write(axi_iic, device_addr, 0x5304, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5305, 0x30);
cam_i2c_write(axi_iic, device_addr, 0x5306, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5307, 0x80);
cam_i2c_write(axi_iic, device_addr, 0x5314, 0x08);
cam_i2c_write(axi_iic, device_addr, 0x5315, 0x20);
cam_i2c_write(axi_iic, device_addr, 0x5319, 0x30);
cam_i2c_write(axi_iic, device_addr, 0x5316, 0x10);
cam_i2c_write(axi_iic, device_addr, 0x5317, 0x08);
cam_i2c_write(axi_iic, device_addr, 0x5318, 0x02);
cam_i2c_write(axi_iic, device_addr, 0x5380, 0x01);
cam_i2c_write(axi_iic, device_addr, 0x5381, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5382, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5383, 0x1f);
cam_i2c_write(axi_iic, device_addr, 0x5384, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5385, 0x06);
cam_i2c_write(axi_iic, device_addr, 0x5386, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5387, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5388, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5389, 0xE1);
cam_i2c_write(axi_iic, device_addr, 0x538A, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x538B, 0x2B);
cam_i2c_write(axi_iic, device_addr, 0x538C, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x538D, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x538E, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x538F, 0x10);
cam_i2c_write(axi_iic, device_addr, 0x5390, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5391, 0xB3);
cam_i2c_write(axi_iic, device_addr, 0x5392, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5393, 0xA6);
cam_i2c_write(axi_iic, device_addr, 0x5394, 0x08);
cam_i2c_write(axi_iic, device_addr, 0x5480, 0xd);
cam_i2c_write(axi_iic, device_addr, 0x5481, 0x18);
cam_i2c_write(axi_iic, device_addr, 0x5482, 0x2a);
cam_i2c_write(axi_iic, device_addr, 0x5483, 0x49);
cam_i2c_write(axi_iic, device_addr, 0x5484, 0x56);
cam_i2c_write(axi_iic, device_addr, 0x5485, 0x62);
cam_i2c_write(axi_iic, device_addr, 0x5486, 0x6c);
cam_i2c_write(axi_iic, device_addr, 0x5487, 0x76);
cam_i2c_write(axi_iic, device_addr, 0x5488, 0x80);
cam_i2c_write(axi_iic, device_addr, 0x5489, 0x88);
cam_i2c_write(axi_iic, device_addr, 0x548a, 0x96);
cam_i2c_write(axi_iic, device_addr, 0x548b, 0xa2);
cam_i2c_write(axi_iic, device_addr, 0x548c, 0xb8);
cam_i2c_write(axi_iic, device_addr, 0x548d, 0xcc);
cam_i2c_write(axi_iic, device_addr, 0x548e, 0xe0);
cam_i2c_write(axi_iic, device_addr, 0x548f, 0x10);
cam_i2c_write(axi_iic, device_addr, 0x5490, 0x3);
cam_i2c_write(axi_iic, device_addr, 0x5491, 0x40);
cam_i2c_write(axi_iic, device_addr, 0x5492, 0x3);
cam_i2c_write(axi_iic, device_addr, 0x5493, 0x0);
cam_i2c_write(axi_iic, device_addr, 0x5494, 0x2);
cam_i2c_write(axi_iic, device_addr, 0x5495, 0xa0);
cam_i2c_write(axi_iic, device_addr, 0x5496, 0x2);
cam_i2c_write(axi_iic, device_addr, 0x5497, 0x48);
cam_i2c_write(axi_iic, device_addr, 0x5498, 0x2);
cam_i2c_write(axi_iic, device_addr, 0x5499, 0x26);
cam_i2c_write(axi_iic, device_addr, 0x549a, 0x2);
cam_i2c_write(axi_iic, device_addr, 0x549b, 0xb);
cam_i2c_write(axi_iic, device_addr, 0x549c, 0x1);
cam_i2c_write(axi_iic, device_addr, 0x549d, 0xee);
cam_i2c_write(axi_iic, device_addr, 0x549e, 0x1);
cam_i2c_write(axi_iic, device_addr, 0x549f, 0xd8);
cam_i2c_write(axi_iic, device_addr, 0x54a0, 0x1);
cam_i2c_write(axi_iic, device_addr, 0x54a1, 0xc7);
cam_i2c_write(axi_iic, device_addr, 0x54a2, 0x1);
cam_i2c_write(axi_iic, device_addr, 0x54a3, 0xb3);
cam_i2c_write(axi_iic, device_addr, 0x54a4, 0x1);
cam_i2c_write(axi_iic, device_addr, 0x54a5, 0x90);
cam_i2c_write(axi_iic, device_addr, 0x54a6, 0x1);
cam_i2c_write(axi_iic, device_addr, 0x54a7, 0x62);
cam_i2c_write(axi_iic, device_addr, 0x54a8, 0x1);
cam_i2c_write(axi_iic, device_addr, 0x54a9, 0x27);
cam_i2c_write(axi_iic, device_addr, 0x54aa, 0x01);
cam_i2c_write(axi_iic, device_addr, 0x54ab, 0x09);
cam_i2c_write(axi_iic, device_addr, 0x54ac, 0x01);
cam_i2c_write(axi_iic, device_addr, 0x54ad, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x54ae, 0x0);
cam_i2c_write(axi_iic, device_addr, 0x54af, 0x40);
cam_i2c_write(axi_iic, device_addr, 0x54b0, 0x1);
cam_i2c_write(axi_iic, device_addr, 0x54b1, 0x20);
cam_i2c_write(axi_iic, device_addr, 0x54b2, 0x1);
cam_i2c_write(axi_iic, device_addr, 0x54b3, 0x40);
cam_i2c_write(axi_iic, device_addr, 0x54b4, 0x0);
cam_i2c_write(axi_iic, device_addr, 0x54b5, 0xf0);
cam_i2c_write(axi_iic, device_addr, 0x54b6, 0x1);
cam_i2c_write(axi_iic, device_addr, 0x54b7, 0xdf);
cam_i2c_write(axi_iic, device_addr, 0x5583, 0x5d);
cam_i2c_write(axi_iic, device_addr, 0x5584, 0x5d);
cam_i2c_write(axi_iic, device_addr, 0x5580, 0x06);
cam_i2c_write(axi_iic, device_addr, 0x5587, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5588, 0x20);
cam_i2c_write(axi_iic, device_addr, 0x558a, 0x09);
cam_i2c_write(axi_iic, device_addr, 0x5589, 0x10);
cam_i2c_write(axi_iic, device_addr, 0x5000, 0xcf);
cam_i2c_write(axi_iic, device_addr, 0x5800, 0x48);
cam_i2c_write(axi_iic, device_addr, 0x5801, 0x31);
cam_i2c_write(axi_iic, device_addr, 0x5802, 0x21);
cam_i2c_write(axi_iic, device_addr, 0x5803, 0x1b);
cam_i2c_write(axi_iic, device_addr, 0x5804, 0x1a);
cam_i2c_write(axi_iic, device_addr, 0x5805, 0x1e);
cam_i2c_write(axi_iic, device_addr, 0x5806, 0x29);
cam_i2c_write(axi_iic, device_addr, 0x5807, 0x38);
cam_i2c_write(axi_iic, device_addr, 0x5808, 0x26);
cam_i2c_write(axi_iic, device_addr, 0x5809, 0x17);
cam_i2c_write(axi_iic, device_addr, 0x580a, 0x11);
cam_i2c_write(axi_iic, device_addr, 0x580b, 0xe);
cam_i2c_write(axi_iic, device_addr, 0x580c, 0xd);
cam_i2c_write(axi_iic, device_addr, 0x580d, 0xe);
cam_i2c_write(axi_iic, device_addr, 0x580e, 0x13);
cam_i2c_write(axi_iic, device_addr, 0x580f, 0x1a);
cam_i2c_write(axi_iic, device_addr, 0x5810, 0x15);
cam_i2c_write(axi_iic, device_addr, 0x5811, 0xd);
cam_i2c_write(axi_iic, device_addr, 0x5812, 0x8);
cam_i2c_write(axi_iic, device_addr, 0x5813, 0x5);
cam_i2c_write(axi_iic, device_addr, 0x5814, 0x4);
cam_i2c_write(axi_iic, device_addr, 0x5815, 0x5);
cam_i2c_write(axi_iic, device_addr, 0x5816, 0x9);
cam_i2c_write(axi_iic, device_addr, 0x5817, 0xd);
cam_i2c_write(axi_iic, device_addr, 0x5818, 0x11);
cam_i2c_write(axi_iic, device_addr, 0x5819, 0xa);
cam_i2c_write(axi_iic, device_addr, 0x581a, 0x4);
cam_i2c_write(axi_iic, device_addr, 0x581b, 0x0);
cam_i2c_write(axi_iic, device_addr, 0x581c, 0x0);
cam_i2c_write(axi_iic, device_addr, 0x581d, 0x1);
cam_i2c_write(axi_iic, device_addr, 0x581e, 0x6);
cam_i2c_write(axi_iic, device_addr, 0x581f, 0x9);
cam_i2c_write(axi_iic, device_addr, 0x5820, 0x12);
cam_i2c_write(axi_iic, device_addr, 0x5821, 0xb);
cam_i2c_write(axi_iic, device_addr, 0x5822, 0x4);
cam_i2c_write(axi_iic, device_addr, 0x5823, 0x0);
cam_i2c_write(axi_iic, device_addr, 0x5824, 0x0);
cam_i2c_write(axi_iic, device_addr, 0x5825, 0x1);
cam_i2c_write(axi_iic, device_addr, 0x5826, 0x6);
cam_i2c_write(axi_iic, device_addr, 0x5827, 0xa);
cam_i2c_write(axi_iic, device_addr, 0x5828, 0x17);
cam_i2c_write(axi_iic, device_addr, 0x5829, 0xf);
cam_i2c_write(axi_iic, device_addr, 0x582a, 0x9);
cam_i2c_write(axi_iic, device_addr, 0x582b, 0x6);
cam_i2c_write(axi_iic, device_addr, 0x582c, 0x5);
cam_i2c_write(axi_iic, device_addr, 0x582d, 0x6);
cam_i2c_write(axi_iic, device_addr, 0x582e, 0xa);
cam_i2c_write(axi_iic, device_addr, 0x582f, 0xe);
cam_i2c_write(axi_iic, device_addr, 0x5830, 0x28);
cam_i2c_write(axi_iic, device_addr, 0x5831, 0x1a);
cam_i2c_write(axi_iic, device_addr, 0x5832, 0x11);
cam_i2c_write(axi_iic, device_addr, 0x5833, 0xe);
cam_i2c_write(axi_iic, device_addr, 0x5834, 0xe);
cam_i2c_write(axi_iic, device_addr, 0x5835, 0xf);
cam_i2c_write(axi_iic, device_addr, 0x5836, 0x15);
cam_i2c_write(axi_iic, device_addr, 0x5837, 0x1d);
cam_i2c_write(axi_iic, device_addr, 0x5838, 0x6e);
cam_i2c_write(axi_iic, device_addr, 0x5839, 0x39);
cam_i2c_write(axi_iic, device_addr, 0x583a, 0x27);
cam_i2c_write(axi_iic, device_addr, 0x583b, 0x1f);
cam_i2c_write(axi_iic, device_addr, 0x583c, 0x1e);
cam_i2c_write(axi_iic, device_addr, 0x583d, 0x23);
cam_i2c_write(axi_iic, device_addr, 0x583e, 0x2f);
cam_i2c_write(axi_iic, device_addr, 0x583f, 0x41);
cam_i2c_write(axi_iic, device_addr, 0x5840, 0xe);
cam_i2c_write(axi_iic, device_addr, 0x5841, 0xc);
cam_i2c_write(axi_iic, device_addr, 0x5842, 0xd);
cam_i2c_write(axi_iic, device_addr, 0x5843, 0xc);
cam_i2c_write(axi_iic, device_addr, 0x5844, 0xc);
cam_i2c_write(axi_iic, device_addr, 0x5845, 0xc);
cam_i2c_write(axi_iic, device_addr, 0x5846, 0xc);
cam_i2c_write(axi_iic, device_addr, 0x5847, 0xc);
cam_i2c_write(axi_iic, device_addr, 0x5848, 0xd);
cam_i2c_write(axi_iic, device_addr, 0x5849, 0xe);
cam_i2c_write(axi_iic, device_addr, 0x584a, 0xe);
cam_i2c_write(axi_iic, device_addr, 0x584b, 0xa);
cam_i2c_write(axi_iic, device_addr, 0x584c, 0xe);
cam_i2c_write(axi_iic, device_addr, 0x584d, 0xe);
cam_i2c_write(axi_iic, device_addr, 0x584e, 0x10);
cam_i2c_write(axi_iic, device_addr, 0x584f, 0x10);
cam_i2c_write(axi_iic, device_addr, 0x5850, 0x11);
cam_i2c_write(axi_iic, device_addr, 0x5851, 0xa);
cam_i2c_write(axi_iic, device_addr, 0x5852, 0xf);
cam_i2c_write(axi_iic, device_addr, 0x5853, 0xe);
cam_i2c_write(axi_iic, device_addr, 0x5854, 0x10);
cam_i2c_write(axi_iic, device_addr, 0x5855, 0x10);
cam_i2c_write(axi_iic, device_addr, 0x5856, 0x10);
cam_i2c_write(axi_iic, device_addr, 0x5857, 0xa);
cam_i2c_write(axi_iic, device_addr, 0x5858, 0xe);
cam_i2c_write(axi_iic, device_addr, 0x5859, 0xe);
cam_i2c_write(axi_iic, device_addr, 0x585a, 0xf);
cam_i2c_write(axi_iic, device_addr, 0x585b, 0xf);
cam_i2c_write(axi_iic, device_addr, 0x585c, 0xf);
cam_i2c_write(axi_iic, device_addr, 0x585d, 0xa);
cam_i2c_write(axi_iic, device_addr, 0x585e, 0x9);
cam_i2c_write(axi_iic, device_addr, 0x585f, 0xd);
cam_i2c_write(axi_iic, device_addr, 0x5860, 0xc);
cam_i2c_write(axi_iic, device_addr, 0x5861, 0xb);
cam_i2c_write(axi_iic, device_addr, 0x5862, 0xd);
cam_i2c_write(axi_iic, device_addr, 0x5863, 0x7);
cam_i2c_write(axi_iic, device_addr, 0x5864, 0x17);
cam_i2c_write(axi_iic, device_addr, 0x5865, 0x14);
cam_i2c_write(axi_iic, device_addr, 0x5866, 0x18);
cam_i2c_write(axi_iic, device_addr, 0x5867, 0x18);
cam_i2c_write(axi_iic, device_addr, 0x5868, 0x16);
cam_i2c_write(axi_iic, device_addr, 0x5869, 0x12);
cam_i2c_write(axi_iic, device_addr, 0x586a, 0x1b);
cam_i2c_write(axi_iic, device_addr, 0x586b, 0x1a);
cam_i2c_write(axi_iic, device_addr, 0x586c, 0x16);
cam_i2c_write(axi_iic, device_addr, 0x586d, 0x16);
cam_i2c_write(axi_iic, device_addr, 0x586e, 0x18);
cam_i2c_write(axi_iic, device_addr, 0x586f, 0x1f);
cam_i2c_write(axi_iic, device_addr, 0x5870, 0x1c);
cam_i2c_write(axi_iic, device_addr, 0x5871, 0x16);
cam_i2c_write(axi_iic, device_addr, 0x5872, 0x10);
cam_i2c_write(axi_iic, device_addr, 0x5873, 0xf);
cam_i2c_write(axi_iic, device_addr, 0x5874, 0x13);
cam_i2c_write(axi_iic, device_addr, 0x5875, 0x1c);
cam_i2c_write(axi_iic, device_addr, 0x5876, 0x1e);
cam_i2c_write(axi_iic, device_addr, 0x5877, 0x17);
cam_i2c_write(axi_iic, device_addr, 0x5878, 0x11);
cam_i2c_write(axi_iic, device_addr, 0x5879, 0x11);
cam_i2c_write(axi_iic, device_addr, 0x587a, 0x14);
cam_i2c_write(axi_iic, device_addr, 0x587b, 0x1e);
cam_i2c_write(axi_iic, device_addr, 0x587c, 0x1c);
cam_i2c_write(axi_iic, device_addr, 0x587d, 0x1c);
cam_i2c_write(axi_iic, device_addr, 0x587e, 0x1a);
cam_i2c_write(axi_iic, device_addr, 0x587f, 0x1a);
cam_i2c_write(axi_iic, device_addr, 0x5880, 0x1b);
cam_i2c_write(axi_iic, device_addr, 0x5881, 0x1f);
cam_i2c_write(axi_iic, device_addr, 0x5882, 0x14);
cam_i2c_write(axi_iic, device_addr, 0x5883, 0x1a);
cam_i2c_write(axi_iic, device_addr, 0x5884, 0x1d);
cam_i2c_write(axi_iic, device_addr, 0x5885, 0x1e);
cam_i2c_write(axi_iic, device_addr, 0x5886, 0x1a);
cam_i2c_write(axi_iic, device_addr, 0x5887, 0x1a);
cam_i2c_write(axi_iic, device_addr, 0x528a, 0x02);
cam_i2c_write(axi_iic, device_addr, 0x528b, 0x06);
cam_i2c_write(axi_iic, device_addr, 0x528c, 0x20);
cam_i2c_write(axi_iic, device_addr, 0x528d, 0x30);
cam_i2c_write(axi_iic, device_addr, 0x528e, 0x40);
cam_i2c_write(axi_iic, device_addr, 0x528f, 0x50);
cam_i2c_write(axi_iic, device_addr, 0x5290, 0x60);
cam_i2c_write(axi_iic, device_addr, 0x5292, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5293, 0x02);
cam_i2c_write(axi_iic, device_addr, 0x5294, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5295, 0x04);
cam_i2c_write(axi_iic, device_addr, 0x5296, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5297, 0x08);
cam_i2c_write(axi_iic, device_addr, 0x5298, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5299, 0x10);
cam_i2c_write(axi_iic, device_addr, 0x529a, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x529b, 0x20);
cam_i2c_write(axi_iic, device_addr, 0x529c, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x529d, 0x28);
cam_i2c_write(axi_iic, device_addr, 0x529e, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x529f, 0x30);
cam_i2c_write(axi_iic, device_addr, 0x5282, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5680, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5681, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5682, 0x05);
cam_i2c_write(axi_iic, device_addr, 0x5683, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5684, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5685, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x5686, 0x03);
cam_i2c_write(axi_iic, device_addr, 0x5687, 0xc0);
cam_i2c_write(axi_iic, device_addr, 0x5180, 0xff);
cam_i2c_write(axi_iic, device_addr, 0x5181, 0x52);
cam_i2c_write(axi_iic, device_addr, 0x5182, 0x11);
cam_i2c_write(axi_iic, device_addr, 0x5183, 0x14);
cam_i2c_write(axi_iic, device_addr, 0x5184, 0x25);
cam_i2c_write(axi_iic, device_addr, 0x5185, 0x24);
cam_i2c_write(axi_iic, device_addr, 0x5186, 0x14);
cam_i2c_write(axi_iic, device_addr, 0x5187, 0x14);
cam_i2c_write(axi_iic, device_addr, 0x5188, 0x14);
cam_i2c_write(axi_iic, device_addr, 0x5189, 0x80);
cam_i2c_write(axi_iic, device_addr, 0x518a, 0x60);
cam_i2c_write(axi_iic, device_addr, 0x518b, 0xa2);
cam_i2c_write(axi_iic, device_addr, 0x518c, 0x9c);
cam_i2c_write(axi_iic, device_addr, 0x518d, 0x36);
cam_i2c_write(axi_iic, device_addr, 0x518e, 0x34);
cam_i2c_write(axi_iic, device_addr, 0x518f, 0x54);
cam_i2c_write(axi_iic, device_addr, 0x5190, 0x4c);
cam_i2c_write(axi_iic, device_addr, 0x5191, 0xf8);
cam_i2c_write(axi_iic, device_addr, 0x5192, 0x04);
cam_i2c_write(axi_iic, device_addr, 0x5193, 0x70);
cam_i2c_write(axi_iic, device_addr, 0x5194, 0xf0);
cam_i2c_write(axi_iic, device_addr, 0x5195, 0xf0);
cam_i2c_write(axi_iic, device_addr, 0x5196, 0x03);
cam_i2c_write(axi_iic, device_addr, 0x5197, 0x01);
cam_i2c_write(axi_iic, device_addr, 0x5198, 0x05);
cam_i2c_write(axi_iic, device_addr, 0x5199, 0x2f);
cam_i2c_write(axi_iic, device_addr, 0x519a, 0x04);
cam_i2c_write(axi_iic, device_addr, 0x519b, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x519c, 0x06);
cam_i2c_write(axi_iic, device_addr, 0x519d, 0xa0);
cam_i2c_write(axi_iic, device_addr, 0x519e, 0xa0);
cam_i2c_write(axi_iic, device_addr, 0x3a0f, 0x3c);
cam_i2c_write(axi_iic, device_addr, 0x3a10, 0x30);
cam_i2c_write(axi_iic, device_addr, 0x3a1b, 0x3c);
cam_i2c_write(axi_iic, device_addr, 0x3a1e, 0x30);
cam_i2c_write(axi_iic, device_addr, 0x3a11, 0x70);
cam_i2c_write(axi_iic, device_addr, 0x3a1f, 0x10);
cam_i2c_write(axi_iic, device_addr, 0x3800, 0x1);
cam_i2c_write(axi_iic, device_addr, 0x3801, 0x50);
cam_i2c_write(axi_iic, device_addr, 0x3802, 0x0);
cam_i2c_write(axi_iic, device_addr, 0x3803, 0x8);
cam_i2c_write(axi_iic, device_addr, 0x3804, 0x5);
cam_i2c_write(axi_iic, device_addr, 0x3805, 0x0);
cam_i2c_write(axi_iic, device_addr, 0x3806, 0x3);
cam_i2c_write(axi_iic, device_addr, 0x3807, 0xc0);
cam_i2c_write(axi_iic, device_addr, 0x3808, 0x3);
cam_i2c_write(axi_iic, device_addr, 0x3809, 0x20);
cam_i2c_write(axi_iic, device_addr, 0x380a, 0x2);
cam_i2c_write(axi_iic, device_addr, 0x380b, 0x58);
cam_i2c_write(axi_iic, device_addr, 0x380c, 0xc);
cam_i2c_write(axi_iic, device_addr, 0x380d, 0x80);
cam_i2c_write(axi_iic, device_addr, 0x380e, 0x3);
cam_i2c_write(axi_iic, device_addr, 0x380f, 0xe8);
cam_i2c_write(axi_iic, device_addr, 0x5001, 0x7f);
cam_i2c_write(axi_iic, device_addr, 0x5680, 0x0);
cam_i2c_write(axi_iic, device_addr, 0x5681, 0x0);
cam_i2c_write(axi_iic, device_addr, 0x5682, 0x5);
cam_i2c_write(axi_iic, device_addr, 0x5683, 0x0);
cam_i2c_write(axi_iic, device_addr, 0x5684, 0x0);
cam_i2c_write(axi_iic, device_addr, 0x5685, 0x0);
cam_i2c_write(axi_iic, device_addr, 0x5686, 0x3);
cam_i2c_write(axi_iic, device_addr, 0x5687, 0xc0);
cam_i2c_write(axi_iic, device_addr, 0x5687, 0xc0);
cam_i2c_write(axi_iic, device_addr, 0x3815, 0x02);
cam_i2c_write(axi_iic, device_addr, 0x3503, 0x00);
cam_i2c_write(axi_iic, device_addr, 0x3818, 0x81); // No Mirror
cam_i2c_write(axi_iic, device_addr, 0x3621, 0xa7);
cam_i2c_write(axi_iic, device_addr, 0x4740, 0x21);
cam_i2c_write(axi_iic, device_addr, 0x501e, 0x2a);
cam_i2c_write(axi_iic, device_addr, 0x5002, 0x78);
cam_i2c_write(axi_iic, device_addr, 0x501f, 0x01);
cam_i2c_write(axi_iic, device_addr, 0x4300, 0x61);
return(0);
}
です。Ultra96用PMOD拡張基板 1枚
レベル変換IC、LSF0108,LSF0108QPWRQ1 2個
1608 パッケージの 1KΩ 16個 + 1 個予備
1608 パッケージの100 KΩ 4個 + 1 個予備
Ultra96用PMOD拡張ボード・パーツリスト,,,,,,,,
,,,,,,,,
番号,パーツ名,規格,メーカー,販売店,販売店品番,数量,URL,備考
1,DC-DCコンバータ(3.3V0.5A),M78AR033-0.5,MINMAX,秋月電子,M-07178,1,http://akizukidenshi.com/catalog/g/gM-07178/,
2,L型ピンソケット 2×10(20P),,,秋月電子,C-05755,2,http://akizukidenshi.com/catalog/g/gC-05755/,2x6に割って使用する
3,チップ積層セラミックコンデンサー 0.1ΜF50V (1608),,,秋月電子,P-13374,5,http://akizukidenshi.com/catalog/g/gP-13374/,40個入りなのでその内の5個
4,チップ積層セラミックコンデンサー 10μF35V (1608),,,秋月電子,P-13161,1,http://akizukidenshi.com/catalog/g/gP-13161/,10個入りなのでその内の1個
5,2mmピッチピンヘッダ 2×40 (80P),,,秋月電子,C-06075,0.5,http://akizukidenshi.com/catalog/g/gC-06075/,2x20Pが必要なので半分に割る
set_property PACKAGE_PIN D7 [get_ports {red[0]}]
set_property PACKAGE_PIN F8 [get_ports {red[1]}]
set_property PACKAGE_PIN F7 [get_ports {red[2]}]
set_property PACKAGE_PIN G7 [get_ports {red[3]}]
set_property PACKAGE_PIN F6 [get_ports {blue[0]}]
set_property PACKAGE_PIN G5 [get_ports {blue[1]}]
set_property PACKAGE_PIN A6 [get_ports {blue[2]}]
set_property PACKAGE_PIN A7 [get_ports {blue[3]}]
set_property PACKAGE_PIN G6 [get_ports {green[0]}]
set_property PACKAGE_PIN E6 [get_ports {green[1]}]
set_property PACKAGE_PIN E5 [get_ports {green[2]}]
set_property PACKAGE_PIN D6 [get_ports {green[3]}]
set_property PACKAGE_PIN D5 [get_ports {hsyncx[0]}]
set_property PACKAGE_PIN C7 [get_ports {vsyncx[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {blue[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {blue[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {blue[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {blue[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {hsyncx[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {vsyncx[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {green[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {green[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {green[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {green[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {red[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {red[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {red[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {red[0]}]
// vflip_dma_write.h
// 2019/01/01 by marsee
//
#ifndef __VFLIP_DMA_WRITE_H__
#define __VFLIP_DMA_WRITE_H__
#include "ap_axi_sdata.h"
#include "hls_video.h"
#define MAX_WIDTH 800
#define MAX_HEIGHT 600
typedef hls::stream<ap_axiu<32,1,1,1> > AXI_STREAM;
typedef ap_axiu<32,1,1,1> AP_AXIU32;
typedef hls::Scalar<3, unsigned char> RGB_PIXEL;
typedef hls::Mat<MAX_HEIGHT, MAX_WIDTH, HLS_8UC3> RGB_IMAGE;
typedef hls::Mat<MAX_HEIGHT, MAX_WIDTH, HLS_8UC1> GRAY_IMAGE;
#endif
// vflip_dma_write.cpp
// 2019/01/01 by marsee
//
#include <ap_int.h>
#include <hls_stream.h>
#include <ap_axi_sdata.h>
#include "vflip_dma_write.h"
int vflip_dma_write(AXI_STREAM & ins,
volatile ap_int<32> *fb0, volatile ap_int<32> *fb1, volatile ap_int<32> *fb2,
volatile ap_uint<2> &active_frame){
#pragma HLS INTERFACE s_axilite port=active_frame
#pragma HLS INTERFACE m_axi depth=480000 port=fb0 offset=slave
#pragma HLS INTERFACE m_axi depth=480000 port=fb1 offset=slave
#pragma HLS INTERFACE m_axi depth=480000 port=fb2 offset=slave
#pragma HLS INTERFACE axis register both port=ins
#pragma HLS INTERFACE s_axilite port=return
AP_AXIU32 pix;
int max_fb_chk;
active_frame = 0;
LOOP_WAIT0: do { // user が 1になった時にフレームがスタートする
#pragma HLS LOOP_TRIPCOUNT min=1 max=1 avg=1
ins >> pix;
} while(pix.user == 0);
LOOP_Y0: for (int y=MAX_HEIGHT-1; y>=0; y--){ // vflip
LOOP_X0: for (int x=0; x<MAX_WIDTH; x++){
#pragma HLS PIPELINE II=1
if (!(x==0 && y==0)) // 最初の入力はすでに入力されている
ins >> pix; // AXI4-Stream からの入力
fb0[(y*MAX_WIDTH)+x] = pix.data;
}
}
active_frame = 1;
LOOP_WAIT1: do { // user が 1になった時にフレームがスタートする
#pragma HLS LOOP_TRIPCOUNT min=1 max=1 avg=1
ins >> pix;
} while(pix.user == 0);
LOOP_Y1: for (int y=MAX_HEIGHT-1; y>=0; y--){ // vflip
LOOP_X1: for (int x=0; x<MAX_WIDTH; x++){
#pragma HLS PIPELINE II=1
if (!(x==0 && y==0)) // 最初の入力はすでに入力されている
ins >> pix; // AXI4-Stream からの入力
fb1[(y*MAX_WIDTH)+x] = pix.data;
}
}
active_frame = 2;
LOOP_WAIT2: do { // user が 1になった時にフレームがスタートする
#pragma HLS LOOP_TRIPCOUNT min=1 max=1 avg=1
ins >> pix;
} while(pix.user == 0);
LOOP_Y2: for (int y=MAX_HEIGHT-1; y>=0; y--){ // vflip
LOOP_X2: for (int x=0; x<MAX_WIDTH; x++){
#pragma HLS PIPELINE II=1
if (!(x==0 && y==0)) // 最初の入力はすでに入力されている
ins >> pix; // AXI4-Stream からの入力
fb2[(y*MAX_WIDTH)+x] = pix.data;
}
}
end:
return(0);
}
// vflip_dma_write_tb_tb.cpp
// 2019/01/01 by marsee
//
#include <ap_int.h>
#include <hls_stream.h>
#include <iostream>
#include <fstream>
#include "hls_opencv.h"
#include "vflip_dma_write.h"
int vflip_dma_write(AXI_STREAM & ins,
volatile ap_int<32> *fb0, volatile ap_int<32> *fb1, volatile ap_int<32> *fb2,
volatile ap_uint<2> &active_frame);
#define NUM_FRAME_BUFFER 3
int main()
{
using namespace cv;
AXI_STREAM ins;
AP_AXIU32 pix;
ap_uint<2> active_frame;
int *frame_buffer;
// OpenCV で 画像を読み込む
Mat src = imread("bmp_file0_vflip.bmp");
AXI_STREAM src_axi, dst_axi;
// Mat フォーマットから AXI4 Stream へ変換、3画面分
for(int i=0; i<NUM_FRAME_BUFFER; i++){
cvMat2AXIvideo(src, src_axi);
for (int y=0; y<MAX_HEIGHT; y++){
for (int x=0; x<MAX_WIDTH; x++){
src_axi >> pix;
ins << pix;
}
}
}
// frame buffer をアロケートする、3倍の領域を取ってそれを3つに分ける
if ((frame_buffer =(int *)malloc(NUM_FRAME_BUFFER * sizeof(int) * (MAX_WIDTH * MAX_HEIGHT))) == NULL){
fprintf(stderr, "Can't allocate frame_buffer0 ~ 2\n");
exit(1);
}
vflip_dma_write(ins, (volatile ap_int<32> *)frame_buffer,
(volatile ap_int<32> *)&frame_buffer[MAX_WIDTH * MAX_HEIGHT],
(volatile ap_int<32> *)&frame_buffer[2 * (MAX_WIDTH * MAX_HEIGHT)],
active_frame);
// AXI4 Stream から Mat フォーマットへ変換
// dst は宣言時にサイズとカラー・フォーマットを定義する必要がある
Mat dst[3];
for(int i=0; i<NUM_FRAME_BUFFER; i++){
dst[i] = Mat(src.rows, src.cols, CV_8UC3);
}
// dst[i] にframe_bufferから画像データをロード
for(int i=0; i<NUM_FRAME_BUFFER; i++){
Mat_<Vec3b> dst_vec3b = Mat_<Vec3b>(dst[i]);
for(int y=0; y<dst[i].rows; y++){
for(int x=0; x<dst[i].cols; x++){
Vec3b pixel;
int rgb = frame_buffer[i*(MAX_WIDTH * MAX_HEIGHT)+y*MAX_WIDTH+x];
pixel[0] = (rgb & 0xff); // blue
pixel[1] = (rgb & 0xff00) >> 8; // green
pixel[2] = (rgb & 0xff0000) >> 16; // red
dst_vec3b(y,x) = pixel;
}
}
}
// DMAされたデータをBMPフィルに書き込む
char output_file[] = "dma_result0.bmp";
for (int i=0; i<NUM_FRAME_BUFFER; i++){
switch (i){
case 0:
strcpy(output_file,"dma_result0.bmp");
break;
case 1:
strcpy(output_file,"dma_result1.bmp");
break;
case 2:
strcpy(output_file,"dma_result2.bmp");
break;
}
// Mat フォーマットからファイルに書き込み
imwrite(output_file, dst[i]);
}
//free(frame_buffer);
return 0;
}
// vhflip_dma_write.h
// 2019/01/01 by marsee
//
#ifndef __VHFLIP_DMA_WRITE_H__
#define __VHFLIP_DMA_WRITE_H__
#include "ap_axi_sdata.h"
#include "hls_video.h"
#define MAX_WIDTH 800
#define MAX_HEIGHT 600
typedef hls::stream<ap_axiu<32,1,1,1> > AXI_STREAM;
typedef ap_axiu<32,1,1,1> AP_AXIU32;
typedef hls::Scalar<3, unsigned char> RGB_PIXEL;
typedef hls::Mat<MAX_HEIGHT, MAX_WIDTH, HLS_8UC3> RGB_IMAGE;
typedef hls::Mat<MAX_HEIGHT, MAX_WIDTH, HLS_8UC1> GRAY_IMAGE;
#endif
// vhflip_dma_write.cpp
// 2019/01/01 by marsee
//
#include <ap_int.h>
#include <hls_stream.h>
#include <ap_axi_sdata.h>
#include "vhflip_dma_write.h"
int vhflip_dma_write(AXI_STREAM & ins,
volatile ap_int<32> *fb0, volatile ap_int<32> *fb1, volatile ap_int<32> *fb2,
volatile ap_uint<2> &active_frame){
#pragma HLS INTERFACE s_axilite port=active_frame
#pragma HLS INTERFACE m_axi depth=480000 port=fb0 offset=slave
#pragma HLS INTERFACE m_axi depth=480000 port=fb1 offset=slave
#pragma HLS INTERFACE m_axi depth=480000 port=fb2 offset=slave
#pragma HLS INTERFACE axis register both port=ins
#pragma HLS INTERFACE s_axilite port=return
AP_AXIU32 pix;
int max_fb_chk;
active_frame = 0;
LOOP_WAIT0: do { // user が 1になった時にフレームがスタートする
#pragma HLS LOOP_TRIPCOUNT min=1 max=1 avg=1
ins >> pix;
} while(pix.user == 0);
LOOP_Y0: for (int y=MAX_HEIGHT-1; y>=0; y--){ // vflip
LOOP_X0: for (int x=MAX_WIDTH-1; x>=0; x--){ // hflip
#pragma HLS PIPELINE II=1
if (!(x==0 && y==0)) // 最初の入力はすでに入力されている
ins >> pix; // AXI4-Stream からの入力
fb0[(y*MAX_WIDTH)+x] = pix.data;
}
}
active_frame = 1;
LOOP_WAIT1: do { // user が 1になった時にフレームがスタートする
#pragma HLS LOOP_TRIPCOUNT min=1 max=1 avg=1
ins >> pix;
} while(pix.user == 0);
LOOP_Y1: for (int y=MAX_HEIGHT-1; y>=0; y--){ // vflip
LOOP_X1: for (int x=MAX_WIDTH-1; x>=0; x--){ // hflip
#pragma HLS PIPELINE II=1
if (!(x==0 && y==0)) // 最初の入力はすでに入力されている
ins >> pix; // AXI4-Stream からの入力
fb1[(y*MAX_WIDTH)+x] = pix.data;
}
}
active_frame = 2;
LOOP_WAIT2: do { // user が 1になった時にフレームがスタートする
#pragma HLS LOOP_TRIPCOUNT min=1 max=1 avg=1
ins >> pix;
} while(pix.user == 0);
LOOP_Y2: for (int y=MAX_HEIGHT-1; y>=0; y--){ // vflip
LOOP_X2: for (int x=MAX_WIDTH-1; x>=0; x--){ // hflip
#pragma HLS PIPELINE II=1
if (!(x==0 && y==0)) // 最初の入力はすでに入力されている
ins >> pix; // AXI4-Stream からの入力
fb2[(y*MAX_WIDTH)+x] = pix.data;
}
}
end:
return(0);
}
// vhflip_dma_write_tb_tb.cpp
// 2019/01/01 by marsee
//
#include <ap_int.h>
#include <hls_stream.h>
#include <iostream>
#include <fstream>
#include "hls_opencv.h"
#include "vhflip_dma_write.h"
int vhflip_dma_write(AXI_STREAM & ins,
volatile ap_int<32> *fb0, volatile ap_int<32> *fb1, volatile ap_int<32> *fb2,
volatile ap_uint<2> &active_frame);
#define NUM_FRAME_BUFFER 3
int main()
{
using namespace cv;
AXI_STREAM ins;
AP_AXIU32 pix;
ap_uint<2> active_frame;
int *frame_buffer;
// OpenCV で 画像を読み込む
Mat src = imread("bmp_file0_vhflip.bmp");
AXI_STREAM src_axi, dst_axi;
// Mat フォーマットから AXI4 Stream へ変換、3画面分
for(int i=0; i<NUM_FRAME_BUFFER; i++){
cvMat2AXIvideo(src, src_axi);
for (int y=0; y<MAX_HEIGHT; y++){
for (int x=0; x<MAX_WIDTH; x++){
src_axi >> pix;
ins << pix;
}
}
}
// frame buffer をアロケートする、3倍の領域を取ってそれを3つに分ける
if ((frame_buffer =(int *)malloc(NUM_FRAME_BUFFER * sizeof(int) * (MAX_WIDTH * MAX_HEIGHT))) == NULL){
fprintf(stderr, "Can't allocate frame_buffer0 ~ 2\n");
exit(1);
}
vhflip_dma_write(ins, (volatile ap_int<32> *)frame_buffer,
(volatile ap_int<32> *)&frame_buffer[MAX_WIDTH * MAX_HEIGHT],
(volatile ap_int<32> *)&frame_buffer[2 * (MAX_WIDTH * MAX_HEIGHT)],
active_frame);
// AXI4 Stream から Mat フォーマットへ変換
// dst は宣言時にサイズとカラー・フォーマットを定義する必要がある
Mat dst[3];
for(int i=0; i<NUM_FRAME_BUFFER; i++){
dst[i] = Mat(src.rows, src.cols, CV_8UC3);
}
// dst[i] にframe_bufferから画像データをロード
for(int i=0; i<NUM_FRAME_BUFFER; i++){
Mat_<Vec3b> dst_vec3b = Mat_<Vec3b>(dst[i]);
for(int y=0; y<dst[i].rows; y++){
for(int x=0; x<dst[i].cols; x++){
Vec3b pixel;
int rgb = frame_buffer[i*(MAX_WIDTH * MAX_HEIGHT)+y*MAX_WIDTH+x];
pixel[0] = (rgb & 0xff); // blue
pixel[1] = (rgb & 0xff00) >> 8; // green
pixel[2] = (rgb & 0xff0000) >> 16; // red
dst_vec3b(y,x) = pixel;
}
}
}
// DMAされたデータをBMPフィルに書き込む
char output_file[] = "dma_result0.bmp";
for (int i=0; i<NUM_FRAME_BUFFER; i++){
switch (i){
case 0:
strcpy(output_file,"dma_result0.bmp");
break;
case 1:
strcpy(output_file,"dma_result1.bmp");
break;
case 2:
strcpy(output_file,"dma_result2.bmp");
break;
}
// Mat フォーマットからファイルに書き込み
imwrite(output_file, dst[i]);
}
//free(frame_buffer);
return 0;
}
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