set_property platform.design_intent.embedded true [current_project]
set_property platform.design_intent.server_managed false [current_project]
set_property platform.design_intent.external_host false [current_project]
set_property platform.design_intent.datacenter false [current_project]
set_property platform.default_output_type "sd_card" [current_project]
Vivado HLS の基礎的なサンプル
AXI4 Lite Slave 編
AXI4 Master 編
AXI4 Stream 編
Device[0]: program successful!
TEST PASSED
U-Boot 2019.01 (Nov 25 2019 - 04:39:59 +0000) Xilinx Zynq ZC702
CPU: Zynq 7z020
Silicon: v3.1
DRAM: ECC disabled 1 GiB
MMC: mmc@e0100000: 0
Loading Environment from SPI Flash... SF: Detected s25fl128s_64k with page size 256 Bytes, erase size 64 KiB, total 16 MiB
*** Warning - bad CRC, using default environment
In: serial@e0001000
Out: serial@e0001000
Err: serial@e0001000
Net: ZYNQ GEM: e000b000, phyaddr ffffffff, interface rgmii-id
eth0: ethernet@e000b000
U-BOOT for zybo_z7_20_min
ethernet@e000b000 Waiting for PHY auto negotiation to complete......... TIMEOUT !
Hit any key to stop autoboot: 0
Device: mmc@e0100000
Manufacturer ID: 9f
OEM: 5449
Name: SPCCBus Speed: 25000000
Mode : SD Legacy
Rd Block Len: 512
SD version 3.0
High Capacity: Yes
Capacity: 14.6 GiB
Bus Width: 4-bit
Erase Group Size: 512 Bytes
4124340 bytes read in 360 ms (10.9 MiB/s)
## Loading kernel from FIT Image at 10000000 ...
Using 'conf@system-top.dtb' configuration
Verifying Hash Integrity ... OK
Trying 'kernel@1' kernel subimage
Description: Linux kernel
Type: Kernel Image
Compression: uncompressed
Data Start: 0x100000f4
Data Size: 4108384 Bytes = 3.9 MiB
Architecture: ARM
OS: Linux
Load Address: 0x00008000
Entry Point: 0x00008000
Hash algo: sha1
Hash value: 4be0ff978b7eac351ee07468445ce106499d57b3
Verifying Hash Integrity ... sha1+ OK
## Loading fdt from FIT Image at 10000000 ...
Using 'conf@system-top.dtb' configuration
Verifying Hash Integrity ... OK
Trying 'fdt@system-top.dtb' fdt subimage
Description: Flattened Device Tree blob
Type: Flat Device Tree
Compression: uncompressed
Data Start: 0x103eb254
Data Size: 14061 Bytes = 13.7 KiB
Architecture: ARM
Hash algo: sha1
Hash value: a12b86da0bc898497d48a5922cc1004d39ccb195
Verifying Hash Integrity ... sha1+ OK
Booting using the fdt blob at 0x103eb254
Loading Kernel Image ... OK
Loading Device Tree to 07ff9000, end 07fff6ec ... OK
Starting kernel ...
Booting Linux on physical CPU 0x0
Linux version 4.19.0-xilinx-v2019.2 (oe-user@oe-host) (gcc version 8.2.0 (GCC)) #1 SMP PREEMPT Mon Nov 25 04:37:41 UTC 2019
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
OF: fdt: Machine model: xlnx,zynq-7000
earlycon: cdns0 at MMIO 0xe0001000 (options '115200n8')
bootconsole [cdns0] enabled
Memory policy: Data cache writealloc
cma: Reserved 256 MiB at 0x30000000
random: get_random_bytes called from start_kernel+0x80/0x3c4 with crng_init=0
percpu: Embedded 16 pages/cpu @(ptrval) s34956 r8192 d22388 u65536
Built 1 zonelists, mobility grouping on. Total pages: 260608
Kernel command line: console=ttyPS0,115200 earlycon root=/dev/mmcblk0p2 rw rootwait
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
Memory: 767092K/1048576K available (6144K kernel code, 202K rwdata, 1596K rodata, 1024K init, 246K bss, 19340K reserved, 262144K cma-reserved, 0K highmem)
Virtual kernel memory layout:
vector : 0xffff0000 - 0xffff1000 ( 4 kB)
fixmap : 0xffc00000 - 0xfff00000 (3072 kB)
vmalloc : 0xf0800000 - 0xff800000 ( 240 MB)
lowmem : 0xc0000000 - 0xf0000000 ( 768 MB)
pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB)
modules : 0xbf000000 - 0xbfe00000 ( 14 MB)
.text : 0x(ptrval) - 0x(ptrval) (7136 kB)
.init : 0x(ptrval) - 0x(ptrval) (1024 kB)
.data : 0x(ptrval) - 0x(ptrval) ( 203 kB)
.bss : 0x(ptrval) - 0x(ptrval) ( 247 kB)
rcu: Preemptible hierarchical RCU implementation.
rcu: RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
Tasks RCU enabled.
rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
efuse mapped to (ptrval)
slcr mapped to (ptrval)
L2C: platform modifies aux control register: 0x72360000 -> 0x72760000
L2C: DT/platform modifies aux control register: 0x72360000 -> 0x72760000
L2C-310 erratum 769419 enabled
L2C-310 enabling early BRESP for Cortex-A9
L2C-310 full line of zeros enabled for Cortex-A9
L2C-310 ID prefetch enabled, offset 1 lines
L2C-310 dynamic clock gating enabled, standby mode enabled
L2C-310 cache controller enabled, 8 ways, 512 kB
L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x76760001
zynq_clock_init: clkc starts at (ptrval)
Zynq clock init
sched_clock: 64 bits at 333MHz, resolution 3ns, wraps every 4398046511103ns
clocksource: arm_global_timer: mask: 0xffffffffffffffff max_cycles: 0x4ce07af025, max_idle_ns: 440795209040 ns
Switching to timer-based delay loop, resolution 3ns
clocksource: ttc_clocksource: mask: 0xffff max_cycles: 0xffff, max_idle_ns: 537538477 ns
timer #0 at (ptrval), irq=17
Console: colour dummy device 80x30
Calibrating delay loop (skipped), value calculated using timer frequency.. 666.66 BogoMIPS (lpj=3333333)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
CPU: Testing write buffer coherency: ok
CPU0: Spectre v2: using BPIALL workaround
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0x100000 - 0x100060
rcu: Hierarchical SRCU implementation.
smp: Bringing up secondary CPUs ...
CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
CPU1: Spectre v2: using BPIALL workaround
smp: Brought up 1 node, 2 CPUs
SMP: Total of 2 processors activated (1333.33 BogoMIPS).
CPU: All CPU(s) started in SVC mode.
devtmpfs: initialized
VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
futex hash table entries: 512 (order: 3, 32768 bytes)
pinctrl core: initialized pinctrl subsystem
NET: Registered protocol family 16
DMA: preallocated 256 KiB pool for atomic coherent allocations
hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
hw-breakpoint: maximum watchpoint size is 4 bytes.
zynq-ocm f800c000.ocmc: ZYNQ OCM pool: 256 KiB @ 0x(ptrval)
zynq-pinctrl 700.pinctrl: zynq pinctrl initialized
e0001000.serial: ttyPS0 at MMIO 0xe0001000 (irq = 25, base_baud = 6249999) is a xuartps
console [ttyPS0] enabled
console [ttyPS0] enabled
bootconsole [cdns0] disabled
bootconsole [cdns0] disabled
vgaarb: loaded
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
media: Linux media interface: v0.10
videodev: Linux video capture interface: v2.00
pps_core: LinuxPPS API ver. 1 registered
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
PTP clock support registered
EDAC MC: Ver: 3.0.0
FPGA manager framework
Advanced Linux Sound Architecture Driver Initialized.
clocksource: Switched to clocksource arm_global_timer
NET: Registered protocol family 2
tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 6144 bytes)
TCP established hash table entries: 8192 (order: 3, 32768 bytes)
TCP bind hash table entries: 8192 (order: 4, 65536 bytes)
TCP: Hash tables configured (established 8192 bind 8192)
UDP hash table entries: 512 (order: 2, 16384 bytes)
UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
hw perfevents: no interrupt-affinity property for /pmu@f8891000, guessing.
hw perfevents: enabled with armv7_cortex_a9 PMU driver, 7 counters available
workingset: timestamp_bits=30 max_order=18 bucket_order=0
jffs2: version 2.2. (NAND) (SUMMARY) © 2001-2006 Red Hat, Inc.
bounce: pool size: 64 pages
io scheduler noop registered
io scheduler deadline registered
io scheduler cfq registered (default)
io scheduler mq-deadline registered
io scheduler kyber registered
dma-pl330 f8003000.dmac: Loaded driver for PL330 DMAC-241330
dma-pl330 f8003000.dmac: DBUFF-128x8bytes Num_Chans-8 Num_Peri-4 Num_Events-16
brd: module loaded
loop: module loaded
m25p80 spi0.0: found s25fl128s, expected n25q512a
m25p80 spi0.0: s25fl128s (16384 Kbytes)
4 fixed-partitions partitions found on MTD device spi0.0
Creating 4 MTD partitions on "spi0.0":
0x000000000000-0x000000500000 : "boot"
0x000000500000-0x000000520000 : "bootenv"
0x000000520000-0x000000fa0000 : "kernel"
0x000000fa0000-0x000001000000 : "spare"
libphy: Fixed MDIO Bus: probed
CAN device driver interface
libphy: MACB_mii_bus: probed
RTL8211E Gigabit Ethernet e000b000.ethernet-ffffffff:00: attached PHY driver [RTL8211E Gigabit Ethernet] (mii_bus:phy_addr=e000b000.ethernet-ffffffff:00, irq=POLL)
macb e000b000.ethernet eth0: Cadence GEM rev 0x00020118 at 0xe000b000 irq 27 (00:0a:35:00:1e:53)
e1000e: Intel(R) PRO/1000 Network Driver - 3.2.6-k
e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
ehci-pci: EHCI PCI platform driver
usbcore: registered new interface driver usb-storage
i2c /dev entries driver
cdns-wdt f8005000.watchdog: Xilinx Watchdog Timer with timeout 10s
EDAC MC: ECC not enabled
sdhci: Secure Digital Host Controller Interface driver
sdhci: Copyright(c) Pierre Ossman
sdhci-pltfm: SDHCI platform and OF driver helper
mmc0: SDHCI controller on e0100000.mmc [e0100000.mmc] using ADMA
ledtrig-cpu: registered to indicate activity on CPUs
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
xlnk xlnk: Major 244
xlnk xlnk: xlnk driver loaded
xlnk xlnk: xlnk_pdev is not null
fpga_manager fpga0: Xilinx Zynq FPGA Manager registered
NET: Registered protocol family 10
Segment Routing with IPv6
sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
NET: Registered protocol family 17
can: controller area network core (rev 20170425 abi 9)
NET: Registered protocol family 29
can: raw protocol (rev 20170425)
can: broadcast manager protocol (rev 20170425 t)
can: netlink gateway (rev 20170425) max_hops=1
Registering SWP/SWPB emulation handler
of-fpga-region fpga-full: FPGA Region probed
hctosys: unable to open rtc device (rtc0)
of_cfs_init
of_cfs_init: OK
ALSA device list:
No soundcards found.
Waiting for root device /dev/mmcblk0p2...
mmc0: Problem switching card into high-speed mode!
mmc0: new SDHC card at address 0001
mmcblk0: mmc0:0001 SPCC 14.6 GiB
mmcblk0: p1 p2
EXT4-fs (mmcblk0p2): mounted filesystem with ordered data mode. Opts: (null)
VFS: Mounted root (ext4 filesystem) on device 179:2.
devtmpfs: mounted
Freeing unused kernel memory: 1024K
Run /sbin/init as init process
INIT: version 2.88 booting
random: fast init done
Starting udev
udevd[732]: starting version 3.2.5
random: udevd: uninitialized urandom read (16 bytes read)
random: udevd: uninitialized urandom read (16 bytes read)
random: udevd: uninitialized urandom read (16 bytes read)
udevd[733]: starting eudev-3.2.5
FAT-fs (mmcblk0p1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck.
EXT4-fs (mmcblk0p2): re-mounted. Opts: (null)
hwclock: can't open '/dev/misc/rtc': No such file or directory
Thu Jan 1 00:19:28 UTC 1970
hwclock: can't open '/dev/misc/rtc': No such file or directory
urandom_read: 2 callbacks suppressed
random: dd: uninitialized urandom read (512 bytes read)
INIT: Entering runlevel: 5
Configuring network interfaces... IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
udhcpc: started, v1.29.2
udhcpc: sending discover
udhcpc: sending discover
udhcpc: sending discover
udhcpc: no lease, forking to background
done.
Starting system message bus: random: dbus-daemon: uninitialized urandom read (12 bytes read)
random: dbus-daemon: uninitialized urandom read (12 bytes read)
dbus.
Starting haveged: haveged: listening socket at 3
haveged: haveged starting up
Starting Dropbear SSH server: random: dropbear: uninitialized urandom read (32 bytes read)
dropbear.
hwclock: can't open '/dev/misc/rtc': No such file or directory
Starting internet superserver: inetd.
Starting syslogd/klogd: done
Starting tcf-agent: OK
PetaLinux 2019.2 zybo_z7_20_min /dev/ttyPS0
zybo_z7_20_min login: random: crng init done
PetaLinux 2019.2 zybo_z7_20_min /dev/ttyPS0
zybo_z7_20_min login: root
root@zybo_z7_20_min:~# insmod /lib/modules/4.19.0-xilinx-v2019.2/extra/zocl.ko
zocl: loading out-of-tree module taints kernel.
[drm] Probing for xlnx,zocl
[drm] PR Isolation addr 0x0
[drm] Initialized zocl 2018.2.1 20180313 for 80000000.zyxclmm_drm on minor 0
root@zybo_z7_20_min:~# cd /run/media/mmcblk0p1/
root@zybo_z7_20_min:/run/media/mmcblk0p1# export XILINX_XRT=/usr
root@zybo_z7_20_min:/run/media/mmcblk0p1# ./init.sh
[drm] Pid 1152 opened device
[drm] Pid 1152 closed device
[drm] Pid 1152 opened device
Found Platform
Platform Name: Xilinx
INFO: Reading ./build_dir.hw.zybo_z7_20_min/vadd.xclbin
Loading: './build_dir.hw.zybo_z7_20_min/vadd.xclbin'
Trying to program device[0]: edge
[drm] Finding IP_LAYOUT section header
[drm] Section IP_LAYOUT details:
[drm] offset = 0x3dbf28
[drm] size = 0x58
[drm] Finding DEBUG_IP_LAYOUT section header
[drm] AXLF section DEBUG_IP_LAYOUT header not found
[drm] Finding CONNECTIVITY section header
[drm] Section CONNECTIVITY details:
[drm] offset = 0x3dbf80
[drm] size = 0x28
[drm] Finding MEM_TOPOLOGY section header
[drm] Section MEM_TOPOLOGY details:
[drm] offset = 0x3dbe58
[drm] size = 0xd0
[drm] No ERT scheduler on MPSoC, using KDS
[drm] Fail to install CU 0 interrupt handler: -22. Fall back to polling mode.
[drm] scheduler config ert(0)
[drm] cus(1)
[drm] slots(16)
[drm] num_cu_masks(1)
[drm] cu_shift(16)
[drm] cu_base(0x40000000)
Device[0]: program successful!
TEST PASSED
[drm] polling(1)
[drm] zocl_free_userptr_bo: obj 0x3c156f65
[drm] zocl_free_userptr_bo: obj 0x8b19c77d
[drm] zocl_free_userptr_bo: obj 0x8f0540b9
[drm] Pid 1152 closed device
root@zybo_z7_20_min:/run/media/mmcblk0p1#
masaaki@masaaki-H110M4-M01:~/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition$ make all TARGET=hw DEVICE=ultra96v2_min HOST_ARCH=aarch64 SYSROOT=/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min/images/linux/ultra96v2_min_pkg/pfm/sysroots/aarch64-xilinx-linux/
/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/gnu/aarch64/lin/aarch64-linux/bin/aarch64-linux-gnu-g++ -I../..//common/includes/xcl2 -I/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min/images/linux/ultra96v2_min_pkg/pfm/sysroots/aarch64-xilinx-linux//usr//include/xrt -I/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vivado/2019.2/include -Wall -O0 -g -std=c++11 -fmessage-length=0 ../..//common/includes/xcl2/xcl2.cpp src/host.cpp -o 'array_partition' -L/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min/images/linux/ultra96v2_min_pkg/pfm/sysroots/aarch64-xilinx-linux//usr//lib -lOpenCL -lpthread -lrt -lstdc++ --sysroot=/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min/images/linux/ultra96v2_min_pkg/pfm/sysroots/aarch64-xilinx-linux/
mkdir -p ./_x.hw.ultra96v2_min
v++ -t hw --platform ultra96v2_min --save-temps --temp_dir ./_x.hw.ultra96v2_min -c -k matmul -I'src' -o'_x.hw.ultra96v2_min/matmul.xo' 'src/matmul.cpp'
Option Map File Used: '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/data/vitis/vpp/optMap.xml'
****** v++ v2019.2 (64-bit)
**** SW Build 2700185 on Thu Oct 24 18:45:48 MDT 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
INFO: [v++ 60-1306] Additional information associated with this v++ compile can be found at:
Reports: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/_x.hw.ultra96v2_min/reports/matmul
Log files: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/_x.hw.ultra96v2_min/logs/matmul
Running Dispatch Server on port:33265
INFO: [v++ 60-1548] Creating build summary session with primary output /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/_x.hw.ultra96v2_min/matmul.xo.compile_summary, at Sat Nov 23 07:53:02 2019
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Sat Nov 23 07:53:02 2019
Running Rule Check Server on port:46729
INFO: [v++ 60-1315] Creating rulecheck session with output '/home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/_x.hw.ultra96v2_min/reports/matmul/v++_compile_matmul_guidance.html', at Sat Nov 23 07:53:03 2019
INFO: [v++ 60-895] Target platform: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min/ultra96v2_min.xpfm
INFO: [v++ 60-1578] This platform contains Xilinx Shell Archive '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min/hw/ultra96v2_min.xsa'
INFO: [v++ 60-585] Compiling for hardware target
INFO: [v++ 60-423] Target device: ultra96v2_min
INFO: [v++ 60-242] Creating kernel: 'matmul'
===>The following messages were generated while performing high-level synthesis for kernel: matmul Log file: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/_x.hw.ultra96v2_min/matmul/matmul/vivado_hls.log :
INFO: [v++ 204-61] Option 'relax_ii_for_timing' is enabled, will increase II to preserve clock frequency constraints.
INFO: [v++ 204-61] Pipelining loop 'readA'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining loop 'readB'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining loop 'nopart1_nopart2'.
WARNING: [v++ 204-69] Unable to schedule 'load' operation ('B_load_2', /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/src/matmul.cpp:99) on array 'B', /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/src/matmul.cpp:59 due to limited memory ports. Please consider using a memory core with more ports or partitioning the array 'B'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 8, Depth = 10.
INFO: [v++ 204-61] Pipelining loop 'writeC'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 200-790] **** Loop Constraint Status: All loop constraints were NOT satisfied.
INFO: [v++ 200-789] **** Estimated Fmax: 136.99 MHz
INFO: [v++ 60-594] Finished kernel compilation
INFO: [v++ 60-244] Generating system estimate report...
INFO: [v++ 60-1092] Generated system estimate report: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/_x.hw.ultra96v2_min/reports/matmul/system_estimate_matmul.xtxt
INFO: [v++ 60-586] Created _x.hw.ultra96v2_min/matmul.xo
INFO: [v++ 60-791] Total elapsed time: 0h 0m 31s
mkdir -p ./_x.hw.ultra96v2_min
v++ -t hw --platform ultra96v2_min --save-temps --temp_dir ./_x.hw.ultra96v2_min -c -k matmul_partition -I'src' -o'_x.hw.ultra96v2_min/matmul_partition.xo' 'src/matmul_partition.cpp'
Option Map File Used: '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/data/vitis/vpp/optMap.xml'
****** v++ v2019.2 (64-bit)
**** SW Build 2700185 on Thu Oct 24 18:45:48 MDT 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
INFO: [v++ 60-1306] Additional information associated with this v++ compile can be found at:
Reports: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/_x.hw.ultra96v2_min/reports/matmul_partition
Log files: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/_x.hw.ultra96v2_min/logs/matmul_partition
Running Dispatch Server on port:34733
INFO: [v++ 60-1548] Creating build summary session with primary output /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/_x.hw.ultra96v2_min/matmul_partition.xo.compile_summary, at Sat Nov 23 07:53:36 2019
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Sat Nov 23 07:53:36 2019
Running Rule Check Server on port:37765
INFO: [v++ 60-1315] Creating rulecheck session with output '/home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/_x.hw.ultra96v2_min/reports/matmul_partition/v++_compile_matmul_partition_guidance.html', at Sat Nov 23 07:53:37 2019
INFO: [v++ 60-895] Target platform: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min/ultra96v2_min.xpfm
INFO: [v++ 60-1578] This platform contains Xilinx Shell Archive '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min/hw/ultra96v2_min.xsa'
INFO: [v++ 60-585] Compiling for hardware target
INFO: [v++ 60-423] Target device: ultra96v2_min
INFO: [v++ 60-242] Creating kernel: 'matmul_partition'
===>The following messages were generated while performing high-level synthesis for kernel: matmul_partition Log file: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/_x.hw.ultra96v2_min/matmul_partition/matmul_partition/vivado_hls.log :
INFO: [v++ 204-61] Option 'relax_ii_for_timing' is enabled, will increase II to preserve clock frequency constraints.
INFO: [v++ 204-61] Pipelining loop 'read_A'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining loop 'read_B'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining loop 'arraypart1_arraypart2'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [v++ 204-61] Pipelining loop 'writeC'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 200-790] **** Loop Constraint Status: All loop constraints were satisfied.
INFO: [v++ 200-789] **** Estimated Fmax: 136.99 MHz
INFO: [v++ 60-594] Finished kernel compilation
INFO: [v++ 60-244] Generating system estimate report...
INFO: [v++ 60-1092] Generated system estimate report: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/_x.hw.ultra96v2_min/reports/matmul_partition/system_estimate_matmul_partition.xtxt
INFO: [v++ 60-586] Created _x.hw.ultra96v2_min/matmul_partition.xo
INFO: [v++ 60-791] Total elapsed time: 0h 0m 31s
mkdir -p ./build_dir.hw.ultra96v2_min
v++ -t hw --platform ultra96v2_min --save-temps --temp_dir ./build_dir.hw.ultra96v2_min -l -o'build_dir.hw.ultra96v2_min/matmul.xclbin' _x.hw.ultra96v2_min/matmul.xo _x.hw.ultra96v2_min/matmul_partition.xo
Option Map File Used: '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/data/vitis/vpp/optMap.xml'
****** v++ v2019.2 (64-bit)
**** SW Build 2700185 on Thu Oct 24 18:45:48 MDT 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
INFO: [v++ 60-1306] Additional information associated with this v++ link can be found at:
Reports: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/reports/link
Log files: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/logs/link
Running Dispatch Server on port:37971
INFO: [v++ 60-1548] Creating build summary session with primary output /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/matmul.xclbin.link_summary, at Sat Nov 23 07:54:09 2019
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Sat Nov 23 07:54:09 2019
Running Rule Check Server on port:35129
INFO: [v++ 60-1315] Creating rulecheck session with output '/home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/reports/link/v++_link_matmul_guidance.html', at Sat Nov 23 07:54:10 2019
INFO: [v++ 60-895] Target platform: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min/ultra96v2_min.xpfm
INFO: [v++ 60-1578] This platform contains Xilinx Shell Archive '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min/hw/ultra96v2_min.xsa'
INFO: [v++ 60-629] Linking for hardware target
INFO: [v++ 60-423] Target device: ultra96v2_min
INFO: [v++ 60-1332] Run 'run_link' status: Not started
INFO: [v++ 60-1443] [07:54:10] Run run_link: Step system_link: Started
INFO: [v++ 60-1453] Command Line: system_link --xo /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/_x.hw.ultra96v2_min/matmul.xo --xo /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/_x.hw.ultra96v2_min/matmul_partition.xo -keep --xpfm /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min/ultra96v2_min.xpfm --target hw --output_dir /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int --temp_dir /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/sys_link
INFO: [v++ 60-1454] Run Directory: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/run_link
INFO: [SYSTEM_LINK 82-76] Reading emulation BD and HPFM information
INFO: [SYSTEM_LINK 60-1316] Initiating connection to rulecheck server, at Sat Nov 23 07:54:11 2019
INFO: [SYSTEM_LINK 82-70] Extracting xo v3 file /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/_x.hw.ultra96v2_min/matmul.xo
INFO: [KernelCheck 83-118] 'matmul' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'in1' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'in2' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'out_r' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'size' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [SYSTEM_LINK 82-70] Extracting xo v3 file /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/_x.hw.ultra96v2_min/matmul_partition.xo
INFO: [KernelCheck 83-118] 'matmul_partition' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'in1' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'in2' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'out_r' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'size' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [SYSTEM_LINK 82-53] Creating IP database /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/sys_link/_sysl/.cdb/xd_ip_db.xml
INFO: [SYSTEM_LINK 82-38] [07:54:11] build_xd_ip_db started: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/bin/build_xd_ip_db -ip_search 0 -sds-pf /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/sys_link/ultra96v2_min.hpfm -clkid 0 -ip /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/sys_link/iprepo/xilinx_com_hls_matmul_1_0,matmul -ip /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/sys_link/iprepo/xilinx_com_hls_matmul_partition_1_0,matmul_partition -o /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/sys_link/_sysl/.cdb/xd_ip_db.xml
INFO: [SYSTEM_LINK 82-37] [07:54:14] build_xd_ip_db finished successfully
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 296.438 ; gain = 0.000 ; free physical = 1937 ; free virtual = 38456
INFO: [SYSTEM_LINK 82-51] Create system connectivity graph
INFO: [SYSTEM_LINK 82-102] Applying explicit connections to the system connectivity graph: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/sys_link/cfgraph/cfgen_cfgraph.xml
INFO: [SYSTEM_LINK 82-38] [07:54:14] cfgen started: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/bin/cfgen -dmclkid 0 -r /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/sys_link/cfgraph/cfgen_cfgraph.xml
INFO: [CFGEN 83-0] Kernel Specs:
INFO: [CFGEN 83-0] kernel: matmul, num: 1 {matmul_1}
INFO: [CFGEN 83-0] kernel: matmul_partition, num: 1 {matmul_partition_1}
INFO: [CFGEN 83-2226] Inferring mapping for argument matmul_1.in1 to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument matmul_1.in2 to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument matmul_1.out_r to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument matmul_partition_1.in1 to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument matmul_partition_1.in2 to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument matmul_partition_1.out_r to HP
INFO: [SYSTEM_LINK 82-37] [07:54:15] cfgen finished successfully
Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.28 . Memory (MB): peak = 296.438 ; gain = 0.000 ; free physical = 1937 ; free virtual = 38456
INFO: [SYSTEM_LINK 82-52] Create top-level block diagram
INFO: [SYSTEM_LINK 82-38] [07:54:15] cf2bd started: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/bin/cf2bd --linux --trace_buffer 1024 --input_file /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/sys_link/cfgraph/cfgen_cfgraph.xml --ip_db /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/sys_link/_sysl/.cdb/xd_ip_db.xml --cf_name dr --working_dir /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/sys_link/_sysl/.xsd --temp_dir /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/sys_link --output_dir /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int
INFO: [CF2BD 82-31] Launching cf2xd: cf2xd -linux -trace-buffer 1024 -i /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/sys_link/cfgraph/cfgen_cfgraph.xml -r /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o dr.xml
INFO: [CF2BD 82-28] cf2xd finished successfully
INFO: [CF2BD 82-31] Launching cf_xsd: cf_xsd -disable-address-gen -dn dr -dp /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/sys_link/_sysl/.xsd
rlwrap: warning: your $TERM is 'xterm-256color' but rlwrap couldn't find it in the terminfo database. Expect some problems.: Inappropriate ioctl for device
INFO: [CF2BD 82-28] cf_xsd finished successfully
INFO: [SYSTEM_LINK 82-37] [07:54:17] cf2bd finished successfully
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 296.438 ; gain = 0.000 ; free physical = 1930 ; free virtual = 38453
INFO: [v++ 60-1441] [07:54:17] Run run_link: Step system_link: Completed
Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 677.902 ; gain = 0.000 ; free physical = 1948 ; free virtual = 38472
INFO: [v++ 60-1443] [07:54:17] Run run_link: Step cf2sw: Started
INFO: [v++ 60-1453] Command Line: cf2sw -sdsl /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/sdsl.dat -rtd /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/cf2sw.rtd -xclbin /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/xclbin_orig.xml -o /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/xclbin_orig.1.xml
INFO: [v++ 60-1454] Run Directory: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/run_link
INFO: [v++ 60-1441] [07:54:17] Run run_link: Step cf2sw: Completed
Time (s): cpu = 00:00:00.57 ; elapsed = 00:00:00.60 . Memory (MB): peak = 677.902 ; gain = 0.000 ; free physical = 1946 ; free virtual = 38470
INFO: [v++ 60-1443] [07:54:17] Run run_link: Step rtd2_system_diagram: Started
INFO: [v++ 60-1453] Command Line: rtd2SystemDiagram --rtdJsonFileName /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/cf2sw.rtd --diagramJsonFileName /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/systemDiagramModel.json --platformFilePath /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min/ultra96v2_min.xpfm --generatedByName v++ --generatedByVersion 2019.2 --generatedByChangeList 2700185 --generatedByTimeStamp Thu Oct 24 18:45:48 MDT 2019 --generatedByOptions /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/bin/unwrapped/lnx64.o/v++ -t hw --platform ultra96v2_min --save-temps --temp_dir ./build_dir.hw.ultra96v2_min -l -obuild_dir.hw.ultra96v2_min/matmul.xclbin _x.hw.ultra96v2_min/matmul.xo _x.hw.ultra96v2_min/matmul_partition.xo --generatedByXclbinName matmul --kernelInfoDataFileName /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/kernel_info.dat
INFO: [v++ 60-1454] Run Directory: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/run_link
WARNING: [v++ 82-164] Unable to populate user region instance path. The platform file does not contain a hardwarePlatform.devices..core.instPath entry.
INFO: [v++ 60-839] Read in kernel information from file '/home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/kernel_info.dat'.
WARNING: [v++ 82-163] Unable to populate user region available resources. The platform file deos not contain a hardwarePlatform.devices..core.availableResources entry
INFO: [v++ 60-1441] [07:54:19] Run run_link: Step rtd2_system_diagram: Completed
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 677.902 ; gain = 0.000 ; free physical = 1949 ; free virtual = 38472
INFO: [v++ 60-1443] [07:54:19] Run run_link: Step vpl: Started
INFO: [v++ 60-1453] Command Line: vpl -t hw -f ultra96v2_min -s --output_dir /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int --log_dir /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/logs/link --report_dir /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/reports/link --config /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/vplConfig.ini -k /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/kernel_info.dat --webtalk_flag Vitis --temp_dir /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link --no-info --tlog_dir /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/.tlog/v++_link_matmul --iprepo /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/xo/ip_repo/xilinx_com_hls_matmul_partition_1_0 --iprepo /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/xo/ip_repo/xilinx_com_hls_matmul_1_0 --messageDb /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/run_link/vpl.pb /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/dr.bd.tcl
INFO: [v++ 60-1454] Run Directory: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/run_link
****** vpl v2019.2 (64-bit)
**** SW Build 2700185 on Thu Oct 24 18:45:48 MDT 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
INFO: [VPL 60-839] Read in kernel information from file '/home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/kernel_info.dat'.
INFO: [VPL 60-423] Target device: ultra96v2_min
INFO: [VPL 60-1032] Extracting hardware platform to /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/vivado/vpl/.local/hw_platform
[07:54:30] Run vpl: Step create_project: Started
Creating Vivado project.
[07:54:39] Run vpl: Step create_project: Completed
[07:54:39] Run vpl: Step create_bd: Started
[07:54:49] Run vpl: Step create_bd: Completed
[07:54:49] Run vpl: Step update_bd: Started
[07:54:50] Run vpl: Step update_bd: Completed
[07:54:50] Run vpl: Step generate_target: Started
[07:55:24] Run vpl: Step generate_target: Completed
[07:55:24] Run vpl: Step config_hw_runs: Started
[07:55:26] Run vpl: Step config_hw_runs: Completed
[07:55:26] Run vpl: Step synth: Started
[07:55:57] Block-level synthesis in progress, 0 of 17 jobs complete, 2 jobs running.
[07:56:27] Block-level synthesis in progress, 0 of 17 jobs complete, 2 jobs running.
[07:56:57] Block-level synthesis in progress, 0 of 17 jobs complete, 2 jobs running.
[07:57:27] Block-level synthesis in progress, 0 of 17 jobs complete, 2 jobs running.
[07:57:58] Block-level synthesis in progress, 1 of 17 jobs complete, 1 job running.
[07:58:28] Block-level synthesis in progress, 2 of 17 jobs complete, 1 job running.
[07:58:58] Block-level synthesis in progress, 2 of 17 jobs complete, 2 jobs running.
[07:59:28] Block-level synthesis in progress, 2 of 17 jobs complete, 2 jobs running.
[07:59:58] Block-level synthesis in progress, 2 of 17 jobs complete, 2 jobs running.
[08:00:28] Block-level synthesis in progress, 3 of 17 jobs complete, 1 job running.
[08:00:58] Block-level synthesis in progress, 4 of 17 jobs complete, 2 jobs running.
[08:01:28] Block-level synthesis in progress, 4 of 17 jobs complete, 2 jobs running.
[08:01:58] Block-level synthesis in progress, 4 of 17 jobs complete, 2 jobs running.
[08:02:28] Block-level synthesis in progress, 5 of 17 jobs complete, 1 job running.
[08:02:58] Block-level synthesis in progress, 6 of 17 jobs complete, 1 job running.
[08:03:28] Block-level synthesis in progress, 6 of 17 jobs complete, 2 jobs running.
[08:03:59] Block-level synthesis in progress, 8 of 17 jobs complete, 1 job running.
[08:04:29] Block-level synthesis in progress, 8 of 17 jobs complete, 2 jobs running.
[08:04:59] Block-level synthesis in progress, 8 of 17 jobs complete, 2 jobs running.
[08:05:29] Block-level synthesis in progress, 8 of 17 jobs complete, 2 jobs running.
[08:05:59] Block-level synthesis in progress, 10 of 17 jobs complete, 0 jobs running.
[08:06:29] Block-level synthesis in progress, 10 of 17 jobs complete, 2 jobs running.
[08:06:59] Block-level synthesis in progress, 10 of 17 jobs complete, 2 jobs running.
[08:07:29] Block-level synthesis in progress, 10 of 17 jobs complete, 2 jobs running.
[08:07:59] Block-level synthesis in progress, 11 of 17 jobs complete, 1 job running.
[08:08:30] Block-level synthesis in progress, 12 of 17 jobs complete, 1 job running.
[08:09:00] Block-level synthesis in progress, 12 of 17 jobs complete, 2 jobs running.
[08:09:30] Block-level synthesis in progress, 12 of 17 jobs complete, 2 jobs running.
[08:10:00] Block-level synthesis in progress, 12 of 17 jobs complete, 2 jobs running.
[08:10:30] Block-level synthesis in progress, 13 of 17 jobs complete, 1 job running.
[08:11:00] Block-level synthesis in progress, 14 of 17 jobs complete, 1 job running.
[08:11:30] Block-level synthesis in progress, 14 of 17 jobs complete, 2 jobs running.
[08:12:00] Block-level synthesis in progress, 14 of 17 jobs complete, 2 jobs running.
[08:12:31] Block-level synthesis in progress, 14 of 17 jobs complete, 2 jobs running.
[08:13:01] Block-level synthesis in progress, 16 of 17 jobs complete, 0 jobs running.
[08:13:31] Block-level synthesis in progress, 17 of 17 jobs complete, 0 jobs running.
[08:14:01] Top-level synthesis in progress.
[08:14:31] Top-level synthesis in progress.
[08:15:01] Top-level synthesis in progress.
[08:15:13] Run vpl: Step synth: Completed
[08:15:13] Run vpl: Step impl: Started
[08:17:14] Finished 2nd of 6 tasks (FPGA linking synthesized kernels to platform). Elapsed time: 00h 22m 53s
[08:17:14] Starting logic optimization..
[08:17:44] Phase 1 Retarget
[08:17:44] Phase 2 Constant propagation
[08:17:44] Phase 3 Sweep
[08:17:44] Phase 4 BUFG optimization
[08:17:44] Phase 5 Shift Register Optimization
[08:17:44] Phase 6 Post Processing Netlist
[08:18:15] Finished 3rd of 6 tasks (FPGA logic optimization). Elapsed time: 00h 01m 00s
[08:18:15] Starting logic placement..
[08:18:15] Phase 1 Placer Initialization
[08:18:15] Phase 1.1 Placer Initialization Netlist Sorting
[08:18:15] Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
[08:18:15] Phase 1.3 Build Placer Netlist Model
[08:18:15] Phase 1.4 Constrain Clocks/Macros
[08:18:15] Phase 2 Global Placement
[08:18:15] Phase 2.1 Floorplanning
[08:18:15] Phase 2.2 Global Placement Core
[08:18:45] Phase 2.2.1 Physical Synthesis In Placer
[08:18:45] Phase 3 Detail Placement
[08:18:45] Phase 3.1 Commit Multi Column Macros
[08:18:45] Phase 3.2 Commit Most Macros & LUTRAMs
[08:18:45] Phase 3.3 Area Swap Optimization
[08:18:45] Phase 3.4 Pipeline Register Optimization
[08:18:45] Phase 3.5 Small Shape DP
[08:18:45] Phase 3.5.1 Small Shape Clustering
[08:18:45] Phase 3.5.2 Flow Legalize Slice Clusters
[08:18:45] Phase 3.5.3 Slice Area Swap
[08:18:45] Phase 3.5.4 Commit Slice Clusters
[08:18:45] Phase 3.6 Re-assign LUT pins
[08:18:45] Phase 3.7 Pipeline Register Optimization
[08:18:45] Phase 4 Post Placement Optimization and Clean-Up
[08:18:45] Phase 4.1 Post Commit Optimization
[08:19:15] Finished 4th of 6 tasks (FPGA logic placement). Elapsed time: 00h 01m 00s
[08:19:15] Starting logic routing..
[08:19:15] Phase 1 Build RT Design
[08:19:15] Phase 4.1.1 Post Placement Optimization
[08:19:15] Phase 4.1.1.1 BUFG Insertion
[08:19:15] Phase 4.2 Post Placement Cleanup
[08:19:15] Phase 4.3 Placer Reporting
[08:19:15] Phase 4.4 Final Placement Cleanup
[08:19:45] Phase 2 Router Initialization
[08:19:45] Phase 2.1 Create Timer
[08:19:45] Phase 2.2 Fix Topology Constraints
[08:19:45] Phase 2.3 Pre Route Cleanup
[08:19:45] Phase 2.4 Global Clock Net Routing
[08:19:45] Phase 2.5 Update Timing
[08:20:15] Phase 3 Initial Routing
[08:20:15] Phase 4 Rip-up And Reroute
[08:20:15] Phase 4.1 Global Iteration 0
[08:20:46] Phase 4.2 Additional Iteration for Hold
[08:20:46] Phase 5 Delay and Skew Optimization
[08:20:46] Phase 5.1 Delay CleanUp
[08:20:46] Phase 5.1.1 Update Timing
[08:20:46] Phase 5.2 Clock Skew Optimization
[08:20:46] Phase 6 Post Hold Fix
[08:20:46] Phase 6.1 Hold Fix Iter
[08:20:46] Phase 6.1.1 Update Timing
[08:20:46] Phase 7 Route finalize
[08:20:46] Phase 8 Verifying routed nets
[08:20:46] Phase 9 Depositing Routes
[08:20:46] Phase 10 Post Router Timing
[08:20:46] Finished 5th of 6 tasks (FPGA routing). Elapsed time: 00h 01m 30s
[08:20:46] Starting bitstream generation..
[08:21:12] Creating bitmap...
[08:21:12] Writing bitstream ./Ultra96V2_Platform1_wrapper.bit...
[08:21:12] Finished 6th of 6 tasks (FPGA bitstream generation). Elapsed time: 00h 00m 26s
[08:21:11] Run vpl: Step impl: Completed
[08:21:12] Run vpl: FINISHED. Run Status: impl Complete!
INFO: [v++ 60-1441] [08:21:12] Run run_link: Step vpl: Completed
Time (s): cpu = 00:00:08 ; elapsed = 00:26:53 . Memory (MB): peak = 677.902 ; gain = 0.000 ; free physical = 5173 ; free virtual = 38264
INFO: [v++ 60-1443] [08:21:12] Run run_link: Step rtdgen: Started
INFO: [v++ 60-1453] Command Line: rtdgen
INFO: [v++ 60-1454] Run Directory: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/run_link
INFO: [v++ 60-1453] Command Line: cf2sw -a /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/address_map.xml -sdsl /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/sdsl.dat -xclbin /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/xclbin_orig.xml -rtd /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/matmul.rtd -o /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/matmul.xml
INFO: [v++ 60-1618] Launching
INFO: [v++ 60-1441] [08:21:15] Run run_link: Step rtdgen: Completed
Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 677.902 ; gain = 0.000 ; free physical = 5916 ; free virtual = 39010
INFO: [v++ 60-1443] [08:21:15] Run run_link: Step xclbinutil: Started
INFO: [v++ 60-1453] Command Line: xclbinutil --add-section BITSTREAM:RAW:/home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/system.bit --force --key-value SYS:mode:flat --add-section :JSON:/home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/matmul.rtd --add-section CLOCK_FREQ_TOPOLOGY:JSON:/home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/matmul_xml.rtd --add-section BUILD_METADATA:JSON:/home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/matmul_build.rtd --add-section EMBEDDED_METADATA:RAW:/home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/matmul.xml --add-section SYSTEM_METADATA:RAW:/home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/systemDiagramModelSlrBaseAddress.json --key-value SYS:PlatformVBNV:vendor_Ultra96V2_Ultra96V2_Platform1_1_0 --output /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/matmul.xclbin
INFO: [v++ 60-1454] Run Directory: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/run_link
XRT Build Version: 2.3.1301
Build Date: 2019-10-24 20:05:16
Hash ID: 192e706aea53163a04c574f9b3fe9ed76b6ca471
Creating a default 'in-memory' xclbin image.
Section: 'BITSTREAM'(0) was successfully added.
Size : 5568799 bytes
Format : RAW
File : '/home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/system.bit'
Section: 'MEM_TOPOLOGY'(6) was successfully added.
Format : JSON
File : 'mem_topology'
Section: 'IP_LAYOUT'(8) was successfully added.
Format : JSON
File : 'ip_layout'
Section: 'CONNECTIVITY'(7) was successfully added.
Format : JSON
File : 'connectivity'
WARNING: Skipping CLOCK_FREQ_TOPOLOGY section for count size is zero.
WARNING: Section 'CLOCK_FREQ_TOPOLOGY' content is empty. No data in the given JSON file.
Section: 'CLOCK_FREQ_TOPOLOGY'(11) was empty. No action taken.
Format : JSON
File : '/home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/matmul_xml.rtd'
Section: 'BUILD_METADATA'(14) was successfully added.
Size : 3025 bytes
Format : JSON
File : '/home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/matmul_build.rtd'
Section: 'EMBEDDED_METADATA'(2) was successfully added.
Size : 4360 bytes
Format : RAW
File : '/home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/matmul.xml'
Section: 'SYSTEM_METADATA'(22) was successfully added.
Size : 12517 bytes
Format : RAW
File : '/home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/systemDiagramModelSlrBaseAddress.json'
Successfully wrote (5595859 bytes) to the output file: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/matmul.xclbin
Leaving xclbinutil.
INFO: [v++ 60-1441] [08:21:15] Run run_link: Step xclbinutil: Completed
Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.12 . Memory (MB): peak = 677.902 ; gain = 0.000 ; free physical = 5903 ; free virtual = 39009
INFO: [v++ 60-1443] [08:21:15] Run run_link: Step xclbinutilinfo: Started
INFO: [v++ 60-1453] Command Line: xclbinutil --quiet --info /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/matmul.xclbin.info --input /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/matmul.xclbin
INFO: [v++ 60-1454] Run Directory: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/run_link
INFO: [v++ 60-1441] [08:21:15] Run run_link: Step xclbinutilinfo: Completed
Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.07 . Memory (MB): peak = 677.902 ; gain = 0.000 ; free physical = 5903 ; free virtual = 39009
INFO: [v++ 60-244] Generating system estimate report...
INFO: [v++ 60-1092] Generated system estimate report: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/reports/link/system_estimate_matmul.xtxt
INFO: [v++ 60-907] Packaging to directory: 'build_dir.hw.ultra96v2_min/sd_card'
INFO: [v++ 60-586] Created build_dir.hw.ultra96v2_min/matmul.xclbin
INFO: [v++ 60-1307] Run completed. Additional information can be found in:
Guidance: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/reports/link/v++_link_matmul_guidance.html
Timing Report: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/reports/link/imp/Ultra96V2_Platform1_wrapper_timing_summary_routed.rpt
Vivado Log: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/logs/link/vivado.log
Steps Log File: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/logs/link/link.steps.log
INFO: [v++ 60-791] Total elapsed time: 0h 27m 9s
emconfigutil --platform ultra96v2_min --od ./_x.hw.ultra96v2_min
****** configutil v2019.2 (64-bit)
**** SW Build 2700185 on Thu Oct 24 18:45:48 MDT 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
INFO: [ConfigUtil 60-895] Target platform: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min/ultra96v2_min.xpfm
INFO: [ConfigUtil 60-1578] This platform contains Xilinx Shell Archive '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min/hw/ultra96v2_min.xsa'
emulation configuration file `emconfig.json` is created in ./_x.hw.ultra96v2_min directory
mkdir -p sd_card/./build_dir.hw.ultra96v2_min
cp -rf `/home/masaaki/Vitis_Work/Vitis_Accel_Examples/common/utility/parse_platform_list.py ultra96v2_min`/ultra96v2_min/sw/ultra96v2_min/boot/generic.readme `/home/masaaki/Vitis_Work/Vitis_Accel_Examples/common/utility/parse_platform_list.py ultra96v2_min`/ultra96v2_min/sw/ultra96v2_min/xrt/image/* xrt.ini array_partition sd_card
cp: 'None/ultra96v2_min/sw/ultra96v2_min/boot/generic.readme' を stat できません: そのようなファイルやディレクトリはありません
cp: 'None/ultra96v2_min/sw/ultra96v2_min/xrt/image/*' を stat できません: そのようなファイルやディレクトリはありません
Makefile:135: recipe for target 'sd_card' failed
make: *** [sd_card] Error 1
masaaki@masaaki-H110M4-M01:~/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition$ make all TARGET=hw DEVICE=ultra96v2_min HOST_ARCH=aarch64 SYSROOT=/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min/images/linux/ultra96v2_min_pkg/pfm/sysroots/aarch64-xilinx-linux/
/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/gnu/aarch64/lin/aarch64-linux/bin/aarch64-linux-gnu-g++ -I../..//common/includes/xcl2 -I/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min/images/linux/ultra96v2_min_pkg/pfm/sysroots/aarch64-xilinx-linux//usr//include/xrt -I/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vivado/2019.2/include -Wall -O0 -g -std=c++11 -fmessage-length=0 ../..//common/includes/xcl2/xcl2.cpp src/host.cpp -o 'array_partition' -L/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min/images/linux/ultra96v2_min_pkg/pfm/sysroots/aarch64-xilinx-linux//usr//lib -lOpenCL -lpthread -lrt -lstdc++ --sysroot=/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min/images/linux/ultra96v2_min_pkg/pfm/sysroots/aarch64-xilinx-linux/
mkdir -p sd_card/./build_dir.hw.ultra96v2_min
#cp -rf `/home/masaaki/Vitis_Work/Vitis_Accel_Examples/common/utility/parse_platform_list.py ultra96v2_min`/ultra96v2_min/sw/ultra96v2_min/boot/generic.readme `/home/masaaki/Vitis_Work/Vitis_Accel_Examples/common/utility/parse_platform_list.py ultra96v2_min`/ultra96v2_min/sw/ultra96v2_min/xrt/image/* xrt.ini array_partition sd_card
cp -rf ./build_dir.hw.ultra96v2_min/*.xclbin sd_card/./build_dir.hw.ultra96v2_min/
[ -f sd_card/BOOT.BIN ] && echo "INFO: BOOT.BIN already exists" || cp -rf ./build_dir.hw.ultra96v2_min/sd_card/BOOT.BIN sd_card/
root@ultra96v2_min:/run/media/mmcblk0p1# ./init.sh
A:
0 1 8 5 5 2 0 7 7 10 …
7 0 4 0 4 7 6 10 9 5 …
2 0 8 3 6 8 10 4 2 10 …
2 4 8 5 2 3 3 1 5 9 …
10 5 2 0 10 0 5 4 3 10 …
9 1 0 7 9 6 8 7 10 9 …
4 9 2 4 5 5 3 1 1 6 …
6 9 6 9 1 2 7 1 1 3 …
1 3 9 7 1 7 4 4 5 1 …
10 4 1 6 2 5 5 10 1 2 …
… … … … … … … … … … ⋱
B:
7 7 2 9 7 9 1 0 8 6 …
4 2 7 3 8 8 4 3 2 0 …
6 1 9 1 10 2 2 1 2 6 …
0 6 2 3 7 1 8 5 6 6 …
8 6 8 3 1 5 3 6 5 4 …
3 0 4 2 7 7 5 8 7 10 …
4 6 10 1 7 3 5 5 9 0 …
2 9 7 5 8 0 1 7 7 4 …
1 0 5 0 1 9 8 8 4 0 …
4 6 7 7 5 3 8 4 7 3 …
… … … … … … … … … … ⋱
Gold:
196 311 428 206 384 291 305 363 405 243 …
286 472 448 296 490 425 382 430 500 367 …
269 439 555 260 529 390 416 425 559 370 …
231 293 419 231 365 385 361 356 384 235 …
307 479 484 313 453 477 368 366 529 295 …
31[ 41.449920] [drm] Pid 2170 opened device
7 474 488 357 472 458 439 457 564 341 …
246 339 3[ 41.455037] [drm] Pid 2170 closed device
85 272 381 424 364 324 386 263 …
234 367 312 217 430 307 334 248 314 284 …
231 370 403 197 453 334 353 410 382 344 …
246 432 363 321 462 324 291 330[ 41.475501] [drm] Pid 2170 opened device
436 322 …
… … … … … … … … … … ⋱
Found Platform
Platform Name: Xilinx
INFO: Reading ./build_dir.hw.ultra96v2_min/matmul.xclbin
Loading: './build_dir.hw.ultra96v2_min/matmul.xclbin'
Trying to program device[0]: edge
[ 41.799701] [drm] Finding IP_LAYOUT section header
[ 41.799714] [drm] Section IP_LAYOUT details:
[ 41.804527] [drm] offset = 0x54fcf8
[ 41.808789] [drm] size = 0xa8
[ 41.812452] [drm] Finding DEBUG_IP_LAYOUT section header
[ 41.815585] [drm] AXLF section DEBUG_IP_LAYOUT header not found
[ 41.820891] [drm] Finding CONNECTIVITY section header
[ 41.826799] [drm] Section CONNECTIVITY details:
[ 41.831843] [drm] offset = 0x54fda0
[ 41.836363] [drm] size = 0x4c
[ 41.840026] [drm] Finding MEM_TOPOLOGY section header
[ 41.843173] [drm] Section MEM_TOPOLOGY details:
[ 41.848222] [drm] offset = 0x54fc00
[ 41.852745] [drm] size = 0xf8
[ 41.858442] [drm] No ERT scheduler on MPSoC, using KDS
[ 41.867228] [drm] Fail to install CU 0 interrupt handler: -22. Fall back to polling mode.
[ 41.875414] [drm] scheduler config ert(0)
[ 41.875416] [drm] cus(2)
[ 41.879418] [drm] slots(16)
[ 41.882117] [drm] num_cu_masks(1)
[ 41.885071] [drm] cu_shift(16)
[ 41.888551] [drm] cu_base(0xa0000000)
Device[0]: program successful!
|-------------------------+-------------------------|
| Kernel | Wall-Clock Time (ns) |
|-------------------------+-----------------------[ 41.891769] [drm] polling(1)
--|
| matmul: | 927760 |
| ma[ 41.911552] [drm] zocl_free_userptr_bo: obj 0x00000000c1210b3c
tmul: partition | 134180 |
|------------[ 41.918961] [drm] zocl_free_userptr_bo: obj 0x00000000f1560de0
-------------+-------------------------|
Note: Wall Clock Time is meaningful for real hardware execution only, not for emulation.
Please refer to profile summary for kernel execution time fo[ 41.930308] [drm] zocl_free_userptr_bo: obj 0x000000003f79d183
r hardware emulation.
TEST PASSED
[ 41.954490] [drm] Pid 2170 closed device
Device[0]: program successful!
|-------------------------+-------------------------|
| Kernel | Wall-Clock Time (ns) |
|-------------------------+-------------------------|
| matmul: | 927760 |
| matmul: partition | 134180 |
|-------------------------+-------------------------|
Note: Wall Clock Time is meaningful for real hardware execution only, not for emulation.
Please refer to profile summary for kernel execution time for hardware emulation.
TEST PASSED
と表示されていれば成功だ。Device[0]: program successful!
TEST PASSED
root@ultra96v2_min:/sys/devices/platform/amba/a0000000.zyxclmm_drm# insmod /lib/modules/4.19.0-xilinx-v2019.2/extra/zocl.ko
[ 261.956918] zocl: loading out-of-tree module taints kernel.
[ 261.966193] [drm] Probing for xlnx,zocl
[ 261.970113] [drm] FPGA programming device pcap founded.
[ 261.975331] [drm] PR Isolation addr 0x0
[ 261.977830] [drm] Initialized zocl 2018.2.1 20180313 for a0000000.zyxclmm_drm on minor 1
root@ultra96v2_min:/sys/devices/platform/amba/a0000000.zyxclmm_drm# ls
connectivity driver_override kds_custat memstat of_node uevent
debug_ip_layout drm kds_numcus memstat_raw power xclbinid
driver ip_layout mem_topology modalias subsystem
なので、成功した。Device[0]: program successful!
TEST PASSED
root@ultra96v2_min:/run/media/mmcblk0p1# ./init.sh
[ 508.084360] [drm] Pid 2202 opened device
[ 508.088315] [drm] Pid 2202 closed device
[ 508.103272] [drm] Pid 2202 opened device
Found Platform
Platform Name: Xilinx
INFO: Reading ./build_dir.hw.ultra96v2_min/vadd.xclbin
Loading: './build_dir.hw.ultra96v2_min/vadd.xclbin'
Trying to program device[0]: edge
[ 508.425398] [drm] Finding IP_LAYOUT section header
[ 508.425410] [drm] Section IP_LAYOUT details:
[ 508.430222] [drm] offset = 0x54fcf8
[ 508.434485] [drm] size = 0x58
[ 508.438146] [drm] Finding DEBUG_IP_LAYOUT section header
[ 508.441275] [drm] AXLF section DEBUG_IP_LAYOUT header not found
[ 508.446582] [drm] Finding CONNECTIVITY section header
[ 508.452495] [drm] Section CONNECTIVITY details:
[ 508.457539] [drm] offset = 0x54fd50
[ 508.462060] [drm] size = 0x28
[ 508.465713] [drm] Finding MEM_TOPOLOGY section header
[ 508.468850] [drm] Section MEM_TOPOLOGY details:
[ 508.473891] [drm] offset = 0x54fc00
[ 508.478414] [drm] size = 0xf8
[ 508.483568] [drm] No ERT scheduler on MPSoC, using KDS
[ 508.492196] [drm] Fail to install CU 0 interrupt handler: -22. Fall back to polling mode.
[ 508.500373] [drm] scheduler config ert(0)
[ 508.500376] [drm] cus(1)
[ 508.504376] [drm] slots(16)
[ 508.507076] [drm] num_cu_masks(1)
[ 508.510038] [drm] cu_shift(16)
[ 508.513510] [drm] cu_base(0xa0000000)
Device[0]: program successful!
TEST PASSED
[ 508.516728] [drm] polling(1)
[ 508.533040] [drm] zocl_free_userptr_bo: obj 0x00000000477b200d
[ 508.536152] [drm] zocl_free_userptr_bo: obj 0x00000000e86ec7cd
[ 508.542003] [drm] zocl_free_userptr_bo: obj 0x0000000073e8a3a0
[ 508.604948] [drm] Pid 2202 closed device
root@ultra96v2_min:/run/media/mmcblk0p1# ./init.sh
XRT build version: 2.3.0
Build hash: 7e3540d2707443d8c824669ef4272b33ce2f9ba4
Build date: 2019-10-22 07:31:35
Git branch: 2019.2
PID: 2371
UID: 0
[Thu Jan 1 00:02:41 1970]
HOST: ultra96v2_min
EXE: /run/media/mmcblk0p1/host
[XRT] ERROR: Library liboclxdp.so not found! XILINX_XRT not set
[XRT] ERROR: XILINX_XRT must be set
[XRT] ERROR: XILINX_XRT must be set
..//common/includes/xcl2/xcl2.cpp:40 Error calling err = cl::Platform::get(&platforms), error code is: -1001
root@ultra96v2_min:/run/media/mmcblk0p1# ./init.sh
XRT build version: 2.3.0
Build hash: 7e3540d2707443d8c824669ef4272b33ce2f9ba4
Build date: 2019-10-22 07:31:35
Git branch: 2019.2
PID: 2380
UID: 0
[Thu Jan 1 00:05:03 1970]
HOST: ultra96v2_min
EXE: /run/media/mmcblk0p1/host
[XRT] WARNING: No devices found
[XRT] ERROR: No devices found
[XRT] ERROR: No devices found
[XRT] ERROR: No devices found
..//common/includes/xcl2/xcl2.cpp:40 Error calling err = cl::Platform::get(&platforms), error code is: -1001
Xilinx Zynq MP First Stage Boot Loader
Release 2019.2 Nov 17 2019 - 19:30:30
NOTICE: ATF running on XCZU3EG/silicon v4/RTL5.1 at 0xfffea000
NOTICE: BL31: Secure code at 0x0
NOTICE: BL31: Non secure code at 0x8000000
NOTICE: BL31: v2.0(release):xilinx-v2019.1-12-g713dace9
NOTICE: BL31: Built : 19:28:16, Nov 17 2019
PMUFW: v1.1
U-Boot 2019.01 (Nov 17 2019 - 19:28:49 +0000)
Board: Xilinx ZynqMP
DRAM: 2 GiB
usb dr_mode not found
usb dr_mode not found
EL Level: EL2
Chip ID: zu3eg
MMC: mmc@ff160000: 0, mmc@ff170000: 1
Loading Environment from FAT... *** Warning - bad CRC, using default environment
In: serial@ff010000
Out: serial@ff010000
Err: serial@ff010000
Board: Xilinx ZynqMP
Bootmode: SD_MODE
Reset reason: EXTERNAL
U-BOOT for ultra96v2_min
Hit any key to stop autoboot: 0
Device: mmc@ff160000
Manufacturer ID: 74
OEM: 4a60
Name: USD
Bus Speed: 50000000
Mode : SD High Speed (50MHz)
Rd Block Len: 512
SD version 3.0
High Capacity: Yes
Capacity: 7.5 GiB
Bus Width: 4-bit
Erase Group Size: 512 Bytes
18112496 bytes read in 1305 ms (13.2 MiB/s)
## Loading kernel from FIT Image at 10000000 ...
Using 'conf@system-top.dtb' configuration
Trying 'kernel@1' kernel subimage
Description: Linux kernel
Type: Kernel Image
Compression: uncompressed
Data Start: 0x100000f8
Data Size: 18080256 Bytes = 17.2 MiB
Architecture: AArch64
OS: Linux
Load Address: 0x00080000
Entry Point: 0x00080000
Hash algo: sha1
Hash value: e731f698a6f475f6bfcba5559661fc24b07061c1
Verifying Hash Integrity ... sha1+ OK
## Loading fdt from FIT Image at 10000000 ...
Using 'conf@system-top.dtb' configuration
Trying 'fdt@system-top.dtb' fdt subimage
Description: Flattened Device Tree blob
Type: Flat Device Tree
Compression: uncompressed
Data Start: 0x1113e3fc
Data Size: 30333 Bytes = 29.6 KiB
Architecture: AArch64
Hash algo: sha1
Hash value: 23c5de85dbb7d7a5d4e7bba9285b81eb959b8ed0
Verifying Hash Integrity ... sha1+ OK
Booting using the fdt blob at 0x1113e3fc
Loading Kernel Image ... OK
Loading Device Tree to 0000000007ff5000, end 0000000007fff67c ... OK
Starting kernel ...
[ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
[ 0.000000] Linux version 4.19.0-xilinx-v2019.2 (oe-user@oe-host) (gcc version 8.2.0 (GCC)) #1 SMP Sat Nov 16 21:03:15 UTC 2019
[ 0.000000] Machine model: xlnx,zynqmp
[ 0.000000] earlycon: cdns0 at MMIO 0x00000000ff010000 (options '115200n8')
[ 0.000000] bootconsole [cdns0] enabled
[ 0.000000] efi: Getting EFI parameters from FDT:
[ 0.000000] efi: UEFI not found.
[ 0.000000] cma: Reserved 1024 MiB at 0x000000003fc00000
[ 0.000000] psci: probing for conduit method from DT.
[ 0.000000] psci: PSCIv1.1 detected in firmware.
[ 0.000000] psci: Using standard PSCI v0.2 function IDs
[ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
[ 0.000000] psci: SMC Calling Convention v1.1
[ 0.000000] random: get_random_bytes called from start_kernel+0x94/0x3f8 with crng_init=0
[ 0.000000] percpu: Embedded 22 pages/cpu @(____ptrval____) s52568 r8192 d29352 u90112
[ 0.000000] Detected VIPT I-cache on CPU0
[ 0.000000] CPU features: enabling workaround for ARM erratum 845719
[ 0.000000] Speculative Store Bypass Disable mitigation not required
[ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 516867
[ 0.000000] Kernel command line: earlycon console=ttyPS0,115200 clk_ignore_unused root=/dev/mmcblk0p2 rw rootwait
[ 0.000000] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes)
[ 0.000000] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes)
[ 0.000000] Memory: 997048K/2096128K available (10748K kernel code, 632K rwdata, 5408K rodata, 832K init, 511K bss, 50504K reserved, 1048576K cma-reserved)
[ 0.000000] rcu: Hierarchical RCU implementation.
[ 0.000000] rcu: RCU event tracing is enabled.
[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
[ 0.000000] GIC: Adjusting CPU interface base to 0x00000000f902f000
[ 0.000000] GIC: Using split EOI/Deactivate mode
[ 0.000000] arch_timer: cp15 timer(s) running at 100.00MHz (phys).
[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x171024e7e0, max_idle_ns: 440795205315 ns
[ 0.000004] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 4398046511100ns
[ 0.008329] Console: colour dummy device 80x25
[ 0.012484] Calibrating delay loop (skipped), value calculated using timer frequency.. 200.00 BogoMIPS (lpj=400000)
[ 0.022839] pid_max: default: 32768 minimum: 301
[ 0.027550] Mount-cache hash table entries: 4096 (order: 3, 32768 bytes)
[ 0.034093] Mountpoint-cache hash table entries: 4096 (order: 3, 32768 bytes)
[ 0.042099] ASID allocator initialised with 32768 entries
[ 0.046597] rcu: Hierarchical SRCU implementation.
[ 0.051583] EFI services will not be available.
[ 0.055933] smp: Bringing up secondary CPUs ...
[ 0.060614] Detected VIPT I-cache on CPU1
[ 0.060655] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
[ 0.060998] Detected VIPT I-cache on CPU2
[ 0.061018] CPU2: Booted secondary processor 0x0000000002 [0x410fd034]
[ 0.061329] Detected VIPT I-cache on CPU3
[ 0.061349] CPU3: Booted secondary processor 0x0000000003 [0x410fd034]
[ 0.061393] smp: Brought up 1 node, 4 CPUs
[ 0.095756] SMP: Total of 4 processors activated.
[ 0.100430] CPU features: detected: 32-bit EL0 Support
[ 0.108144] CPU: All CPU(s) started at EL2
[ 0.109610] alternatives: patching kernel code
[ 0.115362] devtmpfs: initialized
[ 0.120904] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
[ 0.126999] futex hash table entries: 1024 (order: 4, 65536 bytes)
[ 0.159009] xor: measuring software checksum speed
[ 0.197371] 8regs : 2375.000 MB/sec
[ 0.237399] 8regs_prefetch: 2052.000 MB/sec
[ 0.277429] 32regs : 2725.000 MB/sec
[ 0.317461] 32regs_prefetch: 2309.000 MB/sec
[ 0.317506] xor: using function: 32regs (2725.000 MB/sec)
[ 0.321809] pinctrl core: initialized pinctrl subsystem
[ 0.327864] NET: Registered protocol family 16
[ 0.331770] audit: initializing netlink subsys (disabled)
[ 0.336902] audit: type=2000 audit(0.284:1): state=initialized audit_enabled=0 res=1
[ 0.344461] vdso: 2 pages (1 code @ (____ptrval____), 1 data @ (____ptrval____))
[ 0.344469] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
[ 0.359484] DMA: preallocated 256 KiB pool for atomic allocations
[ 0.379566] HugeTLB registered 2.00 MiB page size, pre-allocated 0 pages
[ 0.448864] raid6: int64x1 gen() 445 MB/s
[ 0.516860] raid6: int64x1 xor() 451 MB/s
[ 0.584986] raid6: int64x2 gen() 680 MB/s
[ 0.653010] raid6: int64x2 xor() 599 MB/s
[ 0.721064] raid6: int64x4 gen() 980 MB/s
[ 0.789154] raid6: int64x4 xor() 737 MB/s
[ 0.857225] raid6: int64x8 gen() 1162 MB/s
[ 0.925273] raid6: int64x8 xor() 759 MB/s
[ 0.993381] raid6: neonx1 gen() 735 MB/s
[ 1.061423] raid6: neonx1 xor() 880 MB/s
[ 1.129490] raid6: neonx2 gen() 1129 MB/s
[ 1.197547] raid6: neonx2 xor() 1173 MB/s
[ 1.265632] raid6: neonx4 gen() 1479 MB/s
[ 1.333689] raid6: neonx4 xor() 1417 MB/s
[ 1.401776] raid6: neonx8 gen() 1536 MB/s
[ 1.469823] raid6: neonx8 xor() 1459 MB/s
[ 1.469864] raid6: using algorithm neonx8 gen() 1536 MB/s
[ 1.473809] raid6: .... xor() 1459 MB/s, rmw enabled
[ 1.478745] raid6: using neon recovery algorithm
[ 1.484308] SCSI subsystem initialized
[ 1.487273] usbcore: registered new interface driver usbfs
[ 1.492536] usbcore: registered new interface driver hub
[ 1.497811] usbcore: registered new device driver usb
[ 1.502867] media: Linux media interface: v0.10
[ 1.507317] videodev: Linux video capture interface: v2.00
[ 1.512767] pps_core: LinuxPPS API ver. 1 registered
[ 1.517671] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[ 1.526765] PTP clock support registered
[ 1.530664] EDAC MC: Ver: 3.0.0
[ 1.534268] zynqmp-ipi-mbox mailbox@ff990400: Probed ZynqMP IPI Mailbox driver.
[ 1.541393] FPGA manager framework
[ 1.544577] Advanced Linux Sound Architecture Driver Initialized.
[ 1.550829] Bluetooth: Core ver 2.22
[ 1.554017] NET: Registered protocol family 31
[ 1.558413] Bluetooth: HCI device and connection manager initialized
[ 1.564731] Bluetooth: HCI socket layer initialized
[ 1.569572] Bluetooth: L2CAP socket layer initialized
[ 1.574610] Bluetooth: SCO socket layer initialized
[ 1.579884] clocksource: Switched to clocksource arch_sys_counter
[ 1.585605] VFS: Disk quotas dquot_6.6.0
[ 1.589431] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
[ 1.601316] NET: Registered protocol family 2
[ 1.601795] tcp_listen_portaddr_hash hash table entries: 1024 (order: 2, 16384 bytes)
[ 1.608362] TCP established hash table entries: 16384 (order: 5, 131072 bytes)
[ 1.615607] TCP bind hash table entries: 16384 (order: 6, 262144 bytes)
[ 1.622433] TCP: Hash tables configured (established 16384 bind 16384)
[ 1.628668] UDP hash table entries: 1024 (order: 3, 32768 bytes)
[ 1.634572] UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes)
[ 1.641079] NET: Registered protocol family 1
[ 1.645527] RPC: Registered named UNIX socket transport module.
[ 1.651147] RPC: Registered udp transport module.
[ 1.655813] RPC: Registered tcp transport module.
[ 1.660484] RPC: Registered tcp NFSv4.1 backchannel transport module.
[ 1.667740] hw perfevents: no interrupt-affinity property for /pmu, guessing.
[ 1.674153] hw perfevents: enabled with armv8_pmuv3 PMU driver, 7 counters available
[ 1.682706] Initialise system trusted keyrings
[ 1.686163] workingset: timestamp_bits=62 max_order=19 bucket_order=0
[ 1.693325] NFS: Registering the id_resolver key type
[ 1.697521] Key type id_resolver registered
[ 1.701660] Key type id_legacy registered
[ 1.705643] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
[ 1.712314] jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
[ 2.800459] NET: Registered protocol family 38
[ 2.858505] Key type asymmetric registered
[ 2.858547] Asymmetric key parser 'x509' registered
[ 2.861851] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 247)
[ 2.869168] io scheduler noop registered
[ 2.873056] io scheduler deadline registered
[ 2.877327] io scheduler cfq registered (default)
[ 2.881967] io scheduler mq-deadline registered
[ 2.886464] io scheduler kyber registered
[ 2.923758] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[ 2.928220] cacheinfo: Unable to detect cache hierarchy for CPU 0
[ 2.936106] brd: module loaded
[ 2.941291] loop: module loaded
[ 2.942259] mtdoops: mtd device (mtddev=name/number) must be supplied
[ 2.946844] libphy: Fixed MDIO Bus: probed
[ 2.950748] tun: Universal TUN/TAP device driver, 1.6
[ 2.954457] CAN device driver interface
[ 2.959118] usbcore: registered new interface driver asix
[ 2.963497] usbcore: registered new interface driver ax88179_178a
[ 2.969540] usbcore: registered new interface driver cdc_ether
[ 2.975333] usbcore: registered new interface driver net1080
[ 2.980955] usbcore: registered new interface driver cdc_subset
[ 2.986836] usbcore: registered new interface driver zaurus
[ 2.992385] usbcore: registered new interface driver cdc_ncm
[ 2.998578] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[ 3.004461] ehci-pci: EHCI PCI platform driver
[ 3.009162] usbcore: registered new interface driver uas
[ 3.014182] usbcore: registered new interface driver usb-storage
[ 3.020762] rtc_zynqmp ffa60000.rtc: rtc core: registered ffa60000.rtc as rtc0
[ 3.027354] i2c /dev entries driver
[ 3.032392] usbcore: registered new interface driver uvcvideo
[ 3.036464] USB Video Class driver (1.1.1)
[ 3.041341] Bluetooth: HCI UART driver ver 2.3
[ 3.044949] Bluetooth: HCI UART protocol H4 registered
[ 3.050045] Bluetooth: HCI UART protocol BCSP registered
[ 3.055345] Bluetooth: HCI UART protocol LL registered
[ 3.060425] Bluetooth: HCI UART protocol ATH3K registered
[ 3.065804] Bluetooth: HCI UART protocol Three-wire (H5) registered
[ 3.072057] Bluetooth: HCI UART protocol Intel registered
[ 3.077397] Bluetooth: HCI UART protocol QCA registered
[ 3.082602] usbcore: registered new interface driver bcm203x
[ 3.088222] usbcore: registered new interface driver bpa10x
[ 3.093756] usbcore: registered new interface driver bfusb
[ 3.099206] usbcore: registered new interface driver btusb
[ 3.104626] Bluetooth: Generic Bluetooth SDIO driver ver 0.1
[ 3.110300] usbcore: registered new interface driver ath3k
[ 3.115833] EDAC MC: ECC not enabled
[ 3.119388] EDAC DEVICE0: Giving out device to module edac controller cache_err: DEV edac (POLLED)
[ 3.128338] EDAC DEVICE1: Giving out device to module zynqmp-ocm-edac controller zynqmp_ocm: DEV ff960000.memory-controller (INTERRUPT)
[ 3.140534] sdhci: Secure Digital Host Controller Interface driver
[ 3.146406] sdhci: Copyright(c) Pierre Ossman
[ 3.150730] sdhci-pltfm: SDHCI platform and OF driver helper
[ 3.156694] ledtrig-cpu: registered to indicate activity on CPUs
[ 3.162378] zynqmp_firmware_probe Platform Management API v1.1
[ 3.168123] zynqmp_firmware_probe Trustzone version v1.0
[ 3.197015] zynqmp_clk_mux_get_parent() getparent failed for clock: lpd_wdt, ret = -22
[ 3.199769] alg: No test for xilinx-zynqmp-aes (zynqmp-aes)
[ 3.204843] zynqmp_aes zynqmp_aes: AES Successfully Registered
[ 3.204843]
[ 3.212364] alg: No test for xilinx-keccak-384 (zynqmp-keccak-384)
[ 3.218486] alg: No test for xilinx-zynqmp-rsa (zynqmp-rsa)
[ 3.224146] usbcore: registered new interface driver usbhid
[ 3.229386] usbhid: USB HID core driver
[ 3.233354] xlnk xlnk: Major 243
[ 3.236532] xlnk xlnk: xlnk driver loaded
[ 3.240374] xlnk xlnk: xlnk_pdev is not null
[ 3.247025] fpga_manager fpga0: Xilinx ZynqMP FPGA Manager registered
[ 3.251426] usbcore: registered new interface driver snd-usb-audio
[ 3.258118] pktgen: Packet Generator for packet performance testing. Version: 2.75
[ 3.265157] Initializing XFRM netlink socket
[ 3.269015] NET: Registered protocol family 10
[ 3.273782] Segment Routing with IPv6
[ 3.277064] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
[ 3.283245] NET: Registered protocol family 17
[ 3.287264] NET: Registered protocol family 15
[ 3.291682] bridge: filtering via arp/ip/ip6tables is no longer available by default. Update your scripts to load br_netfilter if you need this.
[ 3.304609] can: controller area network core (rev 20170425 abi 9)
[ 3.310737] NET: Registered protocol family 29
[ 3.315109] can: raw protocol (rev 20170425)
[ 3.319345] can: broadcast manager protocol (rev 20170425 t)
[ 3.324971] can: netlink gateway (rev 20170425) max_hops=1
[ 3.330803] Bluetooth: RFCOMM TTY layer initialized
[ 3.335269] Bluetooth: RFCOMM socket layer initialized
[ 3.340380] Bluetooth: RFCOMM ver 1.11
[ 3.344088] Bluetooth: BNEP (Ethernet Emulation) ver 1.3
[ 3.349359] Bluetooth: BNEP filters: protocol multicast
[ 3.354552] Bluetooth: BNEP socket layer initialized
[ 3.359480] Bluetooth: HIDP (Human Interface Emulation) ver 1.2
[ 3.365364] Bluetooth: HIDP socket layer initialized
[ 3.370447] 9pnet: Installing 9P2000 support
[ 3.374552] Key type dns_resolver registered
[ 3.379287] registered taskstats version 1
[ 3.382840] Loading compiled-in X.509 certificates
[ 3.388013] Btrfs loaded, crc32c=crc32c-generic
[ 3.399778] ff000000.serial: ttyPS1 at MMIO 0xff000000 (irq = 40, base_baud = 6249999) is a xuartps
[ 3.403916] ff010000.serial: ttyPS0 at MMIO 0xff010000 (irq = 41, base_baud = 6249999) is a xuartps
[ 3.417915] console [ttyPS0] enabled
[ 3.417915] console [ttyPS0] enabled
[ 3.421517] bootconsole [cdns0] disabled
[ 3.421517] bootconsole [cdns0] disabled
[ 3.429649] of-fpga-region fpga-full: FPGA Region probed
[ 3.439142] xilinx-dpdma fd4c0000.dma: Xilinx DPDMA engine is probed
[ 3.445760] xilinx-zynqmp-dma fd500000.dma: ZynqMP DMA driver Probe success
[ 3.452891] xilinx-zynqmp-dma fd510000.dma: ZynqMP DMA driver Probe success
[ 3.460017] xilinx-zynqmp-dma fd520000.dma: ZynqMP DMA driver Probe success
[ 3.467132] xilinx-zynqmp-dma fd530000.dma: ZynqMP DMA driver Probe success
[ 3.474241] xilinx-zynqmp-dma fd540000.dma: ZynqMP DMA driver Probe success
[ 3.481356] xilinx-zynqmp-dma fd550000.dma: ZynqMP DMA driver Probe success
[ 3.488475] xilinx-zynqmp-dma fd560000.dma: ZynqMP DMA driver Probe success
[ 3.495593] xilinx-zynqmp-dma fd570000.dma: ZynqMP DMA driver Probe success
[ 3.502787] xilinx-zynqmp-dma ffa80000.dma: ZynqMP DMA driver Probe success
[ 3.509906] xilinx-zynqmp-dma ffa90000.dma: ZynqMP DMA driver Probe success
[ 3.517020] xilinx-zynqmp-dma ffaa0000.dma: ZynqMP DMA driver Probe success
[ 3.524141] xilinx-zynqmp-dma ffab0000.dma: ZynqMP DMA driver Probe success
[ 3.531257] xilinx-zynqmp-dma ffac0000.dma: ZynqMP DMA driver Probe success
[ 3.538372] xilinx-zynqmp-dma ffad0000.dma: ZynqMP DMA driver Probe success
[ 3.545491] xilinx-zynqmp-dma ffae0000.dma: ZynqMP DMA driver Probe success
[ 3.552611] xilinx-zynqmp-dma ffaf0000.dma: ZynqMP DMA driver Probe success
[ 3.559986] xilinx-psgtr fd400000.zynqmp_phy: Lane:1 type:8 protocol:4 pll_locked:yes
[ 3.570955] xilinx-dp-snd-codec fd4a0000.zynqmp-display:zynqmp_dp_snd_codec0: Xilinx DisplayPort Sound Codec probed
[ 3.581708] xilinx-dp-snd-pcm zynqmp_dp_snd_pcm0: Xilinx DisplayPort Sound PCM probed
[ 3.589767] xilinx-dp-snd-pcm zynqmp_dp_snd_pcm1: Xilinx DisplayPort Sound PCM probed
[ 3.598721] xilinx-dp-snd-card fd4a0000.zynqmp-display:zynqmp_dp_snd_card: xilinx-dp-snd-codec-dai <-> xilinx-dp-snd-codec-dai mapping ok
[ 3.611228] xilinx-dp-snd-card fd4a0000.zynqmp-display:zynqmp_dp_snd_card: xilinx-dp-snd-codec-dai <-> xilinx-dp-snd-codec-dai mapping ok
[ 3.623995] xilinx-dp-snd-card fd4a0000.zynqmp-display:zynqmp_dp_snd_card: Xilinx DisplayPort Sound Card probed
[ 3.634220] OF: graph: no port node found in /amba/zynqmp-display@fd4a0000
[ 3.641298] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[ 3.647904] [drm] No driver support for vblank timestamp query.
[ 3.653909] xlnx-drm xlnx-drm.0: bound fd4a0000.zynqmp-display (ops 0xffffff8008bbea78)
[ 4.739899] [drm] Cannot find any crtc or sizes
[ 4.744700] [drm] Initialized xlnx 1.0.0 20130509 for fd4a0000.zynqmp-display on minor 0
[ 4.752801] zynqmp-display fd4a0000.zynqmp-display: ZynqMP DisplayPort Subsystem driver probed
[ 4.762922] xilinx-axipmon ffa00000.perf-monitor: Probed Xilinx APM
[ 4.769465] xilinx-axipmon fd0b0000.perf-monitor: Probed Xilinx APM
[ 4.775978] xilinx-axipmon fd490000.perf-monitor: Probed Xilinx APM
[ 4.782475] xilinx-axipmon ffa10000.perf-monitor: Probed Xilinx APM
[ 4.788993] dwc3-of-simple ff9d0000.usb0: dwc3_simple_set_phydata: Can't find usb3-phy
[ 4.797415] dwc3 fe200000.dwc3: Failed to get clk 'ref': -2
[ 4.803747] dwc3-of-simple ff9e0000.usb1: dwc3_simple_set_phydata: Can't find usb3-phy
[ 4.812080] dwc3 fe300000.dwc3: Failed to get clk 'ref': -2
[ 4.819141] cdns-i2c ff030000.i2c: 400 kHz mmio ff030000 irq 30
[ 4.825447] cdns-wdt fd4d0000.watchdog: Xilinx Watchdog Timer with timeout 60s
[ 4.832898] cdns-wdt ff150000.watchdog: Xilinx Watchdog Timer with timeout 10s
[ 4.840878] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
[ 4.846378] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1
[ 4.854989] xhci-hcd xhci-hcd.0.auto: hcc params 0x0238f625 hci version 0x100 quirks 0x0000000202010010
[ 4.864403] xhci-hcd xhci-hcd.0.auto: irq 50, io mem 0xfe300000
[ 4.870592] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 4.19
[ 4.878852] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[ 4.886071] usb usb1: Product: xHCI Host Controller
[ 4.890938] usb usb1: Manufacturer: Linux 4.19.0-xilinx-v2019.2 xhci-hcd
[ 4.897630] usb usb1: SerialNumber: xhci-hcd.0.auto
[ 4.902887] hub 1-0:1.0: USB hub found
[ 4.906656] hub 1-0:1.0: 1 port detected
[ 4.910788] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
[ 4.916278] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2
[ 4.923950] xhci-hcd xhci-hcd.0.auto: Host supports USB 3.0 SuperSpeed
[ 4.930572] mmc0: SDHCI controller on ff160000.mmc [ff160000.mmc] using ADMA 64-bit
[ 4.938403] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
[ 4.947276] usb usb2: New USB device found, idVendor=1d6b, idProduct=0003, bcdDevice= 4.19
[ 4.955540] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[ 4.962757] usb usb2: Product: xHCI Host Controller
[ 4.967625] usb usb2: Manufacturer: Linux 4.19.0-xilinx-v2019.2 xhci-hcd
[ 4.974317] usb usb2: SerialNumber: xhci-hcd.0.auto
[ 4.979473] hub 2-0:1.0: USB hub found
[ 4.983237] hub 2-0:1.0: 1 port detected
[ 5.018560] mmc1: SDHCI controller on ff170000.mmc [ff170000.mmc] using ADMA 64-bit
[ 5.029479] mmc0: new high speed SDHC card at address 59b4
[ 5.035654] mmcblk0: mmc0:59b4 USD 7.51 GiB
[ 5.043624] rtc_zynqmp ffa60000.rtc: setting system clock to 1970-01-01 00:00:08 UTC (8)
[ 5.051724] of_cfs_init
[ 5.054205] of_cfs_init: OK
[ 5.057120] cfg80211: Loading compiled-in X.509 certificates for regulatory database
[ 5.065806] mmcblk0: p1 p2
[ 5.083717] mmc1: new high speed SDIO card at address 0001
[ 5.196669] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
[ 5.203200] clk: Not disabling unused clocks
[ 5.207469] ALSA device list:
[ 5.210430] #0: DisplayPort monitor
[ 5.214516] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
[ 5.223128] cfg80211: failed to load regulatory.db
[ 5.243894] usb 1-1: new high-speed USB device number 2 using xhci-hcd
[ 5.311520] EXT4-fs (mmcblk0p2): mounted filesystem with ordered data mode. Opts: (null)
[ 5.319627] VFS: Mounted root (ext4 filesystem) on device 179:2.
[ 5.332794] devtmpfs: mounted
[ 5.336053] Freeing unused kernel memory: 832K
[ 5.340535] Run /sbin/init as init process
[ 5.396374] usb 1-1: New USB device found, idVendor=0424, idProduct=2744, bcdDevice= 2.05
[ 5.404563] usb 1-1: New USB device strings: Mfr=1, Product=2, SerialNumber=0
[ 5.411691] usb 1-1: Product: USB2744
[ 5.415347] usb 1-1: Manufacturer: Microchip Tech
INIT: version 2.88 booting
[ 5.474751] hub 1-1:1.0: USB hub found
[ 5.478535] hub 1-1:1.0: 4 ports detected
[ 5.509403] random: fast init done
Starting udev
[ 5.827919] usb 1-1.4: new high-speed USB device number 3 using xhci-hcd
[ 5.851917] [drm] Cannot find any crtc or sizes
[ 5.934260] udevd[1783]: starting version 3.2.5
[ 5.936653] usb 1-1.4: New USB device found, idVendor=0424, idProduct=2740, bcdDevice= 2.00
[ 5.945259] random: udevd: uninitialized urandom read (16 bytes read)
[ 5.947141] usb 1-1.4: New USB device strings: Mfr=1, Product=2, SerialNumber=0
[ 5.954224] random: udevd: uninitialized urandom read (16 bytes read)
[ 5.960855] usb 1-1.4: Product: Hub Controller
[ 5.960860] usb 1-1.4: Manufacturer: Microchip Tech
[ 5.967936] random: udevd: uninitialized urandom read (16 bytes read)
[ 6.022538] udevd[1784]: starting eudev-3.2.5
[ 6.620884] FAT-fs (mmcblk0p1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck.
[ 6.671295] EXT4-fs (mmcblk0p2): re-mounted. Opts: (null)
[ 8.094115] urandom_read: 4 callbacks suppressed
[ 8.094121] random: dd: uninitialized urandom read (512 bytes read)
Configuring packages on first boot....
(This may take several minutes. Please do not power off the machine.)
Running postinst /etc/rpm-postinsts/100-xrt...
[ 10.324545] INFO: Creating ICD entry for Xilinx Platform
Running postinst /etc/rpm-postinsts/101-sysvinit-inittab...
Running postinst /etc/rpm-postinsts/102-libmali-xlnx...
[ 10.508872] update-alternatives: Linking /usr/lib/libMali.so.9.0 to /usr/lib/x11/libMali.so.9.0
[ 10.562599] random: ln: uninitialized urandom read (6 bytes read)
[ 10.569434] update-alternatives: Linking /usr/lib/libMali.so.9.0 to /usr/lib/x11/libMali.so.9.0
[ 10.606313] Warn: update-alternatives: libmali-xlnx has multiple providers with the same priority, please check /usr/lib/opkg/alternatives/libmali-xlnx for details
[ 10.638197] random: ln: uninitialized urandom read (6 bytes read)
[ 10.645010] update-alternatives: Linking /usr/lib/libMali.so.9.0 to /usr/lib/x11/libMali.so.9.0
[ 10.699216] update-alternatives: Linking /usr/lib/libMali.so.9.0 to /usr/lib/x11/libMali.so.9.0
update-rc.d: /etc/init.d/run-postinsts exists during rc.d purge (continuing)
Removing any system startup links for run-postinsts ...
/etc/rcS.d/S99run-postinsts
INIT: Entering runlevel: 5
Configuring network interfaces... Cannot find device "eth0"
Starting system message bus: dbus.
Starting haveged: haveged: listening socket at 3
haveged: haveged starting up
Starting Dropbear SSH server: Generating 2048 bit rsa key, this may take a while...
haveged: haveged: ver: 1.9.4; arch: generic; vend: ; build: (gcc 8.2.0 CTV); collect: 128K
haveged: haveged: cpu: (VC); data: 16K (D); inst: 16K (D); idx: 11/40; sz: 15528/64688
haveged: haveged: tot tests(BA8): A:1/1 B:1/1 continuous tests(B): last entropy estimate 8.00043
haveged: haveged: fills: 0, generated: 0
[ 11.832395] random: crng init done
Public key portion is:
ssh-rsa AAAAB3NzaC1yc2EAAAADAQABAAABAQClgIPUvRJMncuVZRLC/YwbsjRYKGDbnVqdOWuh/loLd2t8k3MzRVOzTiNu6inSj2+dcIHeXI0OqjuCqswJMPrUS8AebThSB3zosmkcToHAzPXnMBXVg9jQvEqiYFbY0Xfm24rm4CskNj49/1CiiO1xAhwWp7xiHUZ7prlC7gqzvxPRb6xaGfhAzxYYh8ONVR+hFLejuANuDRse6TUZsE0w+kVXGgm9z5NvCJvGdsvRrT2MPEKGtXHbwdi+cd8wquAYI9spVcSANmnPXKBUINF7YzKOWwe3KxmEd8UZw9gOZVykRw3J+DPjad3Ef7wjIzosPILCpPhPGq3slW421a6b root@ultra96v2_min
Fingerprint: sha1!! 83:dd:7f:48:6b:01:eb:90:4c:c0:3b:ba:0f:d0:1e:77:32:75:48:51
dropbear.
Starting internet superserver: inetd.
Starting syslogd/klogd: done
Starting tcf-agent: OK
PetaLinux 2019.2 ultra96v2_min /dev/ttyPS0
ultra96v2_min login: root
と書かれている。やはりデフォルトのクロックは id = 0 にする必要があるらしい? 早速やってみよう。Set id = 0.
masaaki@masaaki-H110M4-M01:~/Vitis_Work/Vitis_Accel_Examples/hello_world$ make all TARGET=hw DEVICE=ultra96v2_min HOST_ARCH=aarch64 SYSROOT=/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min/images/linux/ultra96v2_min_pkg/pfm/sysroots/aarch64-xilinx-linux/
/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/gnu/aarch64/lin/aarch64-linux/bin/aarch64-linux-gnu-g++ -I..//common/includes/xcl2 -I/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min/images/linux/ultra96v2_min_pkg/pfm/sysroots/aarch64-xilinx-linux//usr//include/xrt -I/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vivado/2019.2/include -Wall -O0 -g -std=c++11 -fmessage-length=0 ..//common/includes/xcl2/xcl2.cpp src/host.cpp -o 'host' -L/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min/images/linux/ultra96v2_min_pkg/pfm/sysroots/aarch64-xilinx-linux//usr//lib -lOpenCL -lpthread -lrt -lstdc++ --sysroot=/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min/images/linux/ultra96v2_min_pkg/pfm/sysroots/aarch64-xilinx-linux/
mkdir -p ./build_dir.hw.ultra96v2_min
v++ -t hw --platform ultra96v2_min --save-temps --temp_dir ./build_dir.hw.ultra96v2_min -l -o'build_dir.hw.ultra96v2_min/vadd.xclbin' _x.hw.ultra96v2_min/vadd.xo
Option Map File Used: '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/data/vitis/vpp/optMap.xml'
****** v++ v2019.2 (64-bit)
**** SW Build 2700185 on Thu Oct 24 18:45:48 MDT 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
INFO: [v++ 60-1306] Additional information associated with this v++ link can be found at:
Reports: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/reports/link
Log files: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/logs/link
Running Dispatch Server on port:42947
INFO: [v++ 60-1548] Creating build summary session with primary output /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/vadd.xclbin.link_summary, at Mon Nov 18 05:02:19 2019
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Mon Nov 18 05:02:19 2019
Running Rule Check Server on port:35157
INFO: [v++ 60-1315] Creating rulecheck session with output '/home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/reports/link/v++_link_vadd_guidance.html', at Mon Nov 18 05:02:20 2019
INFO: [v++ 60-895] Target platform: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min/ultra96v2_min.xpfm
INFO: [v++ 60-1578] This platform contains Xilinx Shell Archive '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min/hw/ultra96v2_min.xsa'
INFO: [v++ 60-629] Linking for hardware target
INFO: [v++ 60-423] Target device: ultra96v2_min
INFO: [v++ 60-1332] Run 'run_link' status: Not started
INFO: [v++ 60-1443] [05:02:20] Run run_link: Step system_link: Started
INFO: [v++ 60-1453] Command Line: system_link --xo /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/_x.hw.ultra96v2_min/vadd.xo -keep --xpfm /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min/ultra96v2_min.xpfm --target hw --output_dir /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/int --temp_dir /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/sys_link
INFO: [v++ 60-1454] Run Directory: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/run_link
INFO: [SYSTEM_LINK 82-76] Reading emulation BD and HPFM information
INFO: [SYSTEM_LINK 60-1316] Initiating connection to rulecheck server, at Mon Nov 18 05:02:21 2019
INFO: [SYSTEM_LINK 82-70] Extracting xo v3 file /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/_x.hw.ultra96v2_min/vadd.xo
INFO: [KernelCheck 83-118] 'vadd' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'in1' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'in2' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'out_r' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'size' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [SYSTEM_LINK 82-53] Creating IP database /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/sys_link/_sysl/.cdb/xd_ip_db.xml
INFO: [SYSTEM_LINK 82-38] [05:02:21] build_xd_ip_db started: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/bin/build_xd_ip_db -ip_search 0 -sds-pf /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/sys_link/ultra96v2_min.hpfm -clkid 0 -ip /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/sys_link/iprepo/xilinx_com_hls_vadd_1_0,vadd -o /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/sys_link/_sysl/.cdb/xd_ip_db.xml
INFO: [SYSTEM_LINK 82-37] [05:02:24] build_xd_ip_db finished successfully
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 296.438 ; gain = 0.000 ; free physical = 327 ; free virtual = 34652
INFO: [SYSTEM_LINK 82-51] Create system connectivity graph
INFO: [SYSTEM_LINK 82-102] Applying explicit connections to the system connectivity graph: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/sys_link/cfgraph/cfgen_cfgraph.xml
INFO: [SYSTEM_LINK 82-38] [05:02:24] cfgen started: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/bin/cfgen -dmclkid 0 -r /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/sys_link/cfgraph/cfgen_cfgraph.xml
INFO: [CFGEN 83-0] Kernel Specs:
INFO: [CFGEN 83-0] kernel: vadd, num: 1 {vadd_1}
INFO: [CFGEN 83-2226] Inferring mapping for argument vadd_1.in1 to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument vadd_1.in2 to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument vadd_1.out_r to HP
INFO: [SYSTEM_LINK 82-37] [05:02:25] cfgen finished successfully
Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.29 . Memory (MB): peak = 296.438 ; gain = 0.000 ; free physical = 330 ; free virtual = 34655
INFO: [SYSTEM_LINK 82-52] Create top-level block diagram
INFO: [SYSTEM_LINK 82-38] [05:02:25] cf2bd started: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/bin/cf2bd --linux --trace_buffer 1024 --input_file /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/sys_link/cfgraph/cfgen_cfgraph.xml --ip_db /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/sys_link/_sysl/.cdb/xd_ip_db.xml --cf_name dr --working_dir /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/sys_link/_sysl/.xsd --temp_dir /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/sys_link --output_dir /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/int
INFO: [CF2BD 82-31] Launching cf2xd: cf2xd -linux -trace-buffer 1024 -i /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/sys_link/cfgraph/cfgen_cfgraph.xml -r /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o dr.xml
INFO: [CF2BD 82-28] cf2xd finished successfully
INFO: [CF2BD 82-31] Launching cf_xsd: cf_xsd -disable-address-gen -dn dr -dp /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/sys_link/_sysl/.xsd
rlwrap: warning: your $TERM is 'xterm-256color' but rlwrap couldn't find it in the terminfo database. Expect some problems.: Inappropriate ioctl for device
INFO: [CF2BD 82-28] cf_xsd finished successfully
INFO: [SYSTEM_LINK 82-37] [05:02:26] cf2bd finished successfully
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 296.438 ; gain = 0.000 ; free physical = 321 ; free virtual = 34652
INFO: [v++ 60-1441] [05:02:26] Run run_link: Step system_link: Completed
Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 677.902 ; gain = 0.000 ; free physical = 340 ; free virtual = 34670
INFO: [v++ 60-1443] [05:02:26] Run run_link: Step cf2sw: Started
INFO: [v++ 60-1453] Command Line: cf2sw -sdsl /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/int/sdsl.dat -rtd /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/int/cf2sw.rtd -xclbin /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/int/xclbin_orig.xml -o /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/int/xclbin_orig.1.xml
INFO: [v++ 60-1454] Run Directory: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/run_link
INFO: [v++ 60-1441] [05:02:27] Run run_link: Step cf2sw: Completed
Time (s): cpu = 00:00:00.48 ; elapsed = 00:00:00.54 . Memory (MB): peak = 677.902 ; gain = 0.000 ; free physical = 338 ; free virtual = 34670
INFO: [v++ 60-1443] [05:02:27] Run run_link: Step rtd2_system_diagram: Started
INFO: [v++ 60-1453] Command Line: rtd2SystemDiagram --rtdJsonFileName /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/int/cf2sw.rtd --diagramJsonFileName /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/int/systemDiagramModel.json --platformFilePath /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min/ultra96v2_min.xpfm --generatedByName v++ --generatedByVersion 2019.2 --generatedByChangeList 2700185 --generatedByTimeStamp Thu Oct 24 18:45:48 MDT 2019 --generatedByOptions /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/bin/unwrapped/lnx64.o/v++ -t hw --platform ultra96v2_min --save-temps --temp_dir ./build_dir.hw.ultra96v2_min -l -obuild_dir.hw.ultra96v2_min/vadd.xclbin _x.hw.ultra96v2_min/vadd.xo --generatedByXclbinName vadd --kernelInfoDataFileName /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/int/kernel_info.dat
INFO: [v++ 60-1454] Run Directory: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/run_link
WARNING: [v++ 82-164] Unable to populate user region instance path. The platform file does not contain a hardwarePlatform.devices..core.instPath entry.
INFO: [v++ 60-839] Read in kernel information from file '/home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/int/kernel_info.dat'.
WARNING: [v++ 82-158] Unable to populate kernel available resources DSP entry.
WARNING: [v++ 82-163] Unable to populate user region available resources. The platform file deos not contain a hardwarePlatform.devices..core.availableResources entry
INFO: [v++ 60-1441] [05:02:29] Run run_link: Step rtd2_system_diagram: Completed
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 677.902 ; gain = 0.000 ; free physical = 342 ; free virtual = 34672
INFO: [v++ 60-1443] [05:02:29] Run run_link: Step vpl: Started
INFO: [v++ 60-1453] Command Line: vpl -t hw -f ultra96v2_min -s --output_dir /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/int --log_dir /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/logs/link --report_dir /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/reports/link --config /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/int/vplConfig.ini -k /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/int/kernel_info.dat --webtalk_flag Vitis --temp_dir /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link --no-info --tlog_dir /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/.tlog/v++_link_vadd --iprepo /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/int/xo/ip_repo/xilinx_com_hls_vadd_1_0 --messageDb /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/run_link/vpl.pb /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/int/dr.bd.tcl
INFO: [v++ 60-1454] Run Directory: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/run_link
****** vpl v2019.2 (64-bit)
**** SW Build 2700185 on Thu Oct 24 18:45:48 MDT 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
INFO: [VPL 60-839] Read in kernel information from file '/home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/int/kernel_info.dat'.
INFO: [VPL 60-423] Target device: ultra96v2_min
INFO: [VPL 60-1032] Extracting hardware platform to /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/vivado/vpl/.local/hw_platform
[05:02:41] Run vpl: Step create_project: Started
Creating Vivado project.
[05:02:50] Run vpl: Step create_project: Completed
[05:02:50] Run vpl: Step create_bd: Started
[05:03:01] Run vpl: Step create_bd: Completed
[05:03:01] Run vpl: Step update_bd: Started
[05:03:02] Run vpl: Step update_bd: Completed
[05:03:02] Run vpl: Step generate_target: Started
[05:03:42] Run vpl: Step generate_target: Completed
[05:03:42] Run vpl: Step config_hw_runs: Started
[05:03:44] Run vpl: Step config_hw_runs: Completed
[05:03:44] Run vpl: Step synth: Started
[05:04:15] Block-level synthesis in progress, 0 of 7 jobs complete, 2 jobs running.
[05:04:45] Block-level synthesis in progress, 0 of 7 jobs complete, 2 jobs running.
[05:05:15] Block-level synthesis in progress, 0 of 7 jobs complete, 2 jobs running.
[05:05:45] Block-level synthesis in progress, 0 of 7 jobs complete, 2 jobs running.
[05:06:15] Block-level synthesis in progress, 1 of 7 jobs complete, 1 job running.
[05:06:46] Block-level synthesis in progress, 2 of 7 jobs complete, 1 job running.
[05:07:16] Block-level synthesis in progress, 2 of 7 jobs complete, 2 jobs running.
[05:07:46] Block-level synthesis in progress, 2 of 7 jobs complete, 2 jobs running.
[05:08:16] Block-level synthesis in progress, 2 of 7 jobs complete, 2 jobs running.
[05:08:46] Block-level synthesis in progress, 4 of 7 jobs complete, 1 job running.
[05:09:16] Block-level synthesis in progress, 4 of 7 jobs complete, 2 jobs running.
[05:09:46] Block-level synthesis in progress, 4 of 7 jobs complete, 2 jobs running.
[05:10:16] Block-level synthesis in progress, 4 of 7 jobs complete, 2 jobs running.
[05:10:46] Block-level synthesis in progress, 6 of 7 jobs complete, 0 jobs running.
[05:11:16] Block-level synthesis in progress, 6 of 7 jobs complete, 1 job running.
[05:11:46] Block-level synthesis in progress, 6 of 7 jobs complete, 1 job running.
[05:12:16] Block-level synthesis in progress, 6 of 7 jobs complete, 1 job running.
[05:12:46] Block-level synthesis in progress, 6 of 7 jobs complete, 1 job running.
[05:13:16] Block-level synthesis in progress, 7 of 7 jobs complete, 0 jobs running.
[05:13:47] Top-level synthesis in progress.
[05:14:17] Top-level synthesis in progress.
[05:14:47] Top-level synthesis in progress.
[05:15:03] Run vpl: Step synth: Completed
[05:15:03] Run vpl: Step impl: Started
[05:17:04] Finished 2nd of 6 tasks (FPGA linking synthesized kernels to platform). Elapsed time: 00h 14m 33s
[05:17:04] Starting logic optimization..
[05:17:04] Phase 1 Retarget
[05:17:04] Phase 2 Constant propagation
[05:17:04] Phase 3 Sweep
[05:17:04] Phase 4 BUFG optimization
[05:17:04] Phase 5 Shift Register Optimization
[05:17:04] Phase 6 Post Processing Netlist
[05:17:34] Finished 3rd of 6 tasks (FPGA logic optimization). Elapsed time: 00h 00m 30s
[05:17:34] Starting logic placement..
[05:17:34] Phase 1 Placer Initialization
[05:17:34] Phase 1.1 Placer Initialization Netlist Sorting
[05:17:34] Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
[05:17:34] Phase 1.3 Build Placer Netlist Model
[05:17:34] Phase 1.4 Constrain Clocks/Macros
[05:17:34] Phase 2 Global Placement
[05:17:34] Phase 2.1 Floorplanning
[05:17:34] Phase 2.2 Global Placement Core
[05:17:34] Phase 2.2.1 Physical Synthesis In Placer
[05:17:34] Phase 3 Detail Placement
[05:17:34] Phase 3.1 Commit Multi Column Macros
[05:17:34] Phase 3.2 Commit Most Macros & LUTRAMs
[05:17:34] Phase 3.3 Area Swap Optimization
[05:18:04] Finished 4th of 6 tasks (FPGA logic placement). Elapsed time: 00h 00m 30s
[05:18:04] Starting logic routing..
[05:18:04] Phase 1 Build RT Design
[05:18:04] Phase 3.4 Pipeline Register Optimization
[05:18:04] Phase 3.5 Small Shape DP
[05:18:04] Phase 3.5.1 Small Shape Clustering
[05:18:04] Phase 3.5.2 Flow Legalize Slice Clusters
[05:18:04] Phase 3.5.3 Slice Area Swap
[05:18:04] Phase 3.5.4 Commit Slice Clusters
[05:18:04] Phase 3.6 Re-assign LUT pins
[05:18:04] Phase 3.7 Pipeline Register Optimization
[05:18:04] Phase 4 Post Placement Optimization and Clean-Up
[05:18:04] Phase 4.1 Post Commit Optimization
[05:18:04] Phase 4.1.1 Post Placement Optimization
[05:18:04] Phase 4.1.1.1 BUFG Insertion
[05:18:04] Phase 4.2 Post Placement Cleanup
[05:18:04] Phase 4.3 Placer Reporting
[05:18:04] Phase 4.4 Final Placement Cleanup
[05:18:35] Phase 2 Router Initialization
[05:18:35] Phase 2.1 Create Timer
[05:18:35] Phase 2.2 Fix Topology Constraints
[05:18:35] Phase 2.3 Pre Route Cleanup
[05:18:35] Phase 2.4 Global Clock Net Routing
[05:18:35] Phase 2.5 Update Timing
[05:18:35] Phase 3 Initial Routing
[05:18:35] Phase 4 Rip-up And Reroute
[05:18:35] Phase 4.1 Global Iteration 0
[05:19:05] Phase 4.2 Additional Iteration for Hold
[05:19:05] Phase 5 Delay and Skew Optimization
[05:19:05] Phase 5.1 Delay CleanUp
[05:19:05] Phase 5.1.1 Update Timing
[05:19:05] Phase 5.2 Clock Skew Optimization
[05:19:05] Phase 6 Post Hold Fix
[05:19:05] Phase 6.1 Hold Fix Iter
[05:19:05] Phase 6.1.1 Update Timing
[05:19:05] Phase 7 Route finalize
[05:19:05] Phase 8 Verifying routed nets
[05:19:05] Phase 9 Depositing Routes
[05:19:05] Phase 10 Post Router Timing
[05:19:05] Finished 5th of 6 tasks (FPGA routing). Elapsed time: 00h 01m 00s
[05:19:05] Starting bitstream generation..
[05:19:21] Creating bitmap...
[05:19:21] Writing bitstream ./Ultra96V2_Platform1_wrapper.bit...
[05:19:21] Finished 6th of 6 tasks (FPGA bitstream generation). Elapsed time: 00h 00m 16s
[05:19:20] Run vpl: Step impl: Completed
[05:19:21] Run vpl: FINISHED. Run Status: impl Complete!
INFO: [v++ 60-1441] [05:19:21] Run run_link: Step vpl: Completed
Time (s): cpu = 00:00:05 ; elapsed = 00:16:52 . Memory (MB): peak = 677.902 ; gain = 0.000 ; free physical = 4601 ; free virtual = 34076
INFO: [v++ 60-1443] [05:19:21] Run run_link: Step rtdgen: Started
INFO: [v++ 60-1453] Command Line: rtdgen
INFO: [v++ 60-1454] Run Directory: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/run_link
INFO: [v++ 60-1453] Command Line: cf2sw -a /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/int/address_map.xml -sdsl /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/int/sdsl.dat -xclbin /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/int/xclbin_orig.xml -rtd /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/int/vadd.rtd -o /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/int/vadd.xml
INFO: [v++ 60-1618] Launching
INFO: [v++ 60-1441] [05:19:23] Run run_link: Step rtdgen: Completed
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 677.902 ; gain = 0.000 ; free physical = 4614 ; free virtual = 34090
INFO: [v++ 60-1443] [05:19:23] Run run_link: Step xclbinutil: Started
INFO: [v++ 60-1453] Command Line: xclbinutil --add-section BITSTREAM:RAW:/home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/int/system.bit --force --key-value SYS:mode:flat --add-section :JSON:/home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/int/vadd.rtd --add-section CLOCK_FREQ_TOPOLOGY:JSON:/home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/int/vadd_xml.rtd --add-section BUILD_METADATA:JSON:/home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/int/vadd_build.rtd --add-section EMBEDDED_METADATA:RAW:/home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/int/vadd.xml --add-section SYSTEM_METADATA:RAW:/home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/int/systemDiagramModelSlrBaseAddress.json --key-value SYS:PlatformVBNV:vendor_Ultra96V2_Ultra96V2_Platform1_1_0 --output /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/int/vadd.xclbin
INFO: [v++ 60-1454] Run Directory: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/run_link
XRT Build Version: 2.3.1301
Build Date: 2019-10-24 20:05:16
Hash ID: 192e706aea53163a04c574f9b3fe9ed76b6ca471
Creating a default 'in-memory' xclbin image.
Section: 'BITSTREAM'(0) was successfully added.
Size : 5568799 bytes
Format : RAW
File : '/home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/int/system.bit'
Section: 'MEM_TOPOLOGY'(6) was successfully added.
Format : JSON
File : 'mem_topology'
Section: 'IP_LAYOUT'(8) was successfully added.
Format : JSON
File : 'ip_layout'
Section: 'CONNECTIVITY'(7) was successfully added.
Format : JSON
File : 'connectivity'
WARNING: Skipping CLOCK_FREQ_TOPOLOGY section for count size is zero.
WARNING: Section 'CLOCK_FREQ_TOPOLOGY' content is empty. No data in the given JSON file.
Section: 'CLOCK_FREQ_TOPOLOGY'(11) was empty. No action taken.
Format : JSON
File : '/home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/int/vadd_xml.rtd'
Section: 'BUILD_METADATA'(14) was successfully added.
Size : 2090 bytes
Format : JSON
File : '/home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/int/vadd_build.rtd'
Section: 'EMBEDDED_METADATA'(2) was successfully added.
Size : 2699 bytes
Format : RAW
File : '/home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/int/vadd.xml'
Section: 'SYSTEM_METADATA'(22) was successfully added.
Size : 7407 bytes
Format : RAW
File : '/home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/int/systemDiagramModelSlrBaseAddress.json'
Successfully wrote (5586736 bytes) to the output file: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/int/vadd.xclbin
Leaving xclbinutil.
INFO: [v++ 60-1441] [05:19:23] Run run_link: Step xclbinutil: Completed
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.14 . Memory (MB): peak = 677.902 ; gain = 0.000 ; free physical = 4606 ; free virtual = 34091
INFO: [v++ 60-1443] [05:19:23] Run run_link: Step xclbinutilinfo: Started
INFO: [v++ 60-1453] Command Line: xclbinutil --quiet --info /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/int/vadd.xclbin.info --input /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/int/vadd.xclbin
INFO: [v++ 60-1454] Run Directory: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/run_link
INFO: [v++ 60-1441] [05:19:23] Run run_link: Step xclbinutilinfo: Completed
Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.07 . Memory (MB): peak = 677.902 ; gain = 0.000 ; free physical = 4606 ; free virtual = 34091
INFO: [v++ 60-244] Generating system estimate report...
INFO: [v++ 60-1092] Generated system estimate report: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/reports/link/system_estimate_vadd.xtxt
INFO: [v++ 60-907] Packaging to directory: 'build_dir.hw.ultra96v2_min/sd_card'
INFO: [v++ 60-586] Created build_dir.hw.ultra96v2_min/vadd.xclbin
INFO: [v++ 60-1307] Run completed. Additional information can be found in:
Guidance: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/reports/link/v++_link_vadd_guidance.html
Timing Report: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/reports/link/imp/Ultra96V2_Platform1_wrapper_timing_summary_routed.rpt
Vivado Log: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/logs/link/vivado.log
Steps Log File: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/logs/link/link.steps.log
INFO: [v++ 60-791] Total elapsed time: 0h 17m 8s
emconfigutil --platform ultra96v2_min --od ./_x.hw.ultra96v2_min
****** configutil v2019.2 (64-bit)
**** SW Build 2700185 on Thu Oct 24 18:45:48 MDT 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
INFO: [ConfigUtil 60-895] Target platform: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min/ultra96v2_min.xpfm
INFO: [ConfigUtil 60-1578] This platform contains Xilinx Shell Archive '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min/hw/ultra96v2_min.xsa'
emulation configuration file `emconfig.json` is created in ./_x.hw.ultra96v2_min directory
mkdir -p sd_card/./build_dir.hw.ultra96v2_min
cp -rf `/home/masaaki/Vitis_Work/Vitis_Accel_Examples/common/utility/parse_platform_list.py ultra96v2_min`/ultra96v2_min/sw/ultra96v2_min/boot/generic.readme `/home/masaaki/Vitis_Work/Vitis_Accel_Examples/common/utility/parse_platform_list.py ultra96v2_min`/ultra96v2_min/sw/ultra96v2_min/xrt/image/* xrt.ini host sd_card
cp: 'None/ultra96v2_min/sw/ultra96v2_min/boot/generic.readme' を stat できません: そのようなファイルやディレクトリはありません
cp: 'None/ultra96v2_min/sw/ultra96v2_min/xrt/image/*' を stat できません: そのようなファイルやディレクトリはありません
Makefile:131: recipe for target 'sd_card' failed
make: *** [sd_card] Error 1
<?xml version="1.0" encoding="UTF-8"?>
<sdx:platform sdx:vendor="xilinx.com"
sdx:library="sdx"
sdx:name="ultra96v2_min"
sdx:version="1.0"
xmlns:sdx="http://www.xilinx.com/sdx">
<sdx:description>
ultra96v2_min
</sdx:description>
<sdx:hardwarePlatforms>
<sdx:hardwarePlatform sdx:path="hw" sdx:name="ultra96v2_min.xsa"/>
</sdx:hardwarePlatforms>
<sdx:softwarePlatforms>
<sdx:softwarePlatform sdx:path="sw" sdx:name="ultra96v2_min.spfm"/>
</sdx:softwarePlatforms>
</sdx:platform>
ということで、Vivado のプロジェクトを見てみよう。ERROR: [CFGEN 83-2299] Clock ID 0 must exist. Please correct the targetted platform.
masaaki@masaaki-H110M4-M01:~/Vitis_Work/Vitis_Accel_Examples/hello_world$ make all TARGET=sw_emu DEVICE=ultra96v2_min HOST_ARCH=aarch64 SYSROOT=/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min/images/linux/ultra96v2_min_pkg/pfm/sysroots/aarch64-xilinx-linux/
/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/gnu/aarch64/lin/aarch64-linux/bin/aarch64-linux-gnu-g++ -I..//common/includes/xcl2 -I/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min/images/linux/ultra96v2_min_pkg/pfm/sysroots/aarch64-xilinx-linux//usr//include/xrt -I/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vivado/2019.2/include -Wall -O0 -g -std=c++11 -fmessage-length=0 ..//common/includes/xcl2/xcl2.cpp src/host.cpp -o 'host' -L/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min/images/linux/ultra96v2_min_pkg/pfm/sysroots/aarch64-xilinx-linux//usr//lib -lOpenCL -lpthread -lrt -lstdc++ --sysroot=/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min/images/linux/ultra96v2_min_pkg/pfm/sysroots/aarch64-xilinx-linux/
mkdir -p ./_x.sw_emu.ultra96v2_min
v++ -t sw_emu --platform ultra96v2_min --save-temps -g --temp_dir ./_x.sw_emu.ultra96v2_min -c -k vadd -I'src' -o'_x.sw_emu.ultra96v2_min/vadd.xo' 'src/vadd.cpp'
Option Map File Used: '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/data/vitis/vpp/optMap.xml'
****** v++ v2019.2 (64-bit)
**** SW Build 2700185 on Thu Oct 24 18:45:48 MDT 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
INFO: [v++ 60-1306] Additional information associated with this v++ compile can be found at:
Reports: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/_x.sw_emu.ultra96v2_min/reports/vadd
Log files: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/_x.sw_emu.ultra96v2_min/logs/vadd
Running Dispatch Server on port:35071
INFO: [v++ 60-1548] Creating build summary session with primary output /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/_x.sw_emu.ultra96v2_min/vadd.xo.compile_summary, at Sun Nov 17 20:43:57 2019
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Sun Nov 17 20:43:57 2019
Running Rule Check Server on port:34973
INFO: [v++ 60-1315] Creating rulecheck session with output '/home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/_x.sw_emu.ultra96v2_min/reports/vadd/v++_compile_vadd_guidance.html', at Sun Nov 17 20:43:58 2019
INFO: [v++ 60-895] Target platform: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min/ultra96v2_min.xpfm
INFO: [v++ 60-1578] This platform contains Xilinx Shell Archive '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min/hw/ultra96v2_min.xsa'
INFO: [v++ 60-585] Compiling for software emulation target
INFO: [v++ 60-423] Target device: ultra96v2_min
INFO: [v++ 60-242] Creating kernel: 'vadd'
===>The following messages were generated while performing high-level synthesis for kernel: vadd Log file: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/_x.sw_emu.ultra96v2_min/vadd/vadd/vivado_hls.log :
INFO: [v++ 204-61] Option 'relax_ii_for_timing' is enabled, will increase II to preserve clock frequency constraints.
INFO: [v++ 60-594] Finished kernel compilation
INFO: [v++ 60-586] Created _x.sw_emu.ultra96v2_min/vadd.xo
INFO: [v++ 60-791] Total elapsed time: 0h 0m 12s
mkdir -p ./build_dir.sw_emu.ultra96v2_min
v++ -t sw_emu --platform ultra96v2_min --save-temps -g --temp_dir ./build_dir.sw_emu.ultra96v2_min -l -o'build_dir.sw_emu.ultra96v2_min/vadd.xclbin' _x.sw_emu.ultra96v2_min/vadd.xo
Option Map File Used: '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/data/vitis/vpp/optMap.xml'
****** v++ v2019.2 (64-bit)
**** SW Build 2700185 on Thu Oct 24 18:45:48 MDT 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
INFO: [v++ 60-1306] Additional information associated with this v++ link can be found at:
Reports: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.sw_emu.ultra96v2_min/reports/link
Log files: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.sw_emu.ultra96v2_min/logs/link
Running Dispatch Server on port:35365
INFO: [v++ 60-1548] Creating build summary session with primary output /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.sw_emu.ultra96v2_min/vadd.xclbin.link_summary, at Sun Nov 17 20:44:11 2019
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Sun Nov 17 20:44:11 2019
Running Rule Check Server on port:33481
INFO: [v++ 60-1315] Creating rulecheck session with output '/home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.sw_emu.ultra96v2_min/reports/link/v++_link_vadd_guidance.html', at Sun Nov 17 20:44:12 2019
INFO: [v++ 60-895] Target platform: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min/ultra96v2_min.xpfm
INFO: [v++ 60-1578] This platform contains Xilinx Shell Archive '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min/hw/ultra96v2_min.xsa'
INFO: [v++ 60-629] Linking for software emulation target
INFO: [v++ 60-423] Target device: ultra96v2_min
INFO: [v++ 60-645] kernel flags are '-g -I /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/src -g'
INFO: [v++ 60-251] Hardware accelerator integration...
INFO: [v++ 60-586] Created build_dir.sw_emu.ultra96v2_min/vadd.xclbin
INFO: [v++ 60-1307] Run completed. Additional information can be found in:
Guidance: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.sw_emu.ultra96v2_min/reports/link/v++_link_vadd_guidance.html
Vivado Log: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.sw_emu.ultra96v2_min/logs/link/vivado.log
Steps Log File: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.sw_emu.ultra96v2_min/logs/link/link.steps.log
INFO: [v++ 60-791] Total elapsed time: 0h 0m 15s
emconfigutil --platform ultra96v2_min --od ./_x.sw_emu.ultra96v2_min
****** configutil v2019.2 (64-bit)
**** SW Build 2700185 on Thu Oct 24 18:45:48 MDT 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
INFO: [ConfigUtil 60-895] Target platform: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min/ultra96v2_min.xpfm
INFO: [ConfigUtil 60-1578] This platform contains Xilinx Shell Archive '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min/hw/ultra96v2_min.xsa'
emulation configuration file `emconfig.json` is created in ./_x.sw_emu.ultra96v2_min directory
mkdir -p sd_card/./build_dir.sw_emu.ultra96v2_min
cp -rf `/home/masaaki/Vitis_Work/Vitis_Accel_Examples/common/utility/parse_platform_list.py ultra96v2_min`/ultra96v2_min/sw/ultra96v2_min/boot/generic.readme `/home/masaaki/Vitis_Work/Vitis_Accel_Examples/common/utility/parse_platform_list.py ultra96v2_min`/ultra96v2_min/sw/ultra96v2_min/xrt/image/* xrt.ini host sd_card
cp: 'None/ultra96v2_min/sw/ultra96v2_min/boot/generic.readme' を stat できません: そのようなファイルやディレクトリはありません
cp: 'None/ultra96v2_min/sw/ultra96v2_min/xrt/image/*' を stat できません: そのようなファイルやディレクトリはありません
Makefile:131: recipe for target 'sd_card' failed
make: *** [sd_card] Error 1
masaaki@masaaki-H110M4-M01:~/Vitis_Work/Vitis_Accel_Examples/hello_world$ make all TARGET=hw DEVICE=ultra96v2_min HOST_ARCH=aarch64 SYSROOT=/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min/images/linux/ultra96v2_min_pkg/pfm/sysroots/aarch64-xilinx-linux/
/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/gnu/aarch64/lin/aarch64-linux/bin/aarch64-linux-gnu-g++ -I..//common/includes/xcl2 -I/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min/images/linux/ultra96v2_min_pkg/pfm/sysroots/aarch64-xilinx-linux//usr//include/xrt -I/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vivado/2019.2/include -Wall -O0 -g -std=c++11 -fmessage-length=0 ..//common/includes/xcl2/xcl2.cpp src/host.cpp -o 'host' -L/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min/images/linux/ultra96v2_min_pkg/pfm/sysroots/aarch64-xilinx-linux//usr//lib -lOpenCL -lpthread -lrt -lstdc++ --sysroot=/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min/images/linux/ultra96v2_min_pkg/pfm/sysroots/aarch64-xilinx-linux/
mkdir -p ./_x.hw.ultra96v2_min
v++ -t hw --platform ultra96v2_min --save-temps --temp_dir ./_x.hw.ultra96v2_min -c -k vadd -I'src' -o'_x.hw.ultra96v2_min/vadd.xo' 'src/vadd.cpp'
Option Map File Used: '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/data/vitis/vpp/optMap.xml'
****** v++ v2019.2 (64-bit)
**** SW Build 2700185 on Thu Oct 24 18:45:48 MDT 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
INFO: [v++ 60-1306] Additional information associated with this v++ compile can be found at:
Reports: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/_x.hw.ultra96v2_min/reports/vadd
Log files: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/_x.hw.ultra96v2_min/logs/vadd
Running Dispatch Server on port:37443
INFO: [v++ 60-1548] Creating build summary session with primary output /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/_x.hw.ultra96v2_min/vadd.xo.compile_summary, at Sun Nov 17 20:52:11 2019
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Sun Nov 17 20:52:11 2019
Running Rule Check Server on port:37525
INFO: [v++ 60-1315] Creating rulecheck session with output '/home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/_x.hw.ultra96v2_min/reports/vadd/v++_compile_vadd_guidance.html', at Sun Nov 17 20:52:12 2019
INFO: [v++ 60-895] Target platform: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min/ultra96v2_min.xpfm
INFO: [v++ 60-1578] This platform contains Xilinx Shell Archive '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min/hw/ultra96v2_min.xsa'
INFO: [v++ 60-585] Compiling for hardware target
INFO: [v++ 60-423] Target device: ultra96v2_min
INFO: [v++ 60-242] Creating kernel: 'vadd'
===>The following messages were generated while performing high-level synthesis for kernel: vadd Log file: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/_x.hw.ultra96v2_min/vadd/vadd/vivado_hls.log :
INFO: [v++ 204-61] Option 'relax_ii_for_timing' is enabled, will increase II to preserve clock frequency constraints.
INFO: [v++ 204-61] Pipelining loop 'read1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining loop 'read2'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining loop 'vadd'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [v++ 204-61] Pipelining loop 'write'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 200-790] **** Loop Constraint Status: All loop constraints were satisfied.
INFO: [v++ 200-789] **** Estimated Fmax: 136.99 MHz
INFO: [v++ 60-594] Finished kernel compilation
INFO: [v++ 60-244] Generating system estimate report...
INFO: [v++ 60-1092] Generated system estimate report: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/_x.hw.ultra96v2_min/reports/vadd/system_estimate_vadd.xtxt
INFO: [v++ 60-586] Created _x.hw.ultra96v2_min/vadd.xo
INFO: [v++ 60-791] Total elapsed time: 0h 0m 36s
mkdir -p ./build_dir.hw.ultra96v2_min
v++ -t hw --platform ultra96v2_min --save-temps --temp_dir ./build_dir.hw.ultra96v2_min -l -o'build_dir.hw.ultra96v2_min/vadd.xclbin' _x.hw.ultra96v2_min/vadd.xo
Option Map File Used: '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/data/vitis/vpp/optMap.xml'
****** v++ v2019.2 (64-bit)
**** SW Build 2700185 on Thu Oct 24 18:45:48 MDT 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
INFO: [v++ 60-1306] Additional information associated with this v++ link can be found at:
Reports: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/reports/link
Log files: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/logs/link
Running Dispatch Server on port:41825
INFO: [v++ 60-1548] Creating build summary session with primary output /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/vadd.xclbin.link_summary, at Sun Nov 17 20:52:49 2019
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Sun Nov 17 20:52:49 2019
Running Rule Check Server on port:36947
INFO: [v++ 60-1315] Creating rulecheck session with output '/home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/reports/link/v++_link_vadd_guidance.html', at Sun Nov 17 20:52:50 2019
INFO: [v++ 60-895] Target platform: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min/ultra96v2_min.xpfm
INFO: [v++ 60-1578] This platform contains Xilinx Shell Archive '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min/hw/ultra96v2_min.xsa'
INFO: [v++ 60-629] Linking for hardware target
INFO: [v++ 60-423] Target device: ultra96v2_min
INFO: [v++ 60-1332] Run 'run_link' status: Not started
INFO: [v++ 60-1443] [20:52:51] Run run_link: Step system_link: Started
INFO: [v++ 60-1453] Command Line: system_link --xo /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/_x.hw.ultra96v2_min/vadd.xo -keep --xpfm /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min/ultra96v2_min.xpfm --target hw --output_dir /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/int --temp_dir /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/sys_link
INFO: [v++ 60-1454] Run Directory: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/run_link
INFO: [SYSTEM_LINK 82-76] Reading emulation BD and HPFM information
INFO: [SYSTEM_LINK 60-1316] Initiating connection to rulecheck server, at Sun Nov 17 20:52:52 2019
INFO: [SYSTEM_LINK 82-70] Extracting xo v3 file /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/_x.hw.ultra96v2_min/vadd.xo
INFO: [KernelCheck 83-118] 'vadd' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'in1' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'in2' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'out_r' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'size' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [SYSTEM_LINK 82-53] Creating IP database /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/sys_link/_sysl/.cdb/xd_ip_db.xml
INFO: [SYSTEM_LINK 82-38] [20:52:52] build_xd_ip_db started: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/bin/build_xd_ip_db -ip_search 0 -sds-pf /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/sys_link/ultra96v2_min.hpfm -clkid 2 -ip /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/sys_link/iprepo/xilinx_com_hls_vadd_1_0,vadd -o /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/sys_link/_sysl/.cdb/xd_ip_db.xml
INFO: [SYSTEM_LINK 82-37] [20:52:55] build_xd_ip_db finished successfully
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 296.438 ; gain = 0.000 ; free physical = 684 ; free virtual = 34977
INFO: [SYSTEM_LINK 82-51] Create system connectivity graph
INFO: [SYSTEM_LINK 82-102] Applying explicit connections to the system connectivity graph: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/sys_link/cfgraph/cfgen_cfgraph.xml
INFO: [SYSTEM_LINK 82-38] [20:52:55] cfgen started: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/bin/cfgen -dmclkid 2 -r /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/sys_link/cfgraph/cfgen_cfgraph.xml
INFO: [CFGEN 83-0] Kernel Specs:
INFO: [CFGEN 83-0] kernel: vadd, num: 1 {vadd_1}
ERROR: [CFGEN 83-2299] Clock ID 0 must exist. Please correct the targetted platform.
ERROR: [CFGEN 83-2298] Exiting due to previous error
ERROR: [SYSTEM_LINK 82-36] [20:52:55] cfgen failed
Time (s): cpu = 00:00:00.19 ; elapsed = 00:00:00.20 . Memory (MB): peak = 296.438 ; gain = 0.000 ; free physical = 681 ; free virtual = 34977
ERROR: [SYSTEM_LINK 82-62] Error generating design file for /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/sys_link/cfgraph/cfgen_cfgraph.xml, command: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/bin/cfgen -dmclkid 2 -r /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o /home/masaaki/Vitis_Work/Vitis_Accel_Examples/hello_world/build_dir.hw.ultra96v2_min/link/sys_link/cfgraph/cfgen_cfgraph.xml
ERROR: [SYSTEM_LINK 82-96] Error applying explicit connections to the system connectivity graph
ERROR: [SYSTEM_LINK 82-79] Unable to create system connectivity graph
INFO: [v++ 60-1442] [20:52:55] Run run_link: Step system_link: Failed
Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 677.902 ; gain = 0.000 ; free physical = 700 ; free virtual = 34996
ERROR: [v++ 60-661] v++ link run 'run_link' failed
ERROR: [v++ 60-626] Kernel link failed to complete
ERROR: [v++ 60-703] Failed to finish linking
Makefile:98: recipe for target 'build_dir.hw.ultra96v2_min/vadd.xclbin' failed
make: *** [build_dir.hw.ultra96v2_min/vadd.xclbin] Error 1
ERROR: [v++ 60-1606] The specified platform is not supported. Platform '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min/ultra96v2_min.xpfm' is a non-accelerated platform. By policy, non-accelerated platforms are not supported by the current tool
ERROR: [v++ 60-592] Failed to finish compilation
Makefile:95: recipe for target '_x.sw_emu.ultra96v2_min/vadd.xo' failed
make: *** [_x.sw_emu.ultra96v2_min/vadd.xo] Error 1
[ 64%] Linking CXX executable xclbinutil
/usr/bin/ld: -lOpenSSL::Crypto が見つかりません
collect2: error: ld returned 1 exit status
runtime_src/tools/xclbin/CMakeFiles/xclbinutil.dir/build.make:1034: recipe for target 'runtime_src/tools/xclbin/xclbinutil' failed
make[2]: *** [runtime_src/tools/xclbin/xclbinutil] Error 1
CMakeFiles/Makefile2:529: recipe for target 'runtime_src/tools/xclbin/CMakeFiles/xclbinutil.dir/all' failed
make[1]: *** [runtime_src/tools/xclbin/CMakeFiles/xclbinutil.dir/all] Error 2
Makefile:160: recipe for target 'all' failed
make: *** [all] Error 2
masaaki@masaaki-H110M4-M01:~/Vitis_Work/XRT$ sudo apt install --reinstall ./xrt_201920.2.3.1301_18.04-xrt.deb
パッケージリストを読み込んでいます... 完了
依存関係ツリーを作成しています
状態情報を読み取っています... 完了
注意、'./xrt_201920.2.3.1301_18.04-xrt.deb' の代わりに 'xrt' を選択します
以下のパッケージが新たにインストールされます:
xrt
アップグレード: 0 個、新規インストール: 1 個、削除: 0 個、保留: 31 個。
8,920 kB 中 0 B のアーカイブを取得する必要があります。
この操作後に追加で 46.1 MB のディスク容量が消費されます。
取得:1 /home/masaaki/Vitis_Work/XRT/xrt_201920.2.3.1301_18.04-xrt.deb xrt amd64 2.3.1301 [8,920 kB]
以前に未選択のパッケージ xrt を選択しています。
(データベースを読み込んでいます ... 現在 335735 個のファイルとディレクトリがインストールされています。)
.../xrt_201920.2.3.1301_18.04-xrt.deb を展開する準備をしています ...
xrt (2.3.1301) を展開しています...
xrt (2.3.1301) を設定しています ...
Unloading old XRT Linux kernel modules
rmmod: ERROR: Module xocl is not currently loaded
rmmod: ERROR: Module xclmgmt is not currently loaded
Invoking DKMS common.postinst for xrt
Loading new xrt-2.3.1301 DKMS files...
Building for 4.15.0-66-generic
Building initial module for 4.15.0-66-generic
Secure Boot not enabled on this system.
Done.
xocl:
Running module version sanity check.
- Original module
- No original module exists within this kernel
- Installation
- Installing to /lib/modules/4.15.0-66-generic/updates/dkms/
xclmgmt.ko:
Running module version sanity check.
- Original module
- No original module exists within this kernel
- Installation
- Installing to /lib/modules/4.15.0-66-generic/updates/dkms/
depmod........
DKMS: install completed.
Finished DKMS common.postinst
Loading new XRT Linux kernel modules
Installing MSD / MPD daemons
Installing pyopencl...
The directory '/home/masaaki/.cache/pip/http' or its parent directory is not owned by the current user and the cache has been disabled. Please check the permissions and owner of that directory. If executing pip with sudo, you may want sudo's -H flag.
The directory '/home/masaaki/.cache/pip' or its parent directory is not owned by the current user and caching wheels has been disabled. check the permissions and owner of that directory. If executing pip with sudo, you may want sudo's -H flag.
Collecting pyopencl
Downloading https://files.pythonhosted.org/packages/7f/92/f9130d750fb7232eda3f48e5de9a59d9d39fda58019174edddcd5564dfbb/pyopencl-2019.1.2-cp27-cp27mu-manylinux1_x86_64.whl (724kB)
100% |████████████████████████████████| 727kB 9.8MB/s
Requirement already satisfied: numpy in /usr/local/lib/python2.7/dist-packages (from pyopencl) (1.14.3)
Collecting pytools>=2017.6 (from pyopencl)
Downloading https://files.pythonhosted.org/packages/00/96/00416762a3eda8876a17d007df4a946f46b2e4ee1057e0b9714926472ef8/pytools-2019.1.1.tar.gz (58kB)
100% |████████████████████████████████| 61kB 16.9MB/s
Collecting appdirs>=1.4.0 (from pyopencl)
Downloading https://files.pythonhosted.org/packages/56/eb/810e700ed1349edde4cbdc1b2a21e28cdf115f9faf263f6bbf8447c1abf3/appdirs-1.4.3-py2.py3-none-any.whl
Requirement already satisfied: six>=1.9.0 in /usr/local/lib/python2.7/dist-packages (from pyopencl) (1.11.0)
Requirement already satisfied: decorator>=3.2.0 in /usr/local/lib/python2.7/dist-packages (from pyopencl) (4.3.0)
Installing collected packages: appdirs, pytools, pyopencl
Running setup.py install for pytools ... done
Successfully installed appdirs-1.4.3 pyopencl-2019.1.2 pytools-2019.1.1
Successfully installed pyopencl
と言われてしまったので、XRT を自分のUbuntu 18.04 にインストールしてみることにする。*** XILINX_XRT variable is not set
CMAバッファー管理とキャッシュ管理
SVMプラットフォーム用のSMMUプログラミング
クライアントプロセスに代わって標準化された計算ユニット実行管理
パーシャルリコンフィギュレーションをサポートするプラットフォーム用のxclbinダウンロード
DMA-BUFを介したバッファーのインポートとエクスポート
計算ユニット完了のための割り込み処理
/* linux */
the_ROM_image:
{
[fsbl_config] a53_x64
[bootloader] <zynqmp_fsbl.elf>
[pmufw_image] <pmufw.elf>
[destination_device=pl] <bitstream>
[destination_cpu=a53-0, exception_level=el-3, trustzone] <bl31.elf>
[destination_cpu=a53-0, exception_level=el-2] <u-boot.elf>
}
#Note: Mention Each package in individual line
#These packages will get added into rootfs menu entry
CONFIG_gpio-demo
CONFIG_peekpoke
CONFIG_xrt
CONFIG_xrt-dev
CONFIG_zocl
CONFIG_opencl-clhpp-dev
CONFIG_opencl-headers-dev
CONFIG_packagegroup-petalinux-opencv
/include/ "system-conf.dtsi"
/ {
xlnk {
compatible = "xlnx,xlnk-1.0";
};
};
&amba {
zyxclmm_drm {
compatible = "xlnx,zocl";
status = "okay";
reg = <0x0 0xA0000000 0x0 0x10000>;
};
};
&sdhci0 {
disable-wp;
};
を追加した。reg = <0x0 0xA0000000 0x0 0x10000>;
set_property platform.design_intent.embedded true [current_project]
set_property platform.design_intent.server_managed false [current_project]
set_property platform.design_intent.external_host false [current_project]
set_property platform.design_intent.datacenter false [current_project]
set_property platform.default_output_type "sd_card" [current_project]
masaaki@masaaki-H110M4-M01:~/Vitis_Work/HLS-Tiny-Tutorials/algorithm_2D_convolution_linebuffer$ vitis_hls -f run_hls.tcl
****** Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2019.2 (64-bit)
**** SW Build 2700185 on Thu Oct 24 18:45:48 MDT 2019
**** IP Build 2699827 on Thu Oct 24 21:16:38 MDT 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
source /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/scripts/vitis_hls/hls.tcl -notrace
INFO: [HLS 200-10] Running '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/bin/unwrapped/lnx64.o/vitis_hls'
INFO: [HLS 200-10] For user 'masaaki' on host 'masaaki-H110M4-M01' (Linux_x86_64 version 4.15.0-66-generic) on Wed Nov 06 20:29:46 JST 2019
INFO: [HLS 200-10] On os Ubuntu 18.04.3 LTS
INFO: [HLS 200-10] In directory '/home/masaaki/Vitis_Work/HLS-Tiny-Tutorials/algorithm_2D_convolution_linebuffer'
WARNING: [HLS 200-40] Environment variable 'C_INCLUDE_PATH' is set to :/usr/local/cuda/include.
Sourcing Tcl script 'run_hls.tcl'
INFO: [HLS 200-10] Creating and opening project '/home/masaaki/Vitis_Work/HLS-Tiny-Tutorials/algorithm_2D_convolution_linebuffer/proj_2D_convolution_with_linebuffer'.
INFO: [HLS 200-10] Adding design file 'convolution.cpp' to the project
INFO: [HLS 200-10] Adding test bench file 'convolution_test.cpp' to the project
INFO: [HLS 200-10] Creating and opening solution '/home/masaaki/Vitis_Work/HLS-Tiny-Tutorials/algorithm_2D_convolution_linebuffer/proj_2D_convolution_with_linebuffer/solution1'.
INFO: [HLS 200-10] Cleaning up the solution database.
INFO: [HLS 200-10] Setting target device to 'xcvu9p-flga2104-2-i'
INFO: [SYN 201-201] Setting up clock 'default' with a period of 6.66ns.
INFO: [SIM 211-2] *************** CSIM start ***************
INFO: [SIM 211-4] CSIM will launch GCC as the compiler.
Compiling ../../../../convolution_test.cpp in debug mode
Compiling ../../../../convolution.cpp in debug mode
Generating csim.exe
*** TEST PASSED ***
INFO: [SIM 211-1] CSim done with 0 errors.
INFO: [SIM 211-3] *************** CSIM finish ***************
INFO: [HLS 200-10] Analyzing design file 'convolution.cpp' ...
WARNING: [HLS 207-1553] '#pragma HLS RESOURCE core=axi' is obsoleted and replaced by '#pragma HLS INTERFACE axi': convolution.cpp:211:9
WARNING: [HLS 207-1553] '#pragma HLS RESOURCE core=axi' is obsoleted and replaced by '#pragma HLS INTERFACE axi': convolution.cpp:213:9
WARNING: [HLS 207-1553] '#pragma HLS RESOURCE core=axi' is obsoleted and replaced by '#pragma HLS INTERFACE axi': convolution.cpp:214:9
WARNING: [HLS 207-1553] '#pragma HLS RESOURCE core=axi' is obsoleted and replaced by '#pragma HLS INTERFACE axi': convolution.cpp:215:9
WARNING: [HLS 207-1553] '#pragma HLS RESOURCE core=axi' is obsoleted and replaced by '#pragma HLS INTERFACE axi': convolution.cpp:216:9
WARNING: [HLS 207-1534] 'region' in '#pragma HLS Inline' is deprecated, and it will be removed in future release: convolution.cpp:218:26
WARNING: [HLS 207-1590] Ignore interface attribute or pragma which is not used in top function: convolution.cpp:210:9
WARNING: [HLS 207-1590] Ignore interface attribute or pragma which is not used in top function: convolution.cpp:210:9
WARNING: [HLS 207-1590] Ignore interface attribute or pragma which is not used in top function: convolution.cpp:212:9
WARNING: [HLS 207-1590] Ignore interface attribute or pragma which is not used in top function: convolution.cpp:212:9
WARNING: [HLS 207-1590] Ignore interface attribute or pragma which is not used in top function: convolution.cpp:212:9
WARNING: [HLS 207-1590] Ignore interface attribute or pragma which is not used in top function: convolution.cpp:210:9
WARNING: [HLS 207-1539] extra token before pragma subject is ignored: convolution.cpp:234:33
WARNING: [HLS 207-1539] extra token before pragma subject is ignored: convolution.cpp:235:33
WARNING: [HLS 207-1534] 'region' in '#pragma HLS Inline' is deprecated, and it will be removed in future release: convolution.cpp:238:26
INFO: [HLS 200-777] Using interface defaults for 'Vivado' target.
INFO: [HLS 214-131] Inlining function 'hls::stream<unsigned int, 0>::read(unsigned int&)' into 'hls::stream<unsigned int, 0>::read()' (/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/common/technology/autopilot/hls_stream_39.h:97:9)
INFO: [HLS 214-131] Inlining function 'hls::stream<unsigned int, 0>::write(unsigned int const&)' into 'hls::stream<unsigned int, 0>::operator<<(unsigned int const&)' (/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/common/technology/autopilot/hls_stream_39.h:76:9)
INFO: [HLS 214-131] Inlining function 'hls::stream<unsigned int, 0>::stream(char const*)' into 'void convolution_strm<unsigned int, 11>(int, int, hls::stream<unsigned int, 0>&, hls::stream<unsigned int, 0>&, unsigned int const*, unsigned int const*)' (convolution.cpp:121:20)
INFO: [HLS 214-131] Inlining function 'hls::stream<unsigned int, 0>::operator<<(unsigned int const&)' into 'void convolution_strm<unsigned int, 11>(int, int, hls::stream<unsigned int, 0>&, hls::stream<unsigned int, 0>&, unsigned int const*, unsigned int const*)' (convolution.cpp:201:17)
INFO: [HLS 214-131] Inlining function 'hls::stream<unsigned int, 0>::read()' into 'void convolution_strm<unsigned int, 11>(int, int, hls::stream<unsigned int, 0>&, hls::stream<unsigned int, 0>&, unsigned int const*, unsigned int const*)' (convolution.cpp:183:36)
INFO: [HLS 214-131] Inlining function 'hls::stream<unsigned int, 0>::operator<<(unsigned int const&)' into 'void convolution_strm<unsigned int, 11>(int, int, hls::stream<unsigned int, 0>&, hls::stream<unsigned int, 0>&, unsigned int const*, unsigned int const*)' (convolution.cpp:170:23)
INFO: [HLS 214-131] Inlining function 'hls::stream<unsigned int, 0>::read()' into 'void convolution_strm<unsigned int, 11>(int, int, hls::stream<unsigned int, 0>&, hls::stream<unsigned int, 0>&, unsigned int const*, unsigned int const*)' (convolution.cpp:160:19)
INFO: [HLS 214-131] Inlining function 'hls::stream<unsigned int, 0>::operator<<(unsigned int const&)' into 'void convolution_strm<unsigned int, 11>(int, int, hls::stream<unsigned int, 0>&, hls::stream<unsigned int, 0>&, unsigned int const*, unsigned int const*)' (convolution.cpp:150:23)
INFO: [HLS 214-131] Inlining function 'hls::stream<unsigned int, 0>::read()' into 'void convolution_strm<unsigned int, 11>(int, int, hls::stream<unsigned int, 0>&, hls::stream<unsigned int, 0>&, unsigned int const*, unsigned int const*)' (convolution.cpp:142:17)
INFO: [HLS 214-131] Inlining function 'hls::stream<unsigned int, 0>::stream(char const*)' into 'void convolution_strm<unsigned int, 11>(int, int, hls::stream<unsigned int, 0>&, hls::stream<unsigned int, 0>&, unsigned int const*, unsigned int const*)' (convolution.cpp:126:20)
INFO: [HLS 214-131] Inlining function 'void convolution_strm<unsigned int, 11>(int, int, hls::stream<unsigned int, 0>&, hls::stream<unsigned int, 0>&, unsigned int const*, unsigned int const*)' into 'filter11x11_strm(int, int, hls::stream<unsigned int, 0>&, hls::stream<unsigned int, 0>&)' (convolution.cpp:244:5)
INFO: [HLS 200-111] Finished Linking Time (s): cpu = 00:00:07 ; elapsed = 00:00:14 . Memory (MB): peak = 933.215 ; gain = 523.031 ; free physical = 853 ; free virtual = 26461
INFO: [HLS 200-111] Finished Checking Pragmas Time (s): cpu = 00:00:07 ; elapsed = 00:00:14 . Memory (MB): peak = 933.215 ; gain = 523.031 ; free physical = 853 ; free virtual = 26461
INFO: [HLS 200-10] Starting code transformations ...
INFO: [HLS 200-111] Finished Standard Transforms Time (s): cpu = 00:00:07 ; elapsed = 00:00:14 . Memory (MB): peak = 933.215 ; gain = 523.031 ; free physical = 842 ; free virtual = 26462
INFO: [HLS 200-10] Checking synthesizability ...
INFO: [HLS 200-111] Finished Checking Synthesizability Time (s): cpu = 00:00:07 ; elapsed = 00:00:14 . Memory (MB): peak = 933.215 ; gain = 523.031 ; free physical = 841 ; free virtual = 26461
INFO: [XFORM 203-502] Unrolling all sub-loops inside loop 'HConvW' (convolution.cpp:140) in function 'filter11x11_strm' for pipelining.
INFO: [XFORM 203-502] Unrolling all sub-loops inside loop 'VConvW' (convolution.cpp:157) in function 'filter11x11_strm' for pipelining.
INFO: [HLS 200-489] Unrolling loop 'HConv' (convolution.cpp:145) in function 'filter11x11_strm' completely with a factor of 11.
INFO: [HLS 200-489] Unrolling loop 'VConv' (convolution.cpp:163) in function 'filter11x11_strm' completely with a factor of 11.
INFO: [XFORM 203-102] Partitioning array 'hwin' (convolution.cpp:120) automatically.
INFO: [XFORM 203-101] Partitioning array 'linebuf' in dimension 1 completely.
INFO: [XFORM 203-721] Changing loop 'Loop_HConvH_proc' (convolution.cpp:139) to a process function for dataflow in function 'filter11x11_strm'.
INFO: [XFORM 203-721] Changing loop 'Loop_VConvH_proc' (convolution.cpp:156) to a process function for dataflow in function 'filter11x11_strm'.
INFO: [XFORM 203-721] Changing loop 'Loop_Border_proc' (convolution.cpp:177) to a process function for dataflow in function 'filter11x11_strm'.
WARNING: [HLS 200-805] An internal stream 'hconv.i1' with default size can result in deadlock. Please consider resizing the stream using the directive 'set_directive_stream' or the 'HLS stream' pragma.
WARNING: [HLS 200-805] An internal stream 'vconv.i2' with default size can result in deadlock. Please consider resizing the stream using the directive 'set_directive_stream' or the 'HLS stream' pragma.
WARNING: [HLS 200-786] Detected dataflow-on-top in function 'filter11x11_strm' with default interface mode 'ap_ctrl_hs'. Overlapped execution of successive kernel calls will not happen unless interface mode 'ap_ctrl_chain' is used (or 'ap_ctrl_none' for a purely data-driven design).
INFO: [XFORM 203-712] Applying dataflow to function 'filter11x11_strm', detected/extracted 5 process function(s):
'filter11x11_strm.entry6'
'Block_.split163_proc'
'Loop_HConvH_proc5'
'Loop_VConvH_proc'
'Loop_Border_proc'.
INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (convolution.cpp:177:35) to (convolution.cpp:176:9) in function 'Loop_Border_proc'... converting 4 basic blocks.
INFO: [XFORM 203-11] Balancing expressions in function 'Loop_VConvH_proc' (convolution.cpp:92:16)...12 expression(s) balanced.
INFO: [XFORM 203-11] Balancing expressions in function 'Loop_HConvH_proc5' (convolution.cpp:92:16)...12 expression(s) balanced.
INFO: [HLS 200-111] Finished Pre-synthesis Time (s): cpu = 00:00:07 ; elapsed = 00:00:14 . Memory (MB): peak = 933.215 ; gain = 523.031 ; free physical = 823 ; free virtual = 26443
INFO: [XFORM 203-541] Flattening a loop nest 'VConvH' (convolution.cpp:156:20) in function 'Loop_VConvH_proc'.
INFO: [XFORM 203-541] Flattening a loop nest 'HConvH' (convolution.cpp:139:20) in function 'Loop_HConvH_proc5'.
INFO: [XFORM 203-541] Flattening a loop nest 'Border' (convolution.cpp:177:35) in function 'Loop_Border_proc'.
WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'linebuf.7'.
WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'linebuf.9'.
WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'linebuf.2'.
WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'linebuf.4'.
WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'linebuf.1'.
WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'linebuf.3'.
WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'linebuf.0'.
WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'linebuf.8'.
WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'linebuf.6'.
WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'linebuf.5'.
INFO: [HLS 200-472] Inferring partial write operation for 'linebuf.0' (convolution.cpp:167:41)
INFO: [HLS 200-472] Inferring partial write operation for 'borderbuf' (convolution.cpp:184:34)
INFO: [HLS 200-111] Finished Architecture Synthesis Time (s): cpu = 00:00:08 ; elapsed = 00:00:15 . Memory (MB): peak = 933.215 ; gain = 523.031 ; free physical = 782 ; free virtual = 26403
INFO: [HLS 200-10] Starting hardware synthesis ...
INFO: [HLS 200-10] Synthesizing 'filter11x11_strm' ...
WARNING: [SYN 201-103] Legalizing function name 'filter11x11_strm.entry6' to 'filter11x11_strm_entry6'.
WARNING: [SYN 201-103] Legalizing function name 'Block_.split163_proc' to 'Block_split163_proc'.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'filter11x11_strm_entry6'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Elapsed time: 14.79 seconds; current allocated memory: 176.923 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Elapsed time: 0.01 seconds; current allocated memory: 177.009 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'Block_split163_proc'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Elapsed time: 0.01 seconds; current allocated memory: 177.080 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Elapsed time: 0 seconds; current allocated memory: 177.165 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'Loop_HConvH_proc5'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-61] Pipelining loop 'HConvH_HConvW'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Elapsed time: 0.07 seconds; current allocated memory: 177.457 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Elapsed time: 0.09 seconds; current allocated memory: 177.785 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'Loop_VConvH_proc'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-61] Pipelining loop 'VConvH_VConvW'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Elapsed time: 0.1 seconds; current allocated memory: 178.117 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Elapsed time: 0.06 seconds; current allocated memory: 178.599 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'Loop_Border_proc'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-61] Pipelining loop 'Border_L'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 5.
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Elapsed time: 0.1 seconds; current allocated memory: 178.915 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Elapsed time: 0.04 seconds; current allocated memory: 179.320 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'filter11x11_strm'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Elapsed time: 0.07 seconds; current allocated memory: 179.495 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Elapsed time: 0.18 seconds; current allocated memory: 179.938 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'filter11x11_strm_entry6'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [RTGEN 206-100] Finished creating RTL model for 'filter11x11_strm_entry6'.
INFO: [HLS 200-111] Elapsed time: 0.13 seconds; current allocated memory: 180.216 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'Block_split163_proc'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [RTGEN 206-100] Generating core module 'filter11x11_strm_add_32ns_32s_32_1_1': 1 instance(s).
INFO: [RTGEN 206-100] Finished creating RTL model for 'Block_split163_proc'.
INFO: [HLS 200-111] Elapsed time: 0.02 seconds; current allocated memory: 180.672 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'Loop_HConvH_proc5'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [RTGEN 206-100] Generating core module 'filter11x11_strm_add_11ns_11ns_11_1_1': 1 instance(s).
INFO: [RTGEN 206-100] Generating core module 'filter11x11_strm_add_32ns_32ns_32_1_1': 2 instance(s).
INFO: [RTGEN 206-100] Generating core module 'filter11x11_strm_add_64ns_64ns_64_1_1': 1 instance(s).
INFO: [RTGEN 206-100] Generating core module 'filter11x11_strm_mul_10ns_32s_32_1_1': 4 instance(s).
INFO: [RTGEN 206-100] Generating core module 'filter11x11_strm_mul_11ns_32s_32_1_1': 3 instance(s).
INFO: [RTGEN 206-100] Generating core module 'filter11x11_strm_mul_32ns_32ns_64_1_1': 1 instance(s).
INFO: [RTGEN 206-100] Generating core module 'filter11x11_strm_mul_8ns_32s_32_1_1': 2 instance(s).
INFO: [RTGEN 206-100] Finished creating RTL model for 'Loop_HConvH_proc5'.
INFO: [HLS 200-111] Elapsed time: 0.04 seconds; current allocated memory: 181.565 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'Loop_VConvH_proc'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [RTGEN 206-100] Generating core module 'filter11x11_strm_add_11ns_11ns_11_1_1': 2 instance(s).
INFO: [RTGEN 206-100] Generating core module 'filter11x11_strm_add_32ns_32ns_32_1_1': 2 instance(s).
INFO: [RTGEN 206-100] Generating core module 'filter11x11_strm_add_64ns_64ns_64_1_1': 1 instance(s).
INFO: [RTGEN 206-100] Generating core module 'filter11x11_strm_mul_10ns_32s_32_1_1': 4 instance(s).
INFO: [RTGEN 206-100] Generating core module 'filter11x11_strm_mul_11ns_32s_32_1_1': 3 instance(s).
INFO: [RTGEN 206-100] Generating core module 'filter11x11_strm_mul_32ns_32ns_64_1_1': 1 instance(s).
INFO: [RTGEN 206-100] Generating core module 'filter11x11_strm_mul_8ns_32s_32_1_1': 2 instance(s).
INFO: [RTGEN 206-100] Finished creating RTL model for 'Loop_VConvH_proc'.
INFO: [HLS 200-111] Elapsed time: 0.17 seconds; current allocated memory: 183.909 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'Loop_Border_proc'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [RTGEN 206-100] Generating core module 'filter11x11_strm_add_11ns_11ns_11_1_1': 2 instance(s).
INFO: [RTGEN 206-100] Generating core module 'filter11x11_strm_add_11ns_11s_11_1_1': 1 instance(s).
INFO: [RTGEN 206-100] Generating core module 'filter11x11_strm_add_32ns_32s_32_1_1': 3 instance(s).
INFO: [RTGEN 206-100] Generating core module 'filter11x11_strm_add_64ns_64ns_64_1_1': 1 instance(s).
INFO: [RTGEN 206-100] Generating core module 'filter11x11_strm_mul_32ns_32ns_64_1_1': 1 instance(s).
INFO: [RTGEN 206-100] Finished creating RTL model for 'Loop_Border_proc'.
INFO: [HLS 200-111] Elapsed time: 0.23 seconds; current allocated memory: 186.334 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'filter11x11_strm'
INFO: [HLS 200-10] ----------------------------------------------------------------
WARNING: [RTGEN 206-101] Design contains AXI ports. Reset is fixed to synchronous and active low.
INFO: [RTGEN 206-500] Setting interface mode on port 'filter11x11_strm/width' to 'ap_none'.
INFO: [RTGEN 206-500] Setting interface mode on port 'filter11x11_strm/height' to 'ap_none'.
INFO: [RTGEN 206-500] Setting interface mode on port 'filter11x11_strm/src_V' to 'axis' (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on port 'filter11x11_strm/dst_V' to 'axis' (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on function 'filter11x11_strm' to 'ap_ctrl_hs'.
INFO: [RTGEN 206-100] Finished creating RTL model for 'filter11x11_strm'.
INFO: [HLS 200-111] Elapsed time: 0.19 seconds; current allocated memory: 188.429 MB.
INFO: [RTMG 210-282] Generating pipelined core: 'filter11x11_strm_filter11x11_strm_mul_32ns_32ns_64_1_1_Multiplier_0'
INFO: [RTMG 210-282] Generating pipelined core: 'filter11x11_strm_filter11x11_strm_mul_8ns_32s_32_1_1_Multiplier_1'
INFO: [RTMG 210-282] Generating pipelined core: 'filter11x11_strm_filter11x11_strm_mul_10ns_32s_32_1_1_Multiplier_2'
INFO: [RTMG 210-282] Generating pipelined core: 'filter11x11_strm_filter11x11_strm_mul_11ns_32s_32_1_1_Multiplier_3'
INFO: [RTMG 210-278] Implementing memory 'filter11x11_strm_Loop_VConvH_proc_linebuf_0_ram (RAM)' using block RAMs with power-on initialization.
INFO: [RTMG 210-278] Implementing memory 'filter11x11_strm_Loop_VConvH_proc_linebuf_1_ram (RAM)' using block RAMs with power-on initialization.
INFO: [RTMG 210-278] Implementing memory 'filter11x11_strm_Loop_Border_proc_borderbuf_ram (RAM)' using block RAMs.
INFO: [RTMG 210-285] Implementing FIFO 'width_c_U(filter11x11_strm_fifo_w32_d2_A)' using Shift Registers.
INFO: [RTMG 210-285] Implementing FIFO 'width_c176_U(filter11x11_strm_fifo_w32_d2_A)' using Shift Registers.
INFO: [RTMG 210-285] Implementing FIFO 'height_c_U(filter11x11_strm_fifo_w32_d2_A)' using Shift Registers.
INFO: [RTMG 210-285] Implementing FIFO 'height_c177_U(filter11x11_strm_fifo_w32_d2_A)' using Shift Registers.
INFO: [RTMG 210-285] Implementing FIFO 'width_c178_U(filter11x11_strm_fifo_w32_d3_A)' using Shift Registers.
INFO: [RTMG 210-285] Implementing FIFO 'height_c179_U(filter11x11_strm_fifo_w32_d2_A)' using Shift Registers.
INFO: [RTMG 210-285] Implementing FIFO 'vconv_xlim_loc_c_U(filter11x11_strm_fifo_w32_d2_A)' using Shift Registers.
INFO: [RTMG 210-285] Implementing FIFO 'hconv_i1_U(filter11x11_strm_fifo_w32_d2_A)' using Shift Registers.
INFO: [RTMG 210-285] Implementing FIFO 'vconv_i2_U(filter11x11_strm_fifo_w32_d2_A)' using Shift Registers.
INFO: [RTMG 210-285] Implementing FIFO 'height_c180_U(filter11x11_strm_fifo_w32_d2_A)' using Shift Registers.
INFO: [RTMG 210-285] Implementing FIFO 'vconv_xlim_loc_c181_U(filter11x11_strm_fifo_w32_d2_A)' using Shift Registers.
INFO: [RTMG 210-285] Implementing FIFO 'start_for_Block_split163_proc_U0_U(filter11x11_strm_start_for_Block_split163_proc_U0)' using Shift Registers.
INFO: [RTMG 210-285] Implementing FIFO 'start_for_Loop_Border_proc_U0_U(filter11x11_strm_start_for_Loop_Border_proc_U0)' using Shift Registers.
INFO: [RTMG 210-285] Implementing FIFO 'start_for_Loop_VConvH_proc_U0_U(filter11x11_strm_start_for_Loop_VConvH_proc_U0)' using Shift Registers.
INFO: [HLS 200-111] Finished generating all RTL models Time (s): cpu = 00:00:10 ; elapsed = 00:00:18 . Memory (MB): peak = 933.215 ; gain = 523.031 ; free physical = 749 ; free virtual = 26381
INFO: [VHDL 208-304] Generating VHDL RTL for filter11x11_strm with prefix filter11x11_strm_.
INFO: [VLOG 209-307] Generating Verilog RTL for filter11x11_strm with prefix filter11x11_strm_.
INFO: [HLS 200-790] **** Loop Constraint Status: All loop constraints were satisfied.
INFO: [HLS 200-789] **** Estimated Fmax: 215.89 MHz
INFO: [HLS 200-112] Total elapsed time: 18.13 seconds; peak allocated memory: 188.429 MB.
INFO: [Common 17-206] Exiting vitis_hls at Wed Nov 6 20:30:04 2019...
// LED_test.c
// 2019/11/04 by marsee
//
#include <stdint.h>
#include <unistd.h>
#include "xparameters.h"
int main(){
volatile uint32_t *axi_gpio_data = (uint32_t *)XPAR_AXI_GPIO_0_BASEADDR;
volatile uint32_t *axi_gpio_tri = (uint32_t *)(XPAR_AXI_GPIO_0_BASEADDR+4);
int i, j;
*axi_gpio_tri = 0; // Set All Output
for(j=0; j<5; j++){
for(i=0; i<16; i++){
*axi_gpio_data = i;
printf("j = %d, i = %d\n",j, i);
usleep(500000); // 0.5sec sleep
}
}
return(0);
}
./sdx_app1_linux.elf: error while loading shared libraries: libsds_lib.so: cannot open shared object file: No such file or directory
root@Ultra96V2_Platform1:/run/media/mmcblk0p1# ./sdx_app1_linux.elf
[ 39.417553] xlnk_eng_probe ...
[ 39.420621] uio name xilinx-xlnk-eng.0
[ 39.424396] xilinx-xlnk-eng xilinx-xlnk-eng.0: physical base : 0xa0000000
[ 39.431181] xilinx-xlnk-eng xilinx-xlnk-eng.0: register range : 0x10000
[ 39.437789] xilinx-xlnk-eng xilinx-xlnk-eng.0: base remapped to: 0xffffff800ca10000
[ 39.445602] xilinx-xlnk-eng xilinx-xlnk-eng.0: xilinx-xlnk-eng uio registered
Xilinx Zynq MP First Stage Boot Loader
Release 2019.1 Oct 25 2019 - 19:37:23
NOTICE: ATF running on XCZU3EG/silicon v4/RTL5.1 at 0xfffea000
NOTICE: BL31: Secure code at 0x0
NOTICE: BL31: Non secure code at 0x8000000
NOTICE: BL31: v2.0(release):xilinx-v2018.3-720-g80d1c790
NOTICE: BL31: Built : 19:37:05, Oct 25 2019
PMUFW: v1.1
U-Boot 2019.01 (Oct 25 2019 - 19:36:32 +0000)
Board: Xilinx ZynqMP
DRAM: 2 GiB
usb dr_mode not found
usb dr_mode not found
EL Level: EL2
Chip ID: zu3eg
MMC: mmc@ff160000: 0, mmc@ff170000: 1
Loading Environment from FAT... *** Warning - bad CRC, using default environment
In: serial@ff010000
Out: serial@ff010000
Err: serial@ff010000
Board: Xilinx ZynqMP
Bootmode: SD_MODE
Reset reason: EXTERNAL
U-BOOT for Ultra96V2_Platform1
Hit any key to stop autoboot: 0
Device: mmc@ff160000
Manufacturer ID: 74
OEM: 4a60
Name: USD
Bus Speed: 50000000
Mode : SD High Speed (50MHz)
Rd Block Len: 512
SD version 3.0
High Capacity: Yes
Capacity: 7.5 GiB
Bus Width: 4-bit
Erase Group Size: 512 Bytes
18114644 bytes read in 1294 ms (13.3 MiB/s)
## Loading kernel from FIT Image at 10000000 ...
Using 'conf@system-top.dtb' configuration
Trying 'kernel@1' kernel subimage
Description: Linux kernel
Type: Kernel Image
Compression: uncompressed
Data Start: 0x10000104
Data Size: 18082304 Bytes = 17.2 MiB
Architecture: AArch64
OS: Linux
Load Address: 0x00080000
Entry Point: 0x00080000
Hash algo: sha1
Hash value: 617dc56366cbe452dc0d885fdf95b6b2b02c9cc3
Verifying Hash Integrity ... sha1+ OK
## Loading fdt from FIT Image at 10000000 ...
Using 'conf@system-top.dtb' configuration
Trying 'fdt@system-top.dtb' fdt subimage
Description: Flattened Device Tree blob
Type: Flat Device Tree
Compression: uncompressed
Data Start: 0x1113ec08
Data Size: 30421 Bytes = 29.7 KiB
Architecture: AArch64
Hash algo: sha1
Hash value: 1451d63dc05df23a47fb8619d525e564a5ee7bc5
Verifying Hash Integrity ... sha1+ OK
Booting using the fdt blob at 0x1113ec08
Loading Kernel Image ... OK
Loading Device Tree to 0000000007ff5000, end 0000000007fff6d4 ... OK
Starting kernel ...
[ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
[ 0.000000] Linux version 4.19.0-xilinx-v2019.1 (oe-user@oe-host) (gcc version 8.2.0 (GCC)) #1 SMP Fri Oct 25 19:26:41 UTC 2019
[ 0.000000] Machine model: xlnx,zynqmp
[ 0.000000] earlycon: cdns0 at MMIO 0x00000000ff010000 (options '115200n8')
[ 0.000000] bootconsole [cdns0] enabled
[ 0.000000] efi: Getting EFI parameters from FDT:
[ 0.000000] efi: UEFI not found.
[ 0.000000] cma: Reserved 1024 MiB at 0x000000003fc00000
[ 0.000000] psci: probing for conduit method from DT.
[ 0.000000] psci: PSCIv1.1 detected in firmware.
[ 0.000000] psci: Using standard PSCI v0.2 function IDs
[ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
[ 0.000000] psci: SMC Calling Convention v1.1
[ 0.000000] random: get_random_bytes called from start_kernel+0x94/0x3f8 with crng_init=0
[ 0.000000] percpu: Embedded 22 pages/cpu @(____ptrval____) s52568 r8192 d29352 u90112
[ 0.000000] Detected VIPT I-cache on CPU0
[ 0.000000] CPU features: enabling workaround for ARM erratum 845719
[ 0.000000] Speculative Store Bypass Disable mitigation not required
[ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 516867
[ 0.000000] Kernel command line: earlycon console=ttyPS0,115200 clk_ignore_unused root=/dev/mmcblk0p2 rw rootwait
[ 0.000000] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes)
[ 0.000000] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes)
[ 0.000000] Memory: 997044K/2096128K available (10748K kernel code, 634K rwdata, 5408K rodata, 832K init, 509K bss, 50508K reserved, 1048576K cma-reserved)
[ 0.000000] rcu: Hierarchical RCU implementation.
[ 0.000000] rcu: RCU event tracing is enabled.
[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
[ 0.000000] GIC: Adjusting CPU interface base to 0x00000000f902f000
[ 0.000000] GIC: Using split EOI/Deactivate mode
[ 0.000000] arch_timer: cp15 timer(s) running at 100.00MHz (phys).
[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x171024e7e0, max_idle_ns: 440795205315 ns
[ 0.000004] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 4398046511100ns
[ 0.008329] Console: colour dummy device 80x25
[ 0.012482] Calibrating delay loop (skipped), value calculated using timer frequency.. 200.00 BogoMIPS (lpj=400000)
[ 0.022839] pid_max: default: 32768 minimum: 301
[ 0.027548] Mount-cache hash table entries: 4096 (order: 3, 32768 bytes)
[ 0.034093] Mountpoint-cache hash table entries: 4096 (order: 3, 32768 bytes)
[ 0.042085] ASID allocator initialised with 32768 entries
[ 0.046597] rcu: Hierarchical SRCU implementation.
[ 0.051584] EFI services will not be available.
[ 0.055933] smp: Bringing up secondary CPUs ...
[ 0.060614] Detected VIPT I-cache on CPU1
[ 0.060653] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
[ 0.061001] Detected VIPT I-cache on CPU2
[ 0.061021] CPU2: Booted secondary processor 0x0000000002 [0x410fd034]
[ 0.061335] Detected VIPT I-cache on CPU3
[ 0.061355] CPU3: Booted secondary processor 0x0000000003 [0x410fd034]
[ 0.061400] smp: Brought up 1 node, 4 CPUs
[ 0.095756] SMP: Total of 4 processors activated.
[ 0.100430] CPU features: detected: 32-bit EL0 Support
[ 0.108148] CPU: All CPU(s) started at EL2
[ 0.109610] alternatives: patching kernel code
[ 0.115342] devtmpfs: initialized
[ 0.120903] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
[ 0.126999] futex hash table entries: 1024 (order: 4, 65536 bytes)
[ 0.158338] xor: measuring software checksum speed
[ 0.197360] 8regs : 2375.000 MB/sec
[ 0.237387] 8regs_prefetch: 2052.000 MB/sec
[ 0.277416] 32regs : 2725.000 MB/sec
[ 0.317448] 32regs_prefetch: 2309.000 MB/sec
[ 0.317479] xor: using function: 32regs (2725.000 MB/sec)
[ 0.321800] pinctrl core: initialized pinctrl subsystem
[ 0.327841] NET: Registered protocol family 16
[ 0.331768] audit: initializing netlink subsys (disabled)
[ 0.336862] audit: type=2000 audit(0.284:1): state=initialized audit_enabled=0 res=1
[ 0.344455] vdso: 2 pages (1 code @ (____ptrval____), 1 data @ (____ptrval____))
[ 0.344463] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
[ 0.359472] DMA: preallocated 256 KiB pool for atomic allocations
[ 0.380195] HugeTLB registered 2.00 MiB page size, pre-allocated 0 pages
[ 0.447232] raid6: int64x1 gen() 445 MB/s
[ 0.515188] raid6: int64x1 xor() 453 MB/s
[ 0.583323] raid6: int64x2 gen() 681 MB/s
[ 0.651291] raid6: int64x2 xor() 600 MB/s
[ 0.719364] raid6: int64x4 gen() 981 MB/s
[ 0.787361] raid6: int64x4 xor() 737 MB/s
[ 0.855420] raid6: int64x8 gen() 1163 MB/s
[ 0.923463] raid6: int64x8 xor() 759 MB/s
[ 0.991569] raid6: neonx1 gen() 736 MB/s
[ 1.059546] raid6: neonx1 xor() 880 MB/s
[ 1.127588] raid6: neonx2 gen() 1127 MB/s
[ 1.195658] raid6: neonx2 xor() 1174 MB/s
[ 1.263695] raid6: neonx4 gen() 1482 MB/s
[ 1.331742] raid6: neonx4 xor() 1418 MB/s
[ 1.399786] raid6: neonx8 gen() 1540 MB/s
[ 1.467816] raid6: neonx8 xor() 1459 MB/s
[ 1.467846] raid6: using algorithm neonx8 gen() 1540 MB/s
[ 1.471807] raid6: .... xor() 1459 MB/s, rmw enabled
[ 1.476738] raid6: using neon recovery algorithm
[ 1.482300] SCSI subsystem initialized
[ 1.485282] usbcore: registered new interface driver usbfs
[ 1.490526] usbcore: registered new interface driver hub
[ 1.495807] usbcore: registered new device driver usb
[ 1.500864] media: Linux media interface: v0.10
[ 1.505308] videodev: Linux video capture interface: v2.00
[ 1.510759] pps_core: LinuxPPS API ver. 1 registered
[ 1.515663] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[ 1.524757] PTP clock support registered
[ 1.528658] EDAC MC: Ver: 3.0.0
[ 1.532266] zynqmp-ipi-mbox mailbox@ff990400: Probed ZynqMP IPI Mailbox driver.
[ 1.539374] FPGA manager framework
[ 1.542585] Advanced Linux Sound Architecture Driver Initialized.
[ 1.548806] Bluetooth: Core ver 2.22
[ 1.552013] NET: Registered protocol family 31
[ 1.556405] Bluetooth: HCI device and connection manager initialized
[ 1.562723] Bluetooth: HCI socket layer initialized
[ 1.567565] Bluetooth: L2CAP socket layer initialized
[ 1.572601] Bluetooth: SCO socket layer initialized
[ 1.577901] clocksource: Switched to clocksource arch_sys_counter
[ 1.583741] VFS: Disk quotas dquot_6.6.0
[ 1.587424] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
[ 1.599633] NET: Registered protocol family 2
[ 1.600103] tcp_listen_portaddr_hash hash table entries: 1024 (order: 2, 16384 bytes)
[ 1.606426] TCP established hash table entries: 16384 (order: 5, 131072 bytes)
[ 1.613600] TCP bind hash table entries: 16384 (order: 6, 262144 bytes)
[ 1.620414] TCP: Hash tables configured (established 16384 bind 16384)
[ 1.626654] UDP hash table entries: 1024 (order: 3, 32768 bytes)
[ 1.632564] UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes)
[ 1.639068] NET: Registered protocol family 1
[ 1.643538] RPC: Registered named UNIX socket transport module.
[ 1.649139] RPC: Registered udp transport module.
[ 1.653815] RPC: Registered tcp transport module.
[ 1.658477] RPC: Registered tcp NFSv4.1 backchannel transport module.
[ 1.665787] hw perfevents: no interrupt-affinity property for /pmu, guessing.
[ 1.672141] hw perfevents: enabled with armv8_pmuv3 PMU driver, 7 counters available
[ 1.680699] Initialise system trusted keyrings
[ 1.684157] workingset: timestamp_bits=62 max_order=19 bucket_order=0
[ 1.691298] NFS: Registering the id_resolver key type
[ 1.695514] Key type id_resolver registered
[ 1.699650] Key type id_legacy registered
[ 1.703636] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
[ 1.710305] jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
[ 2.798226] NET: Registered protocol family 38
[ 2.857391] Key type asymmetric registered
[ 2.857422] Asymmetric key parser 'x509' registered
[ 2.860742] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 247)
[ 2.868056] io scheduler noop registered
[ 2.871942] io scheduler deadline registered
[ 2.876205] io scheduler cfq registered (default)
[ 2.880853] io scheduler mq-deadline registered
[ 2.885349] io scheduler kyber registered
[ 2.920834] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[ 2.925295] cacheinfo: Unable to detect cache hierarchy for CPU 0
[ 2.933097] brd: module loaded
[ 2.938205] loop: module loaded
[ 2.939275] mtdoops: mtd device (mtddev=name/number) must be supplied
[ 2.943776] libphy: Fixed MDIO Bus: probed
[ 2.947600] tun: Universal TUN/TAP device driver, 1.6
[ 2.951393] CAN device driver interface
[ 2.956083] usbcore: registered new interface driver asix
[ 2.960428] usbcore: registered new interface driver ax88179_178a
[ 2.966460] usbcore: registered new interface driver cdc_ether
[ 2.972254] usbcore: registered new interface driver net1080
[ 2.977881] usbcore: registered new interface driver cdc_subset
[ 2.983758] usbcore: registered new interface driver zaurus
[ 2.989303] usbcore: registered new interface driver cdc_ncm
[ 2.995504] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[ 3.001381] ehci-pci: EHCI PCI platform driver
[ 3.006106] usbcore: registered new interface driver uas
[ 3.011103] usbcore: registered new interface driver usb-storage
[ 3.017684] rtc_zynqmp ffa60000.rtc: rtc core: registered ffa60000.rtc as rtc0
[ 3.024280] i2c /dev entries driver
[ 3.029330] usbcore: registered new interface driver uvcvideo
[ 3.033385] USB Video Class driver (1.1.1)
[ 3.038084] Bluetooth: HCI UART driver ver 2.3
[ 3.041858] Bluetooth: HCI UART protocol H4 registered
[ 3.046968] Bluetooth: HCI UART protocol BCSP registered
[ 3.052266] Bluetooth: HCI UART protocol LL registered
[ 3.057347] Bluetooth: HCI UART protocol ATH3K registered
[ 3.062727] Bluetooth: HCI UART protocol Three-wire (H5) registered
[ 3.068982] Bluetooth: HCI UART protocol Intel registered
[ 3.074318] Bluetooth: HCI UART protocol QCA registered
[ 3.079526] usbcore: registered new interface driver bcm203x
[ 3.085143] usbcore: registered new interface driver bpa10x
[ 3.090678] usbcore: registered new interface driver bfusb
[ 3.096125] usbcore: registered new interface driver btusb
[ 3.101546] Bluetooth: Generic Bluetooth SDIO driver ver 0.1
[ 3.107226] usbcore: registered new interface driver ath3k
[ 3.112765] EDAC MC: ECC not enabled
[ 3.116310] EDAC DEVICE0: Giving out device to module edac controller cache_err: DEV edac (POLLED)
[ 3.125261] EDAC DEVICE1: Giving out device to module zynqmp-ocm-edac controller zynqmp_ocm: DEV ff960000.memory-controller (INTERRUPT)
[ 3.137472] sdhci: Secure Digital Host Controller Interface driver
[ 3.143326] sdhci: Copyright(c) Pierre Ossman
[ 3.147649] sdhci-pltfm: SDHCI platform and OF driver helper
[ 3.153624] ledtrig-cpu: registered to indicate activity on CPUs
[ 3.159291] zynqmp_firmware_probe Platform Management API v1.1
[ 3.165040] zynqmp_firmware_probe Trustzone version v1.0
[ 3.193125] zynqmp_clk_mux_get_parent() getparent failed for clock: lpd_wdt, ret = -22
[ 3.195888] alg: No test for xilinx-zynqmp-aes (zynqmp-aes)
[ 3.200946] zynqmp_aes zynqmp_aes: AES Successfully Registered
[ 3.200946]
[ 3.208475] alg: No test for xilinx-keccak-384 (zynqmp-keccak-384)
[ 3.214597] alg: No test for xilinx-zynqmp-rsa (zynqmp-rsa)
[ 3.220336] usbcore: registered new interface driver usbhid
[ 3.225495] usbhid: USB HID core driver
[ 3.229462] xlnk xlnk: Major 243
[ 3.232622] xlnk xlnk: xlnk driver loaded
[ 3.236480] xlnk xlnk: xlnk_pdev is not null
[ 3.243188] fpga_manager fpga0: Xilinx ZynqMP FPGA Manager registered
[ 3.247536] usbcore: registered new interface driver snd-usb-audio
[ 3.254243] pktgen: Packet Generator for packet performance testing. Version: 2.75
[ 3.261241] Initializing XFRM netlink socket
[ 3.265126] NET: Registered protocol family 10
[ 3.269895] Segment Routing with IPv6
[ 3.273175] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
[ 3.279358] NET: Registered protocol family 17
[ 3.283375] NET: Registered protocol family 15
[ 3.287789] bridge: filtering via arp/ip/ip6tables is no longer available by default. Update your scripts to load br_netfilter if you need this.
[ 3.300718] can: controller area network core (rev 20170425 abi 9)
[ 3.306841] NET: Registered protocol family 29
[ 3.311216] can: raw protocol (rev 20170425)
[ 3.315452] can: broadcast manager protocol (rev 20170425 t)
[ 3.321077] can: netlink gateway (rev 20170425) max_hops=1
[ 3.326894] Bluetooth: RFCOMM TTY layer initialized
[ 3.331377] Bluetooth: RFCOMM socket layer initialized
[ 3.336490] Bluetooth: RFCOMM ver 1.11
[ 3.340196] Bluetooth: BNEP (Ethernet Emulation) ver 1.3
[ 3.345468] Bluetooth: BNEP filters: protocol multicast
[ 3.350661] Bluetooth: BNEP socket layer initialized
[ 3.355588] Bluetooth: HIDP (Human Interface Emulation) ver 1.2
[ 3.361473] Bluetooth: HIDP socket layer initialized
[ 3.366552] 9pnet: Installing 9P2000 support
[ 3.370665] Key type dns_resolver registered
[ 3.375401] registered taskstats version 1
[ 3.378950] Loading compiled-in X.509 certificates
[ 3.384104] Btrfs loaded, crc32c=crc32c-generic
[ 3.395800] ff000000.serial: ttyPS1 at MMIO 0xff000000 (irq = 40, base_baud = 6249999) is a xuartps
� 3.399783] f�&�SӦ��i��k��+W/�*LW�Y�X��edff010000 (irq = 41, base_baud = 6249999) is a xuartps
[ 3.413742] console [ttyPS0] enabled
[ 3.417333] bootconsole [cdns0] disabled
[ 3.417333] bootconsole [cdns0] disabled
[ 3.425499] of-fpga-region fpga-full: FPGA Region probed
[ 3.435005] xilinx-dpdma fd4c0000.dma: Xilinx DPDMA engine is probed
[ 3.441623] xilinx-zynqmp-dma fd500000.dma: ZynqMP DMA driver Probe success
[ 3.448748] xilinx-zynqmp-dma fd510000.dma: ZynqMP DMA driver Probe success
[ 3.455864] xilinx-zynqmp-dma fd520000.dma: ZynqMP DMA driver Probe success
[ 3.462972] xilinx-zynqmp-dma fd530000.dma: ZynqMP DMA driver Probe success
[ 3.470086] xilinx-zynqmp-dma fd540000.dma: ZynqMP DMA driver Probe success
[ 3.477203] xilinx-zynqmp-dma fd550000.dma: ZynqMP DMA driver Probe success
[ 3.484324] xilinx-zynqmp-dma fd560000.dma: ZynqMP DMA driver Probe success
[ 3.491437] xilinx-zynqmp-dma fd570000.dma: ZynqMP DMA driver Probe success
[ 3.498634] xilinx-zynqmp-dma ffa80000.dma: ZynqMP DMA driver Probe success
[ 3.505750] xilinx-zynqmp-dma ffa90000.dma: ZynqMP DMA driver Probe success
[ 3.512869] xilinx-zynqmp-dma ffaa0000.dma: ZynqMP DMA driver Probe success
[ 3.519983] xilinx-zynqmp-dma ffab0000.dma: ZynqMP DMA driver Probe success
[ 3.527099] xilinx-zynqmp-dma ffac0000.dma: ZynqMP DMA driver Probe success
[ 3.534216] xilinx-zynqmp-dma ffad0000.dma: ZynqMP DMA driver Probe success
[ 3.541329] xilinx-zynqmp-dma ffae0000.dma: ZynqMP DMA driver Probe success
[ 3.548451] xilinx-zynqmp-dma ffaf0000.dma: ZynqMP DMA driver Probe success
[ 3.555817] xilinx-psgtr fd400000.zynqmp_phy: Lane:1 type:8 protocol:4 pll_locked:yes
[ 3.566093] xilinx-dp-snd-codec fd4a0000.zynqmp-display:zynqmp_dp_snd_codec0: Xilinx DisplayPort Sound Codec probed
[ 3.576833] xilinx-dp-snd-pcm zynqmp_dp_snd_pcm0: Xilinx DisplayPort Sound PCM probed
[ 3.584893] xilinx-dp-snd-pcm zynqmp_dp_snd_pcm1: Xilinx DisplayPort Sound PCM probed
[ 3.593772] xilinx-dp-snd-card fd4a0000.zynqmp-display:zynqmp_dp_snd_card: xilinx-dp-snd-codec-dai <-> xilinx-dp-snd-codec-dai mapping ok
[ 3.606234] xilinx-dp-snd-card fd4a0000.zynqmp-display:zynqmp_dp_snd_card: xilinx-dp-snd-codec-dai <-> xilinx-dp-snd-codec-dai mapping ok
[ 3.619004] xilinx-dp-snd-card fd4a0000.zynqmp-display:zynqmp_dp_snd_card: Xilinx DisplayPort Sound Card probed
[ 3.629227] OF: graph: no port node found in /amba/zynqmp-display@fd4a0000
[ 3.636307] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[ 3.642918] [drm] No driver support for vblank timestamp query.
[ 3.648912] xlnx-drm xlnx-drm.0: bound fd4a0000.zynqmp-display (ops 0xffffff8008bbf5e0)
[ 4.733887] [drm] Cannot find any crtc or sizes
[ 4.738697] [drm] Initialized xlnx 1.0.0 20130509 for fd4a0000.zynqmp-display on minor 0
[ 4.746800] zynqmp-display fd4a0000.zynqmp-display: ZynqMP DisplayPort Subsystem driver probed
[ 4.756817] xilinx-axipmon ffa00000.perf-monitor: Probed Xilinx APM
[ 4.763368] xilinx-axipmon fd0b0000.perf-monitor: Probed Xilinx APM
[ 4.769883] xilinx-axipmon fd490000.perf-monitor: Probed Xilinx APM
[ 4.776388] xilinx-axipmon ffa10000.perf-monitor: Probed Xilinx APM
[ 4.782905] dwc3-of-simple ff9d0000.usb0: dwc3_simple_set_phydata: Can't find usb3-phy
[ 4.791249] dwc3 fe200000.dwc3: Failed to get clk 'ref': -2
[ 4.797546] dwc3-of-simple ff9e0000.usb1: dwc3_simple_set_phydata: Can't find usb3-phy
[ 4.805867] dwc3 fe300000.dwc3: Failed to get clk 'ref': -2
[ 4.812649] cdns-i2c ff030000.i2c: 400 kHz mmio ff030000 irq 30
[ 4.818952] cdns-wdt fd4d0000.watchdog: Xilinx Watchdog Timer at (____ptrval____) with timeout 60s
[ 4.828154] cdns-wdt ff150000.watchdog: Xilinx Watchdog Timer at (____ptrval____) with timeout 10s
[ 4.837817] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
[ 4.843318] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1
[ 4.852304] xhci-hcd xhci-hcd.0.auto: hcc params 0x0238f625 hci version 0x100 quirks 0x0000000202010010
[ 4.861722] xhci-hcd xhci-hcd.0.auto: irq 50, io mem 0xfe300000
[ 4.867902] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 4.19
[ 4.876166] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[ 4.883386] usb usb1: Product: xHCI Host Controller
[ 4.888261] usb usb1: Manufacturer: Linux 4.19.0-xilinx-v2019.1 xhci-hcd
[ 4.894953] usb usb1: SerialNumber: xhci-hcd.0.auto
[ 4.900225] hub 1-0:1.0: USB hub found
[ 4.904000] hub 1-0:1.0: 1 port detected
[ 4.908128] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
[ 4.913619] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2
[ 4.921283] xhci-hcd xhci-hcd.0.auto: Host supports USB 3.0 SuperSpeed
[ 4.927911] mmc0: SDHCI controller on ff160000.mmc [ff160000.mmc] using ADMA 64-bit
[ 4.935739] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
[ 4.944622] usb usb2: New USB device found, idVendor=1d6b, idProduct=0003, bcdDevice= 4.19
[ 4.952880] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[ 4.960097] usb usb2: Product: xHCI Host Controller
[ 4.964966] usb usb2: Manufacturer: Linux 4.19.0-xilinx-v2019.1 xhci-hcd
[ 4.971657] usb usb2: SerialNumber: xhci-hcd.0.auto
[ 4.976826] hub 2-0:1.0: USB hub found
[ 4.980594] hub 2-0:1.0: 1 port detected
[ 5.015864] mmc1: SDHCI controller on ff170000.mmc [ff170000.mmc] using ADMA 64-bit
[ 5.026361] mmc0: new high speed SDHC card at address 59b4
[ 5.032525] mmcblk0: mmc0:59b4 USD 7.51 GiB
[ 5.040402] rtc_zynqmp ffa60000.rtc: setting system clock to 1970-01-01 00:00:08 UTC (8)
[ 5.048496] of_cfs_init
[ 5.050958] of_cfs_init: OK
[ 5.053880] cfg80211: Loading compiled-in X.509 certificates for regulatory database
[ 5.062622] mmcblk0: p1 p2
[ 5.079746] mmc1: new high speed SDIO card at address 0001
[ 5.193537] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
[ 5.200065] clk: Not disabling unused clocks
[ 5.204333] ALSA device list:
[ 5.207293] #0: DisplayPort monitor
[ 5.211341] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
[ 5.219947] cfg80211: failed to load regulatory.db
[ 5.241886] usb 1-1: new high-speed USB device number 2 using xhci-hcd
[ 5.305810] EXT4-fs (mmcblk0p2): mounted filesystem with ordered data mode. Opts: (null)
[ 5.313919] VFS: Mounted root (ext4 filesystem) on device 179:2.
[ 5.320667] devtmpfs: mounted
[ 5.323922] Freeing unused kernel memory: 832K
[ 5.328405] Run /sbin/init as init process
[ 5.394378] usb 1-1: New USB device found, idVendor=0424, idProduct=2744, bcdDevice= 2.05
[ 5.402551] usb 1-1: New USB device strings: Mfr=1, Product=2, SerialNumber=0
[ 5.409685] usb 1-1: Product: USB2744
[ 5.413348] usb 1-1: Manufacturer: Microchip Tech
INIT: version 2.88 booting
[ 5.472153] hub 1-1:1.0: USB hub found
[ 5.475951] hub 1-1:1.0: 4 ports detected
[ 5.497252] random: fast init done
Starting udev
[ 5.773006] udevd[1787]: starting version 3.2.5
[ 5.784925] random: udevd: uninitialized urandom read (16 bytes read)
[ 5.792313] random: udevd: uninitialized urandom read (16 bytes read)
[ 5.799678] random: udevd: uninitialized urandom read (16 bytes read)
[ 5.821890] usb 1-1.4: new high-speed USB device number 3 using xhci-hcd
[ 5.836892] udevd[1788]: starting eudev-3.2.5
[ 5.841911] [drm] Cannot find any crtc or sizes
[ 5.926850] usb 1-1.4: New USB device found, idVendor=0424, idProduct=2740, bcdDevice= 2.00
[ 5.935253] usb 1-1.4: New USB device strings: Mfr=1, Product=2, SerialNumber=0
[ 5.942587] usb 1-1.4: Product: Hub Controller
[ 5.947040] usb 1-1.4: Manufacturer: Microchip Tech
[ 6.391079] FAT-fs (mmcblk0p1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck.
[ 6.433779] EXT4-fs (mmcblk0p2): re-mounted. Opts: (null)
Tue Oct 29 09:06:00 UTC 2019
[ 7.538612] urandom_read: 4 callbacks suppressed
[ 7.538619] random: dd: uninitialized urandom read (512 bytes read)
Configuring packages on first boot....
(This may take several minutes. Please do not power off the machine.)
Running postinst /etc/rpm-postinsts/100-sysvinit-inittab...
update-rc.d: /etc/init.d/run-postinsts exists during rc.d purge (continuing)
Removing any system startup links for run-postinsts ...
/etc/rcS.d/S99run-postinsts
INIT: Entering runlevel: 5
Configuring network interfaces... Cannot find device "eth0"
Starting Dropbear SSH server: [ 7.843872] random: dropbearkey: uninitialized urandom read (32 bytes read)
[ 7.853271] random: dropbearkey: uninitialized urandom read (32 bytes read)
Generating 2048 bit rsa key, this may take a while...
Public key portion is:
ssh-rsa AAAAB3NzaC1yc2EAAAADAQABAAABAQDOI8wj8a6wf7zlg6r5HdDA+z2+FS5KUACaws8skcUWLkM1yVLfnLwvGgYwUaC+Z18s6MZrdSzbitO9GfJD4v6HLRGeifmG7+hA5QnQwmJoHxjBEH9KW7xF6mDpor/eNxld3+uWiX1UJAiVsUQKd3sMJSzPmQtpUDj4iJYxd8SEEbG3QKb3opD9xqoOSqIqWmQgIyi06sW9U9+vkFLF3IuzA+EYOpGt3g9BnJopA4pv8tBVd2p0O0GaOyDthGsdHaA2F3D8kgaCoidycq6Oim9F+grW3fiSZCn9JNAijZ7bt8NE7yCIoEN4S4eQMAzjOkV0FGFxc6Vl2Y6kRCUBZvq9 root@Ultra96V2_Platform1
Fingerprint: sha1!! b6:b3:5e:42:a5:d3:4e:c0:46:b4:bf:05:07:70:2f:24:1e:94:83:82
dropbear.
Starting internet superserver: inetd.
Starting syslogd/klogd: done
Starting tcf-agent: OK
/bin/autologin: line 1: -e: command not found
root@Ultra96V2_Platform1:~#
CentOS7でjava-1.8.0とdevelとりあえず入れた。
— ɯsı¯ɹǝʇsɐ (あすてりず無) (@aster_ism) November 1, 2019
Linuxの場合ですが、インストール先、ディレクトリのパーミッション?が原因で立ち上がりません。rootだと、VivadoのGUIが立ち上がってきません。現状、インストール先を使用するユーザーのUIDにして解決させています。
— ひでみ (@hidemi_ishihara) November 1, 2019
rootでインストールしたvitisさん,起動するときに呼び出す Vitis/2019.2/tps/lnx64/jre9.0.4/bin/java の実行パーミッション(とreadパーミッション)がothersに対して空いてなかった.bin以下と,lib以下のパーミッションあけたら起動した.
日 | 月 | 火 | 水 | 木 | 金 | 土 |
---|---|---|---|---|---|---|
- | - | - | - | - | 1 | 2 |
3 | 4 | 5 | 6 | 7 | 8 | 9 |
10 | 11 | 12 | 13 | 14 | 15 | 16 |
17 | 18 | 19 | 20 | 21 | 22 | 23 |
24 | 25 | 26 | 27 | 28 | 29 | 30 |