FC2カウンター FPGAの部屋 2019年11月24日
FC2ブログ

FPGAやCPLDの話題やFPGA用のツールの話題などです。 マニアックです。 日記も書きます。

FPGAの部屋

FPGAの部屋の有用と思われるコンテンツのまとめサイトを作りました。Xilinx ISEの初心者の方には、FPGAリテラシーおよびチュートリアルのページをお勧めいたします。

Vitis_Accel_Examples を Ultra96V2 のプラットフォームでやってみる1(array_partition)

Vitis_Accel_Examples の hello_world 以外のサンプルを Ultra96V2 のプラットフォームでやってみようと思う。
array_patition を Ultra96V2 のVitis アクセラレーション・プラットフォームでやってみよう。

最初に、 Vitis_Accel_Examples/cpp_kernels/array_partition ディレクトリに入って、make を行った。
make all TARGET=hw DEVICE=ultra96v2_min HOST_ARCH=aarch64 SYSROOT=/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min/images/linux/ultra96v2_min_pkg/pfm/sysroots/aarch64-xilinx-linux/
Vitis_Accel_Examples_48_191123.png

Vitis_Accel_Examples_49_191123.png

ログを示す。

masaaki@masaaki-H110M4-M01:~/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition$ make all TARGET=hw DEVICE=ultra96v2_min HOST_ARCH=aarch64 SYSROOT=/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min/images/linux/ultra96v2_min_pkg/pfm/sysroots/aarch64-xilinx-linux/
/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/gnu/aarch64/lin/aarch64-linux/bin/aarch64-linux-gnu-g++ -I../..//common/includes/xcl2 -I/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min/images/linux/ultra96v2_min_pkg/pfm/sysroots/aarch64-xilinx-linux//usr//include/xrt -I/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vivado/2019.2/include -Wall -O0 -g -std=c++11 -fmessage-length=0 ../..//common/includes/xcl2/xcl2.cpp src/host.cpp  -o 'array_partition'  -L/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min/images/linux/ultra96v2_min_pkg/pfm/sysroots/aarch64-xilinx-linux//usr//lib -lOpenCL -lpthread  -lrt -lstdc++  --sysroot=/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min/images/linux/ultra96v2_min_pkg/pfm/sysroots/aarch64-xilinx-linux/
mkdir -p ./_x.hw.ultra96v2_min
v++ -t hw --platform ultra96v2_min --save-temps  --temp_dir ./_x.hw.ultra96v2_min -c -k matmul -I'src' -o'_x.hw.ultra96v2_min/matmul.xo' 'src/matmul.cpp'
Option Map File Used: '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/data/vitis/vpp/optMap.xml'

****** v++ v2019.2 (64-bit)
  **** SW Build 2700185 on Thu Oct 24 18:45:48 MDT 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

INFO: [v++ 60-1306] Additional information associated with this v++ compile can be found at:
 Reports: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/_x.hw.ultra96v2_min/reports/matmul
 Log files: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/_x.hw.ultra96v2_min/logs/matmul
Running Dispatch Server on port:33265
INFO: [v++ 60-1548] Creating build summary session with primary output /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/_x.hw.ultra96v2_min/matmul.xo.compile_summary, at Sat Nov 23 07:53:02 2019
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Sat Nov 23 07:53:02 2019
Running Rule Check Server on port:46729
INFO: [v++ 60-1315] Creating rulecheck session with output '/home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/_x.hw.ultra96v2_min/reports/matmul/v++_compile_matmul_guidance.html', at Sat Nov 23 07:53:03 2019
INFO: [v++ 60-895]   Target platform: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min/ultra96v2_min.xpfm
INFO: [v++ 60-1578]   This platform contains Xilinx Shell Archive '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min/hw/ultra96v2_min.xsa'
INFO: [v++ 60-585] Compiling for hardware target
INFO: [v++ 60-423]   Target device: ultra96v2_min
INFO: [v++ 60-242] Creating kernel: 'matmul'

===>The following messages were generated while  performing high-level synthesis for kernel: matmul Log file: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/_x.hw.ultra96v2_min/matmul/matmul/vivado_hls.log :
INFO: [v++ 204-61] Option 'relax_ii_for_timing' is enabled, will increase II to preserve clock frequency constraints.
INFO: [v++ 204-61] Pipelining loop 'readA'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining loop 'readB'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining loop 'nopart1_nopart2'.
WARNING: [v++ 204-69] Unable to schedule 'load' operation ('B_load_2', /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/src/matmul.cpp:99) on array 'B', /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/src/matmul.cpp:59 due to limited memory ports. Please consider using a memory core with more ports or partitioning the array 'B'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 8, Depth = 10.
INFO: [v++ 204-61] Pipelining loop 'writeC'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 200-790] **** Loop Constraint Status: All loop constraints were NOT satisfied.
INFO: [v++ 200-789] **** Estimated Fmax: 136.99 MHz
INFO: [v++ 60-594] Finished kernel compilation
INFO: [v++ 60-244] Generating system estimate report...
INFO: [v++ 60-1092] Generated system estimate report: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/_x.hw.ultra96v2_min/reports/matmul/system_estimate_matmul.xtxt
INFO: [v++ 60-586] Created _x.hw.ultra96v2_min/matmul.xo
INFO: [v++ 60-791] Total elapsed time: 0h 0m 31s
mkdir -p ./_x.hw.ultra96v2_min
v++ -t hw --platform ultra96v2_min --save-temps  --temp_dir ./_x.hw.ultra96v2_min -c -k matmul_partition -I'src' -o'_x.hw.ultra96v2_min/matmul_partition.xo' 'src/matmul_partition.cpp'
Option Map File Used: '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/data/vitis/vpp/optMap.xml'

****** v++ v2019.2 (64-bit)
  **** SW Build 2700185 on Thu Oct 24 18:45:48 MDT 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

INFO: [v++ 60-1306] Additional information associated with this v++ compile can be found at:
 Reports: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/_x.hw.ultra96v2_min/reports/matmul_partition
 Log files: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/_x.hw.ultra96v2_min/logs/matmul_partition
Running Dispatch Server on port:34733
INFO: [v++ 60-1548] Creating build summary session with primary output /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/_x.hw.ultra96v2_min/matmul_partition.xo.compile_summary, at Sat Nov 23 07:53:36 2019
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Sat Nov 23 07:53:36 2019
Running Rule Check Server on port:37765
INFO: [v++ 60-1315] Creating rulecheck session with output '/home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/_x.hw.ultra96v2_min/reports/matmul_partition/v++_compile_matmul_partition_guidance.html', at Sat Nov 23 07:53:37 2019
INFO: [v++ 60-895]   Target platform: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min/ultra96v2_min.xpfm
INFO: [v++ 60-1578]   This platform contains Xilinx Shell Archive '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min/hw/ultra96v2_min.xsa'
INFO: [v++ 60-585] Compiling for hardware target
INFO: [v++ 60-423]   Target device: ultra96v2_min
INFO: [v++ 60-242] Creating kernel: 'matmul_partition'

===>The following messages were generated while  performing high-level synthesis for kernel: matmul_partition Log file: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/_x.hw.ultra96v2_min/matmul_partition/matmul_partition/vivado_hls.log :
INFO: [v++ 204-61] Option 'relax_ii_for_timing' is enabled, will increase II to preserve clock frequency constraints.
INFO: [v++ 204-61] Pipelining loop 'read_A'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining loop 'read_B'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining loop 'arraypart1_arraypart2'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [v++ 204-61] Pipelining loop 'writeC'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 200-790] **** Loop Constraint Status: All loop constraints were satisfied.
INFO: [v++ 200-789] **** Estimated Fmax: 136.99 MHz
INFO: [v++ 60-594] Finished kernel compilation
INFO: [v++ 60-244] Generating system estimate report...
INFO: [v++ 60-1092] Generated system estimate report: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/_x.hw.ultra96v2_min/reports/matmul_partition/system_estimate_matmul_partition.xtxt
INFO: [v++ 60-586] Created _x.hw.ultra96v2_min/matmul_partition.xo
INFO: [v++ 60-791] Total elapsed time: 0h 0m 31s
mkdir -p ./build_dir.hw.ultra96v2_min
v++ -t hw --platform ultra96v2_min --save-temps  --temp_dir ./build_dir.hw.ultra96v2_min -l  -o'build_dir.hw.ultra96v2_min/matmul.xclbin' _x.hw.ultra96v2_min/matmul.xo _x.hw.ultra96v2_min/matmul_partition.xo
Option Map File Used: '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/data/vitis/vpp/optMap.xml'

****** v++ v2019.2 (64-bit)
  **** SW Build 2700185 on Thu Oct 24 18:45:48 MDT 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

INFO: [v++ 60-1306] Additional information associated with this v++ link can be found at:
 Reports: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/reports/link
 Log files: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/logs/link
Running Dispatch Server on port:37971
INFO: [v++ 60-1548] Creating build summary session with primary output /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/matmul.xclbin.link_summary, at Sat Nov 23 07:54:09 2019
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Sat Nov 23 07:54:09 2019
Running Rule Check Server on port:35129
INFO: [v++ 60-1315] Creating rulecheck session with output '/home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/reports/link/v++_link_matmul_guidance.html', at Sat Nov 23 07:54:10 2019
INFO: [v++ 60-895]   Target platform: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min/ultra96v2_min.xpfm
INFO: [v++ 60-1578]   This platform contains Xilinx Shell Archive '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min/hw/ultra96v2_min.xsa'
INFO: [v++ 60-629] Linking for hardware target
INFO: [v++ 60-423]   Target device: ultra96v2_min
INFO: [v++ 60-1332] Run 'run_link' status: Not started
INFO: [v++ 60-1443] [07:54:10] Run run_link: Step system_link: Started
INFO: [v++ 60-1453] Command Line: system_link --xo /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/_x.hw.ultra96v2_min/matmul.xo --xo /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/_x.hw.ultra96v2_min/matmul_partition.xo -keep --xpfm /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min/ultra96v2_min.xpfm --target hw --output_dir /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int --temp_dir /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/sys_link
INFO: [v++ 60-1454] Run Directory: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/run_link
INFO: [SYSTEM_LINK 82-76] Reading emulation BD and HPFM information
INFO: [SYSTEM_LINK 60-1316] Initiating connection to rulecheck server, at Sat Nov 23 07:54:11 2019
INFO: [SYSTEM_LINK 82-70] Extracting xo v3 file /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/_x.hw.ultra96v2_min/matmul.xo
INFO: [KernelCheck 83-118] 'matmul' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'in1' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'in2' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'out_r' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'size' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [SYSTEM_LINK 82-70] Extracting xo v3 file /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/_x.hw.ultra96v2_min/matmul_partition.xo
INFO: [KernelCheck 83-118] 'matmul_partition' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'in1' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'in2' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'out_r' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'size' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [SYSTEM_LINK 82-53] Creating IP database /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/sys_link/_sysl/.cdb/xd_ip_db.xml
INFO: [SYSTEM_LINK 82-38] [07:54:11] build_xd_ip_db started: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/bin/build_xd_ip_db -ip_search 0  -sds-pf /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/sys_link/ultra96v2_min.hpfm -clkid 0 -ip /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/sys_link/iprepo/xilinx_com_hls_matmul_1_0,matmul -ip /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/sys_link/iprepo/xilinx_com_hls_matmul_partition_1_0,matmul_partition -o /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/sys_link/_sysl/.cdb/xd_ip_db.xml
INFO: [SYSTEM_LINK 82-37] [07:54:14] build_xd_ip_db finished successfully
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 296.438 ; gain = 0.000 ; free physical = 1937 ; free virtual = 38456
INFO: [SYSTEM_LINK 82-51] Create system connectivity graph
INFO: [SYSTEM_LINK 82-102] Applying explicit connections to the system connectivity graph: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/sys_link/cfgraph/cfgen_cfgraph.xml
INFO: [SYSTEM_LINK 82-38] [07:54:14] cfgen started: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/bin/cfgen -dmclkid 0 -r /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/sys_link/cfgraph/cfgen_cfgraph.xml
INFO: [CFGEN 83-0] Kernel Specs: 
INFO: [CFGEN 83-0]   kernel: matmul, num: 1  {matmul_1}
INFO: [CFGEN 83-0]   kernel: matmul_partition, num: 1  {matmul_partition_1}
INFO: [CFGEN 83-2226] Inferring mapping for argument matmul_1.in1 to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument matmul_1.in2 to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument matmul_1.out_r to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument matmul_partition_1.in1 to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument matmul_partition_1.in2 to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument matmul_partition_1.out_r to HP
INFO: [SYSTEM_LINK 82-37] [07:54:15] cfgen finished successfully
Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.28 . Memory (MB): peak = 296.438 ; gain = 0.000 ; free physical = 1937 ; free virtual = 38456
INFO: [SYSTEM_LINK 82-52] Create top-level block diagram
INFO: [SYSTEM_LINK 82-38] [07:54:15] cf2bd started: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/bin/cf2bd  --linux --trace_buffer 1024 --input_file /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/sys_link/cfgraph/cfgen_cfgraph.xml --ip_db /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/sys_link/_sysl/.cdb/xd_ip_db.xml --cf_name dr --working_dir /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/sys_link/_sysl/.xsd --temp_dir /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/sys_link --output_dir /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int
INFO: [CF2BD 82-31] Launching cf2xd: cf2xd -linux -trace-buffer 1024 -i /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/sys_link/cfgraph/cfgen_cfgraph.xml -r /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o dr.xml
INFO: [CF2BD 82-28] cf2xd finished successfully
INFO: [CF2BD 82-31] Launching cf_xsd: cf_xsd -disable-address-gen -dn dr -dp /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/sys_link/_sysl/.xsd
                                                                                
rlwrap: warning: your $TERM is 'xterm-256color' but rlwrap couldn't find it in the terminfo database. Expect some problems.: Inappropriate ioctl for device
INFO: [CF2BD 82-28] cf_xsd finished successfully
INFO: [SYSTEM_LINK 82-37] [07:54:17] cf2bd finished successfully
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 296.438 ; gain = 0.000 ; free physical = 1930 ; free virtual = 38453
INFO: [v++ 60-1441] [07:54:17] Run run_link: Step system_link: Completed
Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 677.902 ; gain = 0.000 ; free physical = 1948 ; free virtual = 38472
INFO: [v++ 60-1443] [07:54:17] Run run_link: Step cf2sw: Started
INFO: [v++ 60-1453] Command Line: cf2sw -sdsl /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/sdsl.dat -rtd /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/cf2sw.rtd -xclbin /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/xclbin_orig.xml -o /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/xclbin_orig.1.xml
INFO: [v++ 60-1454] Run Directory: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/run_link
INFO: [v++ 60-1441] [07:54:17] Run run_link: Step cf2sw: Completed
Time (s): cpu = 00:00:00.57 ; elapsed = 00:00:00.60 . Memory (MB): peak = 677.902 ; gain = 0.000 ; free physical = 1946 ; free virtual = 38470
INFO: [v++ 60-1443] [07:54:17] Run run_link: Step rtd2_system_diagram: Started
INFO: [v++ 60-1453] Command Line: rtd2SystemDiagram --rtdJsonFileName /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/cf2sw.rtd --diagramJsonFileName /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/systemDiagramModel.json --platformFilePath /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min/ultra96v2_min.xpfm --generatedByName v++ --generatedByVersion 2019.2 --generatedByChangeList 2700185 --generatedByTimeStamp Thu Oct 24 18:45:48 MDT 2019 --generatedByOptions /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/bin/unwrapped/lnx64.o/v++ -t hw --platform ultra96v2_min --save-temps --temp_dir ./build_dir.hw.ultra96v2_min -l -obuild_dir.hw.ultra96v2_min/matmul.xclbin _x.hw.ultra96v2_min/matmul.xo _x.hw.ultra96v2_min/matmul_partition.xo  --generatedByXclbinName matmul --kernelInfoDataFileName /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/kernel_info.dat
INFO: [v++ 60-1454] Run Directory: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/run_link
WARNING: [v++ 82-164] Unable to populate user region instance path.  The platform file does not contain a hardwarePlatform.devices..core.instPath entry.
INFO: [v++ 60-839] Read in kernel information from file '/home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/kernel_info.dat'.
WARNING: [v++ 82-163] Unable to populate user region available resources.  The platform file deos not contain a hardwarePlatform.devices..core.availableResources entry
INFO: [v++ 60-1441] [07:54:19] Run run_link: Step rtd2_system_diagram: Completed
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 677.902 ; gain = 0.000 ; free physical = 1949 ; free virtual = 38472
INFO: [v++ 60-1443] [07:54:19] Run run_link: Step vpl: Started
INFO: [v++ 60-1453] Command Line: vpl -t hw -f ultra96v2_min -s --output_dir /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int --log_dir /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/logs/link --report_dir /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/reports/link --config /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/vplConfig.ini -k /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/kernel_info.dat --webtalk_flag Vitis --temp_dir /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link --no-info --tlog_dir /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/.tlog/v++_link_matmul --iprepo /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/xo/ip_repo/xilinx_com_hls_matmul_partition_1_0 --iprepo /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/xo/ip_repo/xilinx_com_hls_matmul_1_0 --messageDb /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/run_link/vpl.pb /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/dr.bd.tcl
INFO: [v++ 60-1454] Run Directory: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/run_link

****** vpl v2019.2 (64-bit)
  **** SW Build 2700185 on Thu Oct 24 18:45:48 MDT 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

INFO: [VPL 60-839] Read in kernel information from file '/home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/kernel_info.dat'.
INFO: [VPL 60-423]   Target device: ultra96v2_min
INFO: [VPL 60-1032] Extracting hardware platform to /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/vivado/vpl/.local/hw_platform
[07:54:30] Run vpl: Step create_project: Started
Creating Vivado project.
[07:54:39] Run vpl: Step create_project: Completed
[07:54:39] Run vpl: Step create_bd: Started
[07:54:49] Run vpl: Step create_bd: Completed
[07:54:49] Run vpl: Step update_bd: Started
[07:54:50] Run vpl: Step update_bd: Completed
[07:54:50] Run vpl: Step generate_target: Started
[07:55:24] Run vpl: Step generate_target: Completed
[07:55:24] Run vpl: Step config_hw_runs: Started
[07:55:26] Run vpl: Step config_hw_runs: Completed
[07:55:26] Run vpl: Step synth: Started
[07:55:57] Block-level synthesis in progress, 0 of 17 jobs complete, 2 jobs running.
[07:56:27] Block-level synthesis in progress, 0 of 17 jobs complete, 2 jobs running.
[07:56:57] Block-level synthesis in progress, 0 of 17 jobs complete, 2 jobs running.
[07:57:27] Block-level synthesis in progress, 0 of 17 jobs complete, 2 jobs running.
[07:57:58] Block-level synthesis in progress, 1 of 17 jobs complete, 1 job running.
[07:58:28] Block-level synthesis in progress, 2 of 17 jobs complete, 1 job running.
[07:58:58] Block-level synthesis in progress, 2 of 17 jobs complete, 2 jobs running.
[07:59:28] Block-level synthesis in progress, 2 of 17 jobs complete, 2 jobs running.
[07:59:58] Block-level synthesis in progress, 2 of 17 jobs complete, 2 jobs running.
[08:00:28] Block-level synthesis in progress, 3 of 17 jobs complete, 1 job running.
[08:00:58] Block-level synthesis in progress, 4 of 17 jobs complete, 2 jobs running.
[08:01:28] Block-level synthesis in progress, 4 of 17 jobs complete, 2 jobs running.
[08:01:58] Block-level synthesis in progress, 4 of 17 jobs complete, 2 jobs running.
[08:02:28] Block-level synthesis in progress, 5 of 17 jobs complete, 1 job running.
[08:02:58] Block-level synthesis in progress, 6 of 17 jobs complete, 1 job running.
[08:03:28] Block-level synthesis in progress, 6 of 17 jobs complete, 2 jobs running.
[08:03:59] Block-level synthesis in progress, 8 of 17 jobs complete, 1 job running.
[08:04:29] Block-level synthesis in progress, 8 of 17 jobs complete, 2 jobs running.
[08:04:59] Block-level synthesis in progress, 8 of 17 jobs complete, 2 jobs running.
[08:05:29] Block-level synthesis in progress, 8 of 17 jobs complete, 2 jobs running.
[08:05:59] Block-level synthesis in progress, 10 of 17 jobs complete, 0 jobs running.
[08:06:29] Block-level synthesis in progress, 10 of 17 jobs complete, 2 jobs running.
[08:06:59] Block-level synthesis in progress, 10 of 17 jobs complete, 2 jobs running.
[08:07:29] Block-level synthesis in progress, 10 of 17 jobs complete, 2 jobs running.
[08:07:59] Block-level synthesis in progress, 11 of 17 jobs complete, 1 job running.
[08:08:30] Block-level synthesis in progress, 12 of 17 jobs complete, 1 job running.
[08:09:00] Block-level synthesis in progress, 12 of 17 jobs complete, 2 jobs running.
[08:09:30] Block-level synthesis in progress, 12 of 17 jobs complete, 2 jobs running.
[08:10:00] Block-level synthesis in progress, 12 of 17 jobs complete, 2 jobs running.
[08:10:30] Block-level synthesis in progress, 13 of 17 jobs complete, 1 job running.
[08:11:00] Block-level synthesis in progress, 14 of 17 jobs complete, 1 job running.
[08:11:30] Block-level synthesis in progress, 14 of 17 jobs complete, 2 jobs running.
[08:12:00] Block-level synthesis in progress, 14 of 17 jobs complete, 2 jobs running.
[08:12:31] Block-level synthesis in progress, 14 of 17 jobs complete, 2 jobs running.
[08:13:01] Block-level synthesis in progress, 16 of 17 jobs complete, 0 jobs running.
[08:13:31] Block-level synthesis in progress, 17 of 17 jobs complete, 0 jobs running.
[08:14:01] Top-level synthesis in progress.
[08:14:31] Top-level synthesis in progress.
[08:15:01] Top-level synthesis in progress.
[08:15:13] Run vpl: Step synth: Completed
[08:15:13] Run vpl: Step impl: Started
[08:17:14] Finished 2nd of 6 tasks (FPGA linking synthesized kernels to platform). Elapsed time: 00h 22m 53s 

[08:17:14] Starting logic optimization..
[08:17:44] Phase 1 Retarget
[08:17:44] Phase 2 Constant propagation
[08:17:44] Phase 3 Sweep
[08:17:44] Phase 4 BUFG optimization
[08:17:44] Phase 5 Shift Register Optimization
[08:17:44] Phase 6 Post Processing Netlist
[08:18:15] Finished 3rd of 6 tasks (FPGA logic optimization). Elapsed time: 00h 01m 00s 

[08:18:15] Starting logic placement..
[08:18:15] Phase 1 Placer Initialization
[08:18:15] Phase 1.1 Placer Initialization Netlist Sorting
[08:18:15] Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
[08:18:15] Phase 1.3 Build Placer Netlist Model
[08:18:15] Phase 1.4 Constrain Clocks/Macros
[08:18:15] Phase 2 Global Placement
[08:18:15] Phase 2.1 Floorplanning
[08:18:15] Phase 2.2 Global Placement Core
[08:18:45] Phase 2.2.1 Physical Synthesis In Placer
[08:18:45] Phase 3 Detail Placement
[08:18:45] Phase 3.1 Commit Multi Column Macros
[08:18:45] Phase 3.2 Commit Most Macros & LUTRAMs
[08:18:45] Phase 3.3 Area Swap Optimization
[08:18:45] Phase 3.4 Pipeline Register Optimization
[08:18:45] Phase 3.5 Small Shape DP
[08:18:45] Phase 3.5.1 Small Shape Clustering
[08:18:45] Phase 3.5.2 Flow Legalize Slice Clusters
[08:18:45] Phase 3.5.3 Slice Area Swap
[08:18:45] Phase 3.5.4 Commit Slice Clusters
[08:18:45] Phase 3.6 Re-assign LUT pins
[08:18:45] Phase 3.7 Pipeline Register Optimization
[08:18:45] Phase 4 Post Placement Optimization and Clean-Up
[08:18:45] Phase 4.1 Post Commit Optimization
[08:19:15] Finished 4th of 6 tasks (FPGA logic placement). Elapsed time: 00h 01m 00s 

[08:19:15] Starting logic routing..
[08:19:15] Phase 1 Build RT Design
[08:19:15] Phase 4.1.1 Post Placement Optimization
[08:19:15] Phase 4.1.1.1 BUFG Insertion
[08:19:15] Phase 4.2 Post Placement Cleanup
[08:19:15] Phase 4.3 Placer Reporting
[08:19:15] Phase 4.4 Final Placement Cleanup
[08:19:45] Phase 2 Router Initialization
[08:19:45] Phase 2.1 Create Timer
[08:19:45] Phase 2.2 Fix Topology Constraints
[08:19:45] Phase 2.3 Pre Route Cleanup
[08:19:45] Phase 2.4 Global Clock Net Routing
[08:19:45] Phase 2.5 Update Timing
[08:20:15] Phase 3 Initial Routing
[08:20:15] Phase 4 Rip-up And Reroute
[08:20:15] Phase 4.1 Global Iteration 0
[08:20:46] Phase 4.2 Additional Iteration for Hold
[08:20:46] Phase 5 Delay and Skew Optimization
[08:20:46] Phase 5.1 Delay CleanUp
[08:20:46] Phase 5.1.1 Update Timing
[08:20:46] Phase 5.2 Clock Skew Optimization
[08:20:46] Phase 6 Post Hold Fix
[08:20:46] Phase 6.1 Hold Fix Iter
[08:20:46] Phase 6.1.1 Update Timing
[08:20:46] Phase 7 Route finalize
[08:20:46] Phase 8 Verifying routed nets
[08:20:46] Phase 9 Depositing Routes
[08:20:46] Phase 10 Post Router Timing
[08:20:46] Finished 5th of 6 tasks (FPGA routing). Elapsed time: 00h 01m 30s 

[08:20:46] Starting bitstream generation..
[08:21:12] Creating bitmap...
[08:21:12] Writing bitstream ./Ultra96V2_Platform1_wrapper.bit...
[08:21:12] Finished 6th of 6 tasks (FPGA bitstream generation). Elapsed time: 00h 00m 26s 
[08:21:11] Run vpl: Step impl: Completed
[08:21:12] Run vpl: FINISHED. Run Status: impl Complete!
INFO: [v++ 60-1441] [08:21:12] Run run_link: Step vpl: Completed
Time (s): cpu = 00:00:08 ; elapsed = 00:26:53 . Memory (MB): peak = 677.902 ; gain = 0.000 ; free physical = 5173 ; free virtual = 38264
INFO: [v++ 60-1443] [08:21:12] Run run_link: Step rtdgen: Started
INFO: [v++ 60-1453] Command Line: rtdgen
INFO: [v++ 60-1454] Run Directory: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/run_link
INFO: [v++ 60-1453] Command Line: cf2sw -a /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/address_map.xml -sdsl /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/sdsl.dat -xclbin /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/xclbin_orig.xml -rtd /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/matmul.rtd -o /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/matmul.xml
INFO: [v++ 60-1618] Launching 
INFO: [v++ 60-1441] [08:21:15] Run run_link: Step rtdgen: Completed
Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 677.902 ; gain = 0.000 ; free physical = 5916 ; free virtual = 39010
INFO: [v++ 60-1443] [08:21:15] Run run_link: Step xclbinutil: Started
INFO: [v++ 60-1453] Command Line: xclbinutil --add-section BITSTREAM:RAW:/home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/system.bit --force --key-value SYS:mode:flat --add-section :JSON:/home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/matmul.rtd --add-section CLOCK_FREQ_TOPOLOGY:JSON:/home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/matmul_xml.rtd --add-section BUILD_METADATA:JSON:/home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/matmul_build.rtd --add-section EMBEDDED_METADATA:RAW:/home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/matmul.xml --add-section SYSTEM_METADATA:RAW:/home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/systemDiagramModelSlrBaseAddress.json --key-value SYS:PlatformVBNV:vendor_Ultra96V2_Ultra96V2_Platform1_1_0 --output /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/matmul.xclbin
INFO: [v++ 60-1454] Run Directory: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/run_link
XRT Build Version: 2.3.1301
       Build Date: 2019-10-24 20:05:16
          Hash ID: 192e706aea53163a04c574f9b3fe9ed76b6ca471
Creating a default 'in-memory' xclbin image.

Section: 'BITSTREAM'(0) was successfully added.
Size   : 5568799 bytes
Format : RAW
File   : '/home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/system.bit'

Section: 'MEM_TOPOLOGY'(6) was successfully added.
Format : JSON
File   : 'mem_topology'

Section: 'IP_LAYOUT'(8) was successfully added.
Format : JSON
File   : 'ip_layout'

Section: 'CONNECTIVITY'(7) was successfully added.
Format : JSON
File   : 'connectivity'
WARNING: Skipping CLOCK_FREQ_TOPOLOGY section for count size is zero.
WARNING: Section 'CLOCK_FREQ_TOPOLOGY' content is empty.  No data in the given JSON file.

Section: 'CLOCK_FREQ_TOPOLOGY'(11) was empty.  No action taken.
Format : JSON
File   : '/home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/matmul_xml.rtd'

Section: 'BUILD_METADATA'(14) was successfully added.
Size   : 3025 bytes
Format : JSON
File   : '/home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/matmul_build.rtd'

Section: 'EMBEDDED_METADATA'(2) was successfully added.
Size   : 4360 bytes
Format : RAW
File   : '/home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/matmul.xml'

Section: 'SYSTEM_METADATA'(22) was successfully added.
Size   : 12517 bytes
Format : RAW
File   : '/home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/systemDiagramModelSlrBaseAddress.json'
Successfully wrote (5595859 bytes) to the output file: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/matmul.xclbin
Leaving xclbinutil.
INFO: [v++ 60-1441] [08:21:15] Run run_link: Step xclbinutil: Completed
Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.12 . Memory (MB): peak = 677.902 ; gain = 0.000 ; free physical = 5903 ; free virtual = 39009
INFO: [v++ 60-1443] [08:21:15] Run run_link: Step xclbinutilinfo: Started
INFO: [v++ 60-1453] Command Line: xclbinutil --quiet --info /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/matmul.xclbin.info --input /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/int/matmul.xclbin
INFO: [v++ 60-1454] Run Directory: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/link/run_link
INFO: [v++ 60-1441] [08:21:15] Run run_link: Step xclbinutilinfo: Completed
Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.07 . Memory (MB): peak = 677.902 ; gain = 0.000 ; free physical = 5903 ; free virtual = 39009
INFO: [v++ 60-244] Generating system estimate report...
INFO: [v++ 60-1092] Generated system estimate report: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/reports/link/system_estimate_matmul.xtxt
INFO: [v++ 60-907] Packaging to directory: 'build_dir.hw.ultra96v2_min/sd_card'
INFO: [v++ 60-586] Created build_dir.hw.ultra96v2_min/matmul.xclbin
INFO: [v++ 60-1307] Run completed. Additional information can be found in:
 Guidance: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/reports/link/v++_link_matmul_guidance.html
 Timing Report: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/reports/link/imp/Ultra96V2_Platform1_wrapper_timing_summary_routed.rpt
 Vivado Log: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/logs/link/vivado.log
 Steps Log File: /home/masaaki/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition/build_dir.hw.ultra96v2_min/logs/link/link.steps.log

INFO: [v++ 60-791] Total elapsed time: 0h 27m 9s
emconfigutil --platform ultra96v2_min --od ./_x.hw.ultra96v2_min

****** configutil v2019.2 (64-bit)
  **** SW Build 2700185 on Thu Oct 24 18:45:48 MDT 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

INFO: [ConfigUtil 60-895]   Target platform: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min/ultra96v2_min.xpfm
INFO: [ConfigUtil 60-1578]   This platform contains Xilinx Shell Archive '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min/hw/ultra96v2_min.xsa'
emulation configuration file `emconfig.json` is created in ./_x.hw.ultra96v2_min directory 
mkdir -p sd_card/./build_dir.hw.ultra96v2_min
cp -rf `/home/masaaki/Vitis_Work/Vitis_Accel_Examples/common/utility/parse_platform_list.py ultra96v2_min`/ultra96v2_min/sw/ultra96v2_min/boot/generic.readme `/home/masaaki/Vitis_Work/Vitis_Accel_Examples/common/utility/parse_platform_list.py ultra96v2_min`/ultra96v2_min/sw/ultra96v2_min/xrt/image/* xrt.ini array_partition sd_card
cp: 'None/ultra96v2_min/sw/ultra96v2_min/boot/generic.readme' を stat できません: そのようなファイルやディレクトリはありません
cp: 'None/ultra96v2_min/sw/ultra96v2_min/xrt/image/*' を stat できません: そのようなファイルやディレクトリはありません
Makefile:135: recipe for target 'sd_card' failed
make: *** [sd_card] Error 1
masaaki@masaaki-H110M4-M01:~/Vitis_Work/Vitis_Accel_Examples/cpp_kernels/array_partition$ make all TARGET=hw DEVICE=ultra96v2_min HOST_ARCH=aarch64 SYSROOT=/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min/images/linux/ultra96v2_min_pkg/pfm/sysroots/aarch64-xilinx-linux/
/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/gnu/aarch64/lin/aarch64-linux/bin/aarch64-linux-gnu-g++ -I../..//common/includes/xcl2 -I/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min/images/linux/ultra96v2_min_pkg/pfm/sysroots/aarch64-xilinx-linux//usr//include/xrt -I/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vivado/2019.2/include -Wall -O0 -g -std=c++11 -fmessage-length=0 ../..//common/includes/xcl2/xcl2.cpp src/host.cpp  -o 'array_partition'  -L/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min/images/linux/ultra96v2_min_pkg/pfm/sysroots/aarch64-xilinx-linux//usr//lib -lOpenCL -lpthread  -lrt -lstdc++  --sysroot=/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min/images/linux/ultra96v2_min_pkg/pfm/sysroots/aarch64-xilinx-linux/
mkdir -p sd_card/./build_dir.hw.ultra96v2_min
#cp -rf `/home/masaaki/Vitis_Work/Vitis_Accel_Examples/common/utility/parse_platform_list.py ultra96v2_min`/ultra96v2_min/sw/ultra96v2_min/boot/generic.readme `/home/masaaki/Vitis_Work/Vitis_Accel_Examples/common/utility/parse_platform_list.py ultra96v2_min`/ultra96v2_min/sw/ultra96v2_min/xrt/image/* xrt.ini array_partition sd_card
cp -rf ./build_dir.hw.ultra96v2_min/*.xclbin sd_card/./build_dir.hw.ultra96v2_min/
[ -f sd_card/BOOT.BIN ] && echo "INFO: BOOT.BIN already exists" || cp -rf ./build_dir.hw.ultra96v2_min/sd_card/BOOT.BIN sd_card/


例によって、エラー部分のスクリプトをコメントアウトして、もう一度、make した。
Vitis_Accel_Examples_50_191123.png

make all TARGET=hw DEVICE=ultra96v2_min HOST_ARCH=aarch64 SYSROOT=/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min/images/linux/ultra96v2_min_pkg/pfm/sysroots/aarch64-xilinx-linux/

Vitis_Accel_Examples/cpp_kernels/array_partition ディレクトリの様子を示す。
Vitis_Accel_Examples_51_191123.png

Vitis_Accel_Examples/cpp_kernels/array_partition/sd_card ディレクトリの様子を示す。
Vitis_Accel_Examples_52_191123.png

これをMicroSD カードの第1パーティションに書き込んで、Ultra96-V2 に挿入して電源ONするとLinux が立ち上がった。
root ノーパスでログインした。

zocl ドライバを insmod でロードした。
insmod /lib/modules/4.19.0-xilinx-v2019.2/extra/zocl.ko

第1パーティションに行って、array_partition サンプルを実行した。
cd /run/media/mmcblk0p1/
export XILINX_XRT=/usr
./init.sh

Vitis_Accel_Examples_53_191123.png

成功した。
ログを示す。

root@ultra96v2_min:/run/media/mmcblk0p1# ./init.sh
A:
   0    1    8    5    5    2    0    7    7   10 …
   7    0    4    0    4    7    6   10    9    5 …
   2    0    8    3    6    8   10    4    2   10 …
   2    4    8    5    2    3    3    1    5    9 …
  10    5    2    0   10    0    5    4    3   10 …
   9    1    0    7    9    6    8    7   10    9 …
   4    9    2    4    5    5    3    1    1    6 …
   6    9    6    9    1    2    7    1    1    3 …
   1    3    9    7    1    7    4    4    5    1 …
  10    4    1    6    2    5    5   10    1    2 …
   …    …    …    …    …    …    …    …    …    … ⋱

B:
   7    7    2    9    7    9    1    0    8    6 …
   4    2    7    3    8    8    4    3    2    0 …
   6    1    9    1   10    2    2    1    2    6 …
   0    6    2    3    7    1    8    5    6    6 …
   8    6    8    3    1    5    3    6    5    4 …
   3    0    4    2    7    7    5    8    7   10 …
   4    6   10    1    7    3    5    5    9    0 …
   2    9    7    5    8    0    1    7    7    4 …
   1    0    5    0    1    9    8    8    4    0 …
   4    6    7    7    5    3    8    4    7    3 …
   …    …    …    …    …    …    …    …    …    … ⋱

Gold:
 196  311  428  206  384  291  305  363  405  243 …
 286  472  448  296  490  425  382  430  500  367 …
 269  439  555  260  529  390  416  425  559  370 …
 231  293  419  231  365  385  361  356  384  235 …
 307  479  484  313  453  477  368  366  529  295 …
 31[   41.449920] [drm] Pid 2170 opened device
7  474  488  357  472  458  439  457  564  341 …
 246  339  3[   41.455037] [drm] Pid 2170 closed device
85  272  381  424  364  324  386  263 …
 234  367  312  217  430  307  334  248  314  284 …
 231  370  403  197  453  334  353  410  382  344 …
 246  432  363  321  462  324  291  330[   41.475501] [drm] Pid 2170 opened device
  436  322 …
   …    …    …    …    …    …    …    …    …    … ⋱

Found Platform
Platform Name: Xilinx
INFO: Reading ./build_dir.hw.ultra96v2_min/matmul.xclbin
Loading: './build_dir.hw.ultra96v2_min/matmul.xclbin'
Trying to program device[0]: edge
[   41.799701] [drm] Finding IP_LAYOUT section header
[   41.799714] [drm] Section IP_LAYOUT details:
[   41.804527] [drm]   offset = 0x54fcf8
[   41.808789] [drm]   size = 0xa8
[   41.812452] [drm] Finding DEBUG_IP_LAYOUT section header
[   41.815585] [drm] AXLF section DEBUG_IP_LAYOUT header not found
[   41.820891] [drm] Finding CONNECTIVITY section header
[   41.826799] [drm] Section CONNECTIVITY details:
[   41.831843] [drm]   offset = 0x54fda0
[   41.836363] [drm]   size = 0x4c
[   41.840026] [drm] Finding MEM_TOPOLOGY section header
[   41.843173] [drm] Section MEM_TOPOLOGY details:
[   41.848222] [drm]   offset = 0x54fc00
[   41.852745] [drm]   size = 0xf8
[   41.858442] [drm] No ERT scheduler on MPSoC, using KDS
[   41.867228] [drm] Fail to install CU 0 interrupt handler: -22. Fall back to polling mode.
[   41.875414] [drm] scheduler config ert(0)
[   41.875416] [drm]   cus(2)
[   41.879418] [drm]   slots(16)
[   41.882117] [drm]   num_cu_masks(1)
[   41.885071] [drm]   cu_shift(16)
[   41.888551] [drm]   cu_base(0xa0000000)
Device[0]: program successful!
|-------------------------+-------------------------|
| Kernel                  |    Wall-Clock Time (ns) |
|-------------------------+-----------------------[   41.891769] [drm]   polling(1)
--|
| matmul:                 |                  927760 |
| ma[   41.911552] [drm] zocl_free_userptr_bo: obj 0x00000000c1210b3c
tmul: partition       |                  134180 |
|------------[   41.918961] [drm] zocl_free_userptr_bo: obj 0x00000000f1560de0
-------------+-------------------------|
Note: Wall Clock Time is meaningful for real hardware execution only, not for emulation.
Please refer to profile summary for kernel execution time fo[   41.930308] [drm] zocl_free_userptr_bo: obj 0x000000003f79d183
r hardware emulation.
TEST PASSED

[   41.954490] [drm] Pid 2170 closed device


[drm] を除くと表がよく見える。

Device[0]: program successful!
|-------------------------+-------------------------|
| Kernel                  |    Wall-Clock Time (ns) |
|-------------------------+-------------------------|
| matmul:                 |                  927760 |
| matmul: partition       |                  134180 |
|-------------------------+-------------------------|
Note: Wall Clock Time is meaningful for real hardware execution only, not for emulation.
Please refer to profile summary for kernel execution time for hardware emulation.
TEST PASSED


  1. 2019年11月24日 05:28 |
  2. Vitis
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