#!/bin/sh
if [ $# -eq 1 ] ; then
g++ -ggdb `pkg-config --cflags opencv` -o `basename $1 .cpp` $1 `pkg-config --libs opencv`;
else
echo "g++_opencv < C++ file name >"
fi
export PATH=$PATH:~/bin
all:
{
[destination_device = pl] lap_axis_dma_cam_dp.bit
}
/dts-v1/; /plugin/;
/ {
fragment@0 {
target-path = "/fpga-full";
__overlay__ {
firmware-name = "lap_axis_dma_cam_dp.bin";
};
};
fragment@1 {
target-path = "/amba_pl@0";
__overlay__ {
#address-cells = <2>;
#size-cells = <1>;
zyxclmm_drm {
compatible = "xlnx,zocl";
status = "okay";
reg = <0x0 0xB0000000 0x10000>;
};
fclk0 {
compatible = "ikwzm,fclkcfg-0.10.a";
clocks = <&zynqmp_clk 0x47>;
insert-rate = "100000000";
insert-enable = <1>;
remove-rate = "1000000";
remove-enable = <0>;
};
};
};
};
CONFIG_xrt
CONFIG_xrt-dev
CONFIG_zocl
CONFIG_opencl-clhpp-dev
CONFIG_opencl-headers-dev
CONFIG_packagegroup-petalinux-opencv
#Note: Mention Each package in individual line
#These packages will get added into rootfs menu entry
CONFIG_gpio-demo
CONFIG_peekpoke
CONFIG_xrt
CONFIG_xrt-dev
CONFIG_zocl
CONFIG_opencl-clhpp-dev
CONFIG_opencl-headers-dev
CONFIG_packagegroup-petalinux-opencv
/include/ "system-conf.dtsi"
/ {
};
&amba {
zyxclmm_drm {
compatible = "xlnx,zocl";
status = "okay";
};
};
&sdhci0 {
disable-wp;
};
/* linux */
the_ROM_image:
{
[fsbl_config] a53_x64
[bootloader] <zynqmp_fsbl.elf>
[pmufw_image] <pmufw.elf>
[destination_device=pl] <bitstream>
[destination_cpu=a53-0, exception_level=el-3, trustzone] <bl31.elf>
[destination_cpu=a53-0, exception_level=el-2] <u-boot.elf>
}
set_property platform.design_intent.embedded true [current_project]
set_property platform.design_intent.server_managed false [current_project]
set_property platform.design_intent.external_host false [current_project]
set_property platform.design_intent.datacenter false [current_project]
set_property platform.default_output_type "sd_card" [current_project]
#Note: Mention Each package in individual line
#These packages will get added into rootfs menu entry
CONFIG_gpio-demo
CONFIG_peekpoke
CONFIG_gstreamer-vcu-examples
CONFIG_packagegroup-petalinux-v4lutils
CONFIG_packagegroup-petalinux-audio
CONFIG_gstreamer-vcu-notebooks
CONFIG_xrt
CONFIG_mnt-sd
CONFIG_xrt-dev
CONFIG_zocl
CONFIG_opencl-clhpp-dev
CONFIG_opencl-headers-dev
CONFIG_packagegroup-petalinux-opencv
#Note: Mention Each package in individual line
#These packages will get added into rootfs menu entry
CONFIG_gpio-demo
CONFIG_peekpoke
CONFIG_gstreamer-vcu-examples
CONFIG_packagegroup-petalinux-v4lutils
CONFIG_packagegroup-petalinux-audio
CONFIG_gstreamer-vcu-notebooks
CONFIG_xrt
CONFIG_mnt-sd
CONFIG_xrt-dev
CONFIG_zocl
CONFIG_opencl-clhpp-dev
CONFIG_opencl-headers-dev
CONFIG_packagegroup-petalinux-opencv
/include/ "system-conf.dtsi"
/ {
};
&amba {
axi_intc_0: axi-interrupt-ctrl {
#interrupt-cells = <2>;
compatible = "xlnx,xps-intc-1.00.a";
interrupt-controller;
reg = <0x0 0x80020000 0x0 0x1000>;
xlnx,kind-of-intr = <0x0>;
xlnx,num-intr-inputs = <0x20>;
interrupt-parent = <&gic>;
interrupts = <0 89 4>;
};
zyxclmm_drm {
compatible = "xlnx,zocl";
status = "okay";
interrupt-parent = <&axi_intc_0>;
interrupts = <0 4>, <1 4>, <2 4>, <3 4>,
<4 4>, <5 4>, <6 4>, <7 4>,
<8 4>, <9 4>, <10 4>, <11 4>,
<12 4>, <13 4>, <14 4>, <15 4>,
<16 4>, <17 4>, <18 4>, <19 4>,
<20 4>, <21 4>, <22 4>, <23 4>,
<24 4>, <25 4>, <26 4>, <27 4>,
<28 4>, <29 4>, <30 4>, <31 4>;
};
};
で90秒の時間がかかるようだ。A stop job is running for Target Co…n Framework agent
all:
{
[destination_device = pl] sobel_filter_axim.bit
}
;/dts-v1/; /plugin/;
/ {
fragment@0 {
target-path = "/fpga-full";
__overlay__ {
firmware-name = "sobel_filter_axim.bin";
};
};
fragment@1 {
target-path = "/amba_pl@0";
__overlay__ {
#address-cells = <2>;
#size-cells = <1>;
zyxclmm_drm {
compatible = "xlnx,zocl";
status = "okay";
reg = <0x0 0xA0000000 0x10000>;
};
fclk0 {
compatible = "ikwzm,fclkcfg-0.10.a";
clocks = <&zynqmp_clk 0x47>;
insert-rate = "100000000";
insert-enable = <1>;
remove-rate = "1000000";
remove-enable = <0>;
};
};
};
}
cp ../ZynqMP-FPGA-XRT-Example-1-Ultra96/test.bmp .
./sobel_filter_axim.exe sobel_filter_axim.xclbin
// bmp_header.h
// BMP ファイルフォーマットから引用させて頂きました
// http://www.kk.iij4u.or.jp/~kondo/bmp/
//
// 2017/05/04 : takseiさんのご指摘によりintX_tを使った宣言に変更。takseiさんありがとうございました
// 変数の型のサイズの違いによってLinuxの64ビット版では動作しなかったためです
// http://marsee101.blog19.fc2.com/blog-entry-3354.html#comment2808
//
#include <stdio.h>
#include <stdint.h>
// BITMAPFILEHEADER 14bytes
typedef struct tagBITMAPFILEHEADER {
uint16_t bfType;
uint32_t bfSize;
uint16_t bfReserved1;
uint16_t bfReserved2;
uint32_t bfOffBits;
} BITMAPFILEHEADER;
// BITMAPINFOHEADER 40bytes
typedef struct tagBITMAPINFOHEADER{
uint32_t biSize;
int32_t biWidth;
int32_t biHeight;
uint16_t biPlanes;
uint16_t biBitCount;
uint32_t biCompression;
uint32_t biSizeImage;
int32_t biXPixPerMeter;
int32_t biYPixPerMeter;
uint32_t biClrUsed;
uint32_t biClrImporant;
} BITMAPINFOHEADER;
typedef struct BMP24bitsFORMAT {
uint8_t blue;
uint8_t green;
uint8_t red;
} BMP24FORMAT;
// sobel_filter_axim_k.cpp
// 2020/04/15 by marsee
#include <stdint.h>
#define HORIZONTAL 0
#define VERTICAL 1
int32_t sobel_fil(int32_t h_or_v, int32_t x0y0, int32_t x1y0, int32_t x2y0, int32_t x0y1,
int32_t x1y1, int32_t x2y1, int32_t x0y2, int32_t x1y2, int32_t x2y2);
int32_t conv_rgb2y(int32_t rgb);
int32_t square_root8(int32_t val);
#define DISPLAY_WIDTH 64
#define DISPLAY_HIGHT 48
extern "C" {
void sobel_filter_axim(volatile int32_t *cam_fb, volatile int32_t *sobel_fb){
#pragma HLS INTERFACE m_axi depth=3072 port=sobel_fb offset=slave bundle = gmem
#pragma HLS INTERFACE m_axi depth=3072 port=cam_fb offset=slave bundle = gmem
#pragma HLS INTERFACE s_axilite port=return bundle = control
int32_t sobel_val, sobel_h_val, sobel_v_val;
int32_t line_buf[2][DISPLAY_WIDTH];
#pragma HLS array_partition variable=line_buf block factor=2 dim=1
#pragma HLS resource variable=line_buf core=RAM_2P
int32_t pix_mat[3][3];
#pragma HLS array_partition variable=pix_mat complete
LOOP_Y: for(int y=0; y<DISPLAY_HIGHT; y++){
LOOP_X: for(int x=0; x<DISPLAY_WIDTH; x++){
#pragma HLS PIPELINE II=1
LOOP_PIX_MAT_K: for(int k=0; k<3; k++){
LOOP_PIX_MAT_M: for(int m=0; m<2; m++){
pix_mat[k][m] = pix_mat[k][m+1];
}
}
pix_mat[0][2] = line_buf[0][x];
pix_mat[1][2] = line_buf[1][x];
int32_t y_val = conv_rgb2y(cam_fb[y*DISPLAY_WIDTH+x]);
pix_mat[2][2] = y_val;
line_buf[0][x] = line_buf[1][x]; // 行の入れ替え
line_buf[1][x] = y_val;
sobel_h_val = sobel_fil(HORIZONTAL, pix_mat[0][0], pix_mat[0][1], pix_mat[0][2],
pix_mat[1][0], pix_mat[1][1], pix_mat[1][2],
pix_mat[2][0], pix_mat[2][1], pix_mat[2][2]);
sobel_v_val = sobel_fil(VERTICAL, pix_mat[0][0], pix_mat[0][1], pix_mat[0][2],
pix_mat[1][0], pix_mat[1][1], pix_mat[1][2],
pix_mat[2][0], pix_mat[2][1], pix_mat[2][2]);
sobel_val = square_root8(sobel_h_val*sobel_h_val + sobel_v_val*sobel_v_val);
if(x<2 || y<2)
sobel_val = 0;
sobel_fb[y*DISPLAY_WIDTH+x] = (sobel_val<<16)+(sobel_val<<8)+sobel_val;
}
}
}
}
// RGBからYへの変換
// RGBのフォーマットは、{8'd0, R(8bits), G(8bits), B(8bits)}, 1pixel = 32bits
// 輝度信号Yのみに変換する。変換式は、Y = 0.299R + 0.587G + 0.114B
// "YUVフォーマット及び YUV<->RGB変換"を参考にした。http://vision.kuee.kyoto-u.ac.jp/~hiroaki/firewire/yuv.html
// 2013/09/27 : float を止めて、すべてint にした
int32_t conv_rgb2y(int32_t rgb){
int32_t r, g, b, y_f;
int32_t y;
b = rgb & 0xff;
g = (rgb>>8) & 0xff;
r = (rgb>>16) & 0xff;
y_f = 77*r + 150*g + 29*b; //y_f = 0.299*r + 0.587*g + 0.114*b;の係数に256倍した
y = y_f >> 8; // 256で割る
return(y);
}
// sobel filter
// HORZONTAL
// x0y0 x1y0 x2y0 1 2 1
// x0y1 x1y1 x2y1 0 0 0
// x0y2 x1y2 x2y2 -1 -2 -1
// VERTICAL
// x0y0 x1y0 x2y0 1 0 -1
// x0y1 x1y1 x2y1 2 0 -2
// x0y2 x1y2 x2y2 1 0 -1
int32_t sobel_fil(int32_t h_or_v, int32_t x0y0, int32_t x1y0, int32_t x2y0, int32_t x0y1,
int32_t x1y1, int32_t x2y1, int32_t x0y2, int32_t x1y2, int32_t x2y2){
int32_t y;
if(h_or_v == HORIZONTAL){
y = x0y0 + 2*x1y0 + x2y0 - x0y2 - 2*x1y2 - x2y2;
} else {
y = x0y0 - x2y0 + 2*x0y1 - 2*x2y1 + x0y2 - x2y2;
}
if(y<0)
y = -y;
//y = 0;
else if(y>255)
y = 255;
return(y);
}
// square_root8
// 8bit幅のsquare_rootを求める
int32_t square_root8(int32_t val){
int32_t temp = 0;
int32_t square;
for(int i=7; i>=0; --i){
temp += (1 << i);
square = temp * temp;
if(square > val){
temp -= (1 << i);
}
}
return(temp);
}
// sobel_filter_axim_host.cpp
// 2020/04/15 by marsee
//
// Vitis-Tutorials/docs/mixing-c-rtl-kernels/reference-files/src/host/host_step1.cpp のコードを引用します
// https://github.com/Xilinx/Vitis-Tutorials/blob/master/docs/mixing-c-rtl-kernels/reference-files/src/host/host_step1.cpp
#define CL_HPP_CL_1_2_DEFAULT_BUILD
#define CL_HPP_TARGET_OPENCL_VERSION 120
#define CL_HPP_MINIMUM_OPENCL_VERSION 120
#define CL_HPP_ENABLE_PROGRAM_CONSTRUCTION_FROM_ARRAY_COMPATIBILITY 1
#define CL_USE_DEPRECATED_OPENCL_1_2_APIS
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <vector>
#include <CL/cl2.hpp>
#include <iostream>
#include <fstream>
#include <CL/cl_ext_xilinx.h>
#include <unistd.h>
#include <limits.h>
#include <sys/stat.h>
#include <ap_int.h>
#include <hls_stream.h>
#include <ap_axi_sdata.h>
#include "bmp_header.h"
int sobel_fil_soft(int32_t x0y0, int32_t x1y0, int32_t x2y0, int32_t x0y1, int32_t x1y1, int32_t x2y1, int32_t x0y2, int32_t x1y2, int32_t x2y2);
int32_t conv_rgb2y_soft(int32_t rgb);
int32_t sobel_filter_axis_soft(hls::stream<ap_axis<32,1,1,1> >& ins, hls::stream<ap_axis<32,1,1,1> >& outs, int32_t width, int32_t height); // software
static const std::string error_message =
"Error: Result mismatch:\n"
"i = %d CPU result = %d Device result = %d\n";
//Some Library functions to be used.
template <typename T>
struct aligned_allocator
{
using value_type = T;
T* allocate(std::size_t num)
{
void* ptr = nullptr;
if (posix_memalign(&ptr,4096,num*sizeof(T)))
throw std::bad_alloc();
return reinterpret_cast<T*>(ptr);
}
void deallocate(T* p, std::size_t num)
{
free(p);
}
};
#define OCL_CHECK(error,call) \
call; \
if (error != CL_SUCCESS) { \
printf("%s:%d Error calling " #call ", error code is: %d\n", \
__FILE__,__LINE__, error); \
exit(EXIT_FAILURE); \
}
namespace xcl {
std::vector<cl::Device> get_devices(const std::string& vendor_name) {
size_t i;
cl_int err;
std::vector<cl::Platform> platforms;
OCL_CHECK(err, err = cl::Platform::get(&platforms));
cl::Platform platform;
for (i = 0 ; i < platforms.size(); i++){
platform = platforms[i];
OCL_CHECK(err, std::string platformName = platform.getInfo<CL_PLATFORM_NAME>(&err));
if (platformName == vendor_name){
std::cout << "Found Platform" << std::endl;
std::cout << "Platform Name: " << platformName.c_str() << std::endl;
break;
}
}
if (i == platforms.size()) {
std::cout << "Error: Failed to find Xilinx platform" << std::endl;
exit(EXIT_FAILURE);
}
//Getting ACCELERATOR Devices and selecting 1st such device
std::vector<cl::Device> devices;
OCL_CHECK(err, err = platform.getDevices(CL_DEVICE_TYPE_ACCELERATOR, &devices));
return devices;
}
std::vector<cl::Device> get_xil_devices() {
return get_devices("Xilinx");
}
char* read_binary_file(const std::string &xclbin_file_name, unsigned &nb)
{
std::cout << "INFO: Reading " << xclbin_file_name << std::endl;
if(access(xclbin_file_name.c_str(), R_OK) != 0) {
printf("ERROR: %s xclbin not available please build\n", xclbin_file_name.c_str());
exit(EXIT_FAILURE);
}
//Loading XCL Bin into char buffer
std::cout << "Loading: '" << xclbin_file_name.c_str() << "'\n";
std::ifstream bin_file(xclbin_file_name.c_str(), std::ifstream::binary);
bin_file.seekg (0, bin_file.end);
nb = bin_file.tellg();
bin_file.seekg (0, bin_file.beg);
char *buf = new char [nb];
bin_file.read(buf, nb);
return buf;
}
};
int main(int argc, char* argv[])
{
long x, y;
BITMAPFILEHEADER bmpfhr; // BMPファイルのファイルヘッダ(for Read)
BITMAPINFOHEADER bmpihr; // BMPファイルのINFOヘッダ(for Read)
FILE *fbmpr, *fbmpw;
int32_t blue, green, red;
const char* xclbinFilename;
hls::stream<ap_axis<32,1,1,1> > ins_soft;
hls::stream<ap_axis<32,1,1,1> > outs_soft;
ap_axis<32,1,1,1> pix;
ap_axis<32,1,1,1> vals_soft;
if (argc==2) {
xclbinFilename = argv[1];
std::cout <<"Using FPGA binary file specfied through the command line: " << xclbinFilename << std::endl;
}
else {
xclbinFilename = "../sobel_filter_axim.xclbin";
std::cout << "No FPGA binary file specified through the command line, using:" << xclbinFilename <<std::endl;
}
if ((fbmpr = fopen("test.bmp", "rb")) == NULL){ // test.bmp をオープン
fprintf(stderr, "Can't open test.bmp by binary read mode\n");
exit(1);
}
// bmpヘッダの読み出し
fread(&bmpfhr.bfType, sizeof(uint16_t), 1, fbmpr);
fread(&bmpfhr.bfSize, sizeof(uint32_t), 1, fbmpr);
fread(&bmpfhr.bfReserved1, sizeof(uint16_t), 1, fbmpr);
fread(&bmpfhr.bfReserved2, sizeof(uint16_t), 1, fbmpr);
fread(&bmpfhr.bfOffBits, sizeof(uint32_t), 1, fbmpr);
fread(&bmpihr, sizeof(BITMAPINFOHEADER), 1, fbmpr);
// ピクセルを入れるメモリをアロケートする
std::vector<int32_t,aligned_allocator<int32_t>> rd_bmp(bmpihr.biWidth * bmpihr.biHeight);
std::vector<int32_t,aligned_allocator<int32_t>> hw_sobel(bmpihr.biWidth * bmpihr.biHeight);
size_t size_in_bytes = (bmpihr.biWidth * bmpihr.biHeight) * sizeof(int32_t);
// rd_bmp にBMPのピクセルを代入。その際に、行を逆転する必要がある
for (y=0; y<bmpihr.biHeight; y++){
for (x=0; x<bmpihr.biWidth; x++){
blue = fgetc(fbmpr);
green = fgetc(fbmpr);
red = fgetc(fbmpr);
rd_bmp[((bmpihr.biHeight-1)-y)*bmpihr.biWidth+x] = (blue & 0xff) | ((green & 0xff)<<8) | ((red & 0xff)<<16);
}
}
fclose(fbmpr);
std::vector<cl::Device> devices = xcl::get_xil_devices();
cl::Device device = devices[0];
devices.resize(1);
// Creating Context and Command Queue for selected device
cl::Context context(device);
cl::CommandQueue q(context, device, CL_QUEUE_PROFILING_ENABLE);
// Load xclbin
std::cout << "Loading: '" << xclbinFilename << "'\n";
std::ifstream bin_file(xclbinFilename, std::ifstream::binary);
bin_file.seekg (0, bin_file.end);
unsigned nb = bin_file.tellg();
bin_file.seekg (0, bin_file.beg);
char *buf = new char [nb];
bin_file.read(buf, nb);
// Creating Program from Binary File
cl::Program::Binaries bins;
bins.push_back({buf,nb});
cl::Program program(context, devices, bins);
// This call will get the kernel object from program. A kernel is an
// OpenCL function that is executed on the FPGA.
cl::Kernel krnl_sobel_filter(program,"sobel_filter_axim");
// These commands will allocate memory on the Device. The cl::Buffer objects can
// be used to reference the memory locations on the device.
cl::Buffer rd_bmp_buf(context, CL_MEM_USE_HOST_PTR | CL_MEM_READ_ONLY,
size_in_bytes, rd_bmp.data());
cl::Buffer hw_sobel_buf(context, CL_MEM_USE_HOST_PTR | CL_MEM_READ_WRITE,
size_in_bytes, hw_sobel.data());
// Data will be transferred from system memory over PCIe to the FPGA on-board
// DDR memory.
q.enqueueMigrateMemObjects({rd_bmp_buf},0/* 0 means from host*/);
//set the kernel Arguments
krnl_sobel_filter.setArg(0,rd_bmp_buf);
krnl_sobel_filter.setArg(1,hw_sobel_buf);
cl::Event event;
uint64_t sobel_f_start, sobel_f_end;
//Launch the Kernel
q.enqueueTask(krnl_sobel_filter, NULL, &event);
// The result of the previous kernel execution will need to be retrieved in
// order to view the results. This call will transfer the data from FPGA to
// source_results vector
q.enqueueMigrateMemObjects({hw_sobel_buf},CL_MIGRATE_MEM_OBJECT_HOST);
q.finish();
// 時間計測
event.getProfilingInfo<uint64_t>(CL_PROFILING_COMMAND_START, &sobel_f_start);
event.getProfilingInfo<uint64_t>(CL_PROFILING_COMMAND_END, &sobel_f_end);
auto sobel_f_time = sobel_f_end - sobel_f_start;
printf("sobel_filter_axim: %lu ns\n", sobel_f_time);
// ソフトウェアとハードウェアのチェック
// ins_soft に入力データを用意する
for(int i=0; i<5; i++){ // dummy data
pix.user = 0;
pix.data = int32_t(i);
ins_soft << pix;
}
for(int j=0; j < bmpihr.biHeight; j++){
for(int i=0; i < bmpihr.biWidth; i++){
pix.data = rd_bmp[(j*bmpihr.biWidth)+i];
if (j==0 && i==0) // 最初のデータの時に TUSER を 1 にする
pix.user = 1;
else
pix.user = 0;
if (i == bmpihr.biWidth-1) // 行の最後でTLASTをアサートする
pix.last = 1;
else
pix.last = 0;
ins_soft << pix;
}
}
sobel_filter_axis_soft(ins_soft, outs_soft, bmpihr.biWidth, bmpihr.biHeight); // ソフトウェアのソーベル・フィルタ
// ハードウェアとソフトウェアのソーベル・フィルタの値のチェック
for (y=0; y<bmpihr.biHeight; y++){
for (x=0; x<bmpihr.biWidth; x++){
outs_soft >> vals_soft;
if (hw_sobel[y*bmpihr.biWidth+x] != vals_soft.data){
printf("ERROR HW and SW results mismatch x = %ld, y = %ld, HW = %d, SW = %d\n", x, y, int(hw_sobel[y*bmpihr.biWidth+x]), int(vals_soft.data));
//return(1);
}
}
}
printf("Success HW and SW results match\n");
// ハードウェアのソーベルフィルタの結果を temp_sobel.bmp へ出力する
if ((fbmpw=fopen("temp_sobel.bmp", "wb")) == NULL){
fprintf(stderr, "Can't open temp_sobel.bmp by binary write mode\n");
exit(1);
}
// BMPファイルヘッダの書き込み
fwrite(&bmpfhr.bfType, sizeof(uint16_t), 1, fbmpw);
fwrite(&bmpfhr.bfSize, sizeof(uint32_t), 1, fbmpw);
fwrite(&bmpfhr.bfReserved1, sizeof(uint16_t), 1, fbmpw);
fwrite(&bmpfhr.bfReserved2, sizeof(uint16_t), 1, fbmpw);
fwrite(&bmpfhr.bfOffBits, sizeof(uint32_t), 1, fbmpw);
fwrite(&bmpihr, sizeof(BITMAPINFOHEADER), 1, fbmpw);
// RGB データの書き込み、逆順にする
for (y=0; y<bmpihr.biHeight; y++){
for (x=0; x<bmpihr.biWidth; x++){
blue = hw_sobel[((bmpihr.biHeight-1)-y)*bmpihr.biWidth+x] & 0xff;
green = (hw_sobel[((bmpihr.biHeight-1)-y)*bmpihr.biWidth+x] >> 8) & 0xff;
red = (hw_sobel[((bmpihr.biHeight-1)-y)*bmpihr.biWidth+x]>>16) & 0xff;
fputc(blue, fbmpw);
fputc(green, fbmpw);
fputc(red, fbmpw);
}
}
fclose(fbmpw);
return(0);
}
#define HORIZONTAL 0
#define VERTICAL 1
int32_t sobel_fil(int32_t h_or_v, int32_t x0y0, int32_t x1y0, int32_t x2y0, int32_t x0y1,
int32_t x1y1, int32_t x2y1, int32_t x0y2, int32_t x1y2, int32_t x2y2);
int32_t conv_rgb2y(int32_t rgb);
int32_t square_root8(int32_t val);
#define DISPLAY_WIDTH 64
#define DISPLAY_HIGHT 48
int sobel_filter_axis_soft(hls::stream<ap_axis<32,1,1,1> >& ins, hls::stream<ap_axis<32,1,1,1> >& outs, int32_t width, int32_t height){
ap_axis<32,1,1,1> pix;
ap_axis<32,1,1,1> sobel;
int32_t **line_buf;
int32_t pix_mat[3][3];
int32_t sobel_val, sobel_h_val, sobel_v_val;
int32_t i;
// line_buf の1次元目の配列をアロケートする
if ((line_buf =(int32_t **)malloc(sizeof(int32_t *) * 2)) == NULL){
fprintf(stderr, "Can't allocate line_buf[3][]\n");
exit(1);
}
// メモリをアロケートする
for (i=0; i<2; i++){
if ((line_buf[i]=(int32_t *)malloc(sizeof(int32_t) * width)) == NULL){
fprintf(stderr, "Can't allocate line_buf[%d]\n", i);
exit(1);
}
}
do { // user が 1になった時にフレームがスタートする
ins >> pix;
} while(pix.user == 0);
for (int y=0; y<height; y++){
for (int x=0; x<width; x++){
if (!(x==0 && y==0)) // 最初の入力はすでに入力されている
ins >> pix; // AXI4-Stream からの入力
for (int k=0; k<3; k++){
for (int m=0; m<2; m++){
pix_mat[k][m] = pix_mat[k][m+1];
}
}
pix_mat[0][2] = line_buf[0][x];
pix_mat[1][2] = line_buf[1][x];
int32_t y_val = conv_rgb2y_soft(pix.data);
pix_mat[2][2] = y_val;
line_buf[0][x] = line_buf[1][x]; // 行の入れ替え
line_buf[1][x] = y_val;
sobel_h_val = sobel_fil(HORIZONTAL, pix_mat[0][0], pix_mat[0][1], pix_mat[0][2],
pix_mat[1][0], pix_mat[1][1], pix_mat[1][2],
pix_mat[2][0], pix_mat[2][1], pix_mat[2][2]);
sobel_v_val = sobel_fil(VERTICAL, pix_mat[0][0], pix_mat[0][1], pix_mat[0][2],
pix_mat[1][0], pix_mat[1][1], pix_mat[1][2],
pix_mat[2][0], pix_mat[2][1], pix_mat[2][2]);
sobel_val = square_root8(sobel_h_val*sobel_h_val + sobel_v_val*sobel_v_val);
sobel.data = (sobel_val<<16)+(sobel_val<<8)+sobel_val; // RGB同じ値を入れる
if (x<2 || y<2) // 最初の2行とその他の行の最初の2列は無効データなので0とする
sobel.data = 0;
if (x==0 && y==0) // 最初のデータでは、TUSERをアサートする
sobel.user = 1;
else
sobel.user = 0;
if (x == (width-1)) // 行の最後で TLAST をアサートする
sobel.last = 1;
else
sobel.last = 0;
outs << sobel; // AXI4-Stream へ出力
}
}
for (i=0; i<2; i++)
free(line_buf[i]);
free(line_buf);
return 0;
}
// RGBからYへの変換
// RGBのフォーマットは、{8'd0, R(8bits), G(8bits), B(8bits)}, 1pixel = 32bits
// 輝度信号Yのみに変換する。変換式は、Y = 0.299R + 0.587G + 0.114B
// "YUVフォーマット及び YUV<->RGB変換"を参考にした。http://vision.kuee.kyoto-u.ac.jp/~hiroaki/firewire/yuv.html
// 2013/09/27 : float を止めて、すべてint にした
int32_t conv_rgb2y_soft(int32_t rgb){
int32_t r, g, b, y_f;
int32_t y;
b = rgb & 0xff;
g = (rgb>>8) & 0xff;
r = (rgb>>16) & 0xff;
y_f = 77*r + 150*g + 29*b; //y_f = 0.299*r + 0.587*g + 0.114*b;の係数に256倍した
y = y_f >> 8; // 256で割る
return(y);
}
// sobel filter
// HORZONTAL
// x0y0 x1y0 x2y0 1 2 1
// x0y1 x1y1 x2y1 0 0 0
// x0y2 x1y2 x2y2 -1 -2 -1
// VERTICAL
// x0y0 x1y0 x2y0 1 0 -1
// x0y1 x1y1 x2y1 2 0 -2
// x0y2 x1y2 x2y2 1 0 -1
int32_t sobel_fil(int32_t h_or_v, int32_t x0y0, int32_t x1y0, int32_t x2y0, int32_t x0y1,
int32_t x1y1, int32_t x2y1, int32_t x0y2, int32_t x1y2, int32_t x2y2){
int32_t y;
if(h_or_v == HORIZONTAL){
y = x0y0 + 2*x1y0 + x2y0 - x0y2 - 2*x1y2 - x2y2;
} else {
y = x0y0 - x2y0 + 2*x0y1 - 2*x2y1 + x0y2 - x2y2;
}
if(y<0)
y = -y;
//y = 0;
else if(y>255)
y = 255;
return(y);
}
// square_root8
// 8bit幅のsquare_rootを求める
int32_t square_root8(int32_t val){
int32_t temp = 0;
int32_t square;
for(int i=7; i>=0; --i){
temp += (1 << i);
square = temp * temp;
if(square > val){
temp -= (1 << i);
}
}
return(temp);
}
all:
{
[destination_device = pl] lap_filter_axis_dma.bit
}
/dts-v1/; /plugin/;
/ {
fragment@0 {
target-path = "/fpga-full";
__overlay__ {
firmware-name = "lap_filter_axis_dma.bin";
};
};
fragment@1 {
target-path = "/amba_pl@0";
__overlay__ {
#address-cells = <2>;
#size-cells = <1>;
zyxclmm_drm {
compatible = "xlnx,zocl";
status = "okay";
reg = <0x0 0xA0000000 0x10000>;
};
fclk0 {
compatible = "ikwzm,fclkcfg-0.10.a";
clocks = <&zynqmp_clk 0x47>;
insert-rate = "100000000";
insert-enable = <1>;
remove-rate = "1000000";
remove-enable = <0>;
};
};
};
};
[ 2015.009428] fpga_manager fpga0: writing streaming_lap_filter5.bin to Xilinx ZynqMP FPGA Manager
[ 2015.409550] zocl: loading out-of-tree module taints kernel.
[ 2015.411669] fclkcfg amba_pl@0:fclk0: driver installed.
[ 2015.411678] fclkcfg amba_pl@0:fclk0: device name : amba_pl@0:fclk0
[ 2015.411683] fclkcfg amba_pl@0:fclk0: clock name : pl0_ref
[ 2015.411688] fclkcfg amba_pl@0:fclk0: clock rate : 99999999
[ 2015.411712] fclkcfg amba_pl@0:fclk0: clock enabled : 1
[ 2015.411716] fclkcfg amba_pl@0:fclk0: remove rate : 1000000
[ 2015.411720] fclkcfg amba_pl@0:fclk0: remove enable : 0
[ 2015.414984] [drm] Probing for xlnx,zocl
[ 2015.415083] [drm] FPGA programming device pcap founded.
[ 2015.415088] [drm] PR Isolation addr 0x0
[ 2015.415872] [drm] Initialized zocl 2018.2.1 20180313 for a0000000.zyxclmm_drm on minor 1
[ 2015.423517] [drm] Pid 3305 opened device
[ 2015.423591] [drm] Pid 3305 closed device
[ 2015.432958] [drm] Pid 3305 opened device
[ 2015.433029] [drm] Pid 3305 closed device
root@ultra96v2_min2:~# insmod /lib/modules/4.19.0-xilinx-v2019.2/extra/zocl.ko
[ 466.982846] zocl: loading out-of-tree module taints kernel.
[ 466.992109] [drm] Probing for xlnx,zocl
[ 466.996088] [drm] FPGA programming device pcap founded.
[ 467.001317] [drm] PR Isolation addr 0x0
[ 467.002257] [drm] Initialized zocl 2018.2.1 20180313 for a0000000.zyxclmm_drm on minor 1
root@ultra96v2_min2:~# [ 491.788490] [drm] Pid 2226 opened device
[ 491.792482] [drm] Pid 2226 closed device
[ 491.796850] [drm] Pid 2226 opened device
[ 492.438433] [drm] Finding IP_LAYOUT section header
[ 492.438445] [drm] Section IP_LAYOUT details:
[ 492.443273] [drm] offset = 0x54fcf8
[ 492.447538] [drm] size = 0x58
[ 492.451233] [drm] Finding DEBUG_IP_LAYOUT section header
[ 492.454371] [drm] AXLF section DEBUG_IP_LAYOUT header not found
[ 492.459676] [drm] Finding CONNECTIVITY section header
[ 492.465593] [drm] Section CONNECTIVITY details:
[ 492.470636] [drm] offset = 0x54fd50
[ 492.475157] [drm] size = 0x1c
[ 492.478818] [drm] Finding MEM_TOPOLOGY section header
[ 492.481954] [drm] Section MEM_TOPOLOGY details:
[ 492.486997] [drm] offset = 0x54fc00
[ 492.491524] [drm] size = 0xf8
[ 492.496753] [drm] No ERT scheduler on MPSoC, using KDS
[ 492.505441] [drm] Fail to install CU 0 interrupt handler: -22. Fall back to polling mode.
[ 492.513613] [drm] scheduler config ert(0)
[ 492.513621] [drm] cus(1)
[ 492.517620] [drm] slots(16)
[ 492.520320] [drm] num_cu_masks(1)
[ 492.523282] [drm] cu_shift(16)
[ 492.526762] [drm] cu_base(0xa0000000)
[ 492.529989] [drm] polling(1)
[ 492.541388] [drm] User buffer is not physical contiguous
[ 492.549762] [drm] zocl_free_userptr_bo: obj 0x00000000a9266c65
[ 492.551015] [drm] User buffer is not physical contiguous
[ 492.562152] [drm] zocl_free_userptr_bo: obj 0x0000000024b2256c
[ 492.580506] [drm] Pid 2226 closed device
alias xsdk='env SWT_GTK3=0 xsdk'
alias vivado='env SWT_GTK3=0 vivado'
export DISPLAY=localhost:0.0
sudo sed -i.bak -e "s%http://archive.ubuntu.com/ubuntu/%http://ftp.iij.ad.jp/pub/linux/ubuntu/archive/%g" /etc/apt/sources.list
sudo apt update
sudo apt upgrade
sudo apt install -y language-pack-ja
sudo update-locale LANG=ja_JP.UTF-8
sudo apt install -y git build-essential libssl-dev libreadline-dev zlib1g-dev x11-apps x11-utils x11-xserver-utils libsqlite3-dev nodejs fonts-ipafont libxml2-dev libxslt1-dev
sudo apt install -y fcitx-mozc fonts-noto-cjk fonts-noto-color-emoji dbus-x11
sudo sh -c "dbus-uuidgen > /var/lib/dbus/machine-id"
echo 'export GTK_IM_MODULE=fcitx' >> .profile
echo 'export QT_IM_MODULE=fcitx' >> .profile
echo 'export XMODIFIERS=@im=fcitx' >> .profile
echo 'export DefaultIMModule=fcitx' >> .profile
source .profile
fcitx-autostart
リターンキーを押さないとプロンプトが出なかった。
fcitx-config-gtk3
/usr/lib/mozc/mozc_tool --mode=config_dialog
source /mnt/c/WSL/tools/Xilinx/Vitis/2019.2/settings64.sh
source /opt/xilinx/xrt/setup.sh
fpga@ubuntu-fpga:~/work/XRT/build/Edge$ sudo dpkg -i xrt_202010.2.6.0_Ubuntu_18.04-arm64-xrt.deb
Selecting previously unselected package xrt.
(Reading database ... 96811 files and directories currently installed.)
Preparing to unpack xrt_202010.2.6.0_Ubuntu_18.04-arm64-xrt.deb ...
Unpacking xrt (2.6.0) ...
Setting up xrt (2.6.0) ...
Unloading old XRT Linux kernel modules
rmmod: ERROR: Module zocl is not currently loaded
Invoking DKMS common.postinst for xrt
Loading new xrt-2.6.0 DKMS files...
Building for 4.19.0-xlnx-v2019.2-zynqmp-fpga
Building initial module for 4.19.0-xlnx-v2019.2-zynqmp-fpga
Done.
zocl:
Running module version sanity check.
- Original module
- No original module exists within this kernel
- Installation
- Installing to /lib/modules/4.19.0-xlnx-v2019.2-zynqmp-fpga/updates/dkms/
depmod...
DKMS: install completed.
Finished DKMS common.postinst
Loading new XRT Linux kernel modules
Skipping pyopencl installation...
fpga@ubuntu-fpga:~/work/XRT/build/Edge$
/dts-v1/; /plugin/;
/ {
fragment@0 {
target-path = "/fpga-full";
__overlay__ {
firmware-name = "streaming_lap_filter5.bin";
};
};
fragment@1 {
target-path = "/amba_pl@0";
__overlay__ {
#address-cells = <2>;
#size-cells = <1>;
zyxclmm_drm {
compatible = "xlnx,zocl";
status = "okay";
reg = <0x0 0xA0000000 0x10000>;
};
fclk0 {
compatible = "ikwzm,fclkcfg-0.10.a";
clocks = <&zynqmp_clk 0x47>;
insert-rate = "100000000";
insert-enable = <1>;
remove-rate = "1000000";
remove-enable = <0>;
};
};
};
};
fpga@ubuntu-fpga:~/work/XRT/build$ ./build.sh -edge
cmake -DRDI_CCACHE=0 -DCMAKE_BUILD_TYPE=Release -DCMAKE_EXPORT_COMPILE_COMMANDS=ON ../../src
-- The C compiler identification is GNU 8.4.0
-- The CXX compiler identification is GNU 8.4.0
-- Check for working C compiler: /usr/bin/gcc-8
-- Check for working C compiler: /usr/bin/gcc-8 -- works
-- Detecting C compiler ABI info
-- Detecting C compiler ABI info - done
-- Detecting C compile features
-- Detecting C compile features - done
-- Check for working CXX compiler: /usr/bin/g++-8
-- Check for working CXX compiler: /usr/bin/g++-8 -- works
-- Detecting CXX compiler ABI info
-- Detecting CXX compiler ABI info - done
-- Detecting CXX compile features
-- Detecting CXX compile features - done
-- Host system processor is aarch64
-- Target system processor is aarch64
-- XRT_NATIVE_BUILD is yes
-- XRT_EDGE_BUILD is yes
-- Found PkgConfig: /usr/bin/pkg-config (found version "0.29.1")
-- Checking for module 'libdrm'
-- Found libdrm, version 2.4.99
-- Looking for DRM - found at /usr 2.4.99
-- Checking for module 'OpenCL'
-- Found OpenCL, version 2.1
-- Looking for OPENCL - found at /usr 2.1 /usr/include
-- Found Git: /usr/bin/git (found version "2.17.1")
-- Looking for GIT - found at /usr/bin/git
-- Boost version: 1.65.1
-- Boost version: 1.65.1
-- Found the following Boost libraries:
-- system
-- filesystem
-- Found Curses: /usr/lib/aarch64-linux-gnu/libcurses.so
-- XRT CL extension header files
-- include/1_2/CL/cl_ext_xilinx.h
-- include/1_2/CL/cl_ext.h
-- XRT EA eula files /home/fpga/work/XRT/src/../LICENSE
-- Platform/Linux (Ubuntu) (Kernel 4.19.0-xlnx-v2019.2-zynqmp-fpga)
-- Compiler: /usr/bin/g++-8 /usr/bin/gcc-8
-- kernel-doc downloading
-- Boost version: 1.65.1
-- Found the following Boost libraries:
-- system
-- filesystem
-- program_options
-- Found OpenSSL: /usr/lib/aarch64-linux-gnu/libcrypto.a (found version "1.1.1")
-- Found ZLIB: /usr/lib/aarch64-linux-gnu/libz.so (found version "1.2.11")
-- Looking for pthread.h
-- Looking for pthread.h - found
-- Looking for pthread_create
-- Looking for pthread_create - not found
-- Check if compiler accepts -pthread
-- Check if compiler accepts -pthread - yes
-- Found Threads: TRUE
-- Could NOT find GTest (missing: GTEST_LIBRARY GTEST_MAIN_LIBRARY)
-- GTest was not found, skipping generation of test executables
-- XRT xrt++ header files
-- xrt++.hpp
-- xrtexec.hpp
CMake Warning at runtime_src/ert/CMakeLists.txt:49 (message):
****************************************************************
No firmware files built or copied, resulting XRT package will be missing
ERT scheduler firmware. Use build.sh -ertfw <dir> to specify path to a
directory with firmware to copy during XRT build.
****************************************************************
-- XRT header files
-- ert.h
-- xstream.h
-- types.h
-- xcl_axi_checker_codes.h
-- xclbin.h
-- xclerr.h
-- xclfeatures.h
-- xclhal2.h
-- xrt.h
-- xcl_app_debug.h
-- xcl_macros.h
-- xcl_app_debug.h
-- xclperf.h
-- xclhal2_mem.h
-- xrt_mem.h
-- XRT experimental header files
-- xrt-next.h
-- xrt_aie.h
-- xrt_kernel.h
-- xclbin-util.h
-- XRT OS native header files
-- types.h
-- uuid.h
bfl=/usr/lib/aarch64-linux-gnu/libboost_filesystem.a
-- XRT header files for MPSoC only
-- xclhal2_mpsoc.h
-- sk_types.h
-- Found Protobuf: /usr/lib/aarch64-linux-gnu/libprotobuf.so;-pthread (found version "3.0.0")
-- Found Protobuf: /usr/lib/aarch64-linux-gnu/libprotobuf.so;-pthread;-pthread (found version "3.0.0")
-- Found LibXml2: /usr/lib/aarch64-linux-gnu/libxml2.so (found suitable version "2.9.4", minimum required is "2.9.1")
-- Checking for modules 'json-glib-1.0;glib-2.0'
-- Found json-glib-1.0, version 1.4.2
-- Found glib-2.0, version 2.56.4
-- XRT version: 2.6.0
-- Release DEB package
CMake Warning at CMake/lint.cmake:10 (message):
-- run-clang-tidy not found, static code analysis disabled
Call Stack (most recent call first):
CMake/nativeLnx.cmake:144 (include)
CMakeLists.txt:79 (include)
-- XRT DRIVER SRC BASE DIR /home/fpga/work/XRT/src/runtime_src/core
-- Preparing OpenCL ICD xilinx.icd
-- Preparing XRT pkg-config
CMake Warning at CMake/coverity.cmake:5 (message):
-- coverity not found
Call Stack (most recent call first):
CMake/nativeLnx.cmake:167 (include)
CMakeLists.txt:79 (include)
-- Configuring done
-- Generating done
-- Build files have been written to: /home/fpga/work/XRT/build/Edge
real 0m15.918s
user 0m8.948s
sys 0m2.781s
make -j 4 DESTDIR=/home/fpga/work/XRT/build/Edge
Scanning dependencies of target xclbin
Scanning dependencies of target xrt_docs
Scanning dependencies of target xrt_coreutil
Scanning dependencies of target xocl
[ 0%] Generating core/mailbox.rst
...........................
[100%] Linking CXX executable xbtest
[100%] Built target xbtest
real 29m23.585s
user 109m17.732s
sys 3m43.529s
Test project /home/fpga/work/XRT/build/Edge
No tests were found!!!
real 0m0.310s
user 0m0.039s
sys 0m0.028s
[ 0%] Generating documentation with Sphinx
Running Sphinx v1.6.7
loading pickled environment... done
building [mo]: all of 0 po files
building [html]: all source files
updating environment: 0 added, 33 changed, 0 removed
reading sources... [100%] zocl_ioctl.main
looking for now-outdated files... none found
pickling environment... done
checking consistency... /home/fpga/work/XRT/build/Edge/runtime_src/doc/toc/newxsa-bringup.rst: WARNING: document isn't included in any toctree
done
preparing documents... done
writing output... [100%] zocl_ioctl.main
WARNING: dot command 'dot' cannot be run (needed for graphviz output), check the graphviz_dot setting
generating indices... genindex
writing additional pages... search
copying images... [100%] ap_ctrl_chain_2.PNG
copying static files... done
copying extra files... done
dumping search index in English (code: en) ... done
dumping object inventory... done
build succeeded, 2 warnings.
[ 2%] Built target xrt_docs
[ 6%] Built target xrt_coreutil
[ 12%] Built target xdp_core
[ 13%] Built target xdp_lop_plugin
[ 14%] Built target xclbin
[ 48%] Built target xocl
[ 50%] Built target xrt++
[ 51%] Built target xilinxopencl
[ 52%] Built target xdp_debug_plugin
[ 59%] Built target xdp
[ 60%] Built target oclxdp
[ 61%] Built target xdp_appdebug_plugin
[ 62%] Built target xdp_hal_plugin
[ 63%] Built target core_edgeuser_plugin_xdp_objects
[ 63%] Built target core_common_objects
[ 64%] Built target core_edge_common_objects
[ 65%] Built target xrt_core
[ 66%] Built target xdp_hal_api_interface_plugin
[ 67%] Built target xclbinsplit
[ 68%] Built target xclbincat
[ 77%] Built target xclbinutil
[ 81%] Built target xrt_coreutil_static
[ 81%] Built target core_edgeuser_plugin_xdp_no_dl_load_objects
[ 82%] Built target xrt_core_static
[ 83%] Built target common_em_objects
[ 83%] Built target generated_code
[ 83%] Built target common_em
[ 85%] Built target hw_emu_objects
[ 85%] Built target xrt_hwemu
[ 86%] Built target sw_emu_objects
[ 87%] Built target xrt_swemu
[ 88%] Built target skd
[ 88%] Built target xbutil
[ 89%] Built target xma2plugin
[ 92%] Built target xma2api
[ 93%] Built target xmaplugin
[ 96%] Built target xmaapi
[100%] Built target xbtest
Run CPack packaging tool...
CPack: Create package using DEB
CPack: Install projects
CPack: - Run preinstall target for: XRT
CPack: - Install project: XRT
CPack: - Install component: xbtest
CPack: - Install component: xrt
CPack: Create package
CPack: - package: /home/fpga/work/XRT/build/Edge/xrt_202010.2.6.0_Ubuntu_18.04-arm64-xbtest.deb generated.
CPack: - package: /home/fpga/work/XRT/build/Edge/xrt_202010.2.6.0_Ubuntu_18.04-arm64-xrt.deb generated.
CPack: Create package using TGZ
CPack: Install projects
CPack: - Run preinstall target for: XRT
CPack: - Install project: XRT
CPack: - Install component: xbtest
CPack: - Install component: xrt
CPack: Create package
CPack: - package: /home/fpga/work/XRT/build/Edge/xrt_202010.2.6.0_Ubuntu_18.04-arm64-xbtest.tar.gz generated.
CPack: - package: /home/fpga/work/XRT/build/Edge/xrt_202010.2.6.0_Ubuntu_18.04-arm64-xrt.tar.gz generated.
real 2m29.989s
user 2m13.468s
sys 0m6.820s
fpga@ubuntu-fpga:~/work/XRT/build$
#linux_boot_args_console=console=tty1
linux_boot_args_console=console=ttyPS0,115200
root@ultra96v2_min2:~/sd_card# ./init.sh
INFO: Running OpenCL section.
Found Platform
Platform Name: Xilinx
INFO: Device found - edge
XCLBIN File Name: krnl_stereopipeline
INFO: Importing xclbin_ultra96v2_min2_hw/krnl_stereopipeline.xclbin
Loading: 'xclbin_ultra96v2_min2_hw/krnl_stereopipeline.xclbin'
run complete !
root@ultra96v2_min2:~# [ 111.715443] zocl: loading out-of-tree module taints kernel.
[ 111.724722] [drm] Probing for xlnx,zocl
[ 111.728723] [drm] FPGA programming device pcap founded.
[ 111.733956] [drm] PR Isolation addr 0x0
[ 111.734724] [drm] Initialized zocl 2018.2.1 20180313 for a0000000.zyxclmm_drm on minor 1
[ 158.828342] [drm] Pid 2204 opened device
[ 158.832310] [drm] Pid 2204 closed device
[ 158.847453] [drm] Pid 2204 opened device
[ 159.147138] [drm] Finding IP_LAYOUT section header
[ 159.147150] [drm] Section IP_LAYOUT details:
[ 159.151965] [drm] offset = 0x54fcf8
[ 159.156224] [drm] size = 0x58
[ 159.159886] [drm] Finding DEBUG_IP_LAYOUT section header
[ 159.163021] [drm] AXLF section DEBUG_IP_LAYOUT header not found
[ 159.168326] [drm] Finding CONNECTIVITY section header
[ 159.174243] [drm] Section CONNECTIVITY details:
[ 159.179287] [drm] offset = 0x54fd50
[ 159.183807] [drm] size = 0x7c
[ 159.187468] [drm] Finding MEM_TOPOLOGY section header
[ 159.190605] [drm] Section MEM_TOPOLOGY details:
[ 159.195649] [drm] offset = 0x54fc00
[ 159.200169] [drm] size = 0xf8
[ 159.211895] [drm] No ERT scheduler on MPSoC, using KDS
[ 159.220541] [drm] Fail to install CU 0 interrupt handler: -22. Fall back to polling mode.
[ 159.228716] [drm] scheduler config ert(0)
[ 159.228723] [drm] cus(1)
[ 159.232729] [drm] slots(16)
[ 159.235429] [drm] num_cu_masks(1)
[ 159.238387] [drm] cu_shift(16)
[ 159.241862] [drm] cu_base(0xa0000000)
[ 159.245083] [drm] polling(1)
[ 159.424457] [drm] Pid 2204 closed device
1. Vitis のインストール・ディレクトリの settings64.sh を実行
source /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/settings64.sh
2. XRT の setenv.sh を実行
source /opt/xilinx/xrt/setup.sh
3. DEVICE 環境変数にプラットフォームの xpfm ファイルへのパスを設定する
export DEVICE=/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm
4. SYSROOT にプラットフォームの sysroot へのパスを設定する。
export SYSROOT=/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux
だった。ERROR: [v++ 82-216] Invalid integer value for clock.defaultFreqHz option: -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline
v++ -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/xo_ultra96v2_min2_hw/stereopipeline_accel.xo --kernel stereopipeline_accel --compile /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_accel.cpp \
-I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/include -I. -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include -D__SDSVHLS__ -DHLS_NO_XIL_FPO_LIB --clock.defaultFreqHz -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline --target hw --platform /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm --temp_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw --save-temps --debug --kernel_frequency 300 --report_level 2 --xp
v++ -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/pyr_dense_optical_flow_accel.xo --kernel pyr_dense_optical_flow_accel --compile /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_pyr_dense_optical_flow_accel.cpp \
-I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/include -I. -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include -D__SDSVHLS__ -DHLS_NO_XIL_FPO_LIB --xp vivado_prop:run.impl_1.strategy=Performance_Explore --clock.defaultFreqHz 300000000 -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker --target hw --platform /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm --temp_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw --save-temps --debug --kernel_frequency 300 --report_level 2
を追加して、 204 行目をコメントアウトした。VPP_CFLAGS += --clock.defaultFreqHz 300000000
を削除した。$(B_NAME)/sw/$(XDEVICE)/xrt/image/*
masaaki@masaaki-H110M4-M01:/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build$ make host xclbin TARGET=hw BOARD=Zynq ARCH=aarch64
-e ----
Compiling object xf_stereo_pipeline_tb...
mkdir -p /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/obj_ultra96v2_min2
aarch64-linux-gnu-g++ -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/obj_ultra96v2_min2/xf_stereo_pipeline_tb.o -c /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_tb.cpp -D XDEVICE=ultra96v2_min2 -DVIVADO_HLS_SIM -D__SDSVHLS__ -DHLS_NO_XIL_FPO_LIB -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/include -I. -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2 -g --sysroot=/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux -D__ZYNQ -std=c++14 -fPIC -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline -I/opt/xilinx/xrt/include -Wall -Wno-unknown-pragmas -Wno-unused-label -pthread -idirafter /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vivado/2019.2/include
In file included from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include/common/xf_headers.hpp:30,
from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_tb.cpp:17:
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include/common/xf_sw_utils.hpp: 関数 ‘void xf::cv::analyzeDiff(cv::Mat&, int, float&)’ 内:
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include/common/xf_sw_utils.hpp:150:23: 警告: 変数 ‘v_tmp1’ が設定されましたが使用されていません [-Wunused-but-set-variable]
float v_tmp1;
^~~~~~
In file included from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_tb.cpp:21:
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_tb.cpp: 関数 ‘int main(int, char**)’ 内:
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_tb.cpp:113:96: 警告: ISO C++ says that these are ambiguous, even though the worst conversion for the first is better than the worst conversion for the second:
cl::Buffer imageToDeviceL(context, CL_MEM_READ_ONLY, rows * cols, NULL, &err));
^
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2/xcl2.hpp:41:5: 備考: in definition of macro ‘OCL_CHECK’
call; \
^~~~
In file included from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2/xcl2.hpp:48,
from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_tb.cpp:21:
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:3675:5: 備考: 候補 1: ‘cl::Buffer::Buffer(const cl::Context&, cl_mem_flags, cl::size_type, void*, cl_int*)’
Buffer(
^~~~~~
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:8512:1: 備考: 候補 2: ‘cl::Buffer::Buffer(const cl::Context&, IteratorType, IteratorType, bool, bool, cl_int*) [with IteratorType = int; cl_int = int]’
Buffer::Buffer(
^~~~~~
In file included from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_tb.cpp:21:
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_tb.cpp:114:96: 警告: ISO C++ says that these are ambiguous, even though the worst conversion for the first is better than the worst conversion for the second:
cl::Buffer imageToDeviceR(context, CL_MEM_READ_ONLY, rows * cols, NULL, &err));
^
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2/xcl2.hpp:41:5: 備考: in definition of macro ‘OCL_CHECK’
call; \
^~~~
In file included from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2/xcl2.hpp:48,
from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_tb.cpp:21:
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:3675:5: 備考: 候補 1: ‘cl::Buffer::Buffer(const cl::Context&, cl_mem_flags, cl::size_type, void*, cl_int*)’
Buffer(
^~~~~~
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:8512:1: 備考: 候補 2: ‘cl::Buffer::Buffer(const cl::Context&, IteratorType, IteratorType, bool, bool, cl_int*) [with IteratorType = int; cl_int = int]’
Buffer::Buffer(
^~~~~~
In file included from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_tb.cpp:21:
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_tb.cpp:115:102: 警告: ISO C++ says that these are ambiguous, even though the worst conversion for the first is better than the worst conversion for the second:
ffer imageFromDevice(context, CL_MEM_WRITE_ONLY, rows * cols * 2, NULL, &err));
^
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2/xcl2.hpp:41:5: 備考: in definition of macro ‘OCL_CHECK’
call; \
^~~~
In file included from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2/xcl2.hpp:48,
from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_tb.cpp:21:
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:3675:5: 備考: 候補 1: ‘cl::Buffer::Buffer(const cl::Context&, cl_mem_flags, cl::size_type, void*, cl_int*)’
Buffer(
^~~~~~
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:8512:1: 備考: 候補 2: ‘cl::Buffer::Buffer(const cl::Context&, IteratorType, IteratorType, bool, bool, cl_int*) [with IteratorType = int; cl_int = int]’
Buffer::Buffer(
^~~~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_tb.cpp:158:14: 警告: unused variable ‘start’ [-Wunused-variable]
cl_ulong start = 0;
^~~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_tb.cpp:159:14: 警告: unused variable ‘end’ [-Wunused-variable]
cl_ulong end = 0;
^~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_tb.cpp:160:12: 警告: unused variable ‘diff_prof’ [-Wunused-variable]
double diff_prof = 0.0f;
^~~~~~~~~
-e ----
Compiling extra object /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/obj_ultra96v2_min2/xcl2.o...
mkdir -p /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/obj_ultra96v2_min2
aarch64-linux-gnu-g++ -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/obj_ultra96v2_min2/xcl2.o -c /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2/xcl2.cpp -D XDEVICE=ultra96v2_min2 -DVIVADO_HLS_SIM -D__SDSVHLS__ -DHLS_NO_XIL_FPO_LIB -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/include -I. -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2 -g --sysroot=/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux -D__ZYNQ -std=c++14 -fPIC -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline -I/opt/xilinx/xrt/include -Wall -Wno-unknown-pragmas -Wno-unused-label -pthread -idirafter /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vivado/2019.2/include -I /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2
-e ----
Compiling host stereopipeline.exe...
mkdir -p /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/bin_ultra96v2_min2
aarch64-linux-gnu-g++ -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/bin_ultra96v2_min2/stereopipeline.exe /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/obj_ultra96v2_min2/xf_stereo_pipeline_tb.o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/obj_ultra96v2_min2/xcl2.o -D XDEVICE=ultra96v2_min2 -DVIVADO_HLS_SIM -D__SDSVHLS__ -DHLS_NO_XIL_FPO_LIB -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/include -I. -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2 -g --sysroot=/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux -D__ZYNQ -std=c++14 -fPIC -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline -I/opt/xilinx/xrt/include -Wall -Wno-unknown-pragmas -Wno-unused-label -pthread -idirafter /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vivado/2019.2/include -L/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/lib -Wl,-rpath-link=/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/lib/ -L/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/opt/xilinx/xrt/lib -lopencv_imgcodecs -lopencv_core -lopencv_imgproc -lopencv_highgui -lopencv_calib3d -lopencv_features2d -lopencv_flann -pthread -L/opt/xilinx/xrt/lib -lxilinxopencl
-e ----
Compiling kernel stereopipeline_accel...
mkdir -p /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/xo_ultra96v2_min2_hw
v++ -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/xo_ultra96v2_min2_hw/stereopipeline_accel.xo --kernel stereopipeline_accel --compile /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_accel.cpp \
-I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/include -I. -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include -D__SDSVHLS__ -DHLS_NO_XIL_FPO_LIB --clock.defaultFreqHz 300000000 -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline --target hw --platform /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm --temp_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw --save-temps --debug --kernel_frequency 300 --report_level 2 --xp vivado_prop:run.impl_1.strategy=Performance_Explore
WARNING: [v++ 60-1600] The option 'xp' was used directly on the command line, where its usage is deprecated. To ensure input line works for supported operating systems or shells, v++ supports specification for some options in a configuration file. As an alternative, please use options 'advanced.*', 'vivado.*' in a configuration file. Use one or more configuration files along with section headers to define key-value pairs for the advanced properties or parameters. Specify a configuration file using '--config'.
INFO: [v++ 84-14] Sample config file already exists. To regenerate, remove file 'sample_compile.ini'.
Option Map File Used: '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/data/vitis/vpp/optMap.xml'
****** v++ v2019.2 (64-bit)
**** SW Build 2700185 on Thu Oct 24 18:45:48 MDT 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
INFO: [v++ 60-1306] Additional information associated with this v++ compile can be found at:
Reports: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/reports/stereopipeline_accel
Log files: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/logs/stereopipeline_accel
Running Dispatch Server on port:46767
INFO: [v++ 60-1548] Creating build summary session with primary output /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/xo_ultra96v2_min2_hw/stereopipeline_accel.xo.compile_summary, at Thu Apr 2 20:05:40 2020
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Thu Apr 2 20:05:41 2020
Running Rule Check Server on port:42075
INFO: [v++ 60-1315] Creating rulecheck session with output '/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/reports/stereopipeline_accel/v++_compile_stereopipeline_accel_guidance.html', at Thu Apr 2 20:05:42 2020
INFO: [v++ 60-895] Target platform: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm
INFO: [v++ 60-1578] This platform contains Xilinx Shell Archive '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/hw/ultra96v2_min2.xsa'
INFO: [v++ 60-585] Compiling for hardware target
INFO: [v++ 60-423] Target device: ultra96v2_min2
INFO: [v++ 60-242] Creating kernel: 'stereopipeline_accel'
INFO: [v++ 60-1616] Creating a HLS clock using kernel_frequency option: 300 MHz
===>The following messages were generated while performing high-level synthesis for kernel: stereopipeline_accel Log file: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/stereopipeline_accel/stereopipeline_accel/vivado_hls.log :
INFO: [v++ 204-61] Option 'relax_ii_for_timing' is enabled, will increase II to preserve clock frequency constraints.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
WARNING: [v++ 204-69] Unable to schedule bus request on port 'irA_r' (/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_accel.cpp:57->/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_accel.cpp:31) due to limited memory ports. Please consider using a memory core with more ports or partitioning the array.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 4, Depth = 19.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
WARNING: [v++ 204-69] Unable to schedule bus request on port 'distC_r' (/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_accel.cpp:66->/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_accel.cpp:31) due to limited memory ports. Please consider using a memory core with more ports or partitioning the array.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 2, Depth = 17.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining loop 'L1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 4.
INFO: [v++ 204-61] Pipelining function 'xFComputeUndistortCoordinates'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 49.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [v++ 204-61] Pipelining loop 'Loop 2'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [v++ 204-61] Pipelining loop 'loop_height_loop_width'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 58.
INFO: [v++ 204-61] Pipelining loop 'memset_r1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining loop 'memset_r2'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining loop 'loop_width'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 30.
INFO: [v++ 204-61] Pipelining loop 'memset_r1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining loop 'memset_r2'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining loop 'loop_width'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 30.
INFO: [v++ 204-61] Pipelining function 'xFGradientX3x3<0, 3>'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining function 'xFGradientY3x3<0, 3>'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining function 'xFSobel3x3<1, 1, 0, 3>'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining loop 'Clear_Row_Loop'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining loop 'Col_Loop'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 7.
INFO: [v++ 204-61] Pipelining function 'xFImageClipUtility<1>'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining loop 'loop_col_clip'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 5.
INFO: [v++ 204-61] Pipelining loop 'loop_col_clip'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [v++ 204-61] Pipelining loop 'loop_col_clip'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 5.
INFO: [v++ 204-61] Pipelining loop 'loop_col_clip'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [v++ 204-61] Pipelining loop 'loop_row_loop_mux_loop_col'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 76.
INFO: [v++ 204-61] Pipelining function 'write'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [v++ 204-61] Pipelining loop 'L1'.
INFO: [v++ 204-61] Discarding stage scheduling solution.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 2, Depth = 4.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 200-790] **** Loop Constraint Status: All loop constraints were NOT satisfied.
INFO: [v++ 200-789] **** Estimated Fmax: 302.02 MHz
INFO: [v++ 60-594] Finished kernel compilation
INFO: [v++ 60-244] Generating system estimate report...
INFO: [v++ 60-1092] Generated system estimate report: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/reports/stereopipeline_accel/system_estimate_stereopipeline_accel.xtxt
Add Instance StereoBM_15_48_16_0_1_1080_1920_1_false_s StereoBM_15_48_16_0_1_1080_1920_1_false_U0 1224
Add Instance xFFindStereoCorrespondenceLBMNO_1080_1920_0_1_1_15_48_16_3_false_s grp_xFFindStereoCorrespondenceLBMNO_1080_1920_0_1_1_15_48_16_3_false_s_fu_202 202
Add Instance xFSADBlockMatching xFSADBlockMatching_U0 838
Add Instance Sobel_0_3_0_2_1080_1920_1_false_2551550 Sobel_0_3_0_2_1080_1920_1_false_2551550_U0 851
Add Instance xFSobelFilter3x3_0_2_1080_1920_1_0_3_1_1_5_1920_false_1557 grp_xFSobelFilter3x3_0_2_1080_1920_1_0_3_1_1_5_1920_false_1557_fu_94 94
Add Instance xFSobel3x3_1_1_0_3_s call_ret_xFSobel3x3_1_1_0_3_s_fu_426 426
Add Instance xFGradientX3x3_0_3_s GradientvaluesX_V_write_assign_xFGradientX3x3_0_3_s_fu_72 72
Add Instance xFGradientY3x3_0_3_s GradientvaluesY_V_write_assign_xFGradientY3x3_0_3_s_fu_88 88
Add Instance xFGradientX3x3_0_3_s GradientValuesX_0_V_xFGradientX3x3_0_3_s_fu_443 443
Add Instance xFGradientY3x3_0_3_s GradientValuesY_0_V_xFGradientY3x3_0_3_s_fu_459 459
Add Instance Sobel_0_3_0_2_1080_1920_1_false_1553 Sobel_0_3_0_2_1080_1920_1_false_1553_U0 861
Add Instance xFSobelFilter3x3_0_2_1080_1920_1_0_3_1_1_5_1920_false_1557 grp_xFSobelFilter3x3_0_2_1080_1920_1_0_3_1_1_5_1920_false_1557_fu_94 94
Add Instance xFSobel3x3_1_1_0_3_s call_ret_xFSobel3x3_1_1_0_3_s_fu_426 426
Add Instance xFGradientX3x3_0_3_s GradientvaluesX_V_write_assign_xFGradientX3x3_0_3_s_fu_72 72
Add Instance xFGradientY3x3_0_3_s GradientvaluesY_V_write_assign_xFGradientY3x3_0_3_s_fu_88 88
Add Instance xFGradientX3x3_0_3_s GradientValuesX_0_V_xFGradientX3x3_0_3_s_fu_443 443
Add Instance xFGradientY3x3_0_3_s GradientValuesY_0_V_xFGradientY3x3_0_3_s_fu_459 459
Add Instance xFImageClip_1080_1920_1_3_0_2_0_1920_256 xFImageClip_1080_1920_1_3_0_2_0_1920_256_U0 871
Add Instance xFImageClipUtility_1_s pix_1_i_i_xFImageClipUtility_1_s_fu_205 205
Add Instance xFImageClip_1080_1920_1_3_0_2_0_1920_s xFImageClip_1080_1920_1_3_0_2_0_1920_U0 882
Add Instance xFImageClipUtility_1_s pix_1_i_i_xFImageClipUtility_1_s_fu_173 173
Add Instance xFReadOutStream_1080_1920_1_3_0_2_1920_257 xFReadOutStream_1080_1920_1_3_0_2_1920_257_U0 891
Add Instance xFReadOutStream_1080_1920_1_3_0_2_1920_s xFReadOutStream_1080_1920_1_3_0_2_1920_U0 898
Add Instance xFFindStereoCorrespondenceLBMNO_Block_Mat_exit7_i10_proc xFFindStereoCorrespondenceLBMNO_Block_Mat_exit7_i10_proc_U0 905
Add Instance xFFindStereoCorrespondenceLBMNO_Loop_1_proc xFFindStereoCorrespondenceLBMNO_Loop_1_proc_U0 916
Add Instance write_r call_ln800_write_r_fu_101 101
Add Instance xFFindStereoCorrespondenceLBMNO_entry345 xFFindStereoCorrespondenceLBMNO_entry345_U0 924
Add Instance InitUndistortRectifyMapInverse_9_5_4_1080_1920_1_259 InitUndistortRectifyMapInverse_9_5_4_1080_1920_1_259_U0 1239
Add Instance xFInitUndistortRectifyMapInverseKernel grp_xFInitUndistortRectifyMapInverseKernel_fu_64 64
Add Instance xFComputeUndistortCoordinates grp_xFComputeUndistortCoordinates_fu_402 402
Add Instance InitUndistortRectifyMapInverse_9_5_4_1080_1920_1_s InitUndistortRectifyMapInverse_9_5_4_1080_1920_1_U0 1250
Add Instance xFInitUndistortRectifyMapInverseKernel grp_xFInitUndistortRectifyMapInverseKernel_fu_64 64
Add Instance xFComputeUndistortCoordinates grp_xFComputeUndistortCoordinates_fu_402 402
Add Instance remap_128_1_0_4_0_1080_1920_1_false_260 remap_128_1_0_4_0_1080_1920_1_false_260_U0 1261
Add Instance xFRemapLI_0_0_1_4_128_1080_1920_1_false_262 xFRemapLI_0_0_1_4_128_1080_1920_1_false_262_U0 102
Add Instance remap_128_1_0_4_0_1080_1920_1_false_Block_proc261 remap_128_1_0_4_0_1080_1920_1_false_Block_proc261_U0 116
Add Instance remap_128_1_0_4_0_1080_1920_1_false_s remap_128_1_0_4_0_1080_1920_1_false_U0 1271
Add Instance xFRemapLI_0_0_1_4_128_1080_1920_1_false_s xFRemapLI_0_0_1_4_128_1080_1920_1_false_U0 102
Add Instance remap_128_1_0_4_0_1080_1920_1_false_Block_proc remap_128_1_0_4_0_1080_1920_1_false_Block_proc_U0 116
Add Instance Loop_1_proc Loop_1_proc_U0 1281
Add Instance xfMat2Array_32_1_1080_1920_1_s xfMat2Array_32_1_1080_1920_1_U0 1295
Add Instance xfMat2Array_32_1_1080_1920_1_1 grp_xfMat2Array_32_1_1080_1920_1_1_fu_100 100
Add Instance xfMat2hlsStrm_32_1_1080_1920_1_2073600_33 xfMat2hlsStrm_32_1_1080_1920_1_2073600_33_U0 156
Add Instance hlsStrm2Array_32_1080_1920_1_1_16_1036800_s hlsStrm2Array_32_1080_1920_1_1_16_1036800_U0 172
Add Instance Array2xfMat_32_0_1080_1920_1_258 Array2xfMat_32_0_1080_1920_1_258_U0 1305
Add Instance Array2xfMat_32_0_1080_1920_1_s grp_Array2xfMat_32_0_1080_1920_1_s_fu_142 142
Add Instance hlsStrm2xfMat_32_0_1080_1920_1_2073600_s hlsStrm2xfMat_32_0_1080_1920_1_2073600_U0 136
Add Instance Array2hlsStrm_32_1080_1920_1_1_8_518400_s Array2hlsStrm_32_1080_1920_1_1_8_518400_U0 145
Add Instance Array2xfMat_32_0_1080_1920_1_1 Array2xfMat_32_0_1080_1920_1_1_U0 1317
Add Instance Array2xfMat_32_0_1080_1920_1_s grp_Array2xfMat_32_0_1080_1920_1_s_fu_142 142
Add Instance hlsStrm2xfMat_32_0_1080_1920_1_2073600_s hlsStrm2xfMat_32_0_1080_1920_1_2073600_U0 136
Add Instance Array2hlsStrm_32_1080_1920_1_1_8_518400_s Array2hlsStrm_32_1080_1920_1_1_8_518400_U0 145
Add Instance Loop_2_proc Loop_2_proc_U0 1329
Add Instance Block_Mat_exit172_proc Block_Mat_exit172_proc_U0 1339
Add Instance stereopipeline_accel_entry62 stereopipeline_accel_entry62_U0 1362
Add Instance stereopipeline_accel_entry784 stereopipeline_accel_entry784_U0 1402
INFO: [v++ 60-586] Created /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/xo_ultra96v2_min2_hw/stereopipeline_accel.xo
INFO: [v++ 60-791] Total elapsed time: 0h 4m 10s
-e ----
Compiling xclbin...
mkdir -p /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/xclbin_ultra96v2_min2_hw
v++ -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/xclbin_ultra96v2_min2_hw/krnl_stereopipeline.xclbin --link /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/xo_ultra96v2_min2_hw/stereopipeline_accel.xo \
-I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/include -I. -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include -D__SDSVHLS__ -DHLS_NO_XIL_FPO_LIB --clock.defaultFreqHz 300000000 -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline --target hw --platform /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm --temp_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw --save-temps --debug --kernel_frequency 300 --report_level 2 --optimize 2 --jobs 8 --xp "vivado_param:project.writeIntermediateCheckpoints=1" \
--xp vivado_prop:run.impl_1.strategy=Performance_Explore \
WARNING: [v++ 60-1600] The option 'xp' was used directly on the command line, where its usage is deprecated. To ensure input line works for supported operating systems or shells, v++ supports specification for some options in a configuration file. As an alternative, please use options 'advanced.*', 'vivado.*' in a configuration file. Use one or more configuration files along with section headers to define key-value pairs for the advanced properties or parameters. Specify a configuration file using '--config'.
INFO: [v++ 82-185] Check out the auto-generated 'sample_link.ini' configuration file. The file shows how to migrate from deprecated command line --xp switches to configuration file directives.
Option Map File Used: '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/data/vitis/vpp/optMap.xml'
****** v++ v2019.2 (64-bit)
**** SW Build 2700185 on Thu Oct 24 18:45:48 MDT 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
INFO: [v++ 60-1306] Additional information associated with this v++ link can be found at:
Reports: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/reports/link
Log files: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/logs/link
Running Dispatch Server on port:40645
INFO: [v++ 60-1548] Creating build summary session with primary output /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/xclbin_ultra96v2_min2_hw/krnl_stereopipeline.xclbin.link_summary, at Thu Apr 2 20:09:53 2020
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Thu Apr 2 20:09:53 2020
Running Rule Check Server on port:43933
INFO: [v++ 60-1315] Creating rulecheck session with output '/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/reports/link/v++_link_krnl_stereopipeline_guidance.html', at Thu Apr 2 20:09:54 2020
INFO: [v++ 60-895] Target platform: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm
INFO: [v++ 60-1578] This platform contains Xilinx Shell Archive '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/hw/ultra96v2_min2.xsa'
INFO: [v++ 60-629] Linking for hardware target
INFO: [v++ 60-423] Target device: ultra96v2_min2
INFO: [v++ 60-1332] Run 'run_link' status: Not started
INFO: [v++ 60-1443] [20:09:54] Run run_link: Step system_link: Started
INFO: [v++ 60-1453] Command Line: system_link --xo /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/xo_ultra96v2_min2_hw/stereopipeline_accel.xo -keep --config /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/syslinkConfig.ini --xpfm /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm --target hw --output_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int --temp_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/sys_link
INFO: [v++ 60-1454] Run Directory: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/run_link
INFO: [SYSTEM_LINK 82-76] Reading emulation BD and HPFM information
INFO: [SYSTEM_LINK 60-1316] Initiating connection to rulecheck server, at Thu Apr 2 20:09:55 2020
INFO: [SYSTEM_LINK 82-70] Extracting xo v3 file /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/xo_ultra96v2_min2_hw/stereopipeline_accel.xo
INFO: [KernelCheck 83-118] 'stereopipeline_accel' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'img_L' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'img_R' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'img_disp' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'cameraMA_l' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'cameraMA_r' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'distC_l' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'distC_r' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'irA_l' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'irA_r' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'bm_state_arr' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'rows' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'cols' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [SYSTEM_LINK 82-53] Creating IP database /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/sys_link/_sysl/.cdb/xd_ip_db.xml
INFO: [SYSTEM_LINK 82-38] [20:09:56] build_xd_ip_db started: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/bin/build_xd_ip_db -ip_search 0 -sds-pf /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/sys_link/ultra96v2_min2.hpfm -clkid 0 -ip /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/sys_link/iprepo/xilinx_com_hls_stereopipeline_accel_1_0,stereopipeline_accel -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/sys_link/_sysl/.cdb/xd_ip_db.xml
INFO: [SYSTEM_LINK 82-37] [20:09:59] build_xd_ip_db finished successfully
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 296.441 ; gain = 0.000 ; free physical = 11706 ; free virtual = 38418
INFO: [SYSTEM_LINK 82-51] Create system connectivity graph
INFO: [SYSTEM_LINK 82-102] Applying explicit connections to the system connectivity graph: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/sys_link/cfgraph/cfgen_cfgraph.xml
INFO: [SYSTEM_LINK 82-38] [20:09:59] cfgen started: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/bin/cfgen -clock.defaultFreqHz 300000000 -dmclkid 0 -r /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/sys_link/cfgraph/cfgen_cfgraph.xml
INFO: [CFGEN 83-0] Kernel Specs:
INFO: [CFGEN 83-0] kernel: stereopipeline_accel, num: 1 {stereopipeline_accel_1}
INFO: [CFGEN 83-2226] Inferring mapping for argument stereopipeline_accel_1.img_L to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument stereopipeline_accel_1.img_R to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument stereopipeline_accel_1.img_disp to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument stereopipeline_accel_1.cameraMA_l to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument stereopipeline_accel_1.cameraMA_r to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument stereopipeline_accel_1.irA_l to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument stereopipeline_accel_1.irA_r to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument stereopipeline_accel_1.distC_l to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument stereopipeline_accel_1.distC_r to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument stereopipeline_accel_1.bm_state_arr to HP
INFO: [SYSTEM_LINK 82-37] [20:09:59] cfgen finished successfully
Time (s): cpu = 00:00:00.29 ; elapsed = 00:00:00.32 . Memory (MB): peak = 296.441 ; gain = 0.000 ; free physical = 11708 ; free virtual = 38420
INFO: [SYSTEM_LINK 82-52] Create top-level block diagram
INFO: [SYSTEM_LINK 82-38] [20:09:59] cf2bd started: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/bin/cf2bd --linux --trace_buffer 1024 --input_file /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/sys_link/cfgraph/cfgen_cfgraph.xml --ip_db /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/sys_link/_sysl/.cdb/xd_ip_db.xml --cf_name dr --working_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/sys_link/_sysl/.xsd --temp_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/sys_link --output_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int
INFO: [CF2BD 82-31] Launching cf2xd: cf2xd -linux -trace-buffer 1024 -i /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/sys_link/cfgraph/cfgen_cfgraph.xml -r /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o dr.xml
INFO: [CF2BD 82-28] cf2xd finished successfully
INFO: [CF2BD 82-31] Launching cf_xsd: cf_xsd -disable-address-gen -dn dr -dp /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/sys_link/_sysl/.xsd
rlwrap: warning: your $TERM is 'xterm-256color' but rlwrap couldn't find it in the terminfo database. Expect some problems.: Inappropriate ioctl for device
INFO: [CF2BD 82-28] cf_xsd finished successfully
INFO: [SYSTEM_LINK 82-37] [20:10:01] cf2bd finished successfully
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 296.441 ; gain = 0.000 ; free physical = 11704 ; free virtual = 38420
INFO: [v++ 60-1441] [20:10:01] Run run_link: Step system_link: Completed
Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 679.691 ; gain = 0.000 ; free physical = 11726 ; free virtual = 38442
INFO: [v++ 60-1443] [20:10:01] Run run_link: Step cf2sw: Started
INFO: [v++ 60-1453] Command Line: cf2sw -sdsl /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/sdsl.dat -rtd /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/cf2sw.rtd -xclbin /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/xclbin_orig.xml -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/xclbin_orig.1.xml
INFO: [v++ 60-1454] Run Directory: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/run_link
INFO: [v++ 60-1441] [20:10:02] Run run_link: Step cf2sw: Completed
Time (s): cpu = 00:00:00.59 ; elapsed = 00:00:00.67 . Memory (MB): peak = 679.691 ; gain = 0.000 ; free physical = 11728 ; free virtual = 38444
INFO: [v++ 60-1443] [20:10:02] Run run_link: Step rtd2_system_diagram: Started
INFO: [v++ 60-1453] Command Line: rtd2SystemDiagram --rtdJsonFileName /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/cf2sw.rtd --diagramJsonFileName /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/systemDiagramModel.json --platformFilePath /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm --generatedByName v++ --generatedByVersion 2019.2 --generatedByChangeList 2700185 --generatedByTimeStamp Thu Oct 24 18:45:48 MDT 2019 --generatedByOptions /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/bin/unwrapped/lnx64.o/v++ -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/xclbin_ultra96v2_min2_hw/krnl_stereopipeline.xclbin --link /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/xo_ultra96v2_min2_hw/stereopipeline_accel.xo -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/include -I. -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include -D__SDSVHLS__ -DHLS_NO_XIL_FPO_LIB --clock.defaultFreqHz 300000000 -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline --target hw --platform /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm --temp_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw --save-temps --debug --kernel_frequency 300 --report_level 2 --optimize 2 --jobs 8 --xp vivado_param:project.writeIntermediateCheckpoints=1 --xp vivado_prop:run.impl_1.strategy=Performance_Explore --generatedByXclbinName krnl_stereopipeline --kernelInfoDataFileName /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/kernel_info.dat
INFO: [v++ 60-1454] Run Directory: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/run_link
WARNING: [v++ 82-164] Unable to populate user region instance path. The platform file does not contain a hardwarePlatform.devices..core.instPath entry.
INFO: [v++ 60-839] Read in kernel information from file '/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/kernel_info.dat'.
WARNING: [v++ 82-157] Unable to populate kernel available resources BRAM entry.
WARNING: [v++ 82-158] Unable to populate kernel available resources DSP entry.
WARNING: [v++ 82-163] Unable to populate user region available resources. The platform file deos not contain a hardwarePlatform.devices..core.availableResources entry
INFO: [v++ 60-1441] [20:10:04] Run run_link: Step rtd2_system_diagram: Completed
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 679.691 ; gain = 0.000 ; free physical = 11728 ; free virtual = 38444
INFO: [v++ 60-1443] [20:10:04] Run run_link: Step vpl: Started
INFO: [v++ 60-1453] Command Line: vpl -t hw -f /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm -g -j 8 --kernel_frequency 300 -s --output_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int --log_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/logs/link --report_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/reports/link --config /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/vplConfig.ini -k /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/kernel_info.dat --webtalk_flag Vitis --temp_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link --no-info --tlog_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/.tlog/v++_link_krnl_stereopipeline --iprepo /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/xo/ip_repo/xilinx_com_hls_stereopipeline_accel_1_0 --messageDb /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/run_link/vpl.pb /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/dr.bd.tcl
INFO: [v++ 60-1454] Run Directory: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/run_link
****** vpl v2019.2 (64-bit)
**** SW Build 2700185 on Thu Oct 24 18:45:48 MDT 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
INFO: [VPL 60-839] Read in kernel information from file '/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/kernel_info.dat'.
INFO: [VPL 60-423] Target device: ultra96v2_min2
INFO: [VPL 60-1032] Extracting hardware platform to /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/vivado/vpl/.local/hw_platform
[20:10:15] Run vpl: Step create_project: Started
Creating Vivado project.
[20:10:24] Run vpl: Step create_project: Completed
[20:10:24] Run vpl: Step create_bd: Started
[20:10:34] Run vpl: Step create_bd: Completed
[20:10:34] Run vpl: Step update_bd: Started
[20:10:35] Run vpl: Step update_bd: Completed
[20:10:35] Run vpl: Step generate_target: Started
[20:11:11] Run vpl: Step generate_target: Completed
[20:11:11] Run vpl: Step config_hw_runs: Started
[20:11:13] Run vpl: Step config_hw_runs: Completed
[20:11:13] Run vpl: Step synth: Started
[20:12:14] Block-level synthesis in progress, 0 of 21 jobs complete, 8 jobs running.
[20:12:44] Block-level synthesis in progress, 0 of 21 jobs complete, 8 jobs running.
[20:13:16] Block-level synthesis in progress, 0 of 21 jobs complete, 8 jobs running.
[20:13:46] Block-level synthesis in progress, 0 of 21 jobs complete, 8 jobs running.
[20:14:16] Block-level synthesis in progress, 0 of 21 jobs complete, 8 jobs running.
[20:14:46] Block-level synthesis in progress, 0 of 21 jobs complete, 8 jobs running.
[20:15:17] Block-level synthesis in progress, 0 of 21 jobs complete, 8 jobs running.
[20:15:47] Block-level synthesis in progress, 1 of 21 jobs complete, 7 jobs running.
[20:16:18] Block-level synthesis in progress, 2 of 21 jobs complete, 6 jobs running.
[20:16:48] Block-level synthesis in progress, 2 of 21 jobs complete, 7 jobs running.
[20:17:18] Block-level synthesis in progress, 3 of 21 jobs complete, 7 jobs running.
[20:17:49] Block-level synthesis in progress, 5 of 21 jobs complete, 6 jobs running.
[20:18:19] Block-level synthesis in progress, 6 of 21 jobs complete, 5 jobs running.
[20:18:49] Block-level synthesis in progress, 7 of 21 jobs complete, 4 jobs running.
[20:19:20] Block-level synthesis in progress, 10 of 21 jobs complete, 4 jobs running.
[20:19:50] Block-level synthesis in progress, 12 of 21 jobs complete, 4 jobs running.
[20:20:21] Block-level synthesis in progress, 13 of 21 jobs complete, 3 jobs running.
[20:20:51] Block-level synthesis in progress, 18 of 21 jobs complete, 3 jobs running.
[20:21:21] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:21:51] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:22:22] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:22:52] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:23:22] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:23:52] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:24:22] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:24:52] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:25:23] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:25:53] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:26:23] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:26:53] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:27:23] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:27:53] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:28:24] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:28:54] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:29:24] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:29:54] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:30:24] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:30:54] Block-level synthesis in progress, 21 of 21 jobs complete, 0 jobs running.
[20:31:25] Top-level synthesis in progress.
[20:31:55] Top-level synthesis in progress.
[20:32:25] Top-level synthesis in progress.
[20:32:45] Run vpl: Step synth: Completed
[20:32:45] Run vpl: Step impl: Started
[20:35:47] Finished 2nd of 6 tasks (FPGA linking synthesized kernels to platform). Elapsed time: 00h 25m 42s
[20:35:47] Starting logic optimization..
[20:35:47] Phase 1 Retarget
[20:35:47] Phase 2 Constant propagation
[20:35:47] Phase 3 Sweep
[20:36:18] Phase 4 BUFG optimization
[20:36:18] Phase 5 Shift Register Optimization
[20:36:18] Phase 6 Post Processing Netlist
[20:37:48] Finished 3rd of 6 tasks (FPGA logic optimization). Elapsed time: 00h 02m 00s
[20:37:48] Starting logic placement..
[20:37:48] Phase 1 Placer Initialization
[20:37:48] Phase 1.1 Placer Initialization Netlist Sorting
[20:37:48] Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
[20:38:18] Phase 1.3 Build Placer Netlist Model
[20:38:18] Phase 1.4 Constrain Clocks/Macros
[20:38:18] Phase 2 Global Placement
[20:38:18] Phase 2.1 Floorplanning
[20:39:19] Phase 2.2 Global Placement Core
[20:40:49] Phase 2.2.1 Physical Synthesis In Placer
[20:41:20] Phase 3 Detail Placement
[20:41:20] Phase 3.1 Commit Multi Column Macros
[20:41:20] Phase 3.2 Commit Most Macros & LUTRAMs
[20:41:20] Phase 3.3 Area Swap Optimization
[20:41:20] Phase 3.4 Pipeline Register Optimization
[20:41:20] Phase 3.5 IO Cut Optimizer
[20:41:20] Phase 3.6 Fast Optimization
[20:41:50] Phase 3.7 Small Shape DP
[20:41:50] Phase 3.7.1 Small Shape Clustering
[20:41:50] Phase 3.7.2 Flow Legalize Slice Clusters
[20:41:50] Phase 3.7.3 Slice Area Swap
[20:42:20] Phase 3.7.4 Commit Slice Clusters
[20:42:20] Phase 3.8 Re-assign LUT pins
[20:42:20] Phase 3.9 Pipeline Register Optimization
[20:42:20] Phase 3.10 Fast Optimization
[20:42:50] Phase 4 Post Placement Optimization and Clean-Up
[20:42:50] Phase 4.1 Post Commit Optimization
[20:43:21] Phase 4.1.1 Post Placement Optimization
[20:43:21] Phase 4.1.1.1 BUFG Insertion
[20:44:21] Phase 4.2 Post Placement Cleanup
[20:44:21] Phase 4.3 Placer Reporting
[20:44:21] Phase 4.4 Final Placement Cleanup
[20:45:52] Finished 4th of 6 tasks (FPGA logic placement). Elapsed time: 00h 08m 03s
[20:45:52] Starting logic routing..
[20:45:52] Phase 1 Build RT Design
[20:46:22] Phase 2 Router Initialization
[20:46:22] Phase 2.1 Create Timer
[20:46:22] Phase 2.2 Fix Topology Constraints
[20:46:22] Phase 2.3 Pre Route Cleanup
[20:46:22] Phase 2.4 Global Clock Net Routing
[20:46:22] Phase 2.5 Update Timing
[20:46:52] Phase 2.6 Update Timing for Bus Skew
[20:46:52] Phase 2.6.1 Update Timing
[20:47:23] Phase 3 Initial Routing
[20:47:53] Phase 4 Rip-up And Reroute
[20:47:53] Phase 4.1 Global Iteration 0
[21:10:05] Phase 4.2 Global Iteration 1
[21:13:06] Phase 4.3 Global Iteration 2
[21:14:37] Phase 4.4 Global Iteration 3
[21:15:07] Phase 5 Delay and Skew Optimization
[21:15:07] Phase 5.1 Delay CleanUp
[21:15:07] Phase 5.1.1 Update Timing
[21:15:37] Phase 5.2 Clock Skew Optimization
[21:15:37] Phase 6 Post Hold Fix
[21:15:37] Phase 6.1 Hold Fix Iter
[21:15:37] Phase 6.1.1 Update Timing
[21:15:37] Phase 7 Route finalize
[21:15:37] Phase 8 Verifying routed nets
[21:15:37] Phase 9 Depositing Routes
[21:15:37] Phase 10 Route finalize
[21:15:37] Phase 11 Post Router Timing
[21:16:08] Finished 5th of 6 tasks (FPGA routing). Elapsed time: 00h 30m 15s
[21:16:08] Starting bitstream generation..
[21:18:39] Creating bitmap...
[21:18:53] Run vpl: Step impl: Completed
[21:18:53] Writing bitstream ./ultra96v2_min2_wrapper.bit...
[21:18:53] Finished 6th of 6 tasks (FPGA bitstream generation). Elapsed time: 00h 02m 45s
[21:18:53] Run vpl: FINISHED. Run Status: impl Complete!
INFO: [v++ 60-1441] [21:18:53] Run run_link: Step vpl: Completed
Time (s): cpu = 00:00:27 ; elapsed = 01:08:50 . Memory (MB): peak = 679.691 ; gain = 0.000 ; free physical = 14757 ; free virtual = 39166
INFO: [v++ 60-1443] [21:18:53] Run run_link: Step rtdgen: Started
INFO: [v++ 60-1453] Command Line: rtdgen
INFO: [v++ 60-1454] Run Directory: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/run_link
INFO: [v++ 60-1453] Command Line: cf2sw -a /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/address_map.xml -sdsl /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/sdsl.dat -xclbin /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/xclbin_orig.xml -rtd /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/krnl_stereopipeline.rtd -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/krnl_stereopipeline.xml
INFO: [v++ 60-1618] Launching
INFO: [v++ 60-1441] [21:18:56] Run run_link: Step rtdgen: Completed
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 679.691 ; gain = 0.000 ; free physical = 14771 ; free virtual = 39180
INFO: [v++ 60-1443] [21:18:56] Run run_link: Step xclbinutil: Started
INFO: [v++ 60-1453] Command Line: xclbinutil --add-section BITSTREAM:RAW:/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/system.bit --force --key-value SYS:mode:flat --add-section :JSON:/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/krnl_stereopipeline.rtd --add-section CLOCK_FREQ_TOPOLOGY:JSON:/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/krnl_stereopipeline_xml.rtd --add-section BUILD_METADATA:JSON:/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/krnl_stereopipeline_build.rtd --add-section EMBEDDED_METADATA:RAW:/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/krnl_stereopipeline.xml --add-section SYSTEM_METADATA:RAW:/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/systemDiagramModelSlrBaseAddress.json --key-value SYS:PlatformVBNV:vendor_Ultra96V2_ultra96v2_min2_1_0 --output /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/krnl_stereopipeline.xclbin
INFO: [v++ 60-1454] Run Directory: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/run_link
XRT Build Version: 2.3.1301
Build Date: 2019-10-24 20:05:16
Hash ID: 192e706aea53163a04c574f9b3fe9ed76b6ca471
Creating a default 'in-memory' xclbin image.
Section: 'BITSTREAM'(0) was successfully added.
Size : 5568794 bytes
Format : RAW
File : '/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/system.bit'
Section: 'MEM_TOPOLOGY'(6) was successfully added.
Format : JSON
File : 'mem_topology'
Section: 'IP_LAYOUT'(8) was successfully added.
Format : JSON
File : 'ip_layout'
Section: 'CONNECTIVITY'(7) was successfully added.
Format : JSON
File : 'connectivity'
WARNING: Skipping CLOCK_FREQ_TOPOLOGY section for count size is zero.
WARNING: Section 'CLOCK_FREQ_TOPOLOGY' content is empty. No data in the given JSON file.
Section: 'CLOCK_FREQ_TOPOLOGY'(11) was empty. No action taken.
Format : JSON
File : '/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/krnl_stereopipeline_xml.rtd'
Section: 'BUILD_METADATA'(14) was successfully added.
Size : 4830 bytes
Format : JSON
File : '/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/krnl_stereopipeline_build.rtd'
Section: 'EMBEDDED_METADATA'(2) was successfully added.
Size : 32937 bytes
Format : RAW
File : '/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/krnl_stereopipeline.xml'
Section: 'SYSTEM_METADATA'(22) was successfully added.
Size : 18624 bytes
Format : RAW
File : '/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/systemDiagramModelSlrBaseAddress.json'
Successfully wrote (5634244 bytes) to the output file: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/krnl_stereopipeline.xclbin
Leaving xclbinutil.
INFO: [v++ 60-1441] [21:18:56] Run run_link: Step xclbinutil: Completed
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.11 . Memory (MB): peak = 679.691 ; gain = 0.000 ; free physical = 14770 ; free virtual = 39188
INFO: [v++ 60-1443] [21:18:56] Run run_link: Step xclbinutilinfo: Started
INFO: [v++ 60-1453] Command Line: xclbinutil --quiet --info /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/krnl_stereopipeline.xclbin.info --input /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/krnl_stereopipeline.xclbin
INFO: [v++ 60-1454] Run Directory: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/run_link
INFO: [v++ 60-1441] [21:18:56] Run run_link: Step xclbinutilinfo: Completed
Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.06 . Memory (MB): peak = 679.691 ; gain = 0.000 ; free physical = 14790 ; free virtual = 39208
INFO: [v++ 60-244] Generating system estimate report...
INFO: [v++ 60-1092] Generated system estimate report: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/reports/link/system_estimate_krnl_stereopipeline.xtxt
INFO: [v++ 60-907] Packaging to directory: '/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/xclbin_ultra96v2_min2_hw/sd_card'
INFO: [v++ 60-586] Created /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/xclbin_ultra96v2_min2_hw/krnl_stereopipeline.xclbin
INFO: [v++ 60-1307] Run completed. Additional information can be found in:
Guidance: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/reports/link/v++_link_krnl_stereopipeline_guidance.html
Timing Report: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/reports/link/imp/ultra96v2_min2_wrapper_timing_summary_routed.rpt
Vivado Log: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/logs/link/vivado.log
Steps Log File: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/logs/link/link.steps.log
INFO: [v++ 60-791] Total elapsed time: 1h 9m 5s
masaaki@masaaki-H110M4-M01:/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build$
1. Vitis のインストール・ディレクトリの settings64.sh を実行
source /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/settings64.sh
2. XRT の setenv.sh を実行
source /opt/xilinx/xrt/setup.sh
3. DEVICE 環境変数にプラットフォームの xpfm ファイルへのパスを設定する
export DEVICE=/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm
4. SYSROOT にプラットフォームの sysroot へのパスを設定する。
export SYSROOT=/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux
[23:03:48] Run vpl: FINISHED. Run Status: impl ERROR
Design (This design requires more LUT as Logic cells than are available in the target device. This design requires 71617 of such cell types but only 70560 compatible sites are available in the target device.
masaaki@masaaki-H110M4-M01:/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build$ make host xclbin TARGET=hw BOARD=Zynq ARCH=aarch64-e ----
Compiling object xf_corner_tracker_tb...
mkdir -p /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/obj_ultra96v2_min2
aarch64-linux-gnu-g++ -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/obj_ultra96v2_min2/xf_corner_tracker_tb.o -c /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp -D XDEVICE=ultra96v2_min2 -DVIVADO_HLS_SIM -D__SDSVHLS__ -DHLS_NO_XIL_FPO_LIB -I. -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2 -g --sysroot=/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux -D__ZYNQ -std=c++14 -fPIC -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker -I/opt/xilinx/xrt/include -Wall -Wno-unknown-pragmas -Wno-unused-label -pthread -idirafter /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vivado/2019.2/include
In file included from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include/common/xf_headers.hpp:30,
from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:17:
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include/common/xf_sw_utils.hpp: 関数 ‘void xf::cv::analyzeDiff(cv::Mat&, int, float&)’ 内:
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include/common/xf_sw_utils.hpp:150:23: 警告: 変数 ‘v_tmp1’ が設定されましたが使用されていません [-Wunused-but-set-variable]
float v_tmp1;
^~~~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp: 関数 ‘int main(int, char**)’ 内:
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:321:118: 警告: ISO C++ says that these are ambiguous, even though the worst conversion for the first is better than the worst conversion for the second:
ris.rows * inHarris.cols * CH_TYPE), (ap_uint<INPUT_PTR_WIDTH>*)inHarris.data);
^
In file included from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2/xcl2.hpp:48,
from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:25:
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:3675:5: 備考: 候補 1: ‘cl::Buffer::Buffer(const cl::Context&, cl_mem_flags, cl::size_type, void*, cl_int*)’
Buffer(
^~~~~~
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:8512:1: 備考: 候補 2: ‘cl::Buffer::Buffer(const cl::Context&, IteratorType, IteratorType, bool, bool, cl_int*) [with IteratorType = int; cl_int = int]’
Buffer::Buffer(
^~~~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:369:89: 警告: ISO C++ says that these are ambiguous, even though the worst conversion for the first is better than the worst conversion for the second:
(ap_uint<INPUT_PTR_WIDTH>*)imagepyr1[lvl].data);
^
In file included from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2/xcl2.hpp:48,
from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:25:
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:3675:5: 備考: 候補 1: ‘cl::Buffer::Buffer(const cl::Context&, cl_mem_flags, cl::size_type, void*, cl_int*)’
Buffer(
^~~~~~
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:8512:1: 備考: 候補 2: ‘cl::Buffer::Buffer(const cl::Context&, IteratorType, IteratorType, bool, bool, cl_int*) [with IteratorType = int; cl_int = int]’
Buffer::Buffer(
^~~~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:372:96: 警告: ISO C++ says that these are ambiguous, even though the worst conversion for the first is better than the worst conversion for the second:
(ap_uint<OUTPUT_PTR_WIDTH>*)imagepyr1[lvl + 1].data);
^
In file included from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2/xcl2.hpp:48,
from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:25:
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:3675:5: 備考: 候補 1: ‘cl::Buffer::Buffer(const cl::Context&, cl_mem_flags, cl::size_type, void*, cl_int*)’
Buffer(
^~~~~~
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:8512:1: 備考: 候補 2: ‘cl::Buffer::Buffer(const cl::Context&, IteratorType, IteratorType, bool, bool, cl_int*) [with IteratorType = int; cl_int = int]’
Buffer::Buffer(
^~~~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:375:89: 警告: ISO C++ says that these are ambiguous, even though the worst conversion for the first is better than the worst conversion for the second:
(ap_uint<INPUT_PTR_WIDTH>*)imagepyr2[lvl].data);
^
In file included from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2/xcl2.hpp:48,
from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:25:
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:3675:5: 備考: 候補 1: ‘cl::Buffer::Buffer(const cl::Context&, cl_mem_flags, cl::size_type, void*, cl_int*)’
Buffer(
^~~~~~
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:8512:1: 備考: 候補 2: ‘cl::Buffer::Buffer(const cl::Context&, IteratorType, IteratorType, bool, bool, cl_int*) [with IteratorType = int; cl_int = int]’
Buffer::Buffer(
^~~~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:378:96: 警告: ISO C++ says that these are ambiguous, even though the worst conversion for the first is better than the worst conversion for the second:
(ap_uint<OUTPUT_PTR_WIDTH>*)imagepyr2[lvl + 1].data);
^
In file included from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2/xcl2.hpp:48,
from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:25:
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:3675:5: 備考: 候補 1: ‘cl::Buffer::Buffer(const cl::Context&, cl_mem_flags, cl::size_type, void*, cl_int*)’
Buffer(
^~~~~~
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:8512:1: 備考: 候補 2: ‘cl::Buffer::Buffer(const cl::Context&, IteratorType, IteratorType, bool, bool, cl_int*) [with IteratorType = int; cl_int = int]’
Buffer::Buffer(
^~~~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:440:117: 警告: ISO C++ says that these are ambiguous, even though the worst conversion for the first is better than the worst conversion for the second:
S - 1] * pyr_w[NUM_LEVELS - 1] * 4), (ap_uint<OUTPUT_PTR_WIDTH>*)flow_in.data);
^
In file included from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2/xcl2.hpp:48,
from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:25:
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:3675:5: 備考: 候補 1: ‘cl::Buffer::Buffer(const cl::Context&, cl_mem_flags, cl::size_type, void*, cl_int*)’
Buffer(
^~~~~~
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:8512:1: 備考: 候補 2: ‘cl::Buffer::Buffer(const cl::Context&, IteratorType, IteratorType, bool, bool, cl_int*) [with IteratorType = int; cl_int = int]’
Buffer::Buffer(
^~~~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:450:118: 警告: ISO C++ says that these are ambiguous, even though the worst conversion for the first is better than the worst conversion for the second:
(pyr_h[l] * pyr_w[l] * CH_TYPE), (ap_uint<INPUT_PTR_WIDTH>*)imagepyr1[l].data);
^
In file included from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2/xcl2.hpp:48,
from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:25:
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:3675:5: 備考: 候補 1: ‘cl::Buffer::Buffer(const cl::Context&, cl_mem_flags, cl::size_type, void*, cl_int*)’
Buffer(
^~~~~~
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:8512:1: 備考: 候補 2: ‘cl::Buffer::Buffer(const cl::Context&, IteratorType, IteratorType, bool, bool, cl_int*) [with IteratorType = int; cl_int = int]’
Buffer::Buffer(
^~~~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:452:118: 警告: ISO C++ says that these are ambiguous, even though the worst conversion for the first is better than the worst conversion for the second:
(pyr_h[l] * pyr_w[l] * CH_TYPE), (ap_uint<INPUT_PTR_WIDTH>*)imagepyr2[l].data);
^
In file included from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2/xcl2.hpp:48,
from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:25:
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:3675:5: 備考: 候補 1: ‘cl::Buffer::Buffer(const cl::Context&, cl_mem_flags, cl::size_type, void*, cl_int*)’
Buffer(
^~~~~~
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:8512:1: 備考: 候補 2: ‘cl::Buffer::Buffer(const cl::Context&, IteratorType, IteratorType, bool, bool, cl_int*) [with IteratorType = int; cl_int = int]’
Buffer::Buffer(
^~~~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:460:72: 警告: ISO C++ says that these are ambiguous, even though the worst conversion for the first is better than the worst conversion for the second:
(ap_uint<OUTPUT_PTR_WIDTH>*)flow.data);
^
In file included from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2/xcl2.hpp:48,
from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:25:
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:3675:5: 備考: 候補 1: ‘cl::Buffer::Buffer(const cl::Context&, cl_mem_flags, cl::size_type, void*, cl_int*)’
Buffer(
^~~~~~
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:8512:1: 備考: 候補 2: ‘cl::Buffer::Buffer(const cl::Context&, IteratorType, IteratorType, bool, bool, cl_int*) [with IteratorType = int; cl_int = int]’
Buffer::Buffer(
^~~~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:473:21: 警告: unused variable ‘next_width’ [-Wunused-variable]
int next_width = (scale_up_flag == 1) ? pyr_w[l + 1] : pyr_w[l];
^~~~~~~~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:447:17: 警告: unused variable ‘curr_width’ [-Wunused-variable]
int curr_width = pyr_w[l];
^~~~~~~~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:527:112: 警告: ISO C++ says that these are ambiguous, even though the worst conversion for the first is better than the worst conversion for the second:
context, CL_MEM_USE_HOST_PTR | CL_MEM_READ_WRITE, ((MAXCORNERS)*8), listfixed);
^
In file included from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2/xcl2.hpp:48,
from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:25:
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:3675:5: 備考: 候補 1: ‘cl::Buffer::Buffer(const cl::Context&, cl_mem_flags, cl::size_type, void*, cl_int*)’
Buffer(
^~~~~~
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:8512:1: 備考: 候補 2: ‘cl::Buffer::Buffer(const cl::Context&, IteratorType, IteratorType, bool, bool, cl_int*) [with IteratorType = int; cl_int = int]’
Buffer::Buffer(
^~~~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:540:25: 警告: 書式 ‘%d’ は対応した ‘int’ 引数が予期されます [-Wformat=]
fprintf(stderr, "\n flow_rows = %d flow_cols=%d num of corners=%d num_corners=%d harris_flag=%d", flow.rows,
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:566:29: 警告: comparison of integer expressions of different signedness: ‘int’ and ‘unsigned int’ [-Wsign-compare]
for (int li = 0; li < params[0]; li++) {
~~~^~~~~~~~~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:430:14: 警告: unused variable ‘name’ [-Wunused-variable]
char name[50], name1[50];
^~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:430:24: 警告: unused variable ‘name1’ [-Wunused-variable]
char name[50], name1[50];
^~~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:431:14: 警告: unused variable ‘in_name’ [-Wunused-variable]
char in_name[50], in_name1[50];
^~~~~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:431:27: 警告: unused variable ‘in_name1’ [-Wunused-variable]
char in_name[50], in_name1[50];
^~~~~~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:257:10: 警告: unused variable ‘list_name’ [-Wunused-variable]
char list_name[50], list_fix_name[50];
^~~~~~~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:257:25: 警告: unused variable ‘list_fix_name’ [-Wunused-variable]
char list_name[50], list_fix_name[50];
^~~~~~~~~~~~~
In file included from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include/common/xf_common.hpp:20,
from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include/common/xf_sw_utils.hpp:20,
from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include/common/xf_headers.hpp:30,
from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:17:
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include/common/xf_structs.hpp: In instantiation of ‘unsigned char* xf::cv::Mat<T, ROWS, COLS, NPC>::copyFrom() [with int T = 0; int ROWS = 1080; int COLS = 1920; int NPC = 1]’:
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include/common/xf_sw_utils.hpp:50:16: required from ‘void xf::cv::imwrite(const char*, xf::cv::Mat<T, ROWS, COLS, NPC>&) [with int _PTYPE = 0; int _ROWS = 1080; int _COLS = 1920; int _NPC = 1]’
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_tb.cpp:605:60: required from here
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include/common/xf_structs.hpp:831:9: 警告: unused variable ‘diff_ptr’ [-Wunused-variable]
int diff_ptr = 0;
^~~~~~~~
-e ----
Compiling extra object /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/obj_ultra96v2_min2/xcl2.o...
mkdir -p /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/obj_ultra96v2_min2
aarch64-linux-gnu-g++ -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/obj_ultra96v2_min2/xcl2.o -c /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2/xcl2.cpp -D XDEVICE=ultra96v2_min2 -DVIVADO_HLS_SIM -D__SDSVHLS__ -DHLS_NO_XIL_FPO_LIB -I. -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2 -g --sysroot=/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux -D__ZYNQ -std=c++14 -fPIC -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker -I/opt/xilinx/xrt/include -Wall -Wno-unknown-pragmas -Wno-unused-label -pthread -idirafter /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vivado/2019.2/include -I /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2
-e ----
Compiling host cornertracker.exe...
mkdir -p /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/bin_ultra96v2_min2
aarch64-linux-gnu-g++ -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/bin_ultra96v2_min2/cornertracker.exe /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/obj_ultra96v2_min2/xf_corner_tracker_tb.o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/obj_ultra96v2_min2/xcl2.o -D XDEVICE=ultra96v2_min2 -DVIVADO_HLS_SIM -D__SDSVHLS__ -DHLS_NO_XIL_FPO_LIB -I. -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2 -g --sysroot=/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux -D__ZYNQ -std=c++14 -fPIC -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker -I/opt/xilinx/xrt/include -Wall -Wno-unknown-pragmas -Wno-unused-label -pthread -idirafter /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vivado/2019.2/include -L/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/lib -Wl,-rpath-link=/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/lib/ -L/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/opt/xilinx/xrt/lib -lopencv_imgcodecs -lopencv_videoio -lopencv_core -lopencv_imgproc -lopencv_highgui -lopencv_calib3d -lopencv_features2d -lopencv_flann -pthread -L/opt/xilinx/xrt/lib -lxilinxopencl
-e ----
Compiling kernel pyr_dense_optical_flow_accel...
mkdir -p /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw
v++ -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/pyr_dense_optical_flow_accel.xo --kernel pyr_dense_optical_flow_accel --compile /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_pyr_dense_optical_flow_accel.cpp \
-I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/include -I. -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include -D__SDSVHLS__ -DHLS_NO_XIL_FPO_LIB --xp vivado_prop:run.impl_1.strategy=Performance_Explore --clock.defaultFreqHz 300000000 -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker --target hw --platform /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm --temp_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw --save-temps --debug --kernel_frequency 300 --report_level 2
WARNING: [v++ 60-1600] The option 'xp' was used directly on the command line, where its usage is deprecated. To ensure input line works for supported operating systems or shells, v++ supports specification for some options in a configuration file. As an alternative, please use options 'advanced.*', 'vivado.*' in a configuration file. Use one or more configuration files along with section headers to define key-value pairs for the advanced properties or parameters. Specify a configuration file using '--config'.
INFO: [v++ 82-185] Check out the auto-generated 'sample_compile.ini' configuration file. The file shows how to migrate from deprecated command line --xp switches to configuration file directives.
Option Map File Used: '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/data/vitis/vpp/optMap.xml'
****** v++ v2019.2 (64-bit)
**** SW Build 2700185 on Thu Oct 24 18:45:48 MDT 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
INFO: [v++ 60-1306] Additional information associated with this v++ compile can be found at:
Reports: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/reports/pyr_dense_optical_flow_accel
Log files: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/logs/pyr_dense_optical_flow_accel
Running Dispatch Server on port:35977
INFO: [v++ 60-1548] Creating build summary session with primary output /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/pyr_dense_optical_flow_accel.xo.compile_summary, at Wed Apr 1 22:19:22 2020
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Wed Apr 1 22:19:22 2020
Running Rule Check Server on port:46195
INFO: [v++ 60-1315] Creating rulecheck session with output '/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/reports/pyr_dense_optical_flow_accel/v++_compile_pyr_dense_optical_flow_accel_guidance.html', at Wed Apr 1 22:19:23 2020
INFO: [v++ 60-895] Target platform: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm
INFO: [v++ 60-1578] This platform contains Xilinx Shell Archive '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/hw/ultra96v2_min2.xsa'
INFO: [v++ 60-585] Compiling for hardware target
INFO: [v++ 60-423] Target device: ultra96v2_min2
INFO: [v++ 60-242] Creating kernel: 'pyr_dense_optical_flow_accel'
INFO: [v++ 60-1616] Creating a HLS clock using kernel_frequency option: 300 MHz
===>The following messages were generated while performing high-level synthesis for kernel: pyr_dense_optical_flow_accel Log file: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/pyr_dense_optical_flow_accel/pyr_dense_optical_flow_accel/vivado_hls.log :
INFO: [v++ 204-61] Option 'relax_ii_for_timing' is enabled, will increase II to preserve clock frequency constraints.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining loop 'L1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 4.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining loop 'L1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 4.
INFO: [v++ 204-61] Pipelining loop 'Loop 1.1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining function 'compute_result<16, 10, 45, 22, 48, 16>'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 11.
INFO: [v++ 204-61] Pipelining loop 'L3'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 2, Depth = 17.
INFO: [v++ 204-61] Pipelining loop 'Loop 1.1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [v++ 204-61] Pipelining loop 'Loop 1.1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [v++ 204-61] Pipelining function 'findIntensity'.
INFO: [v++ 204-61] Discarding stage scheduling solution.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 17.
INFO: [v++ 204-61] Pipelining loop 'L4'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 20.
INFO: [v++ 204-61] Pipelining loop 'Loop 1.1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining loop 'Loop 2.1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 9.
INFO: [v++ 204-61] Pipelining loop 'Loop 1.1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 168.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining loop 'read_lines.1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining loop 'Col_Loop'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 23.
INFO: [v++ 204-61] Pipelining loop 'Loop 1.1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [v++ 204-61] Pipelining loop 'L1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 2, Depth = 4.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 200-789] **** Estimated Fmax: 293.77 MHz
INFO: [v++ 60-594] Finished kernel compilation
INFO: [v++ 60-244] Generating system estimate report...
INFO: [v++ 60-1092] Generated system estimate report: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/reports/pyr_dense_optical_flow_accel/system_estimate_pyr_dense_optical_flow_accel.xtxt
Add Instance densePyrOpticalFlow_5_50_11_16_10_0_1080_1920_1_false_s densePyrOpticalFlow_5_50_11_16_10_0_1080_1920_1_false_U0 726
Add Instance xFLKOpticalFlowDenseKernel grp_xFLKOpticalFlowDenseKernel_fu_220 220
Add Instance find_flow find_flow_U0 1096
Add Instance auMedianBlur_1080_1920_0_0_0_0_5_25_16_10_false_200 auMedianBlur_1080_1920_0_0_0_0_5_25_16_10_false_200_U0 1118
Add Instance auMedian3x3_1080_1920_0_0_0_1922_5_25_16_10_false_s grp_auMedian3x3_1080_1920_0_0_0_1922_5_25_16_10_false_s_fu_136 136
Add Instance auMedianBlur_1080_1920_0_0_0_0_5_25_16_10_false_s auMedianBlur_1080_1920_0_0_0_0_5_25_16_10_false_U0 1129
Add Instance auMedian3x3_1080_1920_0_0_0_1922_5_25_16_10_false_s grp_auMedian3x3_1080_1920_0_0_0_1922_5_25_16_10_false_s_fu_94 94
Add Instance findGradients findGradients_U0 1138
Add Instance findIntensity grp_findIntensity_fu_1707 1707
Add Instance find_G_and_b_matrix find_G_and_b_matrix_U0 1158
Add Instance scale_up199 scale_up199_U0 1174
Add Instance process_r grp_process_r_fu_375 375
Add Instance compute_result_16_10_45_22_48_16_s grp_compute_result_16_10_45_22_48_16_s_fu_488 488
Add Instance load_data_1920_16_10_45_22_17_1_s grp_load_data_1920_16_10_45_22_17_1_s_fu_390 390
Add Instance scale_up scale_up_U0 1188
Add Instance process_r grp_process_r_fu_333 333
Add Instance compute_result_16_10_45_22_48_16_s grp_compute_result_16_10_45_22_48_16_s_fu_488 488
Add Instance load_data_1920_16_10_45_22_17_1_s grp_load_data_1920_16_10_45_22_17_1_s_fu_348 348
Add Instance split_stream_int_fixed_unsigned_short_1080_unsigned_short_1920_16_10_448 split_stream_int_fixed_unsigned_short_1080_unsigned_short_1920_16_10_448_U0 1200
Add Instance stitch_stream_fixed_int_unsigned_short_1080_unsigned_short_1920_16_10_s stitch_stream_fixed_int_unsigned_short_1080_unsigned_short_1920_16_10_U0 1238
Add Instance Array2xfMat_32_3_1080_1920_1_1 Array2xfMat_32_3_1080_1920_1_1_U0 742
Add Instance Array2xfMat_32_3_1080_1920_1_s grp_Array2xfMat_32_3_1080_1920_1_s_fu_100 100
Add Instance hlsStrm2xfMat_32_3_1080_1920_1_2073600_s hlsStrm2xfMat_32_3_1080_1920_1_2073600_U0 136
Add Instance Array2hlsStrm_32_1080_1920_1_1_32_2073600_s Array2hlsStrm_32_1080_1920_1_1_32_2073600_U0 145
Add Instance xfMat2Array_32_3_1080_1920_1_s xfMat2Array_32_3_1080_1920_1_U0 752
Add Instance xfMat2Array_32_3_1080_1920_1_1 grp_xfMat2Array_32_3_1080_1920_1_1_fu_100 100
Add Instance xfMat2hlsStrm_32_3_1080_1920_1_2073600_22 xfMat2hlsStrm_32_3_1080_1920_1_2073600_22_U0 156
Add Instance hlsStrm2Array_32_1080_1920_1_1_32_2073600_s hlsStrm2Array_32_1080_1920_1_1_32_2073600_U0 172
Add Instance Array2xfMat_32_0_1080_1920_1_1 Array2xfMat_32_0_1080_1920_1_1_U0 762
Add Instance Array2xfMat_32_0_1080_1920_1_s grp_Array2xfMat_32_0_1080_1920_1_s_fu_80 80
Add Instance hlsStrm2xfMat_32_0_1080_1920_1_2073600_s hlsStrm2xfMat_32_0_1080_1920_1_2073600_U0 136
Add Instance Array2hlsStrm_32_1080_1920_1_1_8_518400_s Array2hlsStrm_32_1080_1920_1_1_8_518400_U0 145
Add Instance Array2xfMat_32_0_1080_1920_1_201 Array2xfMat_32_0_1080_1920_1_201_U0 772
Add Instance Array2xfMat_32_0_1080_1920_1_s grp_Array2xfMat_32_0_1080_1920_1_s_fu_142 142
Add Instance hlsStrm2xfMat_32_0_1080_1920_1_2073600_s hlsStrm2xfMat_32_0_1080_1920_1_2073600_U0 136
Add Instance Array2hlsStrm_32_1080_1920_1_1_8_518400_s Array2hlsStrm_32_1080_1920_1_1_8_518400_U0 145
Add Instance Block_proc93651 Block_proc93651_U0 784
INFO: [v++ 60-586] Created /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/pyr_dense_optical_flow_accel.xo
INFO: [v++ 60-791] Total elapsed time: 0h 2m 53s
-e ----
Compiling kernel pyr_down_accel...
mkdir -p /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw
v++ -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/pyr_down_accel.xo --kernel pyr_down_accel --compile /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_pyr_down_accel.cpp \
-I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/include -I. -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include -D__SDSVHLS__ -DHLS_NO_XIL_FPO_LIB --xp vivado_prop:run.impl_1.strategy=Performance_Explore --clock.defaultFreqHz 300000000 -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker --target hw --platform /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm --temp_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw --save-temps --debug --kernel_frequency 300 --report_level 2
WARNING: [v++ 60-1600] The option 'xp' was used directly on the command line, where its usage is deprecated. To ensure input line works for supported operating systems or shells, v++ supports specification for some options in a configuration file. As an alternative, please use options 'advanced.*', 'vivado.*' in a configuration file. Use one or more configuration files along with section headers to define key-value pairs for the advanced properties or parameters. Specify a configuration file using '--config'.
INFO: [v++ 84-14] Sample config file already exists. To regenerate, remove file 'sample_compile.ini'.
Option Map File Used: '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/data/vitis/vpp/optMap.xml'
****** v++ v2019.2 (64-bit)
**** SW Build 2700185 on Thu Oct 24 18:45:48 MDT 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
INFO: [v++ 60-1306] Additional information associated with this v++ compile can be found at:
Reports: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/reports/pyr_down_accel
Log files: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/logs/pyr_down_accel
Running Dispatch Server on port:46365
INFO: [v++ 60-1548] Creating build summary session with primary output /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/pyr_down_accel.xo.compile_summary, at Wed Apr 1 22:22:18 2020
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Wed Apr 1 22:22:18 2020
Running Rule Check Server on port:34213
INFO: [v++ 60-1315] Creating rulecheck session with output '/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/reports/pyr_down_accel/v++_compile_pyr_down_accel_guidance.html', at Wed Apr 1 22:22:19 2020
INFO: [v++ 60-895] Target platform: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm
INFO: [v++ 60-1578] This platform contains Xilinx Shell Archive '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/hw/ultra96v2_min2.xsa'
INFO: [v++ 60-585] Compiling for hardware target
INFO: [v++ 60-423] Target device: ultra96v2_min2
INFO: [v++ 60-242] Creating kernel: 'pyr_down_accel'
INFO: [v++ 60-1616] Creating a HLS clock using kernel_frequency option: 300 MHz
===>The following messages were generated while performing high-level synthesis for kernel: pyr_down_accel Log file: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/pyr_down_accel/pyr_down_accel/vivado_hls.log :
INFO: [v++ 204-61] Option 'relax_ii_for_timing' is enabled, will increase II to preserve clock frequency constraints.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining loop 'L1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 4.
INFO: [v++ 204-61] Pipelining function 'read'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining loop 'read_lines.1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining loop 'Col_Loop'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 9.
INFO: [v++ 204-61] Pipelining function 'write'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [v++ 204-61] Pipelining loop 'L1'.
INFO: [v++ 204-61] Discarding stage scheduling solution.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 2, Depth = 4.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 200-789] **** Estimated Fmax: 411.02 MHz
INFO: [v++ 60-594] Finished kernel compilation
INFO: [v++ 60-244] Generating system estimate report...
INFO: [v++ 60-1092] Generated system estimate report: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/reports/pyr_down_accel/system_estimate_pyr_down_accel.xtxt
Add Instance pyrDown_0_1080_1920_1_false_94 pyrDown_0_1080_1920_1_false_94_U0 604
Add Instance xFpyrDownKernel_1080u_1920u_0u_1u_1_false_s grp_xFpyrDownKernel_1080u_1920u_0u_1u_1_false_s_fu_80 80
Add Instance xFPyrDownGaussianBlur_1080_1920_0_1_1_0_5_25_1_s xFPyrDownGaussianBlur_1080_1920_0_1_1_0_5_25_1_U0 194
Add Instance xf_pyrdown_gaussian_nxn_1080_1920_0_1_1_1922_5_25_1_s grp_xf_pyrdown_gaussian_nxn_1080_1920_0_1_1_1922_5_25_1_s_fu_122 122
Add Instance xFpyrDownKernel_1080u_1920u_0u_1u_1_false_Loop_2_proc97 xFpyrDownKernel_1080u_1920u_0u_1u_1_false_Loop_2_proc97_U0 204
Add Instance write_r call_ln67_write_r_fu_145 145
Add Instance xFpyrDownKernel_1080u_1920u_0u_1u_1_false_Loop_1_proc96 xFpyrDownKernel_1080u_1920u_0u_1u_1_false_Loop_1_proc96_U0 213
Add Instance read_r tmp_V_read_r_fu_142 142
Add Instance pyrDown_0_1080_1920_1_false_s pyrDown_0_1080_1920_1_false_U0 612
Add Instance xFpyrDownKernel_1080u_1920u_0u_1u_1_false_s grp_xFpyrDownKernel_1080u_1920u_0u_1u_1_false_s_fu_80 80
Add Instance xFPyrDownGaussianBlur_1080_1920_0_1_1_0_5_25_1_s xFPyrDownGaussianBlur_1080_1920_0_1_1_0_5_25_1_U0 194
Add Instance xf_pyrdown_gaussian_nxn_1080_1920_0_1_1_1922_5_25_1_s grp_xf_pyrdown_gaussian_nxn_1080_1920_0_1_1_1922_5_25_1_s_fu_122 122
Add Instance xFpyrDownKernel_1080u_1920u_0u_1u_1_false_Loop_2_proc97 xFpyrDownKernel_1080u_1920u_0u_1u_1_false_Loop_2_proc97_U0 204
Add Instance write_r call_ln67_write_r_fu_145 145
Add Instance xFpyrDownKernel_1080u_1920u_0u_1u_1_false_Loop_1_proc96 xFpyrDownKernel_1080u_1920u_0u_1u_1_false_Loop_1_proc96_U0 213
Add Instance read_r tmp_V_read_r_fu_142 142
Add Instance Array2xfMat_32_0_1080_1920_1_93 Array2xfMat_32_0_1080_1920_1_93_U0 620
Add Instance Array2xfMat_32_0_1080_1920_1_s grp_Array2xfMat_32_0_1080_1920_1_s_fu_142 142
Add Instance hlsStrm2xfMat_32_0_1080_1920_1_2073600_s hlsStrm2xfMat_32_0_1080_1920_1_2073600_U0 136
Add Instance Array2hlsStrm_32_1080_1920_1_1_8_518400_s Array2hlsStrm_32_1080_1920_1_1_8_518400_U0 145
Add Instance Array2xfMat_32_0_1080_1920_1_1 Array2xfMat_32_0_1080_1920_1_1_U0 632
Add Instance Array2xfMat_32_0_1080_1920_1_s grp_Array2xfMat_32_0_1080_1920_1_s_fu_142 142
Add Instance hlsStrm2xfMat_32_0_1080_1920_1_2073600_s hlsStrm2xfMat_32_0_1080_1920_1_2073600_U0 136
Add Instance Array2hlsStrm_32_1080_1920_1_1_8_518400_s Array2hlsStrm_32_1080_1920_1_1_8_518400_U0 145
Add Instance xfMat2Array_32_0_1080_1920_1_95 xfMat2Array_32_0_1080_1920_1_95_U0 644
Add Instance xfMat2Array_32_0_1080_1920_1_1 grp_xfMat2Array_32_0_1080_1920_1_1_fu_100 100
Add Instance xfMat2hlsStrm_32_0_1080_1920_1_2073600_13 xfMat2hlsStrm_32_0_1080_1920_1_2073600_13_U0 156
Add Instance hlsStrm2Array_32_1080_1920_1_1_8_518400_s hlsStrm2Array_32_1080_1920_1_1_8_518400_U0 172
Add Instance xfMat2Array_32_0_1080_1920_1_s xfMat2Array_32_0_1080_1920_1_U0 654
Add Instance xfMat2Array_32_0_1080_1920_1_1 grp_xfMat2Array_32_0_1080_1920_1_1_fu_100 100
Add Instance xfMat2hlsStrm_32_0_1080_1920_1_2073600_13 xfMat2hlsStrm_32_0_1080_1920_1_2073600_13_U0 156
Add Instance hlsStrm2Array_32_1080_1920_1_1_8_518400_s hlsStrm2Array_32_1080_1920_1_1_8_518400_U0 172
Add Instance Block_proc40 Block_proc40_U0 664
INFO: [v++ 60-586] Created /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/pyr_down_accel.xo
INFO: [v++ 60-791] Total elapsed time: 0h 1m 6s
-e ----
Compiling kernel cornerupdate_accel...
mkdir -p /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw
v++ -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/cornerupdate_accel.xo --kernel cornerupdate_accel --compile /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_cornerupdate_accel.cpp \
-I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/include -I. -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include -D__SDSVHLS__ -DHLS_NO_XIL_FPO_LIB --xp vivado_prop:run.impl_1.strategy=Performance_Explore --clock.defaultFreqHz 300000000 -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker --target hw --platform /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm --temp_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw --save-temps --debug --kernel_frequency 300 --report_level 2 -D__SDA_MEM_MAP__
WARNING: [v++ 60-1600] The option 'xp' was used directly on the command line, where its usage is deprecated. To ensure input line works for supported operating systems or shells, v++ supports specification for some options in a configuration file. As an alternative, please use options 'advanced.*', 'vivado.*' in a configuration file. Use one or more configuration files along with section headers to define key-value pairs for the advanced properties or parameters. Specify a configuration file using '--config'.
INFO: [v++ 84-14] Sample config file already exists. To regenerate, remove file 'sample_compile.ini'.
Option Map File Used: '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/data/vitis/vpp/optMap.xml'
****** v++ v2019.2 (64-bit)
**** SW Build 2700185 on Thu Oct 24 18:45:48 MDT 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
INFO: [v++ 60-1306] Additional information associated with this v++ compile can be found at:
Reports: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/reports/cornerupdate_accel
Log files: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/logs/cornerupdate_accel
Running Dispatch Server on port:33547
INFO: [v++ 60-1548] Creating build summary session with primary output /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/cornerupdate_accel.xo.compile_summary, at Wed Apr 1 22:23:27 2020
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Wed Apr 1 22:23:27 2020
Running Rule Check Server on port:45645
INFO: [v++ 60-1315] Creating rulecheck session with output '/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/reports/cornerupdate_accel/v++_compile_cornerupdate_accel_guidance.html', at Wed Apr 1 22:23:28 2020
INFO: [v++ 60-895] Target platform: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm
INFO: [v++ 60-1578] This platform contains Xilinx Shell Archive '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/hw/ultra96v2_min2.xsa'
INFO: [v++ 60-585] Compiling for hardware target
INFO: [v++ 60-423] Target device: ultra96v2_min2
INFO: [v++ 60-242] Creating kernel: 'cornerupdate_accel'
INFO: [v++ 60-1616] Creating a HLS clock using kernel_frequency option: 300 MHz
===>The following messages were generated while performing high-level synthesis for kernel: cornerupdate_accel Log file: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/cornerupdate_accel/cornerupdate_accel/vivado_hls.log :
INFO: [v++ 204-61] Option 'relax_ii_for_timing' is enabled, will increase II to preserve clock frequency constraints.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
INFO: [v++ 204-61] Discarding stage scheduling solution.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 33.
INFO: [v++ 200-790] **** Loop Constraint Status: All loop constraints were satisfied.
INFO: [v++ 200-789] **** Estimated Fmax: 347.71 MHz
INFO: [v++ 60-594] Finished kernel compilation
INFO: [v++ 60-244] Generating system estimate report...
INFO: [v++ 60-1092] Generated system estimate report: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/reports/cornerupdate_accel/system_estimate_cornerupdate_accel.xtxt
Add Instance cornerUpdate_10000u_3u_1080u_1920u_1u_s grp_cornerUpdate_10000u_3u_1080u_1920u_1u_s_fu_120 120
INFO: [v++ 60-586] Created /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/cornerupdate_accel.xo
INFO: [v++ 60-791] Total elapsed time: 0h 0m 47s
-e ----
Compiling kernel cornerTracker...
mkdir -p /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw
v++ -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/cornerTracker.xo --kernel cornerTracker --compile /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_corner_tracker_accel.cpp \
-I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/include -I. -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include -D__SDSVHLS__ -DHLS_NO_XIL_FPO_LIB --xp vivado_prop:run.impl_1.strategy=Performance_Explore --clock.defaultFreqHz 300000000 -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker --target hw --platform /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm --temp_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw --save-temps --debug --kernel_frequency 300 --report_level 2
WARNING: [v++ 60-1600] The option 'xp' was used directly on the command line, where its usage is deprecated. To ensure input line works for supported operating systems or shells, v++ supports specification for some options in a configuration file. As an alternative, please use options 'advanced.*', 'vivado.*' in a configuration file. Use one or more configuration files along with section headers to define key-value pairs for the advanced properties or parameters. Specify a configuration file using '--config'.
INFO: [v++ 84-14] Sample config file already exists. To regenerate, remove file 'sample_compile.ini'.
Option Map File Used: '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/data/vitis/vpp/optMap.xml'
****** v++ v2019.2 (64-bit)
**** SW Build 2700185 on Thu Oct 24 18:45:48 MDT 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
INFO: [v++ 60-1306] Additional information associated with this v++ compile can be found at:
Reports: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/reports/cornerTracker
Log files: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/logs/cornerTracker
Running Dispatch Server on port:35195
INFO: [v++ 60-1548] Creating build summary session with primary output /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/cornerTracker.xo.compile_summary, at Wed Apr 1 22:24:16 2020
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Wed Apr 1 22:24:16 2020
Running Rule Check Server on port:41237
INFO: [v++ 60-1315] Creating rulecheck session with output '/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/reports/cornerTracker/v++_compile_cornerTracker_guidance.html', at Wed Apr 1 22:24:17 2020
INFO: [v++ 60-895] Target platform: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm
INFO: [v++ 60-1578] This platform contains Xilinx Shell Archive '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/hw/ultra96v2_min2.xsa'
INFO: [v++ 60-585] Compiling for hardware target
INFO: [v++ 60-423] Target device: ultra96v2_min2
INFO: [v++ 60-242] Creating kernel: 'cornerTracker'
INFO: [v++ 60-1616] Creating a HLS clock using kernel_frequency option: 300 MHz
===>The following messages were generated while performing high-level synthesis for kernel: cornerTracker Log file: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/cornerTracker/cornerTracker/vivado_hls.log :
INFO: [v++ 204-61] Option 'relax_ii_for_timing' is enabled, will increase II to preserve clock frequency constraints.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining loop 'L1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 4.
INFO: [v++ 204-61] Pipelining function 'xFGradientX3x3<0, 3>'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining function 'xFGradientY3x3<0, 3>'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining function 'xFSobel3x3<1, 1, 0, 3>'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining loop 'Clear_Row_Loop'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining loop 'Col_Loop'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 7.
INFO: [v++ 204-61] Pipelining loop 'Col_Loop'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [v++ 204-61] Pipelining loop 'Col_Loop'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [v++ 204-61] Pipelining function 'xfExtractPixels<1, 5, 3>'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining loop 'Col_Loop'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 6.
INFO: [v++ 204-61] Pipelining loop 'Col_Loop'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 6.
INFO: [v++ 204-61] Pipelining loop 'Col_Loop'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 5.
INFO: [v++ 204-61] Pipelining function 'xFApplyMask3x3<3>'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 6.
INFO: [v++ 204-61] Pipelining loop 'bufColLoop'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining loop 'colLoop1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 12.
INFO: [v++ 204-61] Pipelining loop 'Col_Loop'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 12.
INFO: [v++ 204-61] Pipelining loop 'Col_Loop'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining function 'xfExtractPixels<1, 12, 5>'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining function 'xFFindMaxRad1<ap_int<32> >'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining function 'xFSuppressionRad1<1, 5, ap_uint<8> >'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining loop 'Col_Loop'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 7.
INFO: [v++ 204-61] Pipelining loop 'Clear_first_Row'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining loop 'Clear_Row_Loop'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 2, Depth = 9.
INFO: [v++ 204-61] Pipelining loop 'Loop 2'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 8.
INFO: [v++ 200-789] **** Estimated Fmax: 300.03 MHz
INFO: [v++ 60-594] Finished kernel compilation
INFO: [v++ 60-244] Generating system estimate report...
INFO: [v++ 60-1092] Generated system estimate report: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/reports/cornerTracker/system_estimate_cornerTracker.xtxt
Add Instance HarrisImg grp_HarrisImg_fu_168 168
Add Instance cornerHarris_3_3_1_0_1080_1920_1_false_s cornerHarris_3_3_1_0_1080_1920_1_false_U0 172
Add Instance xFCornerHarrisDetector_3_3_0_1080_1920_1_0_1_1_12_1920_5_12_false_s grp_xFCornerHarrisDetector_3_3_0_1080_1920_1_0_1_1_12_1920_5_12_false_s_fu_58 58
Add Instance xFMaxSuppression_5_0_1080_1920_5_0_1_12_1_303 xFMaxSuppression_5_0_1080_1920_5_0_1_12_1_303_U0 398
Add Instance xFMaxSuppressionRad1_5_0_1080_1920_5_0_1_12_1_1920_310 grp_xFMaxSuppressionRad1_5_0_1080_1920_5_0_1_12_1_1920_310_fu_38 38
Add Instance ProcessMax1_5_0_1080_1920_5_0_1_12_1_1920_311 grp_ProcessMax1_5_0_1080_1920_5_0_1_12_1_1920_311_fu_366 366
Add Instance xFSuppressionRad1_1_5_ap_uint_8_s call_ret_xFSuppressionRad1_1_5_ap_uint_8_s_fu_423 423
Add Instance xFFindMaxRad1_ap_int_32_s Max_xFFindMaxRad1_ap_int_32_s_fu_44 44
Add Instance xfExtractPixels_1_12_5_s call_ret3_xfExtractPixels_1_12_5_s_fu_436 436
Add Instance xfExtractPixels_1_12_5_s call_ret2_xfExtractPixels_1_12_5_s_fu_441 441
Add Instance xfExtractPixels_1_12_5_s call_ret4_xfExtractPixels_1_12_5_s_fu_446 446
Add Instance xFFindMaxRad1_ap_int_32_s grp_xFFindMaxRad1_ap_int_32_s_fu_400 400
Add Instance Sobel_0_3_0_2_1080_1920_1_false_302 Sobel_0_3_0_2_1080_1920_1_false_302_U0 407
Add Instance xFSobelFilter3x3_0_2_1080_1920_1_0_3_1_1_5_1920_false_312 grp_xFSobelFilter3x3_0_2_1080_1920_1_0_3_1_1_5_1920_false_312_fu_40 40
Add Instance xFSobel3x3_1_1_0_3_s call_ret_xFSobel3x3_1_1_0_3_s_fu_390 390
Add Instance xFGradientX3x3_0_3_s GradientvaluesX_V_write_assign_xFGradientX3x3_0_3_s_fu_72 72
Add Instance xFGradientY3x3_0_3_s GradientvaluesY_V_write_assign_xFGradientY3x3_0_3_s_fu_88 88
Add Instance xFGradientX3x3_0_3_s GradientValuesX_0_V_xFGradientX3x3_0_3_s_fu_407 407
Add Instance xFGradientY3x3_0_3_s GradientValuesY_0_V_xFGradientY3x3_0_3_s_fu_423 423
Add Instance boxFilter_0_3_2_1080_1920_1_false_208 boxFilter_0_3_2_1080_1920_1_false_208_U0 417
Add Instance xFBoxFilter3x3_2_1080_1920_3_1_5_5_1920_false_s grp_xFBoxFilter3x3_2_1080_1920_3_1_5_5_1920_false_s_fu_38 38
Add Instance xFApplyMask3x3_3_s grp_xFApplyMask3x3_3_s_fu_375 375
Add Instance boxFilter_0_3_2_1080_1920_1_false_209 boxFilter_0_3_2_1080_1920_1_false_209_U0 425
Add Instance xFBoxFilter3x3_2_1080_1920_3_1_5_5_1920_false_s grp_xFBoxFilter3x3_2_1080_1920_3_1_5_5_1920_false_s_fu_38 38
Add Instance xFApplyMask3x3_3_s grp_xFApplyMask3x3_3_s_fu_375 375
Add Instance boxFilter_0_3_2_1080_1920_1_false_s boxFilter_0_3_2_1080_1920_1_false_U0 433
Add Instance xFBoxFilter3x3_2_1080_1920_3_1_5_5_1920_false_s grp_xFBoxFilter3x3_2_1080_1920_3_1_5_5_1920_false_s_fu_38 38
Add Instance xFApplyMask3x3_3_s grp_xFApplyMask3x3_3_s_fu_375 375
Add Instance xFComputeScore_2_5_1080_1920_3_5_1_5_12_1920_s xFComputeScore_2_5_1080_1920_3_5_1_5_12_1920_U0 441
Add Instance xFThreshold_5_1080_1920_5_1_12_1920_s xFThreshold_5_1080_1920_5_1_12_1920_U0 454
Add Instance xFSquare_2_2_1080_1920_3_3_1_5_5_1920_int_207 xFSquare_2_2_1080_1920_3_3_1_5_5_1920_int_207_U0 465
Add Instance xfExtractPixels_1_5_3_s src_buf_0_V_xfExtractPixels_1_5_3_s_fu_137 137
Add Instance xFSquare_2_2_1080_1920_3_3_1_5_5_1920_int_s xFSquare_2_2_1080_1920_3_3_1_5_5_1920_int_U0 475
Add Instance xfExtractPixels_1_5_3_s src_buf_0_V_xfExtractPixels_1_5_3_s_fu_115 115
Add Instance xFMultiply_2_2_1080_1920_3_3_1_5_5_1920_int_s xFMultiply_2_2_1080_1920_3_3_1_5_5_1920_int_U0 483
Add Instance xfExtractPixels_1_5_3_s src_buf1_0_V_xfExtractPixels_1_5_3_s_fu_117 117
Add Instance xfExtractPixels_1_5_3_s src_buf2_0_V_xfExtractPixels_1_5_3_s_fu_123 123
Add Instance xFDuplicate_2_1080_1920_3_1_5_1920_206 xFDuplicate_2_1080_1920_3_1_5_1920_206_U0 492
Add Instance xFDuplicate_2_1080_1920_3_1_5_1920_s xFDuplicate_2_1080_1920_3_1_5_1920_U0 505
Add Instance xFCornerHarrisDetector_entry256 xFCornerHarrisDetector_entry256_U0 516
Add Instance xFCornerHarrisDetector_Block_Mat_exit7715_proc xFCornerHarrisDetector_Block_Mat_exit7715_proc_U0 542
Add Instance Array2xfMat_32_0_1080_1920_1_1 Array2xfMat_32_0_1080_1920_1_1_U0 182
Add Instance Array2xfMat_32_0_1080_1920_1_s grp_Array2xfMat_32_0_1080_1920_1_s_fu_76 76
Add Instance hlsStrm2xfMat_32_0_1080_1920_1_2073600_s hlsStrm2xfMat_32_0_1080_1920_1_2073600_U0 82
Add Instance Array2hlsStrm_32_1080_1920_1_1_8_518400_s Array2hlsStrm_32_1080_1920_1_1_8_518400_U0 91
Add Instance cornersImgToList_10000u_0u_1080u_1920u_1u_s cornersImgToList_10000u_0u_1080u_1920u_1u_U0 194
Add Instance HarrisImg_Block_Mat_exit72_proc27127 HarrisImg_Block_Mat_exit72_proc27127_U0 206
INFO: [v++ 60-586] Created /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/cornerTracker.xo
INFO: [v++ 60-791] Total elapsed time: 0h 1m 36s
-e ----
Compiling xclbin...
mkdir -p /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xclbin_ultra96v2_min2_hw
v++ -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xclbin_ultra96v2_min2_hw/krnl_cornertracker.xclbin --link /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/pyr_dense_optical_flow_accel.xo /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/pyr_down_accel.xo /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/cornerupdate_accel.xo /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/cornerTracker.xo \
-I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/include -I. -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include -D__SDSVHLS__ -DHLS_NO_XIL_FPO_LIB --xp vivado_prop:run.impl_1.strategy=Performance_Explore --clock.defaultFreqHz 300000000 -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker --target hw --platform /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm --temp_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw --save-temps --debug --kernel_frequency 300 --report_level 2 --optimize 2 --jobs 8 --xp "vivado_param:project.writeIntermediateCheckpoints=1" \
-D__SDA_MEM_MAP__ \
WARNING: [v++ 60-1600] The option 'xp' was used directly on the command line, where its usage is deprecated. To ensure input line works for supported operating systems or shells, v++ supports specification for some options in a configuration file. As an alternative, please use options 'advanced.*', 'vivado.*' in a configuration file. Use one or more configuration files along with section headers to define key-value pairs for the advanced properties or parameters. Specify a configuration file using '--config'.
INFO: [v++ 82-185] Check out the auto-generated 'sample_link.ini' configuration file. The file shows how to migrate from deprecated command line --xp switches to configuration file directives.
Option Map File Used: '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/data/vitis/vpp/optMap.xml'
****** v++ v2019.2 (64-bit)
**** SW Build 2700185 on Thu Oct 24 18:45:48 MDT 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
INFO: [v++ 60-1306] Additional information associated with this v++ link can be found at:
Reports: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/reports/link
Log files: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/logs/link
Running Dispatch Server on port:42571
INFO: [v++ 60-1548] Creating build summary session with primary output /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xclbin_ultra96v2_min2_hw/krnl_cornertracker.xclbin.link_summary, at Wed Apr 1 22:25:54 2020
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Wed Apr 1 22:25:54 2020
Running Rule Check Server on port:40987
INFO: [v++ 60-1315] Creating rulecheck session with output '/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/reports/link/v++_link_krnl_cornertracker_guidance.html', at Wed Apr 1 22:25:55 2020
INFO: [v++ 60-895] Target platform: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm
INFO: [v++ 60-1578] This platform contains Xilinx Shell Archive '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/hw/ultra96v2_min2.xsa'
INFO: [v++ 60-629] Linking for hardware target
INFO: [v++ 60-423] Target device: ultra96v2_min2
INFO: [v++ 60-1332] Run 'run_link' status: Not started
INFO: [v++ 60-1443] [22:25:56] Run run_link: Step system_link: Started
INFO: [v++ 60-1453] Command Line: system_link --xo /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/pyr_dense_optical_flow_accel.xo --xo /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/pyr_down_accel.xo --xo /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/cornerupdate_accel.xo --xo /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/cornerTracker.xo -keep --config /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/int/syslinkConfig.ini --xpfm /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm --target hw --output_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/int --temp_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/sys_link
INFO: [v++ 60-1454] Run Directory: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/run_link
INFO: [SYSTEM_LINK 82-76] Reading emulation BD and HPFM information
INFO: [SYSTEM_LINK 60-1316] Initiating connection to rulecheck server, at Wed Apr 1 22:25:57 2020
INFO: [SYSTEM_LINK 82-70] Extracting xo v3 file /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/pyr_dense_optical_flow_accel.xo
INFO: [KernelCheck 83-118] 'pyr_dense_optical_flow_accel' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] '_current_img' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] '_next_image' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] '_streamFlowin' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] '_streamFlowout' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'level' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'scale_up_flag' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'scale_in' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'init_flag' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'cur_img_rows' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'cur_img_cols' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'next_img_rows' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'next_img_cols' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'flow_rows' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'flow_cols' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'flow_iter_rows' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'flow_iter_cols' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [SYSTEM_LINK 82-70] Extracting xo v3 file /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/pyr_down_accel.xo
INFO: [KernelCheck 83-118] 'pyr_down_accel' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'inImgPyr1' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'outImgPyr1' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'inImgPyr2' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'outImgPyr2' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'pyr_h' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'pyr_w' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'pyr_out_h' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'pyr_out_w' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [SYSTEM_LINK 82-70] Extracting xo v3 file /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/cornerupdate_accel.xo
INFO: [KernelCheck 83-118] 'cornerupdate_accel' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'list_fix' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'list' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'nCorners' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'flow_vectors' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'harris_flag' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'flow_rows' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'flow_cols' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [SYSTEM_LINK 82-70] Extracting xo v3 file /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/cornerTracker.xo
INFO: [KernelCheck 83-118] 'cornerTracker' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'inHarris' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'list' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'params' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'harris_rows' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'harris_cols' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [SYSTEM_LINK 82-53] Creating IP database /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/sys_link/_sysl/.cdb/xd_ip_db.xml
INFO: [SYSTEM_LINK 82-38] [22:25:58] build_xd_ip_db started: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/bin/build_xd_ip_db -ip_search 0 -sds-pf /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/sys_link/ultra96v2_min2.hpfm -clkid 0 -ip /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/sys_link/iprepo/xilinx_com_hls_pyr_down_accel_1_0,pyr_down_accel -ip /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/sys_link/iprepo/xilinx_com_hls_cornerTracker_1_0,cornerTracker -ip /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/sys_link/iprepo/xilinx_com_hls_cornerupdate_accel_1_0,cornerupdate_accel -ip /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/sys_link/iprepo/xilinx_com_hls_pyr_dense_optical_flow_accel_1_0,pyr_dense_optical_flow_accel -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/sys_link/_sysl/.cdb/xd_ip_db.xml
INFO: [SYSTEM_LINK 82-37] [22:26:02] build_xd_ip_db finished successfully
Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 296.445 ; gain = 0.000 ; free physical = 8124 ; free virtual = 38651
INFO: [SYSTEM_LINK 82-51] Create system connectivity graph
INFO: [SYSTEM_LINK 82-102] Applying explicit connections to the system connectivity graph: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/sys_link/cfgraph/cfgen_cfgraph.xml
INFO: [SYSTEM_LINK 82-38] [22:26:02] cfgen started: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/bin/cfgen -clock.defaultFreqHz 300000000 -dmclkid 0 -r /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/sys_link/cfgraph/cfgen_cfgraph.xml
INFO: [CFGEN 83-0] Kernel Specs:
INFO: [CFGEN 83-0] kernel: cornerTracker, num: 1 {cornerTracker_1}
INFO: [CFGEN 83-0] kernel: cornerupdate_accel, num: 1 {cornerupdate_accel_1}
INFO: [CFGEN 83-0] kernel: pyr_dense_optical_flow_accel, num: 1 {pyr_dense_optical_flow_accel_1}
INFO: [CFGEN 83-0] kernel: pyr_down_accel, num: 1 {pyr_down_accel_1}
INFO: [CFGEN 83-2226] Inferring mapping for argument cornerTracker_1.inHarris to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument cornerTracker_1.list to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument cornerTracker_1.params to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument cornerupdate_accel_1.list_fix to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument cornerupdate_accel_1.list to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument cornerupdate_accel_1.flow_vectors to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument pyr_dense_optical_flow_accel_1._current_img to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument pyr_dense_optical_flow_accel_1._next_image to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument pyr_dense_optical_flow_accel_1._streamFlowin to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument pyr_dense_optical_flow_accel_1._streamFlowout to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument pyr_down_accel_1.inImgPyr1 to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument pyr_down_accel_1.outImgPyr1 to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument pyr_down_accel_1.inImgPyr2 to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument pyr_down_accel_1.outImgPyr2 to HP
INFO: [SYSTEM_LINK 82-37] [22:26:02] cfgen finished successfully
Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:00.50 . Memory (MB): peak = 296.445 ; gain = 0.000 ; free physical = 8140 ; free virtual = 38667
INFO: [SYSTEM_LINK 82-52] Create top-level block diagram
INFO: [SYSTEM_LINK 82-38] [22:26:02] cf2bd started: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/bin/cf2bd --linux --trace_buffer 1024 --input_file /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/sys_link/cfgraph/cfgen_cfgraph.xml --ip_db /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/sys_link/_sysl/.cdb/xd_ip_db.xml --cf_name dr --working_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/sys_link/_sysl/.xsd --temp_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/sys_link --output_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/int
INFO: [CF2BD 82-31] Launching cf2xd: cf2xd -linux -trace-buffer 1024 -i /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/sys_link/cfgraph/cfgen_cfgraph.xml -r /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o dr.xml
INFO: [CF2BD 82-28] cf2xd finished successfully
INFO: [CF2BD 82-31] Launching cf_xsd: cf_xsd -disable-address-gen -dn dr -dp /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/sys_link/_sysl/.xsd
rlwrap: warning: your $TERM is 'xterm-256color' but rlwrap couldn't find it in the terminfo database. Expect some problems.: Inappropriate ioctl for device
INFO: [CF2BD 82-28] cf_xsd finished successfully
INFO: [SYSTEM_LINK 82-37] [22:26:05] cf2bd finished successfully
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 296.445 ; gain = 0.000 ; free physical = 8132 ; free virtual = 38664
INFO: [v++ 60-1441] [22:26:05] Run run_link: Step system_link: Completed
Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 679.699 ; gain = 0.000 ; free physical = 8153 ; free virtual = 38686
INFO: [v++ 60-1443] [22:26:05] Run run_link: Step cf2sw: Started
INFO: [v++ 60-1453] Command Line: cf2sw -sdsl /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/int/sdsl.dat -rtd /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/int/cf2sw.rtd -xclbin /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/int/xclbin_orig.xml -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/int/xclbin_orig.1.xml
INFO: [v++ 60-1454] Run Directory: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/run_link
INFO: [v++ 60-1441] [22:26:06] Run run_link: Step cf2sw: Completed
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 679.699 ; gain = 0.000 ; free physical = 8151 ; free virtual = 38685
INFO: [v++ 60-1443] [22:26:06] Run run_link: Step rtd2_system_diagram: Started
INFO: [v++ 60-1453] Command Line: rtd2SystemDiagram --rtdJsonFileName /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/int/cf2sw.rtd --diagramJsonFileName /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/int/systemDiagramModel.json --platformFilePath /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm --generatedByName v++ --generatedByVersion 2019.2 --generatedByChangeList 2700185 --generatedByTimeStamp Thu Oct 24 18:45:48 MDT 2019 --generatedByOptions /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/bin/unwrapped/lnx64.o/v++ -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xclbin_ultra96v2_min2_hw/krnl_cornertracker.xclbin --link /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/pyr_dense_optical_flow_accel.xo /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/pyr_down_accel.xo /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/cornerupdate_accel.xo /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/cornerTracker.xo -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/include -I. -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include -D__SDSVHLS__ -DHLS_NO_XIL_FPO_LIB --xp vivado_prop:run.impl_1.strategy=Performance_Explore --clock.defaultFreqHz 300000000 -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker --target hw --platform /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm --temp_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw --save-temps --debug --kernel_frequency 300 --report_level 2 --optimize 2 --jobs 8 --xp vivado_param:project.writeIntermediateCheckpoints=1 -D__SDA_MEM_MAP__ --generatedByXclbinName krnl_cornertracker --kernelInfoDataFileName /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/int/kernel_info.dat
INFO: [v++ 60-1454] Run Directory: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/run_link
WARNING: [v++ 82-164] Unable to populate user region instance path. The platform file does not contain a hardwarePlatform.devices..core.instPath entry.
INFO: [v++ 60-839] Read in kernel information from file '/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/int/kernel_info.dat'.
WARNING: [v++ 82-157] Unable to populate kernel available resources BRAM entry.
WARNING: [v++ 82-158] Unable to populate kernel available resources DSP entry.
WARNING: [v++ 82-157] Unable to populate kernel available resources BRAM entry.
WARNING: [v++ 82-158] Unable to populate kernel available resources DSP entry.
WARNING: [v++ 82-157] Unable to populate kernel available resources BRAM entry.
WARNING: [v++ 82-158] Unable to populate kernel available resources DSP entry.
WARNING: [v++ 82-163] Unable to populate user region available resources. The platform file deos not contain a hardwarePlatform.devices..core.availableResources entry
INFO: [v++ 60-1441] [22:26:08] Run run_link: Step rtd2_system_diagram: Completed
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 679.699 ; gain = 0.000 ; free physical = 8152 ; free virtual = 38684
INFO: [v++ 60-1443] [22:26:08] Run run_link: Step vpl: Started
INFO: [v++ 60-1453] Command Line: vpl -t hw -f /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm -g -j 8 --kernel_frequency 300 -s --output_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/int --log_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/logs/link --report_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/reports/link --config /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/int/vplConfig.ini -k /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/int/kernel_info.dat --webtalk_flag Vitis --temp_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link --no-info --tlog_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/.tlog/v++_link_krnl_cornertracker --iprepo /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/int/xo/ip_repo/xilinx_com_hls_cornerupdate_accel_1_0 --iprepo /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/int/xo/ip_repo/xilinx_com_hls_pyr_down_accel_1_0 --iprepo /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/int/xo/ip_repo/xilinx_com_hls_cornerTracker_1_0 --iprepo /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/int/xo/ip_repo/xilinx_com_hls_pyr_dense_optical_flow_accel_1_0 --messageDb /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/run_link/vpl.pb /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/int/dr.bd.tcl
INFO: [v++ 60-1454] Run Directory: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/run_link
****** vpl v2019.2 (64-bit)
**** SW Build 2700185 on Thu Oct 24 18:45:48 MDT 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
INFO: [VPL 60-839] Read in kernel information from file '/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/int/kernel_info.dat'.
INFO: [VPL 60-423] Target device: ultra96v2_min2
INFO: [VPL 60-1032] Extracting hardware platform to /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/vivado/vpl/.local/hw_platform
[22:26:19] Run vpl: Step create_project: Started
Creating Vivado project.
[22:26:28] Run vpl: Step create_project: Completed
[22:26:28] Run vpl: Step create_bd: Started
[22:26:41] Run vpl: Step create_bd: Completed
[22:26:41] Run vpl: Step update_bd: Started
[22:26:43] Run vpl: Step update_bd: Completed
[22:26:43] Run vpl: Step generate_target: Started
[22:27:30] Run vpl: Step generate_target: Completed
[22:27:30] Run vpl: Step config_hw_runs: Started
[22:27:34] Run vpl: Step config_hw_runs: Completed
[22:27:34] Run vpl: Step synth: Started
[22:28:36] Block-level synthesis in progress, 0 of 49 jobs complete, 8 jobs running.
[22:29:06] Block-level synthesis in progress, 0 of 49 jobs complete, 8 jobs running.
[22:29:38] Block-level synthesis in progress, 0 of 49 jobs complete, 8 jobs running.
[22:30:08] Block-level synthesis in progress, 0 of 49 jobs complete, 8 jobs running.
[22:30:38] Block-level synthesis in progress, 0 of 49 jobs complete, 8 jobs running.
[22:31:09] Block-level synthesis in progress, 0 of 49 jobs complete, 8 jobs running.
[22:31:39] Block-level synthesis in progress, 0 of 49 jobs complete, 8 jobs running.
[22:32:10] Block-level synthesis in progress, 3 of 49 jobs complete, 5 jobs running.
[22:32:40] Block-level synthesis in progress, 3 of 49 jobs complete, 5 jobs running.
[22:33:10] Block-level synthesis in progress, 8 of 49 jobs complete, 3 jobs running.
[22:33:41] Block-level synthesis in progress, 9 of 49 jobs complete, 5 jobs running.
[22:34:11] Block-level synthesis in progress, 11 of 49 jobs complete, 5 jobs running.
[22:34:41] Block-level synthesis in progress, 12 of 49 jobs complete, 7 jobs running.
[22:35:12] Block-level synthesis in progress, 12 of 49 jobs complete, 8 jobs running.
[22:35:42] Block-level synthesis in progress, 12 of 49 jobs complete, 8 jobs running.
[22:36:13] Block-level synthesis in progress, 12 of 49 jobs complete, 8 jobs running.
[22:36:43] Block-level synthesis in progress, 13 of 49 jobs complete, 7 jobs running.
[22:37:14] Block-level synthesis in progress, 13 of 49 jobs complete, 7 jobs running.
[22:37:44] Block-level synthesis in progress, 14 of 49 jobs complete, 7 jobs running.
[22:38:15] Block-level synthesis in progress, 14 of 49 jobs complete, 7 jobs running.
[22:38:46] Block-level synthesis in progress, 15 of 49 jobs complete, 7 jobs running.
[22:39:16] Block-level synthesis in progress, 17 of 49 jobs complete, 5 jobs running.
[22:39:47] Block-level synthesis in progress, 17 of 49 jobs complete, 6 jobs running.
[22:40:18] Block-level synthesis in progress, 19 of 49 jobs complete, 6 jobs running.
[22:40:49] Block-level synthesis in progress, 19 of 49 jobs complete, 7 jobs running.
[22:41:20] Block-level synthesis in progress, 21 of 49 jobs complete, 6 jobs running.
[22:41:51] Block-level synthesis in progress, 22 of 49 jobs complete, 7 jobs running.
[22:42:21] Block-level synthesis in progress, 22 of 49 jobs complete, 7 jobs running.
[22:42:52] Block-level synthesis in progress, 23 of 49 jobs complete, 7 jobs running.
[22:43:23] Block-level synthesis in progress, 24 of 49 jobs complete, 7 jobs running.
[22:43:54] Block-level synthesis in progress, 25 of 49 jobs complete, 6 jobs running.
[22:44:25] Block-level synthesis in progress, 27 of 49 jobs complete, 6 jobs running.
[22:44:56] Block-level synthesis in progress, 27 of 49 jobs complete, 6 jobs running.
[22:45:27] Block-level synthesis in progress, 29 of 49 jobs complete, 6 jobs running.
[22:45:58] Block-level synthesis in progress, 33 of 49 jobs complete, 4 jobs running.
[22:46:29] Block-level synthesis in progress, 34 of 49 jobs complete, 3 jobs running.
[22:47:00] Block-level synthesis in progress, 39 of 49 jobs complete, 3 jobs running.
[22:47:31] Block-level synthesis in progress, 40 of 49 jobs complete, 2 jobs running.
[22:48:01] Block-level synthesis in progress, 46 of 49 jobs complete, 2 jobs running.
[22:48:32] Block-level synthesis in progress, 48 of 49 jobs complete, 1 job running.
[22:49:02] Block-level synthesis in progress, 48 of 49 jobs complete, 1 job running.
[22:49:32] Block-level synthesis in progress, 48 of 49 jobs complete, 1 job running.
[22:50:03] Block-level synthesis in progress, 48 of 49 jobs complete, 1 job running.
[22:50:33] Block-level synthesis in progress, 48 of 49 jobs complete, 1 job running.
[22:51:03] Block-level synthesis in progress, 48 of 49 jobs complete, 1 job running.
[22:51:34] Block-level synthesis in progress, 48 of 49 jobs complete, 1 job running.
[22:52:04] Block-level synthesis in progress, 48 of 49 jobs complete, 1 job running.
[22:52:34] Block-level synthesis in progress, 48 of 49 jobs complete, 1 job running.
[22:53:05] Block-level synthesis in progress, 48 of 49 jobs complete, 1 job running.
[22:53:35] Block-level synthesis in progress, 48 of 49 jobs complete, 1 job running.
[22:54:05] Block-level synthesis in progress, 48 of 49 jobs complete, 1 job running.
[22:54:36] Block-level synthesis in progress, 48 of 49 jobs complete, 1 job running.
[22:55:06] Block-level synthesis in progress, 48 of 49 jobs complete, 1 job running.
[22:55:37] Block-level synthesis in progress, 48 of 49 jobs complete, 1 job running.
[22:56:07] Block-level synthesis in progress, 49 of 49 jobs complete, 0 jobs running.
[22:56:37] Top-level synthesis in progress.
[22:57:08] Top-level synthesis in progress.
[22:57:38] Top-level synthesis in progress.
[22:58:08] Run vpl: Step synth: Completed
[22:58:08] Run vpl: Step impl: Started
[23:01:10] Finished 2nd of 6 tasks (FPGA linking synthesized kernels to platform). Elapsed time: 00h 35m 00s
[23:01:10] Starting logic optimization..
[23:01:40] Phase 1 Retarget
[23:01:40] Phase 2 Constant propagation
[23:01:40] Phase 3 Sweep
[23:01:40] Phase 4 BUFG optimization
[23:01:40] Phase 5 Shift Register Optimization
[23:01:40] Phase 6 Post Processing Netlist
[23:03:48] Run vpl: Step impl: Failed
[23:03:48] Finished 3rd of 6 tasks (FPGA logic optimization). Elapsed time: 00h 02m 37s
[23:03:48] Starting logic placement..
[23:03:48] Run vpl: FINISHED. Run Status: impl ERROR
===>The following messages were generated while processing /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/vivado/vpl/prj/prj.runs/impl_1 :
ERROR: [VPL UTLZ-1] Resource utilization: LUT as Logic over-utilized in Top Level Design (This design requires more LUT as Logic cells than are available in the target device. This design requires 71617 of such cell types but only 70560 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device. Please set tcl parameter "drc.disableLUTOverUtilError" to 1 to change this error to warning.)
ERROR: [VPL UTLZ-1] Resource utilization: Slice LUTs over-utilized in Top Level Design (This design requires more Slice LUTs cells than are available in the target device. This design requires 79831 of such cell types but only 70560 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device. Please set tcl parameter "drc.disableLUTOverUtilError" to 1 to change this error to warning.)
ERROR: [VPL 4-23] Error(s) found during DRC. Placer not run.
WARNING: [VPL 60-732] Link warning: No monitor points found for BD automation.
ERROR: [VPL 60-704] Integration error, problem implementing dynamic region, place_design ERROR, please look at the run log file '/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw/link/vivado/vpl/prj/prj.runs/impl_1/runme.log' for more information
ERROR: [VPL 60-1328] Vpl run 'vpl' failed
ERROR: [VPL 60-806] Failed to finish platform linker
INFO: [v++ 60-1442] [23:03:49] Run run_link: Step vpl: Failed
Time (s): cpu = 00:00:21 ; elapsed = 00:37:41 . Memory (MB): peak = 679.699 ; gain = 0.000 ; free physical = 10742 ; free virtual = 34903
ERROR: [v++ 60-661] v++ link run 'run_link' failed
ERROR: [v++ 60-626] Kernel link failed to complete
ERROR: [v++ 60-703] Failed to finish linking
Makefile:315: recipe for target '/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xclbin_ultra96v2_min2_hw/krnl_cornertracker.xclbin' failed
make: *** [/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xclbin_ultra96v2_min2_hw/krnl_cornertracker.xclbin] Error 1
masaaki@masaaki-H110M4-M01:/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build$
root@ultra96v2_min2:~/sd_card# ./init.sh
INFO: Thresholds loaded.
INFO: Running OpenCL section.
[ 148.580915] [drm] Pid 2199 opened device
[ 148.584874] [drm] Pid 2199 closed device
[ 148.599875] [drm] Pid 2199 opened device
Found Platform
Platform Name: Xilinx
INFO: Device found - edge
XCLBIN File Name: krnl_colordetect
INFO: Importing xclbin_ultra96v2_min2_hw/krnl_colordetect.xclbin
Loading: 'xclbin_ultra96v2_min2_hw/krnl_colordetect.xclbin'
[ 148.885583] [drm] Finding IP_LAYOUT section header
[ 148.885595] [drm] Section IP_LAYOUT details:
[ 148.890421] [drm] offset = 0x54fcf8
[ 148.894690] [drm] size = 0x58
[ 148.898375] [drm] Finding DEBUG_IP_LAYOUT section header
[ 148.901505] [drm] AXLF section DEBUG_IP_LAYOUT header not found
[ 148.906810] [drm] Finding CONNECTIVITY section header
[ 148.912725] [drm] Section CONNECTIVITY details:
[ 148.917770] [drm] offset = 0x54fd50
[ 148.922290] [drm] size = 0x40
[ 148.925949] [drm] Finding MEM_TOPOLOGY section header
[ 148.929081] [drm] Section MEM_TOPOLOGY details:
[ 148.934122] [drm] offset = 0x54fc00
[ 148.938643] [drm] size = 0xf8
[ 148.946261] [drm] No ERT scheduler on MPSoC, using KDS
[ 148.954931] [drm] Fail to install CU 0 interrupt handler: -22. Fall back to polling mode.
[ 148.963100] [drm] scheduler config ert(0)
[ 148.963110] [drm] cus(1)
[ 148.967114] [drm] slots(16)
[ 148.969807] [drm] num_cu_masks(1)
[ 148.972765] [drm] cu_shift(16)
[ 148.976245] [drm] cu_base(0xa0000000)
INFO: Verification results:
Percentage of pixels above error thr[ 148.979466] [drm] polling(1)
eshold = 0%
[ 149.751149] [drm] zocl_free_userptr_bo: obj 0x00000000ec26f684
[ 149.755875] [drm] zocl_free_userptr_bo: obj 0x000000007590285b
[ 149.762818] [drm] zocl_free_userptr_bo: obj 0x00000000bd481cc0
[ 149.877791] [drm] Pid 2199 closed device
root@ultra96v2_min2:~/sd_card#
なので、うまく行ったようだ。INFO: Verification results:
Percentage of pixels above error threshold = 0%
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