FC2カウンター FPGAの部屋 2020年04月03日
FC2ブログ

FPGAやCPLDの話題やFPGA用のツールの話題などです。 マニアックです。 日記も書きます。

FPGAの部屋

FPGAの部屋の有用と思われるコンテンツのまとめサイトを作りました。Xilinx ISEの初心者の方には、FPGAリテラシーおよびチュートリアルのページをお勧めいたします。

Vitis_Libraries/vision/L3/examples/stereopipeline/ をやってみた1

前回、 Vitis_Libraries/vision/L3/examples/cornertracker/ をやってみたが、Ultra96-V2 の UltraScale++ MPSoC のリソースが足りずにインプリメンテーションでエラーがでてしまった。今回は、 Vitis_Libraries/vision/L3/examples/stereopipeline/ をやってみよう。

Vitis_Libraries/vision/L3/examples/colordetect/ をやったばかりで、環境は設定されている。その環境設定方法を示す。

1. Vitis のインストール・ディレクトリの settings64.sh を実行
source /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/settings64.sh

2. XRT の setenv.sh を実行
source /opt/xilinx/xrt/setup.sh

3. DEVICE 環境変数にプラットフォームの xpfm ファイルへのパスを設定する
export DEVICE=/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm

4. SYSROOT にプラットフォームの sysroot へのパスを設定する。
export SYSROOT=/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux


それでは、Vitis_Libraries/vision/L3/examples/stereopipeline/build ディレクトリに cd して、 xclbin を make する
make host xclbin TARGET=hw BOARD=Zynq ARCH=aarch64
を実行した。
するとエラーで終了した。
Vitis_Vision_77_200402.png

エラー内容は

ERROR: [v++ 82-216] Invalid integer value for clock.defaultFreqHz option: -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline

だった。
直前の v++ コマンドを示す。

v++ -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/xo_ultra96v2_min2_hw/stereopipeline_accel.xo --kernel stereopipeline_accel --compile /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_accel.cpp \
-I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/include -I. -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include -D__SDSVHLS__ -DHLS_NO_XIL_FPO_LIB --clock.defaultFreqHz -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline --target hw --platform /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm --temp_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw --save-temps --debug --kernel_frequency 300 --report_level 2 --xp


--clock.defaultFreqHz の後に動作周波数が記述されていなかった。

cornertracker の v++ コマンドを示す。

v++ -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/xo_ultra96v2_min2_hw/pyr_dense_optical_flow_accel.xo --kernel pyr_dense_optical_flow_accel --compile /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/xf_pyr_dense_optical_flow_accel.cpp \
-I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/include -I. -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include -D__SDSVHLS__ -DHLS_NO_XIL_FPO_LIB --xp vivado_prop:run.impl_1.strategy=Performance_Explore --clock.defaultFreqHz 300000000 -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker --target hw --platform /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm --temp_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_ultra96v2_min2_hw --save-temps --debug --kernel_frequency 300 --report_level 2


--clock.defaultFreqHz 300000000 と --clock.defaultFreqHz の後ろに 300000000 の値が入っている。
ここがおかしいので Makefile を以下のように修正した。
Vitis_Vision_78_200402.png

他の値もいじってみたのだが、うまく行かずに 204 行目の後に

VPP_CFLAGS += --clock.defaultFreqHz 300000000

を追加して、 204 行目をコメントアウトした。
これで、
make host xclbin TARGET=hw BOARD=Zynq ARCH=aarch64
を実行したところ、成功した。
Vitis_Vision_79_200402.png

Vitis_Vision_80_200402.png

次に、 sd_card ディレクトリを作成するのだが、いつもエラーなっているので、予め Makefile を編集しておく。
Vitis_Vision_81_200403.png

451 行目の

$(B_NAME)/sw/$(XDEVICE)/xrt/image/*

を削除した。

make run TARGET=hw BOARD=Zynq ARCH=aarch64
を実行したところ、成功した。
Vitis_Vision_82_200403.png

Vitis_Libraries/vision/L3/examples/stereopipeline/build ディレクトリを示す。sd_card ディレクトリができている。
Vitis_Vision_83_200403.png

Vitis_Libraries/vision/L3/examples/stereopipeline/build/sd_card ディレクトリを示す。
Vitis_Vision_84_200403.png

BOOT.BIN ファイルも Vitis_Libraries/vision/L3/examples/stereopipeline/build/xclbin_ultra96v2_min2_hw/sd_card ディレクトリにできていた。
Vitis_Vision_85_200403.png

最後に、 make host xclbin TARGET=hw BOARD=Zynq ARCH=aarch64 実行時のログを示す。

masaaki@masaaki-H110M4-M01:/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build$ make host xclbin TARGET=hw BOARD=Zynq ARCH=aarch64
-e ----
Compiling object xf_stereo_pipeline_tb...
mkdir -p /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/obj_ultra96v2_min2
aarch64-linux-gnu-g++ -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/obj_ultra96v2_min2/xf_stereo_pipeline_tb.o -c /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_tb.cpp -D XDEVICE=ultra96v2_min2 -DVIVADO_HLS_SIM -D__SDSVHLS__ -DHLS_NO_XIL_FPO_LIB -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/include -I. -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2 -g --sysroot=/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux -D__ZYNQ -std=c++14 -fPIC -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline -I/opt/xilinx/xrt/include -Wall -Wno-unknown-pragmas -Wno-unused-label -pthread  -idirafter /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vivado/2019.2/include 
In file included from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include/common/xf_headers.hpp:30,
                 from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_tb.cpp:17:
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include/common/xf_sw_utils.hpp: 関数 ‘void xf::cv::analyzeDiff(cv::Mat&, int, float&)’ 内:
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include/common/xf_sw_utils.hpp:150:23: 警告: 変数 ‘v_tmp1’ が設定されましたが使用されていません [-Wunused-but-set-variable]
                 float v_tmp1;
                       ^~~~~~
In file included from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_tb.cpp:21:
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_tb.cpp: 関数 ‘int main(int, char**)’ 内:
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_tb.cpp:113:96: 警告: ISO C++ says that these are ambiguous, even though the worst conversion for the first is better than the worst conversion for the second:
 cl::Buffer imageToDeviceL(context, CL_MEM_READ_ONLY, rows * cols, NULL, &err));
                                                                             ^

/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2/xcl2.hpp:41:5: 備考: in definition of macro ‘OCL_CHECK’
     call;                                                           \
     ^~~~
In file included from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2/xcl2.hpp:48,
                 from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_tb.cpp:21:
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:3675:5: 備考: 候補 1: ‘cl::Buffer::Buffer(const cl::Context&, cl_mem_flags, cl::size_type, void*, cl_int*)’
     Buffer(
     ^~~~~~
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:8512:1: 備考: 候補 2: ‘cl::Buffer::Buffer(const cl::Context&, IteratorType, IteratorType, bool, bool, cl_int*) [with IteratorType = int; cl_int = int]’
 Buffer::Buffer(
 ^~~~~~
In file included from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_tb.cpp:21:
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_tb.cpp:114:96: 警告: ISO C++ says that these are ambiguous, even though the worst conversion for the first is better than the worst conversion for the second:
 cl::Buffer imageToDeviceR(context, CL_MEM_READ_ONLY, rows * cols, NULL, &err));
                                                                             ^

/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2/xcl2.hpp:41:5: 備考: in definition of macro ‘OCL_CHECK’
     call;                                                           \
     ^~~~
In file included from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2/xcl2.hpp:48,
                 from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_tb.cpp:21:
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:3675:5: 備考: 候補 1: ‘cl::Buffer::Buffer(const cl::Context&, cl_mem_flags, cl::size_type, void*, cl_int*)’
     Buffer(
     ^~~~~~
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:8512:1: 備考: 候補 2: ‘cl::Buffer::Buffer(const cl::Context&, IteratorType, IteratorType, bool, bool, cl_int*) [with IteratorType = int; cl_int = int]’
 Buffer::Buffer(
 ^~~~~~
In file included from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_tb.cpp:21:
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_tb.cpp:115:102: 警告: ISO C++ says that these are ambiguous, even though the worst conversion for the first is better than the worst conversion for the second:
 ffer imageFromDevice(context, CL_MEM_WRITE_ONLY, rows * cols * 2, NULL, &err));
                                                                             ^

/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2/xcl2.hpp:41:5: 備考: in definition of macro ‘OCL_CHECK’
     call;                                                           \
     ^~~~
In file included from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2/xcl2.hpp:48,
                 from /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_tb.cpp:21:
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:3675:5: 備考: 候補 1: ‘cl::Buffer::Buffer(const cl::Context&, cl_mem_flags, cl::size_type, void*, cl_int*)’
     Buffer(
     ^~~~~~
/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/include/CL/cl2.hpp:8512:1: 備考: 候補 2: ‘cl::Buffer::Buffer(const cl::Context&, IteratorType, IteratorType, bool, bool, cl_int*) [with IteratorType = int; cl_int = int]’
 Buffer::Buffer(
 ^~~~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_tb.cpp:158:14: 警告: unused variable ‘start’ [-Wunused-variable]
     cl_ulong start = 0;
              ^~~~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_tb.cpp:159:14: 警告: unused variable ‘end’ [-Wunused-variable]
     cl_ulong end = 0;
              ^~~
/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_tb.cpp:160:12: 警告: unused variable ‘diff_prof’ [-Wunused-variable]
     double diff_prof = 0.0f;
            ^~~~~~~~~
-e ----
Compiling extra object /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/obj_ultra96v2_min2/xcl2.o...
mkdir -p /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/obj_ultra96v2_min2
aarch64-linux-gnu-g++ -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/obj_ultra96v2_min2/xcl2.o -c /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2/xcl2.cpp -D XDEVICE=ultra96v2_min2 -DVIVADO_HLS_SIM -D__SDSVHLS__ -DHLS_NO_XIL_FPO_LIB -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/include -I. -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2 -g --sysroot=/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux -D__ZYNQ -std=c++14 -fPIC -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline -I/opt/xilinx/xrt/include -Wall -Wno-unknown-pragmas -Wno-unused-label -pthread  -idirafter /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vivado/2019.2/include -I /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2
-e ----
Compiling host stereopipeline.exe...
mkdir -p /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/bin_ultra96v2_min2
aarch64-linux-gnu-g++ -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/bin_ultra96v2_min2/stereopipeline.exe /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/obj_ultra96v2_min2/xf_stereo_pipeline_tb.o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/obj_ultra96v2_min2/xcl2.o -D XDEVICE=ultra96v2_min2 -DVIVADO_HLS_SIM -D__SDSVHLS__ -DHLS_NO_XIL_FPO_LIB -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/include -I. -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/ext/xcl2 -g --sysroot=/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux -D__ZYNQ -std=c++14 -fPIC -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline -I/opt/xilinx/xrt/include -Wall -Wno-unknown-pragmas -Wno-unused-label -pthread  -idirafter /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vivado/2019.2/include -L/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/lib -Wl,-rpath-link=/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/usr/lib/ -L/media/masaaki/Ubuntu_Disk/tools/Xilinx/PetaLinux/PetaL_Proj/2019.2/ultra96v2_min2/images/linux/ultra96v2_min2_pkg/pfm/sysroots/aarch64-xilinx-linux/opt/xilinx/xrt/lib -lopencv_imgcodecs -lopencv_core -lopencv_imgproc -lopencv_highgui -lopencv_calib3d -lopencv_features2d -lopencv_flann -pthread -L/opt/xilinx/xrt/lib -lxilinxopencl 
-e ----
Compiling kernel stereopipeline_accel...
mkdir -p /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/xo_ultra96v2_min2_hw
v++ -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/xo_ultra96v2_min2_hw/stereopipeline_accel.xo --kernel stereopipeline_accel --compile /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_accel.cpp \
 -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/include -I. -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include -D__SDSVHLS__ -DHLS_NO_XIL_FPO_LIB --clock.defaultFreqHz 300000000 -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline --target hw --platform /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm --temp_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw --save-temps --debug --kernel_frequency 300  --report_level 2 --xp vivado_prop:run.impl_1.strategy=Performance_Explore 
WARNING: [v++ 60-1600] The option 'xp' was used directly on the command line, where its usage is deprecated. To ensure input line works for supported operating systems or shells, v++ supports specification for some options in a configuration file. As an alternative, please use options 'advanced.*', 'vivado.*' in a configuration file. Use one or more configuration files along with section headers to define key-value pairs for the advanced properties or parameters. Specify a configuration file using '--config'.
INFO: [v++ 84-14] Sample config file already exists. To regenerate, remove file 'sample_compile.ini'.
Option Map File Used: '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/data/vitis/vpp/optMap.xml'

****** v++ v2019.2 (64-bit)
  **** SW Build 2700185 on Thu Oct 24 18:45:48 MDT 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

INFO: [v++ 60-1306] Additional information associated with this v++ compile can be found at:
 Reports: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/reports/stereopipeline_accel
 Log files: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/logs/stereopipeline_accel
Running Dispatch Server on port:46767
INFO: [v++ 60-1548] Creating build summary session with primary output /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/xo_ultra96v2_min2_hw/stereopipeline_accel.xo.compile_summary, at Thu Apr  2 20:05:40 2020
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Thu Apr  2 20:05:41 2020
Running Rule Check Server on port:42075
INFO: [v++ 60-1315] Creating rulecheck session with output '/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/reports/stereopipeline_accel/v++_compile_stereopipeline_accel_guidance.html', at Thu Apr  2 20:05:42 2020
INFO: [v++ 60-895]   Target platform: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm
INFO: [v++ 60-1578]   This platform contains Xilinx Shell Archive '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/hw/ultra96v2_min2.xsa'
INFO: [v++ 60-585] Compiling for hardware target
INFO: [v++ 60-423]   Target device: ultra96v2_min2
INFO: [v++ 60-242] Creating kernel: 'stereopipeline_accel'
INFO: [v++ 60-1616] Creating a HLS clock using kernel_frequency option: 300 MHz

===>The following messages were generated while  performing high-level synthesis for kernel: stereopipeline_accel Log file: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/stereopipeline_accel/stereopipeline_accel/vivado_hls.log :
INFO: [v++ 204-61] Option 'relax_ii_for_timing' is enabled, will increase II to preserve clock frequency constraints.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
WARNING: [v++ 204-69] Unable to schedule bus request on port 'irA_r' (/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_accel.cpp:57->/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_accel.cpp:31) due to limited memory ports. Please consider using a memory core with more ports or partitioning the array.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 4, Depth = 19.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
WARNING: [v++ 204-69] Unable to schedule bus request on port 'distC_r' (/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_accel.cpp:66->/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/xf_stereo_pipeline_accel.cpp:31) due to limited memory ports. Please consider using a memory core with more ports or partitioning the array.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 2, Depth = 17.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining loop 'L1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 4.
INFO: [v++ 204-61] Pipelining function 'xFComputeUndistortCoordinates'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 49.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [v++ 204-61] Pipelining loop 'Loop 2'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [v++ 204-61] Pipelining loop 'loop_height_loop_width'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 58.
INFO: [v++ 204-61] Pipelining loop 'memset_r1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining loop 'memset_r2'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining loop 'loop_width'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 30.
INFO: [v++ 204-61] Pipelining loop 'memset_r1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining loop 'memset_r2'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining loop 'loop_width'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 30.
INFO: [v++ 204-61] Pipelining function 'xFGradientX3x3<0, 3>'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining function 'xFGradientY3x3<0, 3>'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining function 'xFSobel3x3<1, 1, 0, 3>'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining loop 'Clear_Row_Loop'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining loop 'Col_Loop'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 7.
INFO: [v++ 204-61] Pipelining function 'xFImageClipUtility<1>'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining loop 'loop_col_clip'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 5.
INFO: [v++ 204-61] Pipelining loop 'loop_col_clip'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [v++ 204-61] Pipelining loop 'loop_col_clip'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 5.
INFO: [v++ 204-61] Pipelining loop 'loop_col_clip'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [v++ 204-61] Pipelining loop 'loop_row_loop_mux_loop_col'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 76.
INFO: [v++ 204-61] Pipelining function 'write'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [v++ 204-61] Pipelining loop 'L1'.
INFO: [v++ 204-61] Discarding stage scheduling solution.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 2, Depth = 4.
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 200-790] **** Loop Constraint Status: All loop constraints were NOT satisfied.
INFO: [v++ 200-789] **** Estimated Fmax: 302.02 MHz
INFO: [v++ 60-594] Finished kernel compilation
INFO: [v++ 60-244] Generating system estimate report...
INFO: [v++ 60-1092] Generated system estimate report: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/reports/stereopipeline_accel/system_estimate_stereopipeline_accel.xtxt
Add Instance StereoBM_15_48_16_0_1_1080_1920_1_false_s StereoBM_15_48_16_0_1_1080_1920_1_false_U0 1224
Add Instance xFFindStereoCorrespondenceLBMNO_1080_1920_0_1_1_15_48_16_3_false_s grp_xFFindStereoCorrespondenceLBMNO_1080_1920_0_1_1_15_48_16_3_false_s_fu_202 202
Add Instance xFSADBlockMatching xFSADBlockMatching_U0 838
Add Instance Sobel_0_3_0_2_1080_1920_1_false_2551550 Sobel_0_3_0_2_1080_1920_1_false_2551550_U0 851
Add Instance xFSobelFilter3x3_0_2_1080_1920_1_0_3_1_1_5_1920_false_1557 grp_xFSobelFilter3x3_0_2_1080_1920_1_0_3_1_1_5_1920_false_1557_fu_94 94
Add Instance xFSobel3x3_1_1_0_3_s call_ret_xFSobel3x3_1_1_0_3_s_fu_426 426
Add Instance xFGradientX3x3_0_3_s GradientvaluesX_V_write_assign_xFGradientX3x3_0_3_s_fu_72 72
Add Instance xFGradientY3x3_0_3_s GradientvaluesY_V_write_assign_xFGradientY3x3_0_3_s_fu_88 88
Add Instance xFGradientX3x3_0_3_s GradientValuesX_0_V_xFGradientX3x3_0_3_s_fu_443 443
Add Instance xFGradientY3x3_0_3_s GradientValuesY_0_V_xFGradientY3x3_0_3_s_fu_459 459
Add Instance Sobel_0_3_0_2_1080_1920_1_false_1553 Sobel_0_3_0_2_1080_1920_1_false_1553_U0 861
Add Instance xFSobelFilter3x3_0_2_1080_1920_1_0_3_1_1_5_1920_false_1557 grp_xFSobelFilter3x3_0_2_1080_1920_1_0_3_1_1_5_1920_false_1557_fu_94 94
Add Instance xFSobel3x3_1_1_0_3_s call_ret_xFSobel3x3_1_1_0_3_s_fu_426 426
Add Instance xFGradientX3x3_0_3_s GradientvaluesX_V_write_assign_xFGradientX3x3_0_3_s_fu_72 72
Add Instance xFGradientY3x3_0_3_s GradientvaluesY_V_write_assign_xFGradientY3x3_0_3_s_fu_88 88
Add Instance xFGradientX3x3_0_3_s GradientValuesX_0_V_xFGradientX3x3_0_3_s_fu_443 443
Add Instance xFGradientY3x3_0_3_s GradientValuesY_0_V_xFGradientY3x3_0_3_s_fu_459 459
Add Instance xFImageClip_1080_1920_1_3_0_2_0_1920_256 xFImageClip_1080_1920_1_3_0_2_0_1920_256_U0 871
Add Instance xFImageClipUtility_1_s pix_1_i_i_xFImageClipUtility_1_s_fu_205 205
Add Instance xFImageClip_1080_1920_1_3_0_2_0_1920_s xFImageClip_1080_1920_1_3_0_2_0_1920_U0 882
Add Instance xFImageClipUtility_1_s pix_1_i_i_xFImageClipUtility_1_s_fu_173 173
Add Instance xFReadOutStream_1080_1920_1_3_0_2_1920_257 xFReadOutStream_1080_1920_1_3_0_2_1920_257_U0 891
Add Instance xFReadOutStream_1080_1920_1_3_0_2_1920_s xFReadOutStream_1080_1920_1_3_0_2_1920_U0 898
Add Instance xFFindStereoCorrespondenceLBMNO_Block_Mat_exit7_i10_proc xFFindStereoCorrespondenceLBMNO_Block_Mat_exit7_i10_proc_U0 905
Add Instance xFFindStereoCorrespondenceLBMNO_Loop_1_proc xFFindStereoCorrespondenceLBMNO_Loop_1_proc_U0 916
Add Instance write_r call_ln800_write_r_fu_101 101
Add Instance xFFindStereoCorrespondenceLBMNO_entry345 xFFindStereoCorrespondenceLBMNO_entry345_U0 924
Add Instance InitUndistortRectifyMapInverse_9_5_4_1080_1920_1_259 InitUndistortRectifyMapInverse_9_5_4_1080_1920_1_259_U0 1239
Add Instance xFInitUndistortRectifyMapInverseKernel grp_xFInitUndistortRectifyMapInverseKernel_fu_64 64
Add Instance xFComputeUndistortCoordinates grp_xFComputeUndistortCoordinates_fu_402 402
Add Instance InitUndistortRectifyMapInverse_9_5_4_1080_1920_1_s InitUndistortRectifyMapInverse_9_5_4_1080_1920_1_U0 1250
Add Instance xFInitUndistortRectifyMapInverseKernel grp_xFInitUndistortRectifyMapInverseKernel_fu_64 64
Add Instance xFComputeUndistortCoordinates grp_xFComputeUndistortCoordinates_fu_402 402
Add Instance remap_128_1_0_4_0_1080_1920_1_false_260 remap_128_1_0_4_0_1080_1920_1_false_260_U0 1261
Add Instance xFRemapLI_0_0_1_4_128_1080_1920_1_false_262 xFRemapLI_0_0_1_4_128_1080_1920_1_false_262_U0 102
Add Instance remap_128_1_0_4_0_1080_1920_1_false_Block_proc261 remap_128_1_0_4_0_1080_1920_1_false_Block_proc261_U0 116
Add Instance remap_128_1_0_4_0_1080_1920_1_false_s remap_128_1_0_4_0_1080_1920_1_false_U0 1271
Add Instance xFRemapLI_0_0_1_4_128_1080_1920_1_false_s xFRemapLI_0_0_1_4_128_1080_1920_1_false_U0 102
Add Instance remap_128_1_0_4_0_1080_1920_1_false_Block_proc remap_128_1_0_4_0_1080_1920_1_false_Block_proc_U0 116
Add Instance Loop_1_proc Loop_1_proc_U0 1281
Add Instance xfMat2Array_32_1_1080_1920_1_s xfMat2Array_32_1_1080_1920_1_U0 1295
Add Instance xfMat2Array_32_1_1080_1920_1_1 grp_xfMat2Array_32_1_1080_1920_1_1_fu_100 100
Add Instance xfMat2hlsStrm_32_1_1080_1920_1_2073600_33 xfMat2hlsStrm_32_1_1080_1920_1_2073600_33_U0 156
Add Instance hlsStrm2Array_32_1080_1920_1_1_16_1036800_s hlsStrm2Array_32_1080_1920_1_1_16_1036800_U0 172
Add Instance Array2xfMat_32_0_1080_1920_1_258 Array2xfMat_32_0_1080_1920_1_258_U0 1305
Add Instance Array2xfMat_32_0_1080_1920_1_s grp_Array2xfMat_32_0_1080_1920_1_s_fu_142 142
Add Instance hlsStrm2xfMat_32_0_1080_1920_1_2073600_s hlsStrm2xfMat_32_0_1080_1920_1_2073600_U0 136
Add Instance Array2hlsStrm_32_1080_1920_1_1_8_518400_s Array2hlsStrm_32_1080_1920_1_1_8_518400_U0 145
Add Instance Array2xfMat_32_0_1080_1920_1_1 Array2xfMat_32_0_1080_1920_1_1_U0 1317
Add Instance Array2xfMat_32_0_1080_1920_1_s grp_Array2xfMat_32_0_1080_1920_1_s_fu_142 142
Add Instance hlsStrm2xfMat_32_0_1080_1920_1_2073600_s hlsStrm2xfMat_32_0_1080_1920_1_2073600_U0 136
Add Instance Array2hlsStrm_32_1080_1920_1_1_8_518400_s Array2hlsStrm_32_1080_1920_1_1_8_518400_U0 145
Add Instance Loop_2_proc Loop_2_proc_U0 1329
Add Instance Block_Mat_exit172_proc Block_Mat_exit172_proc_U0 1339
Add Instance stereopipeline_accel_entry62 stereopipeline_accel_entry62_U0 1362
Add Instance stereopipeline_accel_entry784 stereopipeline_accel_entry784_U0 1402
INFO: [v++ 60-586] Created /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/xo_ultra96v2_min2_hw/stereopipeline_accel.xo
INFO: [v++ 60-791] Total elapsed time: 0h 4m 10s
-e ----
Compiling xclbin...
mkdir -p /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/xclbin_ultra96v2_min2_hw
v++ -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/xclbin_ultra96v2_min2_hw/krnl_stereopipeline.xclbin --link /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/xo_ultra96v2_min2_hw/stereopipeline_accel.xo \
 -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/include -I. -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include -D__SDSVHLS__ -DHLS_NO_XIL_FPO_LIB --clock.defaultFreqHz 300000000 -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline --target hw --platform /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm --temp_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw --save-temps --debug --kernel_frequency 300  --report_level 2 --optimize 2 --jobs 8 --xp "vivado_param:project.writeIntermediateCheckpoints=1" \
 --xp vivado_prop:run.impl_1.strategy=Performance_Explore  \
 
WARNING: [v++ 60-1600] The option 'xp' was used directly on the command line, where its usage is deprecated. To ensure input line works for supported operating systems or shells, v++ supports specification for some options in a configuration file. As an alternative, please use options 'advanced.*', 'vivado.*' in a configuration file. Use one or more configuration files along with section headers to define key-value pairs for the advanced properties or parameters. Specify a configuration file using '--config'.
INFO: [v++ 82-185] Check out the auto-generated 'sample_link.ini' configuration file. The file shows how to migrate from deprecated command line --xp switches to configuration file directives.
Option Map File Used: '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/data/vitis/vpp/optMap.xml'

****** v++ v2019.2 (64-bit)
  **** SW Build 2700185 on Thu Oct 24 18:45:48 MDT 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

INFO: [v++ 60-1306] Additional information associated with this v++ link can be found at:
 Reports: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/reports/link
 Log files: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/logs/link
Running Dispatch Server on port:40645
INFO: [v++ 60-1548] Creating build summary session with primary output /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/xclbin_ultra96v2_min2_hw/krnl_stereopipeline.xclbin.link_summary, at Thu Apr  2 20:09:53 2020
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Thu Apr  2 20:09:53 2020
Running Rule Check Server on port:43933
INFO: [v++ 60-1315] Creating rulecheck session with output '/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/reports/link/v++_link_krnl_stereopipeline_guidance.html', at Thu Apr  2 20:09:54 2020
INFO: [v++ 60-895]   Target platform: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm
INFO: [v++ 60-1578]   This platform contains Xilinx Shell Archive '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/hw/ultra96v2_min2.xsa'
INFO: [v++ 60-629] Linking for hardware target
INFO: [v++ 60-423]   Target device: ultra96v2_min2
INFO: [v++ 60-1332] Run 'run_link' status: Not started
INFO: [v++ 60-1443] [20:09:54] Run run_link: Step system_link: Started
INFO: [v++ 60-1453] Command Line: system_link --xo /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/xo_ultra96v2_min2_hw/stereopipeline_accel.xo -keep --config /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/syslinkConfig.ini --xpfm /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm --target hw --output_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int --temp_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/sys_link
INFO: [v++ 60-1454] Run Directory: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/run_link
INFO: [SYSTEM_LINK 82-76] Reading emulation BD and HPFM information
INFO: [SYSTEM_LINK 60-1316] Initiating connection to rulecheck server, at Thu Apr  2 20:09:55 2020
INFO: [SYSTEM_LINK 82-70] Extracting xo v3 file /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/xo_ultra96v2_min2_hw/stereopipeline_accel.xo
INFO: [KernelCheck 83-118] 'stereopipeline_accel' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'img_L' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'img_R' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'img_disp' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'cameraMA_l' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'cameraMA_r' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'distC_l' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'distC_r' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'irA_l' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'irA_r' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'bm_state_arr' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'rows' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [KernelCheck 83-118] 'cols' kernel.xml and component.xml caseness discrepency is being corrected, S_AXI_CONTROL is being replaced by s_axi_control
INFO: [SYSTEM_LINK 82-53] Creating IP database /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/sys_link/_sysl/.cdb/xd_ip_db.xml
INFO: [SYSTEM_LINK 82-38] [20:09:56] build_xd_ip_db started: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/bin/build_xd_ip_db -ip_search 0  -sds-pf /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/sys_link/ultra96v2_min2.hpfm -clkid 0 -ip /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/sys_link/iprepo/xilinx_com_hls_stereopipeline_accel_1_0,stereopipeline_accel -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/sys_link/_sysl/.cdb/xd_ip_db.xml
INFO: [SYSTEM_LINK 82-37] [20:09:59] build_xd_ip_db finished successfully
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 296.441 ; gain = 0.000 ; free physical = 11706 ; free virtual = 38418
INFO: [SYSTEM_LINK 82-51] Create system connectivity graph
INFO: [SYSTEM_LINK 82-102] Applying explicit connections to the system connectivity graph: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/sys_link/cfgraph/cfgen_cfgraph.xml
INFO: [SYSTEM_LINK 82-38] [20:09:59] cfgen started: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/bin/cfgen  -clock.defaultFreqHz 300000000 -dmclkid 0 -r /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/sys_link/cfgraph/cfgen_cfgraph.xml
INFO: [CFGEN 83-0] Kernel Specs: 
INFO: [CFGEN 83-0]   kernel: stereopipeline_accel, num: 1  {stereopipeline_accel_1}
INFO: [CFGEN 83-2226] Inferring mapping for argument stereopipeline_accel_1.img_L to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument stereopipeline_accel_1.img_R to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument stereopipeline_accel_1.img_disp to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument stereopipeline_accel_1.cameraMA_l to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument stereopipeline_accel_1.cameraMA_r to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument stereopipeline_accel_1.irA_l to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument stereopipeline_accel_1.irA_r to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument stereopipeline_accel_1.distC_l to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument stereopipeline_accel_1.distC_r to HP
INFO: [CFGEN 83-2226] Inferring mapping for argument stereopipeline_accel_1.bm_state_arr to HP
INFO: [SYSTEM_LINK 82-37] [20:09:59] cfgen finished successfully
Time (s): cpu = 00:00:00.29 ; elapsed = 00:00:00.32 . Memory (MB): peak = 296.441 ; gain = 0.000 ; free physical = 11708 ; free virtual = 38420
INFO: [SYSTEM_LINK 82-52] Create top-level block diagram
INFO: [SYSTEM_LINK 82-38] [20:09:59] cf2bd started: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/bin/cf2bd  --linux --trace_buffer 1024 --input_file /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/sys_link/cfgraph/cfgen_cfgraph.xml --ip_db /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/sys_link/_sysl/.cdb/xd_ip_db.xml --cf_name dr --working_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/sys_link/_sysl/.xsd --temp_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/sys_link --output_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int
INFO: [CF2BD 82-31] Launching cf2xd: cf2xd -linux -trace-buffer 1024 -i /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/sys_link/cfgraph/cfgen_cfgraph.xml -r /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o dr.xml
INFO: [CF2BD 82-28] cf2xd finished successfully
INFO: [CF2BD 82-31] Launching cf_xsd: cf_xsd -disable-address-gen -dn dr -dp /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/sys_link/_sysl/.xsd
                                                                                
rlwrap: warning: your $TERM is 'xterm-256color' but rlwrap couldn't find it in the terminfo database. Expect some problems.: Inappropriate ioctl for device
INFO: [CF2BD 82-28] cf_xsd finished successfully
INFO: [SYSTEM_LINK 82-37] [20:10:01] cf2bd finished successfully
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 296.441 ; gain = 0.000 ; free physical = 11704 ; free virtual = 38420
INFO: [v++ 60-1441] [20:10:01] Run run_link: Step system_link: Completed
Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 679.691 ; gain = 0.000 ; free physical = 11726 ; free virtual = 38442
INFO: [v++ 60-1443] [20:10:01] Run run_link: Step cf2sw: Started
INFO: [v++ 60-1453] Command Line: cf2sw -sdsl /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/sdsl.dat -rtd /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/cf2sw.rtd -xclbin /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/xclbin_orig.xml -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/xclbin_orig.1.xml
INFO: [v++ 60-1454] Run Directory: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/run_link
INFO: [v++ 60-1441] [20:10:02] Run run_link: Step cf2sw: Completed
Time (s): cpu = 00:00:00.59 ; elapsed = 00:00:00.67 . Memory (MB): peak = 679.691 ; gain = 0.000 ; free physical = 11728 ; free virtual = 38444
INFO: [v++ 60-1443] [20:10:02] Run run_link: Step rtd2_system_diagram: Started
INFO: [v++ 60-1453] Command Line: rtd2SystemDiagram --rtdJsonFileName /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/cf2sw.rtd --diagramJsonFileName /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/systemDiagramModel.json --platformFilePath /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm --generatedByName v++ --generatedByVersion 2019.2 --generatedByChangeList 2700185 --generatedByTimeStamp Thu Oct 24 18:45:48 MDT 2019 --generatedByOptions /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/bin/unwrapped/lnx64.o/v++ -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/xclbin_ultra96v2_min2_hw/krnl_stereopipeline.xclbin --link /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/xo_ultra96v2_min2_hw/stereopipeline_accel.xo -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/include -I. -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L1/include -D__SDSVHLS__ -DHLS_NO_XIL_FPO_LIB --clock.defaultFreqHz 300000000 -I/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline --target hw --platform /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm --temp_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw --save-temps --debug --kernel_frequency 300 --report_level 2 --optimize 2 --jobs 8 --xp vivado_param:project.writeIntermediateCheckpoints=1 --xp vivado_prop:run.impl_1.strategy=Performance_Explore  --generatedByXclbinName krnl_stereopipeline --kernelInfoDataFileName /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/kernel_info.dat
INFO: [v++ 60-1454] Run Directory: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/run_link
WARNING: [v++ 82-164] Unable to populate user region instance path.  The platform file does not contain a hardwarePlatform.devices..core.instPath entry.
INFO: [v++ 60-839] Read in kernel information from file '/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/kernel_info.dat'.
WARNING: [v++ 82-157] Unable to populate kernel available resources BRAM entry.
WARNING: [v++ 82-158] Unable to populate kernel available resources DSP entry.
WARNING: [v++ 82-163] Unable to populate user region available resources.  The platform file deos not contain a hardwarePlatform.devices..core.availableResources entry
INFO: [v++ 60-1441] [20:10:04] Run run_link: Step rtd2_system_diagram: Completed
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 679.691 ; gain = 0.000 ; free physical = 11728 ; free virtual = 38444
INFO: [v++ 60-1443] [20:10:04] Run run_link: Step vpl: Started
INFO: [v++ 60-1453] Command Line: vpl -t hw -f /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2019.2/platforms/ultra96v2_min2/ultra96v2_min2.xpfm -g -j 8 --kernel_frequency 300 -s --output_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int --log_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/logs/link --report_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/reports/link --config /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/vplConfig.ini -k /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/kernel_info.dat --webtalk_flag Vitis --temp_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link --no-info --tlog_dir /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/.tlog/v++_link_krnl_stereopipeline --iprepo /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/xo/ip_repo/xilinx_com_hls_stereopipeline_accel_1_0 --messageDb /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/run_link/vpl.pb /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/dr.bd.tcl
INFO: [v++ 60-1454] Run Directory: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/run_link

****** vpl v2019.2 (64-bit)
  **** SW Build 2700185 on Thu Oct 24 18:45:48 MDT 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

INFO: [VPL 60-839] Read in kernel information from file '/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/kernel_info.dat'.
INFO: [VPL 60-423]   Target device: ultra96v2_min2
INFO: [VPL 60-1032] Extracting hardware platform to /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/vivado/vpl/.local/hw_platform
[20:10:15] Run vpl: Step create_project: Started
Creating Vivado project.
[20:10:24] Run vpl: Step create_project: Completed
[20:10:24] Run vpl: Step create_bd: Started
[20:10:34] Run vpl: Step create_bd: Completed
[20:10:34] Run vpl: Step update_bd: Started
[20:10:35] Run vpl: Step update_bd: Completed
[20:10:35] Run vpl: Step generate_target: Started
[20:11:11] Run vpl: Step generate_target: Completed
[20:11:11] Run vpl: Step config_hw_runs: Started
[20:11:13] Run vpl: Step config_hw_runs: Completed
[20:11:13] Run vpl: Step synth: Started
[20:12:14] Block-level synthesis in progress, 0 of 21 jobs complete, 8 jobs running.
[20:12:44] Block-level synthesis in progress, 0 of 21 jobs complete, 8 jobs running.
[20:13:16] Block-level synthesis in progress, 0 of 21 jobs complete, 8 jobs running.
[20:13:46] Block-level synthesis in progress, 0 of 21 jobs complete, 8 jobs running.
[20:14:16] Block-level synthesis in progress, 0 of 21 jobs complete, 8 jobs running.
[20:14:46] Block-level synthesis in progress, 0 of 21 jobs complete, 8 jobs running.
[20:15:17] Block-level synthesis in progress, 0 of 21 jobs complete, 8 jobs running.
[20:15:47] Block-level synthesis in progress, 1 of 21 jobs complete, 7 jobs running.
[20:16:18] Block-level synthesis in progress, 2 of 21 jobs complete, 6 jobs running.
[20:16:48] Block-level synthesis in progress, 2 of 21 jobs complete, 7 jobs running.
[20:17:18] Block-level synthesis in progress, 3 of 21 jobs complete, 7 jobs running.
[20:17:49] Block-level synthesis in progress, 5 of 21 jobs complete, 6 jobs running.
[20:18:19] Block-level synthesis in progress, 6 of 21 jobs complete, 5 jobs running.
[20:18:49] Block-level synthesis in progress, 7 of 21 jobs complete, 4 jobs running.
[20:19:20] Block-level synthesis in progress, 10 of 21 jobs complete, 4 jobs running.
[20:19:50] Block-level synthesis in progress, 12 of 21 jobs complete, 4 jobs running.
[20:20:21] Block-level synthesis in progress, 13 of 21 jobs complete, 3 jobs running.
[20:20:51] Block-level synthesis in progress, 18 of 21 jobs complete, 3 jobs running.
[20:21:21] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:21:51] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:22:22] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:22:52] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:23:22] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:23:52] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:24:22] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:24:52] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:25:23] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:25:53] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:26:23] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:26:53] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:27:23] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:27:53] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:28:24] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:28:54] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:29:24] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:29:54] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:30:24] Block-level synthesis in progress, 20 of 21 jobs complete, 1 job running.
[20:30:54] Block-level synthesis in progress, 21 of 21 jobs complete, 0 jobs running.
[20:31:25] Top-level synthesis in progress.
[20:31:55] Top-level synthesis in progress.
[20:32:25] Top-level synthesis in progress.
[20:32:45] Run vpl: Step synth: Completed
[20:32:45] Run vpl: Step impl: Started
[20:35:47] Finished 2nd of 6 tasks (FPGA linking synthesized kernels to platform). Elapsed time: 00h 25m 42s 

[20:35:47] Starting logic optimization..
[20:35:47] Phase 1 Retarget
[20:35:47] Phase 2 Constant propagation
[20:35:47] Phase 3 Sweep
[20:36:18] Phase 4 BUFG optimization
[20:36:18] Phase 5 Shift Register Optimization
[20:36:18] Phase 6 Post Processing Netlist
[20:37:48] Finished 3rd of 6 tasks (FPGA logic optimization). Elapsed time: 00h 02m 00s 

[20:37:48] Starting logic placement..
[20:37:48] Phase 1 Placer Initialization
[20:37:48] Phase 1.1 Placer Initialization Netlist Sorting
[20:37:48] Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
[20:38:18] Phase 1.3 Build Placer Netlist Model
[20:38:18] Phase 1.4 Constrain Clocks/Macros
[20:38:18] Phase 2 Global Placement
[20:38:18] Phase 2.1 Floorplanning
[20:39:19] Phase 2.2 Global Placement Core
[20:40:49] Phase 2.2.1 Physical Synthesis In Placer
[20:41:20] Phase 3 Detail Placement
[20:41:20] Phase 3.1 Commit Multi Column Macros
[20:41:20] Phase 3.2 Commit Most Macros & LUTRAMs
[20:41:20] Phase 3.3 Area Swap Optimization
[20:41:20] Phase 3.4 Pipeline Register Optimization
[20:41:20] Phase 3.5 IO Cut Optimizer
[20:41:20] Phase 3.6 Fast Optimization
[20:41:50] Phase 3.7 Small Shape DP
[20:41:50] Phase 3.7.1 Small Shape Clustering
[20:41:50] Phase 3.7.2 Flow Legalize Slice Clusters
[20:41:50] Phase 3.7.3 Slice Area Swap
[20:42:20] Phase 3.7.4 Commit Slice Clusters
[20:42:20] Phase 3.8 Re-assign LUT pins
[20:42:20] Phase 3.9 Pipeline Register Optimization
[20:42:20] Phase 3.10 Fast Optimization
[20:42:50] Phase 4 Post Placement Optimization and Clean-Up
[20:42:50] Phase 4.1 Post Commit Optimization
[20:43:21] Phase 4.1.1 Post Placement Optimization
[20:43:21] Phase 4.1.1.1 BUFG Insertion
[20:44:21] Phase 4.2 Post Placement Cleanup
[20:44:21] Phase 4.3 Placer Reporting
[20:44:21] Phase 4.4 Final Placement Cleanup
[20:45:52] Finished 4th of 6 tasks (FPGA logic placement). Elapsed time: 00h 08m 03s 

[20:45:52] Starting logic routing..
[20:45:52] Phase 1 Build RT Design
[20:46:22] Phase 2 Router Initialization
[20:46:22] Phase 2.1 Create Timer
[20:46:22] Phase 2.2 Fix Topology Constraints
[20:46:22] Phase 2.3 Pre Route Cleanup
[20:46:22] Phase 2.4 Global Clock Net Routing
[20:46:22] Phase 2.5 Update Timing
[20:46:52] Phase 2.6 Update Timing for Bus Skew
[20:46:52] Phase 2.6.1 Update Timing
[20:47:23] Phase 3 Initial Routing
[20:47:53] Phase 4 Rip-up And Reroute
[20:47:53] Phase 4.1 Global Iteration 0
[21:10:05] Phase 4.2 Global Iteration 1
[21:13:06] Phase 4.3 Global Iteration 2
[21:14:37] Phase 4.4 Global Iteration 3
[21:15:07] Phase 5 Delay and Skew Optimization
[21:15:07] Phase 5.1 Delay CleanUp
[21:15:07] Phase 5.1.1 Update Timing
[21:15:37] Phase 5.2 Clock Skew Optimization
[21:15:37] Phase 6 Post Hold Fix
[21:15:37] Phase 6.1 Hold Fix Iter
[21:15:37] Phase 6.1.1 Update Timing
[21:15:37] Phase 7 Route finalize
[21:15:37] Phase 8 Verifying routed nets
[21:15:37] Phase 9 Depositing Routes
[21:15:37] Phase 10 Route finalize
[21:15:37] Phase 11 Post Router Timing
[21:16:08] Finished 5th of 6 tasks (FPGA routing). Elapsed time: 00h 30m 15s 

[21:16:08] Starting bitstream generation..
[21:18:39] Creating bitmap...
[21:18:53] Run vpl: Step impl: Completed
[21:18:53] Writing bitstream ./ultra96v2_min2_wrapper.bit...
[21:18:53] Finished 6th of 6 tasks (FPGA bitstream generation). Elapsed time: 00h 02m 45s 
[21:18:53] Run vpl: FINISHED. Run Status: impl Complete!
INFO: [v++ 60-1441] [21:18:53] Run run_link: Step vpl: Completed
Time (s): cpu = 00:00:27 ; elapsed = 01:08:50 . Memory (MB): peak = 679.691 ; gain = 0.000 ; free physical = 14757 ; free virtual = 39166
INFO: [v++ 60-1443] [21:18:53] Run run_link: Step rtdgen: Started
INFO: [v++ 60-1453] Command Line: rtdgen
INFO: [v++ 60-1454] Run Directory: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/run_link
INFO: [v++ 60-1453] Command Line: cf2sw -a /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/address_map.xml -sdsl /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/sdsl.dat -xclbin /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/xclbin_orig.xml -rtd /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/krnl_stereopipeline.rtd -o /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/krnl_stereopipeline.xml
INFO: [v++ 60-1618] Launching 
INFO: [v++ 60-1441] [21:18:56] Run run_link: Step rtdgen: Completed
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 679.691 ; gain = 0.000 ; free physical = 14771 ; free virtual = 39180
INFO: [v++ 60-1443] [21:18:56] Run run_link: Step xclbinutil: Started
INFO: [v++ 60-1453] Command Line: xclbinutil --add-section BITSTREAM:RAW:/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/system.bit --force --key-value SYS:mode:flat --add-section :JSON:/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/krnl_stereopipeline.rtd --add-section CLOCK_FREQ_TOPOLOGY:JSON:/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/krnl_stereopipeline_xml.rtd --add-section BUILD_METADATA:JSON:/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/krnl_stereopipeline_build.rtd --add-section EMBEDDED_METADATA:RAW:/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/krnl_stereopipeline.xml --add-section SYSTEM_METADATA:RAW:/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/systemDiagramModelSlrBaseAddress.json --key-value SYS:PlatformVBNV:vendor_Ultra96V2_ultra96v2_min2_1_0 --output /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/krnl_stereopipeline.xclbin
INFO: [v++ 60-1454] Run Directory: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/run_link
XRT Build Version: 2.3.1301
       Build Date: 2019-10-24 20:05:16
          Hash ID: 192e706aea53163a04c574f9b3fe9ed76b6ca471
Creating a default 'in-memory' xclbin image.

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Format : JSON
File   : 'mem_topology'

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Format : JSON
File   : 'ip_layout'

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Format : JSON
File   : 'connectivity'
WARNING: Skipping CLOCK_FREQ_TOPOLOGY section for count size is zero.
WARNING: Section 'CLOCK_FREQ_TOPOLOGY' content is empty.  No data in the given JSON file.

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File   : '/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/systemDiagramModelSlrBaseAddress.json'
Successfully wrote (5634244 bytes) to the output file: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/krnl_stereopipeline.xclbin
Leaving xclbinutil.
INFO: [v++ 60-1441] [21:18:56] Run run_link: Step xclbinutil: Completed
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.11 . Memory (MB): peak = 679.691 ; gain = 0.000 ; free physical = 14770 ; free virtual = 39188
INFO: [v++ 60-1443] [21:18:56] Run run_link: Step xclbinutilinfo: Started
INFO: [v++ 60-1453] Command Line: xclbinutil --quiet --info /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/krnl_stereopipeline.xclbin.info --input /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/int/krnl_stereopipeline.xclbin
INFO: [v++ 60-1454] Run Directory: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/link/run_link
INFO: [v++ 60-1441] [21:18:56] Run run_link: Step xclbinutilinfo: Completed
Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.06 . Memory (MB): peak = 679.691 ; gain = 0.000 ; free physical = 14790 ; free virtual = 39208
INFO: [v++ 60-244] Generating system estimate report...
INFO: [v++ 60-1092] Generated system estimate report: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/reports/link/system_estimate_krnl_stereopipeline.xtxt
INFO: [v++ 60-907] Packaging to directory: '/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/xclbin_ultra96v2_min2_hw/sd_card'
INFO: [v++ 60-586] Created /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/xclbin_ultra96v2_min2_hw/krnl_stereopipeline.xclbin
INFO: [v++ 60-1307] Run completed. Additional information can be found in:
 Guidance: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/reports/link/v++_link_krnl_stereopipeline_guidance.html
 Timing Report: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/reports/link/imp/ultra96v2_min2_wrapper_timing_summary_routed.rpt
 Vivado Log: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/logs/link/vivado.log
 Steps Log File: /media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build/_x_ultra96v2_min2_hw/logs/link/link.steps.log

INFO: [v++ 60-791] Total elapsed time: 1h 9m 5s
masaaki@masaaki-H110M4-M01:/media/masaaki/Ubuntu_Disk/Vitis_Libraries/vision/L3/examples/stereopipeline/build$ 

  1. 2020年04月03日 04:32 |
  2. Vitis_Vision
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