// display_cont.cpp
// 2015/06/03 by marsee
//
// 画面を4分割した第1象限は赤、第2象限は緑、第3象限は青、第4象限は白を表示する
//
#include <stdio.h>
#include <string.h>
#include <ap_int.h>
// SVGA 解像度
#define H_ACTIVE_VIDEO 800
#define H_FRONT_PORCH 40
#define H_SYNC_PULSE 128
#define H_BACK_PORCH 88
#define H_SUM (H_ACTIVE_VIDEO + H_FRONT_PORCH + H_SYNC_PULSE + H_BACK_PORCH)
#define V_ACTIVE_VIDEO 600
#define V_FRONT_PORCH 1
#define V_SYNC_PULSE 4
#define V_BACK_PORCH 23
#define V_SUM (V_ACTIVE_VIDEO + V_FRONT_PORCH + V_SYNC_PULSE + V_BACK_PORCH)
void display_cont_sub(ap_uint<8> *red, ap_uint<8> *green, ap_uint<8> *blue, ap_uint<1> *display_enable, ap_uint<1> *hsyncx, ap_uint<1> *vsyncx){
#pragma HLS INTERFACE ap_none register port=red
#pragma HLS INTERFACE ap_none register port=green
#pragma HLS INTERFACE ap_none register port=blue
#pragma HLS INTERFACE ap_none register port=display_enable
#pragma HLS INTERFACE ap_none register port=hsyncx
#pragma HLS INTERFACE ap_none register port=vsyncx
#pragma HLS INTERFACE ap_ctrl_hs port=return
ap_uint<16> h_count, v_count;
for (v_count=0; v_count<V_SUM; v_count++){
for (h_count=0; h_count<H_SUM; h_count++){
#pragma HLS PIPELINE II=1 rewind
if (h_count >= (H_ACTIVE_VIDEO +H_FRONT_PORCH) && h_count < (H_ACTIVE_VIDEO + H_FRONT_PORCH + H_SYNC_PULSE))
*hsyncx = 0;
else
*hsyncx = 1;
if (v_count >= (V_ACTIVE_VIDEO + V_FRONT_PORCH) && v_count < (V_ACTIVE_VIDEO + V_FRONT_PORCH + V_SYNC_PULSE))
*vsyncx = 0;
else
*vsyncx = 1;
if (h_count < H_ACTIVE_VIDEO && v_count < V_ACTIVE_VIDEO)
*display_enable = 1;
else
*display_enable = 0;
if (v_count < V_ACTIVE_VIDEO/2){
if (h_count < H_ACTIVE_VIDEO/2){
*red=0xff; *green=0; *blue=0;
} else if (h_count < H_ACTIVE_VIDEO){
*red=0; *green=0xff; *blue=0;
} else {
*red=0; *green=0; *blue=0;
}
} else if (v_count < V_ACTIVE_VIDEO){
if (h_count < H_ACTIVE_VIDEO/2){
*red=0; *green=0; *blue=0xff;
} else if (h_count < H_ACTIVE_VIDEO){
*red=0xff; *green=0xff; *blue=0xff;
} else {
*red=0; *green=0; *blue=0;
}
} else {
*red=0; *green=0; *blue=0;
}
}
}
}
//
// display_cont_tb.cpp
// 2015/06/03 by marsee
//
#include <stdio.h>
#include <string.h>
#include <ap_int.h>
void display_cont_sub(ap_uint<8> *red, ap_uint<8> *green, ap_uint<8> *blue, ap_uint<1> *display_enable, ap_uint<1> *hsyncx, ap_uint<1> *vsyncx);
int main(){
ap_uint<8> redb, *red;
ap_uint<8> greenb, *green;
ap_uint<8> blueb, *blue;
ap_uint<1> deb, *display_enable;
ap_uint<1> hb, *hsyncx;
ap_uint<1> vb, *vsyncx;
red = &redb;
green = &greenb;
blue = &blueb;
display_enable = &deb;
hsyncx = &hb;
vsyncx = &vb;
display_cont_sub(red, green, blue, display_enable, hsyncx, vsyncx);
display_cont_sub(red, green, blue, display_enable, hsyncx, vsyncx);
return 0;
}
entity display_cont_sub is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
red : OUT STD_LOGIC_VECTOR (7 downto 0);
green : OUT STD_LOGIC_VECTOR (7 downto 0);
blue : OUT STD_LOGIC_VECTOR (7 downto 0);
display_enable : OUT STD_LOGIC_VECTOR (0 downto 0);
hsyncx : OUT STD_LOGIC_VECTOR (0 downto 0);
vsyncx : OUT STD_LOGIC_VECTOR (0 downto 0) );
end;
entity display_cont_sub is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
red : OUT STD_LOGIC_VECTOR (7 downto 0);
green : OUT STD_LOGIC_VECTOR (7 downto 0);
blue : OUT STD_LOGIC_VECTOR (7 downto 0);
display_enable : OUT STD_LOGIC_VECTOR (0 downto 0);
hsyncx : OUT STD_LOGIC_VECTOR (0 downto 0);
vsyncx : OUT STD_LOGIC_VECTOR (0 downto 0) );
end;
問題 1:
同じバージョンの Vivado に DCP を読み込むと、名前が変更されたクロックおよび自動生成されたクロック名が正しく維持されず、タイミング解析の結果が間違いになります。
この問題は、DCP が別のバージョンの Vivado で生成され、開かれている場合には発生しません。
問題 2:
階層ピンで定義されている生成クロックがあるとき、インメモリ デザインと読み込まれた DCP との間のタイミング結果値に差が出る可能性があり、そのネットのすべてのロード ピンへクロックが伝播するのをブロックします。
ロード ピンが生成クロックの定義によってブロックされていなければ、この問題は発生しません。
問題 3:
制約にコレクション (opt/place_design を実行する前と opt/place_design を実行した後のリスト) がある場合、置き換えられたオブジェクトの一部がコレクションに追加されます。
リストのリストは Vivado 2020.1 では現在サポートされていません。
デザインが Vivado 2020.1 でインプリメントされていて、同じ Vivado 2020.1 で DCP が再度読み込まれている場合は、問題は発生しません。
インプリメンテーションと DCP の再読み込みで異なるバージョンの Vivado が使われている使用されている場合は、この問題が発生します。
このケースでは、タイミングの不一致が一部あるので、一部のパターンが一致しないことが原因でチェックポイントが再度読み込まれると、警告メッセージが生成されます。
問題 4:
「Phase 1.3 Build Placer Netlist Model」という配置フェーズで Vivado がクラッシュします。
方法 1: (Vivado 2014.4 およびそれ以降のみ)
1. $XILINX_VIVADO/patches ディレクトリ (Linux) または C:\Xilinx\Vivado\\patches ディレクトリ (Windows) に移動します (このディレクトリがない場合は作成します)。
2. 「AR75369」という名前で始まるディレクトリに ZIP アーカイブを解凍します。
注記: ほとんどの解凍ツールでは、ZIP ファイルと同じ名前のディレクトリが解凍時に自動的に作成されます。
3. 元のインストール場所から Vivado を実行します。
があった。以前の Vivado の起動メッセージと比べてみた。Vivado v2020.1_AR75369 (64-bit)
CONFIG_xrt
CONFIG_xrt-dev
CONFIG_zocl
CONFIG_opencl-clhpp-dev
CONFIG_opencl-headers-dev
CONFIG_packagegroup-petalinux-opencv
#Note: Mention Each package in individual line
#These packages will get added into rootfs menu entry
CONFIG_gpio-demo
CONFIG_peekpoke
CONFIG_xrt
CONFIG_xrt-dev
CONFIG_zocl
CONFIG_opencl-clhpp-dev
CONFIG_opencl-headers-dev
CONFIG_packagegroup-petalinux-opencv
/include/ "system-conf.dtsi"
/ {
xlnk {
compatible = "xlnx,xlnk-1.0";
};
};
&amba {
zyxclmm_drm {
compatible = "xlnx,zocl";
status = "okay";
};
};
&sdhci0 {
disable-wp;
};
/* linux */
the_ROM_image:
{
[pmufw_image] <pmufw.elf>
[bootloader, destination_cpu=a53-0] <fsbl.elf>
[destination_device=pl] <bitstream>
[destination_cpu=a53-0, exception_level=el-3, trustzone] <bl31.elf>
[destination_cpu=a53-0, exception_level=el-2] <u-boot.elf>
}
set_property platform.design_intent.embedded true [current_project]
set_property platform.design_intent.server_managed false [current_project]
set_property platform.design_intent.external_host false [current_project]
set_property platform.design_intent.datacenter false [current_project]
set_property platform.default_output_type "sd_card" [current_project]
################################################################
# This is a generated script based on design: ultra96v2_base
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
################################################################
namespace eval _tcl {
proc get_script_folder {} {
set script_path [file normalize [info script]]
set script_folder [file dirname $script_path]
return $script_folder
}
}
variable script_folder
set script_folder [_tcl::get_script_folder]
################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2020.1
set current_vivado_version [version -short]
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
puts ""
catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
return 1
}
################################################################
# START
################################################################
# To test this script, run the following commands from Vivado Tcl console:
# source ultra96v2_base_script.tcl
# If there is no project opened, this script will create a
# project, but make sure you do not have an existing project
# <./myproj/project_1.xpr> in the current working folder.
set list_projs [get_projects -quiet]
if { $list_projs eq "" } {
create_project project_1 myproj -part xczu3eg-sbva484-1-e
set_property BOARD_PART em.avnet.com:ultra96v2:part0:1.0 [current_project]
}
# CHANGE DESIGN NAME HERE
variable design_name
set design_name ultra96v2_base
# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
# create_bd_design $design_name
# Creating design if needed
set errMsg ""
set nRet 0
set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]
if { ${design_name} eq "" } {
# USE CASES:
# 1) Design_name not set
set errMsg "Please set the variable <design_name> to a non-empty value."
set nRet 1
} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
# USE CASES:
# 2): Current design opened AND is empty AND names same.
# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
if { $cur_design ne $design_name } {
common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
set design_name [get_property NAME $cur_design]
}
common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
# USE CASES:
# 5) Current design opened AND has components AND same names.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 1
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
# USE CASES:
# 6) Current opened design, has components, but diff names, design_name exists in project.
# 7) No opened design, design_name exists in project.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 2
} else {
# USE CASES:
# 8) No opened design, design_name not in project.
# 9) Current opened design, has components, but diff names, design_name not in project.
common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
create_bd_design $design_name
common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
current_bd_design $design_name
}
common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
if { $nRet != 0 } {
catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
return $nRet
}
set bCheckIPsPassed 1
##################################################################
# CHECK IPs
##################################################################
set bCheckIPs 1
if { $bCheckIPs == 1 } {
set list_check_ips "\
xilinx.com:ip:axi_intc:4.1\
xilinx.com:ip:axi_register_slice:2.1\
xilinx.com:ip:axi_vip:1.1\
xilinx.com:ip:clk_wiz:6.0\
xilinx.com:ip:proc_sys_reset:5.0\
xilinx.com:ip:zynq_ultra_ps_e:3.3\
"
set list_ips_missing ""
common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
foreach ip_vlnv $list_check_ips {
set ip_obj [get_ipdefs -all $ip_vlnv]
if { $ip_obj eq "" } {
lappend list_ips_missing $ip_vlnv
}
}
if { $list_ips_missing ne "" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
set bCheckIPsPassed 0
}
}
if { $bCheckIPsPassed != 1 } {
common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
return 3
}
##################################################################
# DESIGN PROCs
##################################################################
# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {
variable script_folder
variable design_name
if { $parentCell eq "" } {
set parentCell [get_bd_cells /]
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create interface ports
# Create ports
# Create instance: axi_intc_0, and set properties
set axi_intc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_intc_0 ]
set_property -dict [ list \
CONFIG.C_ASYNC_INTR {0xFFFFFFFF} \
CONFIG.C_IRQ_IS_LEVEL {1} \
] $axi_intc_0
# Create instance: axi_interconnect_hpc0, and set properties
set axi_interconnect_hpc0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_hpc0 ]
set_property -dict [ list \
CONFIG.NUM_MI {1} \
] $axi_interconnect_hpc0
# Create instance: axi_register_slice_0, and set properties
set axi_register_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_0 ]
set_property -dict [ list \
CONFIG.DATA_WIDTH {128} \
] $axi_register_slice_0
# Create instance: axi_vip_0, and set properties
set axi_vip_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vip:1.1 axi_vip_0 ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {32} \
CONFIG.ARUSER_WIDTH {0} \
CONFIG.AWUSER_WIDTH {0} \
CONFIG.BUSER_WIDTH {0} \
CONFIG.DATA_WIDTH {32} \
CONFIG.HAS_BRESP {1} \
CONFIG.HAS_BURST {1} \
CONFIG.HAS_CACHE {1} \
CONFIG.HAS_LOCK {1} \
CONFIG.HAS_PROT {1} \
CONFIG.HAS_QOS {1} \
CONFIG.HAS_REGION {1} \
CONFIG.HAS_RRESP {1} \
CONFIG.HAS_WSTRB {1} \
CONFIG.ID_WIDTH {0} \
CONFIG.INTERFACE_MODE {MASTER} \
CONFIG.PROTOCOL {AXI4} \
CONFIG.READ_WRITE_MODE {READ_WRITE} \
CONFIG.RUSER_BITS_PER_BYTE {0} \
CONFIG.RUSER_WIDTH {0} \
CONFIG.SUPPORTS_NARROW {1} \
CONFIG.WUSER_BITS_PER_BYTE {0} \
CONFIG.WUSER_WIDTH {0} \
] $axi_vip_0
# Create instance: axi_vip_1, and set properties
set axi_vip_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vip:1.1 axi_vip_1 ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {32} \
CONFIG.ARUSER_WIDTH {0} \
CONFIG.AWUSER_WIDTH {0} \
CONFIG.BUSER_WIDTH {0} \
CONFIG.DATA_WIDTH {32} \
CONFIG.HAS_BRESP {1} \
CONFIG.HAS_BURST {1} \
CONFIG.HAS_CACHE {1} \
CONFIG.HAS_LOCK {1} \
CONFIG.HAS_PROT {1} \
CONFIG.HAS_QOS {1} \
CONFIG.HAS_REGION {1} \
CONFIG.HAS_RRESP {1} \
CONFIG.HAS_WSTRB {1} \
CONFIG.ID_WIDTH {0} \
CONFIG.INTERFACE_MODE {MASTER} \
CONFIG.PROTOCOL {AXI4} \
CONFIG.READ_WRITE_MODE {READ_WRITE} \
CONFIG.RUSER_BITS_PER_BYTE {0} \
CONFIG.RUSER_WIDTH {0} \
CONFIG.SUPPORTS_NARROW {1} \
CONFIG.WUSER_BITS_PER_BYTE {0} \
CONFIG.WUSER_WIDTH {0} \
] $axi_vip_1
# Create instance: clk_wiz_0, and set properties
set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0 ]
set_property -dict [ list \
CONFIG.CLKIN1_JITTER_PS {100.01} \
CONFIG.CLKOUT1_JITTER {107.579} \
CONFIG.CLKOUT1_PHASE_ERROR {87.187} \
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {150} \
CONFIG.CLKOUT2_JITTER {94.872} \
CONFIG.CLKOUT2_PHASE_ERROR {87.187} \
CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {300} \
CONFIG.CLKOUT2_USED {true} \
CONFIG.CLKOUT3_JITTER {122.171} \
CONFIG.CLKOUT3_PHASE_ERROR {87.187} \
CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {75} \
CONFIG.CLKOUT3_USED {true} \
CONFIG.CLKOUT4_JITTER {115.843} \
CONFIG.CLKOUT4_PHASE_ERROR {87.187} \
CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {100.000} \
CONFIG.CLKOUT4_USED {true} \
CONFIG.CLKOUT5_JITTER {102.096} \
CONFIG.CLKOUT5_PHASE_ERROR {87.187} \
CONFIG.CLKOUT5_REQUESTED_OUT_FREQ {200.000} \
CONFIG.CLKOUT5_USED {true} \
CONFIG.CLKOUT6_JITTER {90.083} \
CONFIG.CLKOUT6_PHASE_ERROR {87.187} \
CONFIG.CLKOUT6_REQUESTED_OUT_FREQ {400.000} \
CONFIG.CLKOUT6_USED {true} \
CONFIG.CLKOUT7_JITTER {83.777} \
CONFIG.CLKOUT7_PHASE_ERROR {87.187} \
CONFIG.CLKOUT7_REQUESTED_OUT_FREQ {600.000} \
CONFIG.CLKOUT7_USED {true} \
CONFIG.MMCM_CLKFBOUT_MULT_F {12.000} \
CONFIG.MMCM_CLKIN1_PERIOD {10.000} \
CONFIG.MMCM_CLKOUT0_DIVIDE_F {8.000} \
CONFIG.MMCM_CLKOUT1_DIVIDE {4} \
CONFIG.MMCM_CLKOUT2_DIVIDE {16} \
CONFIG.MMCM_CLKOUT3_DIVIDE {12} \
CONFIG.MMCM_CLKOUT4_DIVIDE {6} \
CONFIG.MMCM_CLKOUT5_DIVIDE {3} \
CONFIG.MMCM_CLKOUT6_DIVIDE {2} \
CONFIG.MMCM_DIVCLK_DIVIDE {1} \
CONFIG.NUM_OUT_CLKS {7} \
CONFIG.RESET_PORT {resetn} \
CONFIG.RESET_TYPE {ACTIVE_LOW} \
] $clk_wiz_0
# Create instance: interconnect_axifull, and set properties
set interconnect_axifull [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 interconnect_axifull ]
set_property -dict [ list \
CONFIG.NUM_MI {1} \
] $interconnect_axifull
set_property HDL_ATTRIBUTE.DPA_TRACE_SLAVE {true} [get_bd_cells interconnect_axifull]
# Create instance: interconnect_axihpm0fpd, and set properties
set interconnect_axihpm0fpd [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 interconnect_axihpm0fpd ]
set_property -dict [ list \
CONFIG.NUM_MI {1} \
] $interconnect_axihpm0fpd
set_property HDL_ATTRIBUTE.DPA_TRACE_MASTER {true} [get_bd_cells interconnect_axihpm0fpd]
# Create instance: interconnect_axilite, and set properties
set interconnect_axilite [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 interconnect_axilite ]
set_property -dict [ list \
CONFIG.NUM_MI {1} \
] $interconnect_axilite
set_property HDL_ATTRIBUTE.DPA_AXILITE_MASTER {fallback} [get_bd_cells interconnect_axilite]
# Create instance: proc_sys_reset_0, and set properties
set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ]
# Create instance: proc_sys_reset_1, and set properties
set proc_sys_reset_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_1 ]
# Create instance: proc_sys_reset_2, and set properties
set proc_sys_reset_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_2 ]
# Create instance: proc_sys_reset_3, and set properties
set proc_sys_reset_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_3 ]
# Create instance: proc_sys_reset_4, and set properties
set proc_sys_reset_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_4 ]
# Create instance: proc_sys_reset_5, and set properties
set proc_sys_reset_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_5 ]
# Create instance: proc_sys_reset_6, and set properties
set proc_sys_reset_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_6 ]
# Create instance: zynq_ultra_ps_e_0, and set properties
set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ]
set_property -dict [ list \
CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS18} \
CONFIG.PSU_DDR_RAM_HIGHADDR {0x7FFFFFFF} \
CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x00000002} \
CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {0} \
CONFIG.PSU_MIO_0_DIRECTION {out} \
CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_0_POLARITY {Default} \
CONFIG.PSU_MIO_10_DIRECTION {inout} \
CONFIG.PSU_MIO_10_POLARITY {Default} \
CONFIG.PSU_MIO_11_DIRECTION {inout} \
CONFIG.PSU_MIO_11_POLARITY {Default} \
CONFIG.PSU_MIO_12_DIRECTION {inout} \
CONFIG.PSU_MIO_12_POLARITY {Default} \
CONFIG.PSU_MIO_13_DIRECTION {inout} \
CONFIG.PSU_MIO_13_DRIVE_STRENGTH {4} \
CONFIG.PSU_MIO_13_POLARITY {Default} \
CONFIG.PSU_MIO_14_DIRECTION {inout} \
CONFIG.PSU_MIO_14_DRIVE_STRENGTH {4} \
CONFIG.PSU_MIO_14_POLARITY {Default} \
CONFIG.PSU_MIO_15_DIRECTION {inout} \
CONFIG.PSU_MIO_15_DRIVE_STRENGTH {4} \
CONFIG.PSU_MIO_15_POLARITY {Default} \
CONFIG.PSU_MIO_16_DIRECTION {inout} \
CONFIG.PSU_MIO_16_DRIVE_STRENGTH {4} \
CONFIG.PSU_MIO_16_POLARITY {Default} \
CONFIG.PSU_MIO_17_DIRECTION {inout} \
CONFIG.PSU_MIO_17_POLARITY {Default} \
CONFIG.PSU_MIO_18_DIRECTION {inout} \
CONFIG.PSU_MIO_18_POLARITY {Default} \
CONFIG.PSU_MIO_19_DIRECTION {inout} \
CONFIG.PSU_MIO_19_POLARITY {Default} \
CONFIG.PSU_MIO_1_DIRECTION {in} \
CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_1_POLARITY {Default} \
CONFIG.PSU_MIO_1_SLEW {fast} \
CONFIG.PSU_MIO_20_DIRECTION {inout} \
CONFIG.PSU_MIO_20_POLARITY {Default} \
CONFIG.PSU_MIO_21_DIRECTION {inout} \
CONFIG.PSU_MIO_21_DRIVE_STRENGTH {4} \
CONFIG.PSU_MIO_21_POLARITY {Default} \
CONFIG.PSU_MIO_22_DIRECTION {out} \
CONFIG.PSU_MIO_22_DRIVE_STRENGTH {4} \
CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_22_POLARITY {Default} \
CONFIG.PSU_MIO_23_DIRECTION {inout} \
CONFIG.PSU_MIO_23_POLARITY {Default} \
CONFIG.PSU_MIO_24_DIRECTION {in} \
CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_24_POLARITY {Default} \
CONFIG.PSU_MIO_24_SLEW {fast} \
CONFIG.PSU_MIO_25_DIRECTION {inout} \
CONFIG.PSU_MIO_25_POLARITY {Default} \
CONFIG.PSU_MIO_26_DIRECTION {in} \
CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_26_POLARITY {Default} \
CONFIG.PSU_MIO_26_SLEW {fast} \
CONFIG.PSU_MIO_27_DIRECTION {out} \
CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_27_POLARITY {Default} \
CONFIG.PSU_MIO_28_DIRECTION {in} \
CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_28_POLARITY {Default} \
CONFIG.PSU_MIO_28_SLEW {fast} \
CONFIG.PSU_MIO_29_DIRECTION {out} \
CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_29_POLARITY {Default} \
CONFIG.PSU_MIO_2_DIRECTION {in} \
CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_2_POLARITY {Default} \
CONFIG.PSU_MIO_2_SLEW {fast} \
CONFIG.PSU_MIO_30_DIRECTION {in} \
CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_30_POLARITY {Default} \
CONFIG.PSU_MIO_30_SLEW {fast} \
CONFIG.PSU_MIO_31_DIRECTION {inout} \
CONFIG.PSU_MIO_31_POLARITY {Default} \
CONFIG.PSU_MIO_32_DIRECTION {out} \
CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_32_POLARITY {Default} \
CONFIG.PSU_MIO_33_DIRECTION {out} \
CONFIG.PSU_MIO_33_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_33_POLARITY {Default} \
CONFIG.PSU_MIO_34_DIRECTION {out} \
CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_34_POLARITY {Default} \
CONFIG.PSU_MIO_35_DIRECTION {inout} \
CONFIG.PSU_MIO_35_POLARITY {Default} \
CONFIG.PSU_MIO_36_DIRECTION {inout} \
CONFIG.PSU_MIO_36_POLARITY {Default} \
CONFIG.PSU_MIO_37_DIRECTION {inout} \
CONFIG.PSU_MIO_37_POLARITY {Default} \
CONFIG.PSU_MIO_38_DIRECTION {inout} \
CONFIG.PSU_MIO_38_POLARITY {Default} \
CONFIG.PSU_MIO_39_DIRECTION {inout} \
CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_39_POLARITY {Default} \
CONFIG.PSU_MIO_39_SLEW {fast} \
CONFIG.PSU_MIO_3_DIRECTION {out} \
CONFIG.PSU_MIO_3_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_3_POLARITY {Default} \
CONFIG.PSU_MIO_40_DIRECTION {inout} \
CONFIG.PSU_MIO_40_POLARITY {Default} \
CONFIG.PSU_MIO_41_DIRECTION {inout} \
CONFIG.PSU_MIO_41_POLARITY {Default} \
CONFIG.PSU_MIO_42_DIRECTION {inout} \
CONFIG.PSU_MIO_42_POLARITY {Default} \
CONFIG.PSU_MIO_43_DIRECTION {inout} \
CONFIG.PSU_MIO_43_POLARITY {Default} \
CONFIG.PSU_MIO_44_DIRECTION {inout} \
CONFIG.PSU_MIO_44_POLARITY {Default} \
CONFIG.PSU_MIO_45_DIRECTION {inout} \
CONFIG.PSU_MIO_45_POLARITY {Default} \
CONFIG.PSU_MIO_46_DIRECTION {inout} \
CONFIG.PSU_MIO_46_POLARITY {Default} \
CONFIG.PSU_MIO_47_DIRECTION {inout} \
CONFIG.PSU_MIO_47_POLARITY {Default} \
CONFIG.PSU_MIO_48_DIRECTION {inout} \
CONFIG.PSU_MIO_48_POLARITY {Default} \
CONFIG.PSU_MIO_49_DIRECTION {inout} \
CONFIG.PSU_MIO_49_POLARITY {Default} \
CONFIG.PSU_MIO_4_DIRECTION {inout} \
CONFIG.PSU_MIO_4_POLARITY {Default} \
CONFIG.PSU_MIO_50_DIRECTION {inout} \
CONFIG.PSU_MIO_50_POLARITY {Default} \
CONFIG.PSU_MIO_51_DIRECTION {out} \
CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_51_POLARITY {Default} \
CONFIG.PSU_MIO_52_DIRECTION {in} \
CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_52_POLARITY {Default} \
CONFIG.PSU_MIO_52_SLEW {fast} \
CONFIG.PSU_MIO_53_DIRECTION {in} \
CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_53_POLARITY {Default} \
CONFIG.PSU_MIO_53_SLEW {fast} \
CONFIG.PSU_MIO_54_DIRECTION {inout} \
CONFIG.PSU_MIO_54_POLARITY {Default} \
CONFIG.PSU_MIO_55_DIRECTION {in} \
CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_55_POLARITY {Default} \
CONFIG.PSU_MIO_55_SLEW {fast} \
CONFIG.PSU_MIO_56_DIRECTION {inout} \
CONFIG.PSU_MIO_56_POLARITY {Default} \
CONFIG.PSU_MIO_57_DIRECTION {inout} \
CONFIG.PSU_MIO_57_POLARITY {Default} \
CONFIG.PSU_MIO_58_DIRECTION {out} \
CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_58_POLARITY {Default} \
CONFIG.PSU_MIO_59_DIRECTION {inout} \
CONFIG.PSU_MIO_59_POLARITY {Default} \
CONFIG.PSU_MIO_5_DIRECTION {inout} \
CONFIG.PSU_MIO_5_POLARITY {Default} \
CONFIG.PSU_MIO_60_DIRECTION {inout} \
CONFIG.PSU_MIO_60_POLARITY {Default} \
CONFIG.PSU_MIO_61_DIRECTION {inout} \
CONFIG.PSU_MIO_61_POLARITY {Default} \
CONFIG.PSU_MIO_62_DIRECTION {inout} \
CONFIG.PSU_MIO_62_POLARITY {Default} \
CONFIG.PSU_MIO_63_DIRECTION {inout} \
CONFIG.PSU_MIO_63_POLARITY {Default} \
CONFIG.PSU_MIO_64_DIRECTION {in} \
CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_64_POLARITY {Default} \
CONFIG.PSU_MIO_64_SLEW {fast} \
CONFIG.PSU_MIO_65_DIRECTION {in} \
CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_65_POLARITY {Default} \
CONFIG.PSU_MIO_65_SLEW {fast} \
CONFIG.PSU_MIO_66_DIRECTION {inout} \
CONFIG.PSU_MIO_66_POLARITY {Default} \
CONFIG.PSU_MIO_67_DIRECTION {in} \
CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_67_POLARITY {Default} \
CONFIG.PSU_MIO_67_SLEW {fast} \
CONFIG.PSU_MIO_68_DIRECTION {inout} \
CONFIG.PSU_MIO_68_POLARITY {Default} \
CONFIG.PSU_MIO_69_DIRECTION {inout} \
CONFIG.PSU_MIO_69_POLARITY {Default} \
CONFIG.PSU_MIO_6_DIRECTION {inout} \
CONFIG.PSU_MIO_6_POLARITY {Default} \
CONFIG.PSU_MIO_70_DIRECTION {out} \
CONFIG.PSU_MIO_70_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_70_POLARITY {Default} \
CONFIG.PSU_MIO_71_DIRECTION {inout} \
CONFIG.PSU_MIO_71_POLARITY {Default} \
CONFIG.PSU_MIO_72_DIRECTION {inout} \
CONFIG.PSU_MIO_72_POLARITY {Default} \
CONFIG.PSU_MIO_73_DIRECTION {inout} \
CONFIG.PSU_MIO_73_POLARITY {Default} \
CONFIG.PSU_MIO_74_DIRECTION {inout} \
CONFIG.PSU_MIO_74_POLARITY {Default} \
CONFIG.PSU_MIO_75_DIRECTION {inout} \
CONFIG.PSU_MIO_75_POLARITY {Default} \
CONFIG.PSU_MIO_76_DIRECTION {inout} \
CONFIG.PSU_MIO_76_POLARITY {Default} \
CONFIG.PSU_MIO_77_DIRECTION {inout} \
CONFIG.PSU_MIO_77_POLARITY {Default} \
CONFIG.PSU_MIO_7_DIRECTION {inout} \
CONFIG.PSU_MIO_7_POLARITY {Default} \
CONFIG.PSU_MIO_8_DIRECTION {inout} \
CONFIG.PSU_MIO_8_POLARITY {Default} \
CONFIG.PSU_MIO_9_DIRECTION {inout} \
CONFIG.PSU_MIO_9_POLARITY {Default} \
CONFIG.PSU_MIO_TREE_PERIPHERALS {UART 1#UART 1#UART 0#UART 0#I2C 1#I2C 1#SPI 1#GPIO0 MIO#GPIO0 MIO#SPI 1#SPI 1#SPI 1#GPIO0 MIO#SD 0#SD 0#SD 0#SD 0#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#SD 0#SD 0#GPIO0 MIO#SD 0#GPIO0 MIO#PMU GPI 0#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#PMU GPO 0#PMU GPO 1#PMU GPO 2#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#SPI 0#GPIO1 MIO#GPIO1 MIO#SPI 0#SPI 0#SPI 0#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#GPIO2 MIO#GPIO2 MIO} \
CONFIG.PSU_MIO_TREE_SIGNALS {txd#rxd#rxd#txd#scl_out#sda_out#sclk_out#gpio0[7]#gpio0[8]#n_ss_out[0]#miso#mosi#gpio0[12]#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#gpio0[17]#gpio0[18]#gpio0[19]#gpio0[20]#sdio0_cmd_out#sdio0_clk_out#gpio0[23]#sdio0_cd_n#gpio0[25]#gpi[0]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#gpo[0]#gpo[1]#gpo[2]#gpio1[35]#gpio1[36]#gpio1[37]#sclk_out#gpio1[39]#gpio1[40]#n_ss_out[0]#miso#mosi#gpio1[44]#gpio1[45]#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#gpio2[76]#gpio2[77]} \
CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {4} \
CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \
CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \
CONFIG.PSU__ACT_DDR_FREQ_MHZ {533.333313} \
CONFIG.PSU__AFI0_COHERENCY {0} \
CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \
CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1200.000000} \
CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \
CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \
CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \
CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0} \
CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \
CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \
CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000000} \
CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \
CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {2} \
CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {250.000000} \
CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \
CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {266.666656} \
CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {4} \
CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {533} \
CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \
CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \
CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {64} \
CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0} \
CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \
CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {3} \
CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {24.576040} \
CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {16} \
CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \
CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {1} \
CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.214443} \
CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {15} \
CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {297.029572} \
CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {4} \
CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \
CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {1} \
CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \
CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {500.000000} \
CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {1} \
CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {2} \
CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \
CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \
CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \
CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {533.333313} \
CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \
CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \
CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \
CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {71} \
CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.2871} \
CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {300} \
CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {1} \
CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \
CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000000} \
CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \
CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \
CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {51.724136} \
CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {29} \
CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \
CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \
CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000000} \
CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \
CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {500} \
CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {4} \
CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ {400} \
CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000000} \
CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \
CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1500.000000} \
CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \
CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \
CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \
CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \
CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \
CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \
CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000000} \
CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \
CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {0} \
CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {45} \
CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0} \
CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \
CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \
CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {250.000000} \
CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \
CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \
CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {500.000000} \
CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \
CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \
CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500000} \
CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \
CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {100.000000} \
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {24.999975} \
CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {15} \
CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {4} \
CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {100} \
CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {RPLL} \
CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {299.999700} \
CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {5} \
CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {100} \
CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {RPLL} \
CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {374.999625} \
CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \
CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ {100} \
CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL {RPLL} \
CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \
CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \
CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {70} \
CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.779} \
CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {25} \
CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {1} \
CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {3} \
CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {187.500000} \
CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {8} \
CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.500000} \
CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \
CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {187.500000} \
CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {8} \
CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {187.500000} \
CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {8} \
CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {100.000000} \
CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \
CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100.000000} \
CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \
CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {100.000000} \
CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \
CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \
CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \
CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \
CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20.000000} \
CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {5} \
CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {15} \
CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \
CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \
CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {1} \
CONFIG.PSU__DDRC__ADDR_MIRROR {0} \
CONFIG.PSU__DDRC__AL {0} \
CONFIG.PSU__DDRC__BANK_ADDR_COUNT {3} \
CONFIG.PSU__DDRC__BG_ADDR_COUNT {NA} \
CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \
CONFIG.PSU__DDRC__BUS_WIDTH {32 Bit} \
CONFIG.PSU__DDRC__CL {NA} \
CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \
CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \
CONFIG.PSU__DDRC__COMPONENTS {Components} \
CONFIG.PSU__DDRC__CWL {NA} \
CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \
CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \
CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {NA} \
CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {NA} \
CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {NA} \
CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {NA} \
CONFIG.PSU__DDRC__DDR4_T_REF_MODE {NA} \
CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {NA} \
CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \
CONFIG.PSU__DDRC__DEVICE_CAPACITY {16384 MBits} \
CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \
CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \
CONFIG.PSU__DDRC__DQMAP_0_3 {0} \
CONFIG.PSU__DDRC__DQMAP_12_15 {0} \
CONFIG.PSU__DDRC__DQMAP_16_19 {0} \
CONFIG.PSU__DDRC__DQMAP_20_23 {0} \
CONFIG.PSU__DDRC__DQMAP_24_27 {0} \
CONFIG.PSU__DDRC__DQMAP_28_31 {0} \
CONFIG.PSU__DDRC__DQMAP_32_35 {0} \
CONFIG.PSU__DDRC__DQMAP_36_39 {0} \
CONFIG.PSU__DDRC__DQMAP_40_43 {0} \
CONFIG.PSU__DDRC__DQMAP_44_47 {0} \
CONFIG.PSU__DDRC__DQMAP_48_51 {0} \
CONFIG.PSU__DDRC__DQMAP_4_7 {0} \
CONFIG.PSU__DDRC__DQMAP_52_55 {0} \
CONFIG.PSU__DDRC__DQMAP_56_59 {0} \
CONFIG.PSU__DDRC__DQMAP_60_63 {0} \
CONFIG.PSU__DDRC__DQMAP_64_67 {0} \
CONFIG.PSU__DDRC__DQMAP_68_71 {0} \
CONFIG.PSU__DDRC__DQMAP_8_11 {0} \
CONFIG.PSU__DDRC__DRAM_WIDTH {32 Bits} \
CONFIG.PSU__DDRC__ECC {Disabled} \
CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \
CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {1} \
CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \
CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \
CONFIG.PSU__DDRC__FGRM {NA} \
CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \
CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {NA} \
CONFIG.PSU__DDRC__LP_ASR {NA} \
CONFIG.PSU__DDRC__MEMORY_TYPE {LPDDR 4} \
CONFIG.PSU__DDRC__PARITY_ENABLE {NA} \
CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \
CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \
CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \
CONFIG.PSU__DDRC__ROW_ADDR_COUNT {16} \
CONFIG.PSU__DDRC__SB_TARGET {NA} \
CONFIG.PSU__DDRC__SELF_REF_ABORT {NA} \
CONFIG.PSU__DDRC__SPEED_BIN {LPDDR4_1066} \
CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \
CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \
CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \
CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \
CONFIG.PSU__DDRC__T_FAW {40.0} \
CONFIG.PSU__DDRC__T_RAS_MIN {42} \
CONFIG.PSU__DDRC__T_RC {63} \
CONFIG.PSU__DDRC__T_RCD {10} \
CONFIG.PSU__DDRC__T_RP {12} \
CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \
CONFIG.PSU__DDRC__VREF {0} \
CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {0} \
CONFIG.PSU__DDR_QOS_ENABLE {1} \
CONFIG.PSU__DDR_QOS_FIX_HP0_RDQOS {7} \
CONFIG.PSU__DDR_QOS_FIX_HP0_WRQOS {15} \
CONFIG.PSU__DDR_QOS_FIX_HP1_RDQOS {3} \
CONFIG.PSU__DDR_QOS_FIX_HP1_WRQOS {3} \
CONFIG.PSU__DDR_QOS_FIX_HP2_RDQOS {3} \
CONFIG.PSU__DDR_QOS_FIX_HP2_WRQOS {3} \
CONFIG.PSU__DDR_QOS_FIX_HP3_RDQOS {3} \
CONFIG.PSU__DDR_QOS_FIX_HP3_WRQOS {3} \
CONFIG.PSU__DDR_QOS_HP0_RDQOS {7} \
CONFIG.PSU__DDR_QOS_HP0_WRQOS {15} \
CONFIG.PSU__DDR_QOS_HP1_RDQOS {3} \
CONFIG.PSU__DDR_QOS_HP1_WRQOS {3} \
CONFIG.PSU__DDR_QOS_HP2_RDQOS {3} \
CONFIG.PSU__DDR_QOS_HP2_WRQOS {3} \
CONFIG.PSU__DDR_QOS_HP3_RDQOS {3} \
CONFIG.PSU__DDR_QOS_HP3_WRQOS {3} \
CONFIG.PSU__DDR_QOS_PORT0_TYPE {Low Latency} \
CONFIG.PSU__DDR_QOS_PORT1_VN1_TYPE {Low Latency} \
CONFIG.PSU__DDR_QOS_PORT1_VN2_TYPE {Best Effort} \
CONFIG.PSU__DDR_QOS_PORT2_VN1_TYPE {Low Latency} \
CONFIG.PSU__DDR_QOS_PORT2_VN2_TYPE {Best Effort} \
CONFIG.PSU__DDR_QOS_PORT3_TYPE {Video Traffic} \
CONFIG.PSU__DDR_QOS_PORT4_TYPE {Best Effort} \
CONFIG.PSU__DDR_QOS_PORT5_TYPE {Best Effort} \
CONFIG.PSU__DDR_QOS_RD_HPR_THRSHLD {0} \
CONFIG.PSU__DDR_QOS_RD_LPR_THRSHLD {16} \
CONFIG.PSU__DDR_QOS_WR_THRSHLD {16} \
CONFIG.PSU__DDR__INTERFACE__FREQMHZ {266.500} \
CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \
CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \
CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \
CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \
CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__DLL__ISUSED {1} \
CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \
CONFIG.PSU__DP__LANE_SEL {Dual Lower} \
CONFIG.PSU__DP__REF_CLK_FREQ {27} \
CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk1} \
CONFIG.PSU__ENET3__FIFO__ENABLE {0} \
CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {0} \
CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__ENET3__PTP__ENABLE {0} \
CONFIG.PSU__ENET3__TSU__ENABLE {0} \
CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100.000000} \
CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {100.000000} \
CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \
CONFIG.PSU__FPGA_PL0_ENABLE {1} \
CONFIG.PSU__FPGA_PL1_ENABLE {0} \
CONFIG.PSU__FPGA_PL2_ENABLE {0} \
CONFIG.PSU__FPGA_PL3_ENABLE {0} \
CONFIG.PSU__GEM3_COHERENCY {0} \
CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \
CONFIG.PSU__GEM__TSU__ENABLE {0} \
CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \
CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \
CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__GPIO2_MIO__IO {MIO 52 .. 77} \
CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__GT__LINK_SPEED {HBR} \
CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \
CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \
CONFIG.PSU__HIGH_ADDRESS__ENABLE {0} \
CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 4 .. 5} \
CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \
CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \
CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \
CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \
CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \
CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100.000000} \
CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \
CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100.000000} \
CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \
CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100.000000} \
CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \
CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100.000000} \
CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {100.000000} \
CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {100.000000} \
CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT {APB} \
CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100.000000} \
CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100.000000} \
CONFIG.PSU__MAXIGP0__DATA_WIDTH {128} \
CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \
CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \
CONFIG.PSU__OVERRIDE__BASIC_CLOCK {1} \
CONFIG.PSU__PL_CLK0_BUF {TRUE} \
CONFIG.PSU__PL_CLK1_BUF {FALSE} \
CONFIG.PSU__PL_CLK2_BUF {FALSE} \
CONFIG.PSU__PL_CLK3_BUF {FALSE} \
CONFIG.PSU__PMU_COHERENCY {0} \
CONFIG.PSU__PMU__AIBACK__ENABLE {0} \
CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \
CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \
CONFIG.PSU__PMU__GPI0__ENABLE {1} \
CONFIG.PSU__PMU__GPI0__IO {MIO 26} \
CONFIG.PSU__PMU__GPI1__ENABLE {0} \
CONFIG.PSU__PMU__GPI2__ENABLE {0} \
CONFIG.PSU__PMU__GPI3__ENABLE {0} \
CONFIG.PSU__PMU__GPI4__ENABLE {0} \
CONFIG.PSU__PMU__GPI5__ENABLE {0} \
CONFIG.PSU__PMU__GPO0__ENABLE {1} \
CONFIG.PSU__PMU__GPO0__IO {MIO 32} \
CONFIG.PSU__PMU__GPO1__ENABLE {1} \
CONFIG.PSU__PMU__GPO1__IO {MIO 33} \
CONFIG.PSU__PMU__GPO2__ENABLE {1} \
CONFIG.PSU__PMU__GPO2__IO {MIO 34} \
CONFIG.PSU__PMU__GPO2__POLARITY {high} \
CONFIG.PSU__PMU__GPO3__ENABLE {0} \
CONFIG.PSU__PMU__GPO4__ENABLE {0} \
CONFIG.PSU__PMU__GPO5__ENABLE {0} \
CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__PMU__PLERROR__ENABLE {0} \
CONFIG.PSU__PRESET_APPLIED {1} \
CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;1|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;1|S_AXI_HP3_FPD:NA;1|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;1|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;0|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;0|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \
CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;1|LPD;USB3_1;FF9E0000;FF9EFFFF;1|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;1|LPD;SPI0;FF040000;FF04FFFF;1|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;1|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;0|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;0|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;0|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_GPV;FD700000;FD7FFFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;800000000;0|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|FPD;CCI_GPV;FD6E0000;FD6EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1} \
CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333333} \
CONFIG.PSU__QSPI_COHERENCY {0} \
CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \
CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {0} \
CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__SATA__LANE0__ENABLE {0} \
CONFIG.PSU__SATA__LANE1__ENABLE {0} \
CONFIG.PSU__SATA__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__SAXIGP0__DATA_WIDTH {128} \
CONFIG.PSU__SAXIGP5__DATA_WIDTH {128} \
CONFIG.PSU__SD0_COHERENCY {0} \
CONFIG.PSU__SD0_ROUTE_THROUGH_FPD {0} \
CONFIG.PSU__SD0__DATA_TRANSFER_MODE {4Bit} \
CONFIG.PSU__SD0__GRP_CD__ENABLE {1} \
CONFIG.PSU__SD0__GRP_CD__IO {MIO 24} \
CONFIG.PSU__SD0__GRP_POW__ENABLE {0} \
CONFIG.PSU__SD0__GRP_WP__ENABLE {0} \
CONFIG.PSU__SD0__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__SD0__PERIPHERAL__IO {MIO 13 .. 16 21 22} \
CONFIG.PSU__SD0__RESET__ENABLE {0} \
CONFIG.PSU__SD0__SLOT_TYPE {SD 2.0} \
CONFIG.PSU__SD1_COHERENCY {0} \
CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \
CONFIG.PSU__SD1__DATA_TRANSFER_MODE {4Bit} \
CONFIG.PSU__SD1__GRP_CD__ENABLE {0} \
CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \
CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \
CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \
CONFIG.PSU__SD1__RESET__ENABLE {0} \
CONFIG.PSU__SD1__SLOT_TYPE {SD 2.0} \
CONFIG.PSU__SPI0__GRP_SS0__ENABLE {1} \
CONFIG.PSU__SPI0__GRP_SS0__IO {MIO 41} \
CONFIG.PSU__SPI0__GRP_SS1__ENABLE {0} \
CONFIG.PSU__SPI0__GRP_SS2__ENABLE {0} \
CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__SPI0__PERIPHERAL__IO {MIO 38 .. 43} \
CONFIG.PSU__SPI1__GRP_SS0__ENABLE {1} \
CONFIG.PSU__SPI1__GRP_SS0__IO {MIO 9} \
CONFIG.PSU__SPI1__GRP_SS1__ENABLE {0} \
CONFIG.PSU__SPI1__GRP_SS2__ENABLE {0} \
CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__SPI1__PERIPHERAL__IO {MIO 6 .. 11} \
CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \
CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__SWDT0__RESET__ENABLE {0} \
CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \
CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__SWDT1__RESET__ENABLE {0} \
CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \
CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \
CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \
CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \
CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \
CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \
CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \
CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \
CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \
CONFIG.PSU__UART0__BAUD_RATE {115200} \
CONFIG.PSU__UART0__MODEM__ENABLE {0} \
CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 2 .. 3} \
CONFIG.PSU__UART1__BAUD_RATE {115200} \
CONFIG.PSU__UART1__MODEM__ENABLE {0} \
CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 0 .. 1} \
CONFIG.PSU__USB0_COHERENCY {0} \
CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \
CONFIG.PSU__USB0__REF_CLK_FREQ {26} \
CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk0} \
CONFIG.PSU__USB0__RESET__ENABLE {0} \
CONFIG.PSU__USB1_COHERENCY {0} \
CONFIG.PSU__USB1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__USB1__PERIPHERAL__IO {MIO 64 .. 75} \
CONFIG.PSU__USB1__REF_CLK_FREQ {26} \
CONFIG.PSU__USB1__REF_CLK_SEL {Ref Clk0} \
CONFIG.PSU__USB1__RESET__ENABLE {0} \
CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \
CONFIG.PSU__USB2_1__EMIO__ENABLE {0} \
CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \
CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \
CONFIG.PSU__USB3_1__EMIO__ENABLE {0} \
CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__USB3_1__PERIPHERAL__IO {GT Lane3} \
CONFIG.PSU__USB__RESET__MODE {Boot Pin} \
CONFIG.PSU__USB__RESET__POLARITY {Active Low} \
CONFIG.PSU__USE__IRQ0 {1} \
CONFIG.PSU__USE__M_AXI_GP0 {1} \
CONFIG.PSU__USE__M_AXI_GP1 {0} \
CONFIG.PSU__USE__M_AXI_GP2 {1} \
CONFIG.PSU__USE__S_AXI_GP0 {1} \
CONFIG.PSU__USE__S_AXI_GP5 {1} \
CONFIG.SUBPRESET1 {Custom} \
] $zynq_ultra_ps_e_0
# Create interface connections
connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_pins interconnect_axihpm0fpd/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_FPD]
connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_pins axi_intc_0/s_axi] [get_bd_intf_pins interconnect_axilite/M00_AXI]
connect_bd_intf_net -intf_net axi_interconnect_hpc0_M00_AXI [get_bd_intf_pins axi_interconnect_hpc0/M00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HPC0_FPD]
connect_bd_intf_net -intf_net axi_vip_0_M_AXI [get_bd_intf_pins axi_vip_0/M_AXI] [get_bd_intf_pins interconnect_axifull/S00_AXI]
connect_bd_intf_net -intf_net axi_vip_1_M_AXI [get_bd_intf_pins axi_interconnect_hpc0/S00_AXI] [get_bd_intf_pins axi_vip_1/M_AXI]
connect_bd_intf_net -intf_net interconnect_axifull_M00_AXI [get_bd_intf_pins interconnect_axifull/M00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP3_FPD]
connect_bd_intf_net -intf_net interconnect_axihpm0fpd_M00_AXI [get_bd_intf_pins axi_register_slice_0/S_AXI] [get_bd_intf_pins interconnect_axihpm0fpd/M00_AXI]
connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_LPD [get_bd_intf_pins interconnect_axilite/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_LPD]
# Create port connections
connect_bd_net -net axi_intc_0_irq [get_bd_pins axi_intc_0/irq] [get_bd_pins zynq_ultra_ps_e_0/pl_ps_irq0]
connect_bd_net -net clk_wiz_0_clk_out1 [get_bd_pins clk_wiz_0/clk_out1] [get_bd_pins proc_sys_reset_0/slowest_sync_clk]
connect_bd_net -net clk_wiz_0_clk_out2 [get_bd_pins axi_interconnect_hpc0/ACLK] [get_bd_pins axi_interconnect_hpc0/M00_ACLK] [get_bd_pins axi_interconnect_hpc0/S00_ACLK] [get_bd_pins axi_register_slice_0/aclk] [get_bd_pins axi_vip_0/aclk] [get_bd_pins axi_vip_1/aclk] [get_bd_pins clk_wiz_0/clk_out2] [get_bd_pins interconnect_axifull/ACLK] [get_bd_pins interconnect_axifull/M00_ACLK] [get_bd_pins interconnect_axifull/S00_ACLK] [get_bd_pins interconnect_axihpm0fpd/ACLK] [get_bd_pins interconnect_axihpm0fpd/M00_ACLK] [get_bd_pins interconnect_axihpm0fpd/S00_ACLK] [get_bd_pins proc_sys_reset_1/slowest_sync_clk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/saxihp3_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/saxihpc0_fpd_aclk]
connect_bd_net -net clk_wiz_0_clk_out3 [get_bd_pins axi_intc_0/s_axi_aclk] [get_bd_pins clk_wiz_0/clk_out3] [get_bd_pins interconnect_axilite/ACLK] [get_bd_pins interconnect_axilite/M00_ACLK] [get_bd_pins interconnect_axilite/S00_ACLK] [get_bd_pins proc_sys_reset_2/slowest_sync_clk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_lpd_aclk]
connect_bd_net -net clk_wiz_0_clk_out4 [get_bd_pins clk_wiz_0/clk_out4] [get_bd_pins proc_sys_reset_3/slowest_sync_clk]
connect_bd_net -net clk_wiz_0_clk_out5 [get_bd_pins clk_wiz_0/clk_out5] [get_bd_pins proc_sys_reset_4/slowest_sync_clk]
connect_bd_net -net clk_wiz_0_clk_out6 [get_bd_pins clk_wiz_0/clk_out6] [get_bd_pins proc_sys_reset_5/slowest_sync_clk]
connect_bd_net -net clk_wiz_0_clk_out7 [get_bd_pins clk_wiz_0/clk_out7] [get_bd_pins proc_sys_reset_6/slowest_sync_clk]
connect_bd_net -net clk_wiz_0_locked [get_bd_pins clk_wiz_0/locked] [get_bd_pins proc_sys_reset_0/dcm_locked] [get_bd_pins proc_sys_reset_1/dcm_locked] [get_bd_pins proc_sys_reset_2/dcm_locked] [get_bd_pins proc_sys_reset_3/dcm_locked] [get_bd_pins proc_sys_reset_4/dcm_locked] [get_bd_pins proc_sys_reset_5/dcm_locked] [get_bd_pins proc_sys_reset_6/dcm_locked]
connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_hpc0/ARESETN] [get_bd_pins axi_interconnect_hpc0/M00_ARESETN] [get_bd_pins axi_interconnect_hpc0/S00_ARESETN] [get_bd_pins axi_vip_1/aresetn] [get_bd_pins interconnect_axifull/ARESETN] [get_bd_pins interconnect_axifull/M00_ARESETN] [get_bd_pins interconnect_axifull/S00_ARESETN] [get_bd_pins interconnect_axihpm0fpd/ARESETN] [get_bd_pins interconnect_axihpm0fpd/M00_ARESETN] [get_bd_pins interconnect_axihpm0fpd/S00_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_register_slice_0/aresetn] [get_bd_pins axi_vip_0/aresetn] [get_bd_pins proc_sys_reset_1/peripheral_aresetn]
connect_bd_net -net proc_sys_reset_2_interconnect_aresetn [get_bd_pins axi_intc_0/s_axi_aresetn] [get_bd_pins interconnect_axilite/ARESETN] [get_bd_pins interconnect_axilite/M00_ARESETN] [get_bd_pins interconnect_axilite/S00_ARESETN] [get_bd_pins proc_sys_reset_2/interconnect_aresetn]
connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins clk_wiz_0/clk_in1] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0]
connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins clk_wiz_0/resetn] [get_bd_pins proc_sys_reset_0/ext_reset_in] [get_bd_pins proc_sys_reset_1/ext_reset_in] [get_bd_pins proc_sys_reset_2/ext_reset_in] [get_bd_pins proc_sys_reset_3/ext_reset_in] [get_bd_pins proc_sys_reset_4/ext_reset_in] [get_bd_pins proc_sys_reset_5/ext_reset_in] [get_bd_pins proc_sys_reset_6/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0]
# Create address segments
assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_vip_0/Master_AXI] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP5/HP3_DDR_LOW] -force
assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_vip_1/Master_AXI] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force
assign_bd_address -offset 0x80000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_intc_0/S_AXI/Reg] -force
# Restore current instance
current_bd_instance $oldCurInst
# Create PFM attributes
set_property PFM_NAME {marsee:ultra96v2:ultra96v2_min3_201:1.0} [get_files [current_bd_design].bd]
set_property PFM.IRQ {intr {id 0 range 32}} [get_bd_cells /axi_intc_0]
set_property PFM.AXI_PORT {S01_AXI {memport "S_AXI_HPC" sptag "" memory ""} S02_AXI {memport "S_AXI_HPC" sptag "" memory ""} S03_AXI {memport "S_AXI_HPC" sptag "" memory ""} S04_AXI {memport "S_AXI_HPC" sptag "" memory ""} S05_AXI {memport "S_AXI_HPC" sptag "" memory ""} S06_AXI {memport "S_AXI_HPC" sptag "" memory ""} S07_AXI {memport "S_AXI_HPC" sptag "" memory ""} S08_AXI {memport "S_AXI_HPC" sptag "" memory ""} S09_AXI {memport "S_AXI_HPC" sptag "" memory ""} S10_AXI {memport "S_AXI_HPC" sptag "" memory ""} S11_AXI {memport "S_AXI_HPC" sptag "" memory ""} S12_AXI {memport "S_AXI_HPC" sptag "" memory ""} S13_AXI {memport "S_AXI_HPC" sptag "" memory ""} S14_AXI {memport "S_AXI_HPC" sptag "" memory ""} S15_AXI {memport "S_AXI_HPC" sptag "" memory ""}} [get_bd_cells /axi_interconnect_hpc0]
set_property PFM.CLOCK {clk_out1 {id "0" is_default "true" proc_sys_reset "/proc_sys_reset_0" status "fixed"} clk_out2 {id "1" is_default "false" proc_sys_reset "/proc_sys_reset_1" status "fixed"} clk_out3 {id "2" is_default "false" proc_sys_reset "/proc_sys_reset_2" status "fixed"} clk_out4 {id "3" is_default "false" proc_sys_reset "/proc_sys_reset_3" status "fixed"} clk_out5 {id "4" is_default "false" proc_sys_reset "/proc_sys_reset_4" status "fixed"} clk_out6 {id "5" is_default "false" proc_sys_reset "/proc_sys_reset_5" status "fixed"} clk_out7 {id "6" is_default "false" proc_sys_reset "/proc_sys_reset_6" status "fixed"}} [get_bd_cells /clk_wiz_0]
set_property PFM.AXI_PORT {S01_AXI {memport "S_AXI_HP" sptag "" memory ""} S02_AXI {memport "S_AXI_HP" sptag "" memory ""} S03_AXI {memport "S_AXI_HP" sptag "" memory ""} S04_AXI {memport "S_AXI_HP" sptag "" memory ""} S05_AXI {memport "S_AXI_HP" sptag "" memory ""} S06_AXI {memport "S_AXI_HP" sptag "" memory ""} S07_AXI {memport "S_AXI_HP" sptag "" memory ""} S08_AXI {memport "S_AXI_HP" sptag "" memory ""} S09_AXI {memport "S_AXI_HP" sptag "" memory ""} S10_AXI {memport "S_AXI_HP" sptag "" memory ""} S11_AXI {memport "S_AXI_HP" sptag "" memory ""} S12_AXI {memport "S_AXI_HP" sptag "" memory ""} S13_AXI {memport "S_AXI_HP" sptag "" memory ""} S14_AXI {memport "S_AXI_HP" sptag "" memory ""} S15_AXI {memport "S_AXI_HP" sptag "" memory ""}} [get_bd_cells /interconnect_axifull]
set_property PFM.AXI_PORT {M01_AXI {memport "M_AXI_GP" sptag "" memory ""} M02_AXI {memport "M_AXI_GP" sptag "" memory ""} M03_AXI {memport "M_AXI_GP" sptag "" memory ""} M04_AXI {memport "M_AXI_GP" sptag "" memory ""} M05_AXI {memport "M_AXI_GP" sptag "" memory ""} M06_AXI {memport "M_AXI_GP" sptag "" memory ""} M07_AXI {memport "M_AXI_GP" sptag "" memory ""} M08_AXI {memport "M_AXI_GP" sptag "" memory ""} M09_AXI {memport "M_AXI_GP" sptag "" memory ""} M10_AXI {memport "M_AXI_GP" sptag "" memory ""} M11_AXI {memport "M_AXI_GP" sptag "" memory ""} M12_AXI {memport "M_AXI_GP" sptag "" memory ""} M13_AXI {memport "M_AXI_GP" sptag "" memory ""} M14_AXI {memport "M_AXI_GP" sptag "" memory ""} M15_AXI {memport "M_AXI_GP" sptag "" memory ""} M16_AXI {memport "M_AXI_GP" sptag "" memory ""} M17_AXI {memport "M_AXI_GP" sptag "" memory ""} M18_AXI {memport "M_AXI_GP" sptag "" memory ""} M19_AXI {memport "M_AXI_GP" sptag "" memory ""} M20_AXI {memport "M_AXI_GP" sptag "" memory ""} M21_AXI {memport "M_AXI_GP" sptag "" memory ""} M22_AXI {memport "M_AXI_GP" sptag "" memory ""} M23_AXI {memport "M_AXI_GP" sptag "" memory ""} M24_AXI {memport "M_AXI_GP" sptag "" memory ""} M25_AXI {memport "M_AXI_GP" sptag "" memory ""} M26_AXI {memport "M_AXI_GP" sptag "" memory ""} M27_AXI {memport "M_AXI_GP" sptag "" memory ""} M28_AXI {memport "M_AXI_GP" sptag "" memory ""} M29_AXI {memport "M_AXI_GP" sptag "" memory ""} M30_AXI {memport "M_AXI_GP" sptag "" memory ""} M31_AXI {memport "M_AXI_GP" sptag "" memory ""} M32_AXI {memport "M_AXI_GP" sptag "" memory ""} M33_AXI {memport "M_AXI_GP" sptag "" memory ""} M34_AXI {memport "M_AXI_GP" sptag "" memory ""} M35_AXI {memport "M_AXI_GP" sptag "" memory ""} M36_AXI {memport "M_AXI_GP" sptag "" memory ""} M37_AXI {memport "M_AXI_GP" sptag "" memory ""} M38_AXI {memport "M_AXI_GP" sptag "" memory ""} M39_AXI {memport "M_AXI_GP" sptag "" memory ""} M40_AXI {memport "M_AXI_GP" sptag "" memory ""} M41_AXI {memport "M_AXI_GP" sptag "" memory ""} M42_AXI {memport "M_AXI_GP" sptag "" memory ""} M43_AXI {memport "M_AXI_GP" sptag "" memory ""} M44_AXI {memport "M_AXI_GP" sptag "" memory ""} M45_AXI {memport "M_AXI_GP" sptag "" memory ""} M46_AXI {memport "M_AXI_GP" sptag "" memory ""} M47_AXI {memport "M_AXI_GP" sptag "" memory ""} M48_AXI {memport "M_AXI_GP" sptag "" memory ""} M49_AXI {memport "M_AXI_GP" sptag "" memory ""} M50_AXI {memport "M_AXI_GP" sptag "" memory ""} M51_AXI {memport "M_AXI_GP" sptag "" memory ""} M52_AXI {memport "M_AXI_GP" sptag "" memory ""} M53_AXI {memport "M_AXI_GP" sptag "" memory ""} M54_AXI {memport "M_AXI_GP" sptag "" memory ""} M55_AXI {memport "M_AXI_GP" sptag "" memory ""} M56_AXI {memport "M_AXI_GP" sptag "" memory ""} M57_AXI {memport "M_AXI_GP" sptag "" memory ""} M58_AXI {memport "M_AXI_GP" sptag "" memory ""} M59_AXI {memport "M_AXI_GP" sptag "" memory ""} M60_AXI {memport "M_AXI_GP" sptag "" memory ""} M61_AXI {memport "M_AXI_GP" sptag "" memory ""} M62_AXI {memport "M_AXI_GP" sptag "" memory ""} M63_AXI {memport "M_AXI_GP" sptag "" memory ""}} [get_bd_cells /interconnect_axilite]
set_property PFM.AXI_PORT {M_AXI_HPM1_FPD {memport "M_AXI_GP" sptag "" memory ""} S_AXI_HPC1_FPD {memport "S_AXI_HPC" sptag "" memory ""} S_AXI_HP0_FPD {memport "S_AXI_HP" sptag "" memory ""} S_AXI_HP1_FPD {memport "S_AXI_HP" sptag "" memory ""} S_AXI_HP2_FPD {memport "S_AXI_HP" sptag "" memory ""}} [get_bd_cells /zynq_ultra_ps_e_0]
validate_bd_design
save_bd_design
}
# End of create_root_design()
##################################################################
# MAIN FLOW
##################################################################
create_root_design ""
masaaki@masaaki-H110M4-M01:/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base$ make all
make -C vivado PLATFORM=xilinx_zcu104_base_202010_1
make[1]: ディレクトリ '/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado' に入ります
mkdir -p ../platform_repo/tmp/vivado
/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vivado/2020.1/bin/vivado -mode batch -notrace -source xilinx_zcu104_base_202010_1_xsa.tcl
****** Vivado v2020.1 (64-bit)
**** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020
**** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
source xilinx_zcu104_base_202010_1_xsa.tcl -notrace
INFO: [BD_TCL-3] Currently there is no design <zcu104_base> in project, so creating one...
Wrote : </media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/zcu104_base.bd>
create_bd_design: Time (s): cpu = 00:00:03 ; elapsed = 00:00:07 . Memory (MB): peak = 2214.023 ; gain = 21.051 ; free physical = 6100 ; free virtual = 34074
INFO: [BD_TCL-4] Making design <zcu104_base> as current_bd_design.
INFO: [BD_TCL-5] Currently the variable <design_name> is equal to "zcu104_base".
INFO: [BD_TCL-6] Checking if the following IPs exist in the project's IP catalog: xilinx.com:ip:axi_intc:* xilinx.com:ip:axi_register_slice:* xilinx.com:ip:axi_vip:* xilinx.com:ip:clk_wiz:* xilinx.com:ip:proc_sys_reset:* xilinx.com:ip:zynq_ultra_ps_e:* .
create_bd_cell: Time (s): cpu = 00:00:34 ; elapsed = 00:01:00 . Memory (MB): peak = 2882.402 ; gain = 668.375 ; free physical = 4966 ; free virtual = 32955
INFO: [PSU-1] DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change
WARNING: [BD 41-1306] The connection to interface pin /axi_intc_0/irq is being overridden by the user. This pin will not be connected as a part of interface connection interrupt
WARNING: [BD 41-1731] Type mismatch between connected pins: /axi_intc_0/irq(undef) and /ps_e/pl_ps_irq0(intr)
Slave segment '/ps_e/SAXIGP5/HP3_DDR_LOW' is being assigned into address space '/axi_vip_0/Master_AXI' at <0x0000_0000 [ 2G ]>.
Slave segment '/ps_e/SAXIGP0/HPC0_DDR_LOW' is being assigned into address space '/axi_vip_1/Master_AXI' at <0x0000_0000 [ 2G ]>.
Slave segment '/axi_intc_0/S_AXI/Reg' is being assigned into address space '/ps_e/Data' at <0x8002_0000 [ 4K ]>.
Wrote : </media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/zcu104_base.bd>
INFO: [PSU-1] DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change
WARNING: [xilinx.com:ip:axi_intc:4.1-13] /axi_intc_0: Interrupt output connection Bus is selected, but the interrupt bus interface is not connected to a matching interface. Please consider selecting Single instead.
INFO: [xilinx.com:ip:clk_wiz:6.0-1] /clk_wiz_0 clk_wiz propagate
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps_e/S_AXI_HPC0_FPD(1) and /axi_vip_1/M_AXI(0)
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps_e/S_AXI_HPC0_FPD(1) and /axi_vip_1/M_AXI(0)
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /interconnect_axilite/s00_couplers/auto_pc/S_AXI(0) and /ps_e/M_AXI_HPM0_LPD(16)
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /interconnect_axilite/s00_couplers/auto_pc/S_AXI(0) and /ps_e/M_AXI_HPM0_LPD(16)
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps_e/S_AXI_HP3_FPD(1) and /interconnect_axifull/s00_couplers/auto_us/M_AXI(0)
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps_e/S_AXI_HP3_FPD(1) and /interconnect_axifull/s00_couplers/auto_us/M_AXI(0)
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
Please check your design and connect them as needed:
/axi_intc_0/intr
Wrote : </media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/zcu104_base.bd>
INFO: [BD 41-1662] The design 'zcu104_base.bd' is already validated. Therefore parameter propagation will not be re-run.
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
Please check your design and connect them as needed:
/axi_intc_0/intr
VHDL Output written to : /media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/synth/zcu104_base.v
VHDL Output written to : /media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/sim/zcu104_base.v
VHDL Output written to : /media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/hdl/zcu104_base_wrapper.v
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_intc_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_register_slice_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_vip_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_vip_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_wiz_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block proc_sys_reset_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block proc_sys_reset_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block proc_sys_reset_2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block proc_sys_reset_3 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block proc_sys_reset_4 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block proc_sys_reset_5 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block proc_sys_reset_6 .
INFO: [xilinx.com:ip:zynq_ultra_ps_e:3.3-0] zcu104_base_ps_e_0:
Changes in your design (including the PCW configuration settings) are not automatically exported from Vivado to Xilinx's SDK, Petalinux or Yocto.
This is by design to avoid disrupting existing embedded development efforts. To have any changes of your design taking effect in the embedded software flow please export your
design by going through Vivado's main menu, click on File, then Export finally select Export Hardware, please ensure you click on the Include BitStream option.
The auto-generated HDF file is all you need to import in Xilinx's SDK, Petalinux or Yocto for your changes to be reflected in the Embedded Software Flow.
For more information, please consult PG201, section: Exporting PCW Settings to Embedded Software Flows
INFO: [PSU-0] Address Range of DDR (0x7ff00000 to 0x7fffffff) is reserved by PMU for internal purpose.
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI_HPM0_FPD'. A default connection has been created.
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI_HPM0_LPD'. A default connection has been created.
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI_HPC0_FPD'. A default connection has been created.
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI_HP3_FPD'. A default connection has been created.
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps_e .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_auto_us_0/zcu104_base_auto_us_0_ooc.xdc'
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created.
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created.
INFO: [BD 41-1029] Generation completed for the IP Integrator block interconnect_axifull/s00_couplers/auto_us .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_auto_pc_0/zcu104_base_auto_pc_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block interconnect_axilite/s00_couplers/auto_pc .
Exporting to file /media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/hw_handoff/zcu104_base.hwh
Generated Block Design Tcl file /media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/hw_handoff/zcu104_base_bd.tcl
Generated Hardware Definition File /media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/synth/zcu104_base.hwdef
generate_target: Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 3170.496 ; gain = 161.344 ; free physical = 4692 ; free virtual = 32754
[Mon Jul 20 20:57:27 2020] Launched zcu104_base_proc_sys_reset_6_0_synth_1, zcu104_base_proc_sys_reset_5_0_synth_1, zcu104_base_proc_sys_reset_4_0_synth_1, zcu104_base_proc_sys_reset_3_0_synth_1, zcu104_base_proc_sys_reset_2_0_synth_1, zcu104_base_proc_sys_reset_1_0_synth_1, zcu104_base_proc_sys_reset_0_0_synth_1, zcu104_base_clk_wiz_0_0_synth_1, zcu104_base_axi_vip_1_0_synth_1, zcu104_base_axi_vip_0_0_synth_1, zcu104_base_axi_intc_0_0_synth_1, zcu104_base_axi_register_slice_0_0_synth_1, zcu104_base_ps_e_0_synth_1, zcu104_base_auto_us_0_synth_1, zcu104_base_auto_pc_0_synth_1, synth_1...
Run output will be captured here:
zcu104_base_proc_sys_reset_6_0_synth_1: /media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.runs/zcu104_base_proc_sys_reset_6_0_synth_1/runme.log
zcu104_base_proc_sys_reset_5_0_synth_1: /media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.runs/zcu104_base_proc_sys_reset_5_0_synth_1/runme.log
zcu104_base_proc_sys_reset_4_0_synth_1: /media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.runs/zcu104_base_proc_sys_reset_4_0_synth_1/runme.log
zcu104_base_proc_sys_reset_3_0_synth_1: /media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.runs/zcu104_base_proc_sys_reset_3_0_synth_1/runme.log
zcu104_base_proc_sys_reset_2_0_synth_1: /media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.runs/zcu104_base_proc_sys_reset_2_0_synth_1/runme.log
zcu104_base_proc_sys_reset_1_0_synth_1: /media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.runs/zcu104_base_proc_sys_reset_1_0_synth_1/runme.log
zcu104_base_proc_sys_reset_0_0_synth_1: /media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.runs/zcu104_base_proc_sys_reset_0_0_synth_1/runme.log
zcu104_base_clk_wiz_0_0_synth_1: /media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.runs/zcu104_base_clk_wiz_0_0_synth_1/runme.log
zcu104_base_axi_vip_1_0_synth_1: /media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.runs/zcu104_base_axi_vip_1_0_synth_1/runme.log
zcu104_base_axi_vip_0_0_synth_1: /media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.runs/zcu104_base_axi_vip_0_0_synth_1/runme.log
zcu104_base_axi_intc_0_0_synth_1: /media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.runs/zcu104_base_axi_intc_0_0_synth_1/runme.log
zcu104_base_axi_register_slice_0_0_synth_1: /media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.runs/zcu104_base_axi_register_slice_0_0_synth_1/runme.log
zcu104_base_ps_e_0_synth_1: /media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.runs/zcu104_base_ps_e_0_synth_1/runme.log
zcu104_base_auto_us_0_synth_1: /media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.runs/zcu104_base_auto_us_0_synth_1/runme.log
zcu104_base_auto_pc_0_synth_1: /media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.runs/zcu104_base_auto_pc_0_synth_1/runme.log
synth_1: /media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.runs/synth_1/runme.log
[Mon Jul 20 20:57:27 2020] Launched impl_1...
Run output will be captured here: /media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.runs/impl_1/runme.log
[Mon Jul 20 20:57:27 2020] Waiting for impl_1 to finish...
*** Running vivado
with args -log zcu104_base_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source zcu104_base_wrapper.tcl -notrace
****** Vivado v2020.1 (64-bit)
**** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020
**** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
source zcu104_base_wrapper.tcl -notrace
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vivado/2020.1/data/ip'.
add_files: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2150.168 ; gain = 0.000 ; free physical = 8100 ; free virtual = 32383
Command: link_design -top zcu104_base_wrapper -part xczu7ev-ffvc1156-2-e
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Device 21-403] Loading part xczu7ev-ffvc1156-2-e
INFO: [Project 1-454] Reading design checkpoint '/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_axi_intc_0_0/zcu104_base_axi_intc_0_0.dcp' for cell 'zcu104_base_i/axi_intc_0'
INFO: [Project 1-454] Reading design checkpoint '/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_axi_register_slice_0_0/zcu104_base_axi_register_slice_0_0.dcp' for cell 'zcu104_base_i/axi_register_slice_0'
INFO: [Project 1-454] Reading design checkpoint '/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_axi_vip_0_0/zcu104_base_axi_vip_0_0.dcp' for cell 'zcu104_base_i/axi_vip_0'
INFO: [Project 1-454] Reading design checkpoint '/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_axi_vip_1_0/zcu104_base_axi_vip_1_0.dcp' for cell 'zcu104_base_i/axi_vip_1'
INFO: [Project 1-454] Reading design checkpoint '/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_clk_wiz_0_0/zcu104_base_clk_wiz_0_0.dcp' for cell 'zcu104_base_i/clk_wiz_0'
INFO: [Project 1-454] Reading design checkpoint '/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_proc_sys_reset_0_0/zcu104_base_proc_sys_reset_0_0.dcp' for cell 'zcu104_base_i/proc_sys_reset_0'
INFO: [Project 1-454] Reading design checkpoint '/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_proc_sys_reset_1_0/zcu104_base_proc_sys_reset_1_0.dcp' for cell 'zcu104_base_i/proc_sys_reset_1'
INFO: [Project 1-454] Reading design checkpoint '/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_proc_sys_reset_2_0/zcu104_base_proc_sys_reset_2_0.dcp' for cell 'zcu104_base_i/proc_sys_reset_2'
INFO: [Project 1-454] Reading design checkpoint '/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_proc_sys_reset_3_0/zcu104_base_proc_sys_reset_3_0.dcp' for cell 'zcu104_base_i/proc_sys_reset_3'
INFO: [Project 1-454] Reading design checkpoint '/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_proc_sys_reset_4_0/zcu104_base_proc_sys_reset_4_0.dcp' for cell 'zcu104_base_i/proc_sys_reset_4'
INFO: [Project 1-454] Reading design checkpoint '/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_proc_sys_reset_5_0/zcu104_base_proc_sys_reset_5_0.dcp' for cell 'zcu104_base_i/proc_sys_reset_5'
INFO: [Project 1-454] Reading design checkpoint '/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_proc_sys_reset_6_0/zcu104_base_proc_sys_reset_6_0.dcp' for cell 'zcu104_base_i/proc_sys_reset_6'
INFO: [Project 1-454] Reading design checkpoint '/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_ps_e_0/zcu104_base_ps_e_0.dcp' for cell 'zcu104_base_i/ps_e'
INFO: [Project 1-454] Reading design checkpoint '/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_auto_us_0/zcu104_base_auto_us_0.dcp' for cell 'zcu104_base_i/interconnect_axifull/s00_couplers/auto_us'
INFO: [Project 1-454] Reading design checkpoint '/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_auto_pc_0/zcu104_base_auto_pc_0.dcp' for cell 'zcu104_base_i/interconnect_axilite/s00_couplers/auto_pc'
Netlist sorting complete. Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2726.750 ; gain = 0.000 ; free physical = 7267 ; free virtual = 31550
INFO: [Netlist 29-17] Analyzing 41 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2020.1
INFO: [Project 1-570] Preparing netlist for logic optimization
WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. zcu104_base_i/clk_wiz_0/inst/clkin1_ibuf
Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'zcu104_base_i/clk_wiz_0/clk_in1' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
Parsing XDC File [/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_axi_intc_0_0/zcu104_base_axi_intc_0_0.xdc] for cell 'zcu104_base_i/axi_intc_0/U0'
Finished Parsing XDC File [/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_axi_intc_0_0/zcu104_base_axi_intc_0_0.xdc] for cell 'zcu104_base_i/axi_intc_0/U0'
Parsing XDC File [/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_clk_wiz_0_0/zcu104_base_clk_wiz_0_0_board.xdc] for cell 'zcu104_base_i/clk_wiz_0/inst'
Finished Parsing XDC File [/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_clk_wiz_0_0/zcu104_base_clk_wiz_0_0_board.xdc] for cell 'zcu104_base_i/clk_wiz_0/inst'
Parsing XDC File [/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_clk_wiz_0_0/zcu104_base_clk_wiz_0_0.xdc] for cell 'zcu104_base_i/clk_wiz_0/inst'
INFO: [Timing 38-35] Done setting XDC timing constraints. [/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_clk_wiz_0_0/zcu104_base_clk_wiz_0_0.xdc:57]
INFO: [Timing 38-2] Deriving generated clocks [/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_clk_wiz_0_0/zcu104_base_clk_wiz_0_0.xdc:57]
get_clocks: Time (s): cpu = 00:00:05 ; elapsed = 00:00:09 . Memory (MB): peak = 3420.375 ; gain = 313.359 ; free physical = 6547 ; free virtual = 30831
WARNING: [Vivado 12-2489] -input_jitter contains time 0.100010 which will be rounded to 0.100 to ensure it is an integer multiple of 1 picosecond [/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_clk_wiz_0_0/zcu104_base_clk_wiz_0_0.xdc:57]
Finished Parsing XDC File [/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_clk_wiz_0_0/zcu104_base_clk_wiz_0_0.xdc] for cell 'zcu104_base_i/clk_wiz_0/inst'
Parsing XDC File [/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_proc_sys_reset_0_0/zcu104_base_proc_sys_reset_0_0_board.xdc] for cell 'zcu104_base_i/proc_sys_reset_0/U0'
Finished Parsing XDC File [/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_proc_sys_reset_0_0/zcu104_base_proc_sys_reset_0_0_board.xdc] for cell 'zcu104_base_i/proc_sys_reset_0/U0'
Parsing XDC File [/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_proc_sys_reset_0_0/zcu104_base_proc_sys_reset_0_0.xdc] for cell 'zcu104_base_i/proc_sys_reset_0/U0'
Finished Parsing XDC File [/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_proc_sys_reset_0_0/zcu104_base_proc_sys_reset_0_0.xdc] for cell 'zcu104_base_i/proc_sys_reset_0/U0'
Parsing XDC File [/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_proc_sys_reset_1_0/zcu104_base_proc_sys_reset_1_0_board.xdc] for cell 'zcu104_base_i/proc_sys_reset_1/U0'
Finished Parsing XDC File [/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_proc_sys_reset_1_0/zcu104_base_proc_sys_reset_1_0_board.xdc] for cell 'zcu104_base_i/proc_sys_reset_1/U0'
Parsing XDC File [/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_proc_sys_reset_1_0/zcu104_base_proc_sys_reset_1_0.xdc] for cell 'zcu104_base_i/proc_sys_reset_1/U0'
Finished Parsing XDC File [/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_proc_sys_reset_1_0/zcu104_base_proc_sys_reset_1_0.xdc] for cell 'zcu104_base_i/proc_sys_reset_1/U0'
Parsing XDC File [/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_proc_sys_reset_2_0/zcu104_base_proc_sys_reset_2_0_board.xdc] for cell 'zcu104_base_i/proc_sys_reset_2/U0'
Finished Parsing XDC File [/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_proc_sys_reset_2_0/zcu104_base_proc_sys_reset_2_0_board.xdc] for cell 'zcu104_base_i/proc_sys_reset_2/U0'
Parsing XDC File [/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_proc_sys_reset_2_0/zcu104_base_proc_sys_reset_2_0.xdc] for cell 'zcu104_base_i/proc_sys_reset_2/U0'
Finished Parsing XDC File [/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_proc_sys_reset_2_0/zcu104_base_proc_sys_reset_2_0.xdc] for cell 'zcu104_base_i/proc_sys_reset_2/U0'
Parsing XDC File [/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_proc_sys_reset_3_0/zcu104_base_proc_sys_reset_3_0_board.xdc] for cell 'zcu104_base_i/proc_sys_reset_3/U0'
Finished Parsing XDC File [/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_proc_sys_reset_3_0/zcu104_base_proc_sys_reset_3_0_board.xdc] for cell 'zcu104_base_i/proc_sys_reset_3/U0'
Parsing XDC File [/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_proc_sys_reset_3_0/zcu104_base_proc_sys_reset_3_0.xdc] for cell 'zcu104_base_i/proc_sys_reset_3/U0'
Finished Parsing XDC File [/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_proc_sys_reset_3_0/zcu104_base_proc_sys_reset_3_0.xdc] for cell 'zcu104_base_i/proc_sys_reset_3/U0'
Parsing XDC File [/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_proc_sys_reset_4_0/zcu104_base_proc_sys_reset_4_0_board.xdc] for cell 'zcu104_base_i/proc_sys_reset_4/U0'
Finished Parsing XDC File [/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_proc_sys_reset_4_0/zcu104_base_proc_sys_reset_4_0_board.xdc] for cell 'zcu104_base_i/proc_sys_reset_4/U0'
Parsing XDC File [/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_proc_sys_reset_4_0/zcu104_base_proc_sys_reset_4_0.xdc] for cell 'zcu104_base_i/proc_sys_reset_4/U0'
Finished Parsing XDC File [/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_proc_sys_reset_4_0/zcu104_base_proc_sys_reset_4_0.xdc] for cell 'zcu104_base_i/proc_sys_reset_4/U0'
Parsing XDC File [/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_proc_sys_reset_5_0/zcu104_base_proc_sys_reset_5_0_board.xdc] for cell 'zcu104_base_i/proc_sys_reset_5/U0'
Finished Parsing XDC File [/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_proc_sys_reset_5_0/zcu104_base_proc_sys_reset_5_0_board.xdc] for cell 'zcu104_base_i/proc_sys_reset_5/U0'
Parsing XDC File [/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_proc_sys_reset_5_0/zcu104_base_proc_sys_reset_5_0.xdc] for cell 'zcu104_base_i/proc_sys_reset_5/U0'
Finished Parsing XDC File [/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_proc_sys_reset_5_0/zcu104_base_proc_sys_reset_5_0.xdc] for cell 'zcu104_base_i/proc_sys_reset_5/U0'
Parsing XDC File [/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_proc_sys_reset_6_0/zcu104_base_proc_sys_reset_6_0_board.xdc] for cell 'zcu104_base_i/proc_sys_reset_6/U0'
Finished Parsing XDC File [/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_proc_sys_reset_6_0/zcu104_base_proc_sys_reset_6_0_board.xdc] for cell 'zcu104_base_i/proc_sys_reset_6/U0'
Parsing XDC File [/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_proc_sys_reset_6_0/zcu104_base_proc_sys_reset_6_0.xdc] for cell 'zcu104_base_i/proc_sys_reset_6/U0'
Finished Parsing XDC File [/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_proc_sys_reset_6_0/zcu104_base_proc_sys_reset_6_0.xdc] for cell 'zcu104_base_i/proc_sys_reset_6/U0'
Parsing XDC File [/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_ps_e_0/zcu104_base_ps_e_0.xdc] for cell 'zcu104_base_i/ps_e/inst'
Finished Parsing XDC File [/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_ps_e_0/zcu104_base_ps_e_0.xdc] for cell 'zcu104_base_i/ps_e/inst'
Parsing XDC File [/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_axi_intc_0_0/zcu104_base_axi_intc_0_0_clocks.xdc] for cell 'zcu104_base_i/axi_intc_0/U0'
Finished Parsing XDC File [/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_axi_intc_0_0/zcu104_base_axi_intc_0_0_clocks.xdc] for cell 'zcu104_base_i/axi_intc_0/U0'
Parsing XDC File [/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_axi_register_slice_0_0/zcu104_base_axi_register_slice_0_0_clocks.xdc] for cell 'zcu104_base_i/axi_register_slice_0/inst'
WARNING: [Vivado 12-180] No cells matched '.*15.*_multi/.*/common.srl_fifo_0/asyncclear_.*'. [/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_axi_register_slice_0_0/zcu104_base_axi_register_slice_0_0_clocks.xdc:10]
WARNING: [Vivado 12-508] No pins matched 'get_pins -filter REF_PIN_NAME=~CLR -of_objects [get_cells -hierarchical -regexp .*15.*_multi/.*/common.srl_fifo_0/asyncclear_.*]'. [/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_axi_register_slice_0_0/zcu104_base_axi_register_slice_0_0_clocks.xdc:10]
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-7' -to list should not be empty. [/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_axi_register_slice_0_0/zcu104_base_axi_register_slice_0_0_clocks.xdc:10]
Finished Parsing XDC File [/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_axi_register_slice_0_0/zcu104_base_axi_register_slice_0_0_clocks.xdc] for cell 'zcu104_base_i/axi_register_slice_0/inst'
Parsing XDC File [/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_auto_us_0/zcu104_base_auto_us_0_clocks.xdc] for cell 'zcu104_base_i/interconnect_axifull/s00_couplers/auto_us/inst'
Finished Parsing XDC File [/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.srcs/sources_1/bd/zcu104_base/ip/zcu104_base_auto_us_0/zcu104_base_auto_us_0_clocks.xdc] for cell 'zcu104_base_i/interconnect_axifull/s00_couplers/auto_us/inst'
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3436.395 ; gain = 0.000 ; free physical = 6546 ; free virtual = 30830
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
27 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:48 ; elapsed = 00:01:18 . Memory (MB): peak = 3436.395 ; gain = 1286.227 ; free physical = 6546 ; free virtual = 30830
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xczu7ev'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu7ev'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 4 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3455.359 ; gain = 18.965 ; free physical = 6536 ; free virtual = 30821
Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 1bc874c80
Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.16 . Memory (MB): peak = 3470.359 ; gain = 15.000 ; free physical = 6534 ; free virtual = 30819
Starting Logic Optimization Task
Phase 1 Retarget
INFO: [Opt 31-138] Pushed 21 inverter(s) to 638 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 10bfa5a0a
Time (s): cpu = 00:00:00.57 ; elapsed = 00:00:00.44 . Memory (MB): peak = 3625.172 ; gain = 0.000 ; free physical = 6386 ; free virtual = 30671
INFO: [Opt 31-389] Phase Retarget created 307 cells and removed 613 cells
Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 1 inverter(s) to 1 load pin(s).
Phase 2 Constant propagation | Checksum: 19280c977
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.92 . Memory (MB): peak = 3625.172 ; gain = 0.000 ; free physical = 6386 ; free virtual = 30671
INFO: [Opt 31-389] Phase Constant propagation created 14 cells and removed 1735 cells
Phase 3 Sweep
Phase 3 Sweep | Checksum: 1622a99e6
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3625.172 ; gain = 0.000 ; free physical = 6385 ; free virtual = 30670
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 1837 cells
INFO: [Opt 31-1021] In phase Sweep, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
Phase 4 BUFG optimization
INFO: [Opt 31-1077] Phase BUFG optimization inserted 0 global clock buffer(s) for CLOCK_LOW_FANOUT.
Phase 4 BUFG optimization | Checksum: 1622a99e6
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3625.172 ; gain = 0.000 ; free physical = 6385 ; free virtual = 30670
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 5 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 5 Shift Register Optimization | Checksum: 1622a99e6
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3625.172 ; gain = 0.000 ; free physical = 6385 ; free virtual = 30670
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 6 Post Processing Netlist
Phase 6 Post Processing Netlist | Checksum: 1622a99e6
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3625.172 ; gain = 0.000 ; free physical = 6385 ; free virtual = 30670
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Opt_design Change Summary
=========================
-------------------------------------------------------------------------------------------------------------------------
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
-------------------------------------------------------------------------------------------------------------------------
| Retarget | 307 | 613 | 0 |
| Constant propagation | 14 | 1735 | 0 |
| Sweep | 0 | 1837 | 1 |
| BUFG optimization | 0 | 0 | 0 |
| Shift Register Optimization | 0 | 0 | 0 |
| Post Processing Netlist | 0 | 0 | 0 |
-------------------------------------------------------------------------------------------------------------------------
Starting Connectivity Check Task
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3625.172 ; gain = 0.000 ; free physical = 6384 ; free virtual = 30670
Ending Logic Optimization Task | Checksum: 1a0db0168
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3625.172 ; gain = 0.000 ; free physical = 6384 ; free virtual = 30670
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 1a0db0168
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3625.172 ; gain = 0.000 ; free physical = 6384 ; free virtual = 30669
Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 1a0db0168
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3625.172 ; gain = 0.000 ; free physical = 6384 ; free virtual = 30669
Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3625.172 ; gain = 0.000 ; free physical = 6384 ; free virtual = 30669
Ending Netlist Obfuscation Task | Checksum: 1a0db0168
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3625.172 ; gain = 0.000 ; free physical = 6384 ; free virtual = 30669
INFO: [Common 17-83] Releasing license: Implementation
46 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3625.172 ; gain = 188.777 ; free physical = 6384 ; free virtual = 30669
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-480] Writing timing data to binary archive.
INFO: [Common 17-1381] The checkpoint '/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.runs/impl_1/zcu104_base_wrapper_opt.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file zcu104_base_wrapper_drc_opted.rpt -pb zcu104_base_wrapper_drc_opted.pb -rpx zcu104_base_wrapper_drc_opted.rpx
Command: report_drc -file zcu104_base_wrapper_drc_opted.rpt -pb zcu104_base_wrapper_drc_opted.pb -rpx zcu104_base_wrapper_drc_opted.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 4 threads
INFO: [Coretcl 2-168] The results of DRC are in file /media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.runs/impl_1/zcu104_base_wrapper_drc_opted.rpt.
report_drc completed successfully
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xczu7ev'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu7ev'
INFO: [DRC 23-27] Running DRC with 4 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 4 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 4 CPUs
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3669.863 ; gain = 0.000 ; free physical = 6366 ; free virtual = 30653
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fbe87962
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3669.863 ; gain = 0.000 ; free physical = 6366 ; free virtual = 30653
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3669.863 ; gain = 0.000 ; free physical = 6366 ; free virtual = 30653
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 179bc4ea4
Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 4385.500 ; gain = 715.637 ; free physical = 5908 ; free virtual = 30198
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 2431b1de8
Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 4417.516 ; gain = 747.652 ; free physical = 5872 ; free virtual = 30162
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 2431b1de8
Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 4417.516 ; gain = 747.652 ; free physical = 5872 ; free virtual = 30162
Phase 1 Placer Initialization | Checksum: 2431b1de8
Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 4417.516 ; gain = 747.652 ; free physical = 5870 ; free virtual = 30160
Phase 2 Global Placement
Phase 2.1 Floorplanning
Phase 2.1.1 Partition Driven Placement
Phase 2.1.1.1 PBP: Partition Driven Placement
Phase 2.1.1.1 PBP: Partition Driven Placement | Checksum: 181d944f6
Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 4417.516 ; gain = 747.652 ; free physical = 5864 ; free virtual = 30154
Phase 2.1.1.2 PBP: Clock Region Placement
Phase 2.1.1.2 PBP: Clock Region Placement | Checksum: 16ac61cb5
Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 4417.516 ; gain = 747.652 ; free physical = 5863 ; free virtual = 30153
Phase 2.1.1.3 PBP: Compute Congestion
Phase 2.1.1.3 PBP: Compute Congestion | Checksum: 16ac61cb5
Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 4420.527 ; gain = 750.664 ; free physical = 5848 ; free virtual = 30138
Phase 2.1.1.4 PBP: UpdateTiming
Phase 2.1.1.4 PBP: UpdateTiming | Checksum: 1b6b3bb6f
Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 4420.527 ; gain = 750.664 ; free physical = 5847 ; free virtual = 30138
Phase 2.1.1.5 PBP: Add part constraints
Phase 2.1.1.5 PBP: Add part constraints | Checksum: 1b6b3bb6f
Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 4420.527 ; gain = 750.664 ; free physical = 5847 ; free virtual = 30138
Phase 2.1.1 Partition Driven Placement | Checksum: 1b6b3bb6f
Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 4420.527 ; gain = 750.664 ; free physical = 5848 ; free virtual = 30138
Phase 2.1 Floorplanning | Checksum: 1b6b3bb6f
Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 4420.527 ; gain = 750.664 ; free physical = 5848 ; free virtual = 30138
Phase 2.2 Global Placement Core
Phase 2.2.1 Physical Synthesis In Placer
INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 26 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
INFO: [Physopt 32-775] End 1 Pass. Optimized 12 nets or cells. Created 0 new cell, deleted 12 existing cells and moved 0 existing cell
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed.
INFO: [Physopt 32-949] No candidate nets found for HD net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4423.539 ; gain = 0.000 ; free physical = 5848 ; free virtual = 30138
Summary of Physical Synthesis Optimizations
============================================
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| LUT Combining | 0 | 12 | 12 | 0 | 1 | 00:00:00 |
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Total | 0 | 12 | 12 | 0 | 3 | 00:00:00 |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
Phase 2.2.1 Physical Synthesis In Placer | Checksum: 1de2e305c
Time (s): cpu = 00:00:24 ; elapsed = 00:00:22 . Memory (MB): peak = 4423.539 ; gain = 753.676 ; free physical = 5848 ; free virtual = 30138
Phase 2.2 Global Placement Core | Checksum: 1549ac099
Time (s): cpu = 00:00:26 ; elapsed = 00:00:23 . Memory (MB): peak = 4423.539 ; gain = 753.676 ; free physical = 5842 ; free virtual = 30133
Phase 2 Global Placement | Checksum: 1549ac099
Time (s): cpu = 00:00:26 ; elapsed = 00:00:23 . Memory (MB): peak = 4423.539 ; gain = 753.676 ; free physical = 5845 ; free virtual = 30135
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 1a194812c
Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 4423.539 ; gain = 753.676 ; free physical = 5817 ; free virtual = 30112
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 171791579
Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 4423.539 ; gain = 753.676 ; free physical = 5809 ; free virtual = 30103
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 942af1bc
Time (s): cpu = 00:00:27 ; elapsed = 00:00:24 . Memory (MB): peak = 4423.539 ; gain = 753.676 ; free physical = 5807 ; free virtual = 30102
Phase 3.4 Small Shape DP
Phase 3.4.1 Small Shape Clustering
Phase 3.4.1 Small Shape Clustering | Checksum: ca76b029
Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 4423.539 ; gain = 753.676 ; free physical = 5795 ; free virtual = 30092
Phase 3.4.2 Flow Legalize Slice Clusters
Phase 3.4.2 Flow Legalize Slice Clusters | Checksum: b3d86b8d
Time (s): cpu = 00:00:28 ; elapsed = 00:00:26 . Memory (MB): peak = 4423.539 ; gain = 753.676 ; free physical = 5791 ; free virtual = 30087
Phase 3.4.3 Slice Area Swap
Phase 3.4.3 Slice Area Swap | Checksum: 11798cd89
Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 4423.539 ; gain = 753.676 ; free physical = 5767 ; free virtual = 30071
Phase 3.4 Small Shape DP | Checksum: 1b28d128e
Time (s): cpu = 00:00:30 ; elapsed = 00:00:27 . Memory (MB): peak = 4423.539 ; gain = 753.676 ; free physical = 5793 ; free virtual = 30093
Phase 3.5 Re-assign LUT pins
Phase 3.5 Re-assign LUT pins | Checksum: 1b42d7136
Time (s): cpu = 00:00:30 ; elapsed = 00:00:27 . Memory (MB): peak = 4423.539 ; gain = 753.676 ; free physical = 5793 ; free virtual = 30093
Phase 3.6 Pipeline Register Optimization
Phase 3.6 Pipeline Register Optimization | Checksum: 15f213a8c
Time (s): cpu = 00:00:30 ; elapsed = 00:00:27 . Memory (MB): peak = 4423.539 ; gain = 753.676 ; free physical = 5793 ; free virtual = 30093
Phase 3 Detail Placement | Checksum: 15f213a8c
Time (s): cpu = 00:00:30 ; elapsed = 00:00:27 . Memory (MB): peak = 4423.539 ; gain = 753.676 ; free physical = 5793 ; free virtual = 30093
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 1505948d4
Phase 4.1.1.1 BUFG Insertion
Starting Physical Synthesis Task
Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 4 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=1.027 | TNS=0.000 |
Phase 1 Physical Synthesis Initialization | Checksum: 17f32d393
Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.06 . Memory (MB): peak = 4423.539 ; gain = 0.000 ; free physical = 5790 ; free virtual = 30090
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0.
Ending Physical Synthesis Task | Checksum: 1cc27f18b
Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.07 . Memory (MB): peak = 4423.539 ; gain = 0.000 ; free physical = 5790 ; free virtual = 30090
Phase 4.1.1.1 BUFG Insertion | Checksum: 1505948d4
Time (s): cpu = 00:00:31 ; elapsed = 00:00:28 . Memory (MB): peak = 4423.539 ; gain = 753.676 ; free physical = 5791 ; free virtual = 30091
INFO: [Place 30-746] Post Placement Timing Summary WNS=1.027. For the most accurate timing information please run report_timing.
Phase 4.1.1 Post Placement Optimization | Checksum: 1a5a73527
Time (s): cpu = 00:00:31 ; elapsed = 00:00:28 . Memory (MB): peak = 4423.539 ; gain = 753.676 ; free physical = 5791 ; free virtual = 30091
Phase 4.1 Post Commit Optimization | Checksum: 1a5a73527
Time (s): cpu = 00:00:31 ; elapsed = 00:00:28 . Memory (MB): peak = 4423.539 ; gain = 753.676 ; free physical = 5791 ; free virtual = 30091
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 1a5a73527
Time (s): cpu = 00:00:32 ; elapsed = 00:00:29 . Memory (MB): peak = 4423.539 ; gain = 753.676 ; free physical = 5802 ; free virtual = 30102
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4423.539 ; gain = 0.000 ; free physical = 5777 ; free virtual = 30077
Phase 4.3 Placer Reporting
Phase 4.3 Placer Reporting | Checksum: 1b0962344
Time (s): cpu = 00:00:37 ; elapsed = 00:00:34 . Memory (MB): peak = 4423.539 ; gain = 753.676 ; free physical = 5777 ; free virtual = 30077
Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4423.539 ; gain = 0.000 ; free physical = 5777 ; free virtual = 30077
Phase 4.4 Final Placement Cleanup | Checksum: 1b62cf94c
Time (s): cpu = 00:00:37 ; elapsed = 00:00:34 . Memory (MB): peak = 4423.539 ; gain = 753.676 ; free physical = 5777 ; free virtual = 30077
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1b62cf94c
Time (s): cpu = 00:00:37 ; elapsed = 00:00:34 . Memory (MB): peak = 4423.539 ; gain = 753.676 ; free physical = 5777 ; free virtual = 30077
Ending Placer Task | Checksum: 137bb2daa
Time (s): cpu = 00:00:37 ; elapsed = 00:00:34 . Memory (MB): peak = 4423.539 ; gain = 753.676 ; free physical = 5778 ; free virtual = 30078
INFO: [Common 17-83] Releasing license: Implementation
80 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:40 ; elapsed = 00:00:37 . Memory (MB): peak = 4423.539 ; gain = 753.676 ; free physical = 5844 ; free virtual = 30144
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.10 . Memory (MB): peak = 4423.539 ; gain = 0.000 ; free physical = 5831 ; free virtual = 30137
INFO: [Common 17-1381] The checkpoint '/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.runs/impl_1/zcu104_base_wrapper_placed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_io -file zcu104_base_wrapper_io_placed.rpt
report_io: Time (s): cpu = 00:00:00.22 ; elapsed = 00:00:00.32 . Memory (MB): peak = 4423.539 ; gain = 0.000 ; free physical = 5819 ; free virtual = 30121
INFO: [runtcl-4] Executing : report_utilization -file zcu104_base_wrapper_utilization_placed.rpt -pb zcu104_base_wrapper_utilization_placed.pb
INFO: [runtcl-4] Executing : report_control_sets -verbose -file zcu104_base_wrapper_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.17 . Memory (MB): peak = 4423.539 ; gain = 0.000 ; free physical = 5845 ; free virtual = 30148
Command: phys_opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xczu7ev'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu7ev'
INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations.
INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified.
INFO: [Common 17-83] Releasing license: Implementation
89 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered.
phys_opt_design completed successfully
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.35 ; elapsed = 00:00:00.10 . Memory (MB): peak = 4423.539 ; gain = 0.000 ; free physical = 5819 ; free virtual = 30127
INFO: [Common 17-1381] The checkpoint '/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.runs/impl_1/zcu104_base_wrapper_physopt.dcp' has been generated.
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xczu7ev'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu7ev'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 4 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 4 CPUs
Checksum: PlaceDB: 7618fd47 ConstDB: 0 ShapeSum: b6b34246 RouteDB: aeeee1d
Phase 1 Build RT Design
Nodegraph reading from file. Time (s): cpu = 00:00:00.99 ; elapsed = 00:00:00.92 . Memory (MB): peak = 4423.539 ; gain = 0.000 ; free physical = 5624 ; free virtual = 29935
Phase 1 Build RT Design | Checksum: b6519654
Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 4423.539 ; gain = 0.000 ; free physical = 5657 ; free virtual = 29962
Post Restoration Checksum: NetGraph: 64006a9c NumContArr: c9abfbc9 Constraints: 9a01e8af Timing: 0
Phase 2 Router Initialization
Phase 2.1 Create Timer
Phase 2.1 Create Timer | Checksum: 1c7ae4f14
Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 4423.539 ; gain = 0.000 ; free physical = 5657 ; free virtual = 29963
Phase 2.2 Fix Topology Constraints
Phase 2.2 Fix Topology Constraints | Checksum: 1c7ae4f14
Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 4423.539 ; gain = 0.000 ; free physical = 5626 ; free virtual = 29932
Phase 2.3 Pre Route Cleanup
Phase 2.3 Pre Route Cleanup | Checksum: 1c7ae4f14
Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 4423.539 ; gain = 0.000 ; free physical = 5625 ; free virtual = 29931
Phase 2.4 Global Clock Net Routing
Number of Nodes with overlaps = 0
Phase 2.4 Global Clock Net Routing | Checksum: 1610ac83e
Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 4431.852 ; gain = 8.312 ; free physical = 5606 ; free virtual = 29912
Phase 2.5 Update Timing
Phase 2.5 Update Timing | Checksum: 18720f649
Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 4431.852 ; gain = 8.312 ; free physical = 5612 ; free virtual = 29918
INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.055 | TNS=0.000 | WHS=-0.014 | THS=-0.061 |
Phase 2 Router Initialization | Checksum: 1f7ba0e60
Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 4431.852 ; gain = 8.312 ; free physical = 5609 ; free virtual = 29914
Router Utilization Summary
Global Vertical Routing Utilization = 0 %
Global Horizontal Routing Utilization = 0 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 1094
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 910
Number of Partially Routed Nets = 184
Number of Node Overlaps = 0
Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: 2d7d55361
Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 4444.180 ; gain = 20.641 ; free physical = 5588 ; free virtual = 29894
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 151
Number of Nodes with overlaps = 4
Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.918 | TNS=0.000 | WHS=0.027 | THS=0.000 |
Phase 4.1 Global Iteration 0 | Checksum: 1a55e98c6
Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 4444.180 ; gain = 20.641 ; free physical = 5588 ; free virtual = 29894
Phase 4.2 Additional Iteration for Hold
Phase 4.2 Additional Iteration for Hold | Checksum: 1f2a49e39
Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 4444.180 ; gain = 20.641 ; free physical = 5588 ; free virtual = 29894
Phase 4 Rip-up And Reroute | Checksum: 1f2a49e39
Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 4444.180 ; gain = 20.641 ; free physical = 5588 ; free virtual = 29894
Phase 5 Delay and Skew Optimization
Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: 1f2a49e39
Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 4444.180 ; gain = 20.641 ; free physical = 5592 ; free virtual = 29897
Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 1f2a49e39
Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 4444.180 ; gain = 20.641 ; free physical = 5592 ; free virtual = 29897
Phase 5 Delay and Skew Optimization | Checksum: 1f2a49e39
Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 4444.180 ; gain = 20.641 ; free physical = 5592 ; free virtual = 29897
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 1efee2adb
Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 4444.180 ; gain = 20.641 ; free physical = 5594 ; free virtual = 29900
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.918 | TNS=0.000 | WHS=0.027 | THS=0.000 |
Phase 6.1 Hold Fix Iter | Checksum: 205ac9f24
Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 4444.180 ; gain = 20.641 ; free physical = 5594 ; free virtual = 29900
Phase 6 Post Hold Fix | Checksum: 205ac9f24
Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 4444.180 ; gain = 20.641 ; free physical = 5594 ; free virtual = 29900
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 0.0723249 %
Global Horizontal Routing Utilization = 0.0618382 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Phase 7 Route finalize | Checksum: 1b5a130a1
Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 4444.180 ; gain = 20.641 ; free physical = 5591 ; free virtual = 29897
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 1b5a130a1
Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 4444.180 ; gain = 20.641 ; free physical = 5590 ; free virtual = 29896
Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 1b5a130a1
Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 4444.180 ; gain = 20.641 ; free physical = 5590 ; free virtual = 29896
Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=0.918 | TNS=0.000 | WHS=0.027 | THS=0.000 |
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 1b5a130a1
Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 4444.180 ; gain = 20.641 ; free physical = 5593 ; free virtual = 29899
INFO: [Route 35-16] Router Completed Successfully
Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 4444.180 ; gain = 20.641 ; free physical = 5634 ; free virtual = 29940
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
103 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:11 . Memory (MB): peak = 4444.180 ; gain = 20.641 ; free physical = 5634 ; free virtual = 29940
INFO: [Common 17-600] The following parameters have non-default value.
general.maxThreads
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.35 ; elapsed = 00:00:00.10 . Memory (MB): peak = 4452.184 ; gain = 0.000 ; free physical = 5618 ; free virtual = 29930
INFO: [Common 17-1381] The checkpoint '/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.runs/impl_1/zcu104_base_wrapper_routed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file zcu104_base_wrapper_drc_routed.rpt -pb zcu104_base_wrapper_drc_routed.pb -rpx zcu104_base_wrapper_drc_routed.rpx
Command: report_drc -file zcu104_base_wrapper_drc_routed.rpt -pb zcu104_base_wrapper_drc_routed.pb -rpx zcu104_base_wrapper_drc_routed.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 4 threads
INFO: [Coretcl 2-168] The results of DRC are in file /media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.runs/impl_1/zcu104_base_wrapper_drc_routed.rpt.
report_drc completed successfully
INFO: [runtcl-4] Executing : report_methodology -file zcu104_base_wrapper_methodology_drc_routed.rpt -pb zcu104_base_wrapper_methodology_drc_routed.pb -rpx zcu104_base_wrapper_methodology_drc_routed.rpx
Command: report_methodology -file zcu104_base_wrapper_methodology_drc_routed.rpt -pb zcu104_base_wrapper_methodology_drc_routed.pb -rpx zcu104_base_wrapper_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 4 threads
INFO: [Coretcl 2-1520] The results of Report Methodology are in file /media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.runs/impl_1/zcu104_base_wrapper_methodology_drc_routed.rpt.
report_methodology completed successfully
INFO: [runtcl-4] Executing : report_power -file zcu104_base_wrapper_power_routed.rpt -pb zcu104_base_wrapper_power_summary_routed.pb -rpx zcu104_base_wrapper_power_routed.rpx
Command: report_power -file zcu104_base_wrapper_power_routed.rpt -pb zcu104_base_wrapper_power_summary_routed.pb -rpx zcu104_base_wrapper_power_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
116 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
INFO: [runtcl-4] Executing : report_route_status -file zcu104_base_wrapper_route_status.rpt -pb zcu104_base_wrapper_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file zcu104_base_wrapper_timing_summary_routed.rpt -pb zcu104_base_wrapper_timing_summary_routed.pb -rpx zcu104_base_wrapper_timing_summary_routed.rpx -warn_on_violation
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Temperature grade: E, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
INFO: [runtcl-4] Executing : report_incremental_reuse -file zcu104_base_wrapper_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
INFO: [runtcl-4] Executing : report_clock_utilization -file zcu104_base_wrapper_clock_utilization_routed.rpt
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file zcu104_base_wrapper_bus_skew_routed.rpt -pb zcu104_base_wrapper_bus_skew_routed.pb -rpx zcu104_base_wrapper_bus_skew_routed.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Temperature grade: E, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
Command: write_bitstream -force zcu104_base_wrapper.bit
Attempting to get a license for feature 'Implementation' and/or device 'xczu7ev'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu7ev'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 4 threads
INFO: [Vivado 12-3199] DRC finished with 0 Errors
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 4 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./zcu104_base_wrapper.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-186] '/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/zcu104_base/zcu104_base.runs/impl_1/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Mon Jul 20 21:11:32 2020. For additional details about this file, please refer to the WebTalk help file at /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vivado/2020.1/doc/webtalk_introduction.html.
INFO: [Common 17-83] Releasing license: Implementation
136 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 4621.727 ; gain = 153.535 ; free physical = 5564 ; free virtual = 29896
INFO: [Common 17-206] Exiting Vivado at Mon Jul 20 21:11:32 2020...
[Mon Jul 20 21:11:37 2020] impl_1 finished
wait_on_run: Time (s): cpu = 00:21:36 ; elapsed = 00:14:10 . Memory (MB): peak = 3426.617 ; gain = 0.000 ; free physical = 8482 ; free virtual = 32812
WARNING: [Vivado_Tcl 4-1264] 'write_hwdef' with HDF extension is deprecated, please use 'write_hw_platform'
INFO: [Vivado 12-4895] Creating Hardware Platform: ./xilinx_zcu104_base_202010_1.xsa ...
INFO: [Hsi 55-2053] elapsed time for repository (/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vivado/2020.1/data/embeddedsw) loading 1 seconds
INFO: [Project 1-1042] Successfully generated hpfm file
INFO: [Vivado 12-4896] Successfully created Hardware Platform: /media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado/xilinx_zcu104_base_202010_1.xsa
write_hw_platform: Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 3426.617 ; gain = 0.000 ; free physical = 8416 ; free virtual = 32782
INFO: [Vivado 12-6074] Validating Hardware Platform: './xilinx_zcu104_base_202010_1.xsa'
INFO: [Vivado 12-8115] Found XML metadata file: xsa.xml
INFO: [Vivado 12-6078] Validating platform properties...
INFO: [Vivado 12-6079] Validating unified platform...
INFO: [Vivado 12-6073] Validating 'pre_synth' platform state...
INFO: [Vivado 12-6077] Validating platform files...
INFO: [Vivado 12-6067] Found file 'xilinx_zcu104_base_202010_1.bit' of type 'FULL_BIT' in the Hardware Platform.
INFO: [Vivado 12-6067] Found file 'xilinx_zcu104_base_202010_1.hpfm' of type 'HPFM' in the Hardware Platform.
INFO: [Vivado 12-6067] Found file 'prj/rebuild.tcl' of type 'REBUILD_TCL' in the Hardware Platform.
INFO: [Vivado 12-6066] Finished running validate_dsa for file: './xilinx_zcu104_base_202010_1.xsa'
INFO: [Common 17-206] Exiting Vivado at Mon Jul 20 21:11:51 2020...
make[1]: ディレクトリ '/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado' から出ます
make -C petalinux all XSA_DIR=/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado PLATFORM=xilinx_zcu104_base_202010_1
make[1]: ディレクトリ '/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/petalinux' に入ります
petalinux-config --get-hw-description=/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/vivado --silentconfig
INFO: sourcing build tools
INFO: Getting hardware description...
INFO: Rename xilinx_zcu104_base_202010_1.xsa to system.xsa
[INFO] generating Kconfig for project
[INFO] silentconfig project
[INFO] extracting yocto SDK to components/yocto
[INFO] sourcing build environment
[INFO] generating kconfig for Rootfs
[INFO] silentconfig rootfs
[INFO] generating plnxtool conf
[INFO] generating user layers
[INFO] generating workspace directory
petalinux-config -c xrt --silentconfig
INFO: sourcing build tools
[INFO] silentconfig project
[INFO] sourcing build environment
[INFO] generating kconfig for Rootfs
[INFO] silentconfig rootfs
[INFO] generating plnxtool conf
[INFO] generating user layers
[INFO] generating workspace directory
[INFO] configuring: xrt
[INFO] devtool modify xrt
NOTE: Starting bitbake server...
NOTE: Reconnecting to bitbake server...
NOTE: Retrying server connection (#1)...
NOTE: Reconnecting to bitbake server...
NOTE: Previous bitbake instance shutting down?, waiting to retry...
NOTE: Retrying server connection (#2)...
Parsing recipes: 100% |##########################################| Time: 0:02:12
Parsing of 2961 .bb files complete (0 cached, 2961 parsed). 4230 targets, 168 skipped, 0 masked, 0 errors.
INFO: SRC_URI contains some conditional appends/prepends - will create branches to represent these
NOTE: Resolving any missing task queue dependencies
NOTE: Fetching uninative binary shim from file:///media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/petalinux/components/yocto/downloads/uninative/9498d8bba047499999a7310ac2576d0796461184965351a56f6d32c888a1f216/x86_64-nativesdk-libc.tar.xz;sha256sum=9498d8bba047499999a7310ac2576d0796461184965351a56f6d32c888a1f216
Initialising tasks: 100% |#######################################| Time: 0:00:00
Sstate summary: Wanted 0 Found 0 Missed 0 Current 0 (0% match, 0% complete)
NOTE: No setscene tasks
NOTE: Executing Tasks
NOTE: Tasks Summary: Attempted 3 tasks of which 0 didn't need to be rerun and all succeeded.
INFO: Source tree extracted to /media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/petalinux/components/yocto/workspace/sources/xrt
WARNING: SRC_URI is conditionally overridden in this recipe, thus several devtool-override-* branches have been created, one for each override that makes changes to SRC_URI. It is recommended that you make changes to the devtool branch first, then checkout and rebase each devtool-override-* branch and update any unique patches there (duplicates on those branches will be ignored by devtool finish/update-recipe)
INFO: Recipe xrt now set up to build from /media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/petalinux/components/yocto/workspace/sources/xrt/src
[INFO] devtool configure xrt
NOTE: Starting bitbake server...
NOTE: Reconnecting to bitbake server...
NOTE: Retrying server connection (#1)...
NOTE: Reconnecting to bitbake server...
NOTE: Previous bitbake instance shutting down?, waiting to retry...
NOTE: Retrying server connection (#2)...
Loading cache: 100% |############################################| Time: 0:00:00
Loaded 4229 entries from dependency cache.
Parsing recipes: 100% |##########################################| Time: 0:00:04
Parsing of 2961 .bb files complete (2959 cached, 2 parsed). 4230 targets, 168 skipped, 0 masked, 0 errors.
Loading cache: 100% |############################################| Time: 0:00:01
Loaded 4228 entries from dependency cache.
Parsing recipes: 100% |##########################################| Time: 0:00:04
Parsing of 2961 .bb files complete (2959 cached, 2 parsed). 4230 targets, 168 skipped, 0 masked, 0 errors.
NOTE: Resolving any missing task queue dependencies
Initialising tasks: 100% |#######################################| Time: 0:00:01
Checking sstate mirror object availability: 100% |###############| Time: 0:00:00
Sstate summary: Wanted 93 Found 93 Missed 0 Current 0 (100% match, 0% complete)
NOTE: Executing Tasks
NOTE: Setscene tasks completed
NOTE: Tasks Summary: Attempted 758 tasks of which 755 didn't need to be rerun and all succeeded.
[INFO] successfully configured xrt
petalinux-config -c zocl --silentconfig
INFO: sourcing build tools
[INFO] silentconfig project
[INFO] sourcing build environment
[INFO] generating kconfig for Rootfs
[INFO] silentconfig rootfs
[INFO] generating plnxtool conf
[INFO] generating user layers
[INFO] generating workspace directory
[INFO] configuring: zocl
[INFO] devtool modify zocl
NOTE: Starting bitbake server...
NOTE: Reconnecting to bitbake server...
NOTE: Retrying server connection (#1)...
NOTE: Reconnecting to bitbake server...
NOTE: Previous bitbake instance shutting down?, waiting to retry...
NOTE: Retrying server connection (#2)...
Loading cache: 100% |############################################| Time: 0:00:00
Loaded 4228 entries from dependency cache.
Parsing recipes: 100% |##########################################| Time: 0:00:04
Parsing of 2961 .bb files complete (2959 cached, 2 parsed). 4230 targets, 168 skipped, 0 masked, 0 errors.
INFO: SRC_URI contains some conditional appends/prepends - will create branches to represent these
NOTE: Resolving any missing task queue dependencies
Initialising tasks: 100% |#######################################| Time: 0:00:00
Sstate summary: Wanted 0 Found 0 Missed 0 Current 0 (0% match, 0% complete)
NOTE: No setscene tasks
NOTE: Executing Tasks
NOTE: Tasks Summary: Attempted 3 tasks of which 0 didn't need to be rerun and all succeeded.
INFO: Source tree extracted to /media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/petalinux/components/yocto/workspace/sources/zocl
WARNING: SRC_URI is conditionally overridden in this recipe, thus several devtool-override-* branches have been created, one for each override that makes changes to SRC_URI. It is recommended that you make changes to the devtool branch first, then checkout and rebase each devtool-override-* branch and update any unique patches there (duplicates on those branches will be ignored by devtool finish/update-recipe)
INFO: Using source tree as build directory since that would be the default for this recipe
INFO: Recipe zocl now set up to build from /media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/petalinux/components/yocto/workspace/sources/zocl/src/runtime_src/core/edge/drm/zocl
[INFO] devtool configure zocl
NOTE: Starting bitbake server...
NOTE: Reconnecting to bitbake server...
NOTE: Retrying server connection (#1)...
NOTE: Reconnecting to bitbake server...
NOTE: Previous bitbake instance shutting down?, waiting to retry...
NOTE: Retrying server connection (#2)...
Loading cache: 100% |############################################| Time: 0:00:00
Loaded 4228 entries from dependency cache.
Parsing recipes: 100% |##########################################| Time: 0:00:04
Parsing of 2961 .bb files complete (2958 cached, 3 parsed). 4230 targets, 168 skipped, 0 masked, 0 errors.
Loading cache: 100% |############################################| Time: 0:00:01
Loaded 4227 entries from dependency cache.
Parsing recipes: 100% |##########################################| Time: 0:00:04
Parsing of 2961 .bb files complete (2958 cached, 3 parsed). 4230 targets, 168 skipped, 0 masked, 0 errors.
NOTE: Resolving any missing task queue dependencies
Initialising tasks: 100% |#######################################| Time: 0:00:00
Checking sstate mirror object availability: 100% |###############| Time: 0:00:00
Sstate summary: Wanted 26 Found 25 Missed 1 Current 26 (96% match, 98% complete)
NOTE: Executing Tasks
NOTE: Setscene tasks completed
NOTE: Tasks Summary: Attempted 417 tasks of which 394 didn't need to be rerun and all succeeded.
[INFO] successfully configured zocl
petalinux-config -c kernel --silentconfig
INFO: sourcing build tools
[INFO] silentconfig project
[INFO] sourcing build environment
[INFO] generating kconfig for Rootfs
[INFO] silentconfig rootfs
[INFO] generating plnxtool conf
[INFO] generating user layers
[INFO] generating workspace directory
[INFO] configuring: kernel
[INFO] devtool modify linux-xlnx
NOTE: Starting bitbake server...
NOTE: Reconnecting to bitbake server...
NOTE: Retrying server connection (#1)...
NOTE: Reconnecting to bitbake server...
NOTE: Previous bitbake instance shutting down?, waiting to retry...
NOTE: Retrying server connection (#2)...
Loading cache: 100% |############################################| Time: 0:00:01
Loaded 4227 entries from dependency cache.
Parsing recipes: 100% |##########################################| Time: 0:00:04
Parsing of 2961 .bb files complete (2958 cached, 3 parsed). 4230 targets, 168 skipped, 0 masked, 0 errors.
NOTE: Resolving any missing task queue dependencies
Initialising tasks: 100% |#######################################| Time: 0:00:00
Checking sstate mirror object availability: 100% |###############| Time: 0:00:00
Sstate summary: Wanted 8 Found 8 Missed 0 Current 42 (100% match, 100% complete)
NOTE: Executing Tasks
NOTE: Setscene tasks completed
NOTE: Tasks Summary: Attempted 398 tasks of which 398 didn't need to be rerun and all succeeded.
INFO: Copying kernel config to workspace
INFO: Recipe linux-xlnx now set up to build from /media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/petalinux/components/yocto/workspace/sources/linux-xlnx
[INFO] devtool configure linux-xlnx
NOTE: Starting bitbake server...
NOTE: Reconnecting to bitbake server...
NOTE: Retrying server connection (#1)...
NOTE: Reconnecting to bitbake server...
NOTE: Previous bitbake instance shutting down?, waiting to retry...
NOTE: Retrying server connection (#2)...
Loading cache: 100% |############################################| Time: 0:00:00
Loaded 4227 entries from dependency cache.
Parsing recipes: 100% |##########################################| Time: 0:00:04
Parsing of 2961 .bb files complete (2957 cached, 4 parsed). 4230 targets, 168 skipped, 0 masked, 0 errors.
Loading cache: 100% |############################################| Time: 0:00:01
Loaded 4226 entries from dependency cache.
Parsing recipes: 100% |##########################################| Time: 0:00:04
Parsing of 2961 .bb files complete (2957 cached, 4 parsed). 4230 targets, 168 skipped, 0 masked, 0 errors.
NOTE: Resolving any missing task queue dependencies
Initialising tasks: 100% |#######################################| Time: 0:00:01
Checking sstate mirror object availability: 100% |###############| Time: 0:00:00
Sstate summary: Wanted 8 Found 8 Missed 0 Current 42 (100% match, 100% complete)
NOTE: Executing Tasks
NOTE: Setscene tasks completed
NOTE: Tasks Summary: Attempted 395 tasks of which 388 didn't need to be rerun and all succeeded.
[INFO] successfully configured kernel
petalinux-config -c rootfs --silentconfig
INFO: sourcing build tools
[INFO] silentconfig project
[INFO] generating kconfig for Rootfs
[INFO] silentconfig rootfs
[INFO] generating plnxtool conf
[INFO] successfully configured rootfs
petalinux-build
INFO: sourcing build tools
[INFO] building project
[INFO] sourcing build environment
[INFO] generating user layers
[INFO] generating workspace directory
INFO: bitbake petalinux-image-minimal
Loading cache: 100% |############################################| Time: 0:00:00
Loaded 4226 entries from dependency cache.
Parsing recipes: 100% |##########################################| Time: 0:00:04
Parsing of 2961 .bb files complete (2957 cached, 4 parsed). 4230 targets, 168 skipped, 0 masked, 0 errors.
NOTE: Resolving any missing task queue dependencies
Initialising tasks: 100% |#######################################| Time: 0:00:10
Checking sstate mirror object availability: 100% |###############| Time: 0:00:58
Sstate summary: Wanted 2460 Found 1960 Missed 500 Current 82 (79% match, 80% complete)
NOTE: Executing Tasks
NOTE: Setscene tasks completed
NOTE: linux-xlnx: compiling from external source tree /media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/petalinux/components/yocto/workspace/sources/linux-xlnx
WARNING: dnndkdeploy-1.0-r0 do_fetch: Failed to fetch URL file:///proj/yocto/dnndk/zynqmp_latest, attempting MIRRORS if available
ERROR: dnndkdeploy-1.0-r0 do_fetch: Fetcher failure: Unable to find file file:///proj/yocto/dnndk/zynqmp_latest anywhere. The paths that were searched were:
/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/petalinux/components/yocto/layers/meta-vitis-ai/recipes-support/dnndk/dnndkdeploy-1.0/petalinux
/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/petalinux/components/yocto/layers/meta-vitis-ai/recipes-support/dnndk/dnndkdeploy/petalinux
/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/petalinux/components/yocto/layers/meta-vitis-ai/recipes-support/dnndk/files/petalinux
/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/petalinux/components/yocto/layers/meta-vitis-ai/recipes-support/dnndk/dnndkdeploy-1.0/zcu104-zynqmp
/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/petalinux/components/yocto/layers/meta-vitis-ai/recipes-support/dnndk/dnndkdeploy/zcu104-zynqmp
/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/petalinux/components/yocto/layers/meta-vitis-ai/recipes-support/dnndk/files/zcu104-zynqmp
/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/petalinux/components/yocto/layers/meta-vitis-ai/recipes-support/dnndk/dnndkdeploy-1.0/armv8a
/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/petalinux/components/yocto/layers/meta-vitis-ai/recipes-support/dnndk/dnndkdeploy/armv8a
/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/petalinux/components/yocto/layers/meta-vitis-ai/recipes-support/dnndk/files/armv8a
/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/petalinux/components/yocto/layers/meta-vitis-ai/recipes-support/dnndk/dnndkdeploy-1.0/aarch64
/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/petalinux/components/yocto/layers/meta-vitis-ai/recipes-support/dnndk/dnndkdeploy/aarch64
/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/petalinux/components/yocto/layers/meta-vitis-ai/recipes-support/dnndk/files/aarch64
/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/petalinux/components/yocto/layers/meta-vitis-ai/recipes-support/dnndk/dnndkdeploy-1.0/cortexa72-cortexa53
/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/petalinux/components/yocto/layers/meta-vitis-ai/recipes-support/dnndk/dnndkdeploy/cortexa72-cortexa53
/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/petalinux/components/yocto/layers/meta-vitis-ai/recipes-support/dnndk/files/cortexa72-cortexa53
/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/petalinux/components/yocto/layers/meta-vitis-ai/recipes-support/dnndk/dnndkdeploy-1.0/zynqmp
/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/petalinux/components/yocto/layers/meta-vitis-ai/recipes-support/dnndk/dnndkdeploy/zynqmp
/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/petalinux/components/yocto/layers/meta-vitis-ai/recipes-support/dnndk/files/zynqmp
/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/petalinux/components/yocto/layers/meta-vitis-ai/recipes-support/dnndk/dnndkdeploy-1.0/zynqmpev
/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/petalinux/components/yocto/layers/meta-vitis-ai/recipes-support/dnndk/dnndkdeploy/zynqmpev
/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/petalinux/components/yocto/layers/meta-vitis-ai/recipes-support/dnndk/files/zynqmpev
/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/petalinux/components/yocto/layers/meta-vitis-ai/recipes-support/dnndk/dnndkdeploy-1.0/vcu
/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/petalinux/components/yocto/layers/meta-vitis-ai/recipes-support/dnndk/dnndkdeploy/vcu
/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/petalinux/components/yocto/layers/meta-vitis-ai/recipes-support/dnndk/files/vcu
/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/petalinux/components/yocto/layers/meta-vitis-ai/recipes-support/dnndk/dnndkdeploy-1.0/mali400
/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/petalinux/components/yocto/layers/meta-vitis-ai/recipes-support/dnndk/dnndkdeploy/mali400
/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/petalinux/components/yocto/layers/meta-vitis-ai/recipes-support/dnndk/files/mali400
/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/petalinux/components/yocto/layers/meta-vitis-ai/recipes-support/dnndk/dnndkdeploy-1.0/aarch64
/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/petalinux/components/yocto/layers/meta-vitis-ai/recipes-support/dnndk/dnndkdeploy/aarch64
/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/petalinux/components/yocto/layers/meta-vitis-ai/recipes-support/dnndk/files/aarch64
/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/petalinux/components/yocto/layers/meta-vitis-ai/recipes-support/dnndk/dnndkdeploy-1.0/
/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/petalinux/components/yocto/layers/meta-vitis-ai/recipes-support/dnndk/dnndkdeploy/
/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/petalinux/components/yocto/layers/meta-vitis-ai/recipes-support/dnndk/files/
/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/petalinux/build/downloads
ERROR: dnndkdeploy-1.0-r0 do_fetch: Fetcher failure for URL: 'file:///proj/yocto/dnndk/zynqmp_latest'. Unable to fetch URL from any source.
ERROR: Logfile of failure stored in: /tmp/xilinx-zcu104-2020.1-2020.04.27-21.01.50-0i2/work/zynqmp-xilinx-linux/dnndkdeploy/1.0-r0/temp/log.do_fetch.31711
ERROR: Task (/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/petalinux/components/yocto/layers/meta-vitis-ai/recipes-support/dnndk/dnndkdeploy.bb:do_fetch) failed with exit code '1'
NOTE: Tasks Summary: Attempted 6642 tasks of which 5406 didn't need to be rerun and 1 failed.
Summary: 1 task failed:
/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/petalinux/components/yocto/layers/meta-vitis-ai/recipes-support/dnndk/dnndkdeploy.bb:do_fetch
Summary: There was 1 WARNING message shown.
Summary: There were 2 ERROR messages shown, returning a non-zero exit code.
ERROR: Failed to build project
Makefile:25: recipe for target 'linux' failed
make[1]: *** [linux] Error 255
make[1]: ディレクトリ '/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base/petalinux' から出ます
Makefile:21: recipe for target 'petalinux_proj' failed
make: *** [petalinux_proj] Error 2
masaaki@masaaki-H110M4-M01:/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Embedded_Platform_Source/Xilinx_Official_Platforms/zcu104_base$
ということだ。[Pre-Synthesis Control Flow] ビューは、関数内のホット スポット (演算負荷の高い制御構造) を見つけたり、結果を改善または最適化するためにプラグマまたは指示子を適用するのに便利です。
// square.cpp
// 2019/12/11 by marsee
//
// Vitis_Accel_Examples/cpp_kernels/dataflow_stream/src/adder.cpp を参考にしています
// https://github.com/Xilinx/Vitis_Accel_Examples/blob/master/cpp_kernels/dataflow_stream/src/adder.cpp
#include <hls_stream.h>
#include <stdint.h>
static void read_dma(int32_t *inm, hls::stream<int32_t> &outs, int32_t size){
LOOP_RDMA: for(int i=0; i<size; i++){
#pragma HLS PIPELINE II=1
#pragma HLS LOOP_TRIPCOUNT min=10 max=10
outs.write(inm[i]);
}
}
static void square_stream(hls::stream<int32_t> &ins, hls::stream<int32_t> &outs, int32_t size){
LOOP_SQAURE_ST: for(int i=0; i<size; i++){
#pragma HLS PIPELINE II=1
#pragma HLS LOOP_TRIPCOUNT min=10 max=10
int32_t tmp = ins.read();
outs.write(tmp * tmp);
}
}
static void write_dma(hls::stream<int32_t> &ins, int32_t *outm, int32_t size){
LOOP_WDMA: for(int i=0; i<size; i++){
#pragma HLS PIPELINE II=1
#pragma HLS LOOP_TRIPCOUNT min=10 max=10
outm[i] = ins.read();
}
}
void square(int32_t *inm, int32_t *outm, int32_t size){
#pragma HLS INTERFACE m_axi port = inm offset = slave bundle = gmem
#pragma HLS INTERFACE m_axi port = outm offset = slave bundle = gmem
#pragma HLS INTERFACE s_axilite port=inm bundle=control
#pragma HLS INTERFACE s_axilite port=outm bundle=control
#pragma HLS INTERFACE s_axilite port = size bundle = control
#pragma HLS INTERFACE s_axilite port = return bundle = control
static hls::stream<int32_t> ins;
static hls::stream<int32_t> outs;
#pragma HLS STREAM variable = ins depth = 32
#pragma HLS STREAM variable = outs depth = 32
#pragma HLS dataflow
read_dma(inm, ins, size);
square_stream(ins, outs, size);
write_dma(outs, outm, size);
}
// square_vhls.cpp
// 2019/12/11 by marsee
// 2020/07/14 : ハードウェア・アクセラレーション関数を1つにした
//
#include <stdint.h>
void square(volatile int32_t *inm, volatile int32_t *outm, int32_t size){
#pragma HLS INTERFACE m_axi depth=10 port = inm offset = slave bundle = gmem
#pragma HLS INTERFACE m_axi depth=10 port = outm offset = slave bundle = gmem
//#pragma HLS INTERFACE s_axilite port=inm bundle=control
//#pragma HLS INTERFACE s_axilite port=outm bundle=control
#pragma HLS INTERFACE s_axilite port = size bundle = control
#pragma HLS INTERFACE s_axilite port = return bundle = control
MAIN_LOOP: for(int i=0; i<size; i++){
#pragma HLS PIPELINE II=1
#pragma HLS LOOP_TRIPCOUNT min=10 max=10
int32_t indata = inm[i];
int32_t square_data = indata * indata;
outm[i] = square_data;
}
}
// square_vhls_tb.cpp
// 2020/07/17 by marsee
//
#include <stdint.h>
#include <stdio.h>
void square(volatile int32_t *inm, volatile int32_t *outm, int32_t size);
int main(){
int32_t data[10];
int32_t result[10];
for(int i=0; i<10; i++){
data[i] = i;
}
square(data, result, 10);
for(int i=0; i<10; i++){
printf("i = %d, data[%d] = %d, result[%d] = %d\n", i, i, data[i], i, result[i]);
}
return(0);
}
//------------------------Address Info-------------------
// 0x00 : reserved
// 0x04 : reserved
// 0x08 : reserved
// 0x0c : reserved
// 0x10 : Data signal of inm
// bit 31~0 - inm[31:0] (Read/Write)
// 0x14 : Data signal of inm
// bit 31~0 - inm[63:32] (Read/Write)
// 0x18 : reserved
// 0x1c : Data signal of outm
// bit 31~0 - outm[31:0] (Read/Write)
// 0x20 : Data signal of outm
// bit 31~0 - outm[63:32] (Read/Write)
// 0x24 : reserved
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
//------------------------Address Info-------------------
// 0x00 : Control signals
// bit 0 - ap_start (Read/Write/COH)
// bit 1 - ap_done (Read/COR)
// bit 2 - ap_idle (Read)
// bit 3 - ap_ready (Read)
// bit 7 - auto_restart (Read/Write)
// others - reserved
// 0x04 : Global Interrupt Enable Register
// bit 0 - Global Interrupt Enable (Read/Write)
// others - reserved
// 0x08 : IP Interrupt Enable Register (Read/Write)
// bit 0 - enable ap_done interrupt (Read/Write)
// bit 1 - enable ap_ready interrupt (Read/Write)
// others - reserved
// 0x0c : IP Interrupt Status Register (Read/TOW)
// bit 0 - ap_done (COR/TOW)
// bit 1 - ap_ready (COR/TOW)
// others - reserved
// 0x10 : Data signal of size
// bit 31~0 - size[31:0] (Read/Write)
// 0x14 : reserved
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
//------------------------Address Info-------------------
// 0x00 : Control signals
// bit 0 - ap_start (Read/Write/COH)
// bit 1 - ap_done (Read/COR)
// bit 2 - ap_idle (Read)
// bit 3 - ap_ready (Read)
// bit 7 - auto_restart (Read/Write)
// others - reserved
// 0x04 : Global Interrupt Enable Register
// bit 0 - Global Interrupt Enable (Read/Write)
// others - reserved
// 0x08 : IP Interrupt Enable Register (Read/Write)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// 0x0c : IP Interrupt Status Register (Read/TOW)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// 0x10 : Data signal of inm
// bit 31~0 - inm[31:0] (Read/Write)
// 0x14 : reserved
// 0x18 : Data signal of outm
// bit 31~0 - outm[31:0] (Read/Write)
// 0x1c : reserved
// 0x20 : Data signal of size
// bit 31~0 - size[31:0] (Read/Write)
// 0x24 : reserved
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
#pragma HLS INTERFACE s_axilite port=inm bundle=control
#pragma HLS INTERFACE s_axilite port=outm bundle=control
//------------------------Address Info-------------------
// 0x00 : Control signals
// bit 0 - ap_start (Read/Write/COH)
// bit 1 - ap_done (Read/COR)
// bit 2 - ap_idle (Read)
// bit 3 - ap_ready (Read)
// bit 7 - auto_restart (Read/Write)
// others - reserved
// 0x04 : Global Interrupt Enable Register
// bit 0 - Global Interrupt Enable (Read/Write)
// others - reserved
// 0x08 : IP Interrupt Enable Register (Read/Write)
// bit 0 - enable ap_done interrupt (Read/Write)
// bit 1 - enable ap_ready interrupt (Read/Write)
// others - reserved
// 0x0c : IP Interrupt Status Register (Read/TOW)
// bit 0 - ap_done (COR/TOW)
// bit 1 - ap_ready (COR/TOW)
// others - reserved
// 0x10 : Data signal of inm
// bit 31~0 - inm[31:0] (Read/Write)
// 0x14 : Data signal of inm
// bit 31~0 - inm[63:32] (Read/Write)
// 0x18 : reserved
// 0x1c : Data signal of outm
// bit 31~0 - outm[31:0] (Read/Write)
// 0x20 : Data signal of outm
// bit 31~0 - outm[63:32] (Read/Write)
// 0x24 : reserved
// 0x28 : Data signal of size
// bit 31~0 - size[31:0] (Read/Write)
// 0x2c : reserved
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
extern "C" {
void lap_filter_axis_dma(volatile int32_t *inm, volatile int32_t *outm, int32_t x_size, int32_t y_size){
#pragma HLS INTERFACE m_axi port = inm offset = slave bundle = gmem
#pragma HLS INTERFACE m_axi port = outm offset = slave bundle = gmem
#pragma HLS INTERFACE s_axilite port = inm bundle = control
#pragma HLS INTERFACE s_axilite port = outm bundle = control
#pragma HLS INTERFACE s_axilite port = x_size bundle = control
#pragma HLS INTERFACE s_axilite port = y_size bundle = control
#pragma HLS INTERFACE s_axilite port = return bundle = control
#pragma HLS dataflow
extern "C" {
void square(int32_t *inm, int32_t *outm, int32_t size){
#pragma HLS INTERFACE m_axi port = inm offset = slave bundle = gmem
#pragma HLS INTERFACE m_axi port = outm offset = slave bundle = gmem
#pragma HLS INTERFACE s_axilite port = size bundle = control
#pragma HLS INTERFACE s_axilite port = return bundle = control
void krnl_vadd(
int* a,
int* b,
int* c,
const int n_elements)
{
#pragma HLS INTERFACE m_axi offset=SLAVE bundle=gmem port=a max_read_burst_length = 256
#pragma HLS INTERFACE m_axi offset=SLAVE bundle=gmem port=b max_read_burst_length = 256
#pragma HLS INTERFACE m_axi offset=SLAVE bundle=gmem1 port=c max_write_burst_length = 256
#pragma HLS INTERFACE s_axilite port=a bundle=control
#pragma HLS INTERFACE s_axilite port=b bundle=control
#pragma HLS INTERFACE s_axilite port=c bundle=control
#pragma HLS INTERFACE s_axilite port=n_elements bundle=control
#pragma HLS INTERFACE s_axilite port=return bundle=control
extern "C" {
void square(int *inm, int *outm, int size){
#pragma HLS INTERFACE m_axi port = inm offset = slave bundle = gmem
#pragma HLS INTERFACE m_axi port = outm offset = slave bundle = gmem
#pragma HLS INTERFACE s_axilite port=inm bundle=control
#pragma HLS INTERFACE s_axilite port=outm bundle=control
#pragma HLS INTERFACE s_axilite port = size bundle = control
#pragma HLS INTERFACE s_axilite port = return bundle = control
fpga@debian-fpga:~/Vitis_work/square$ ./square_u96v2 square_c.xclbin
Using FPGA binary file specfied through the command line: square_c.xclbin
Found Platform
Platform Name: Xilinx
Loading: 'square_c.xclbin'
Error: i = 1 i^2 = 1 square_data = 0
Error: i = 2 i^2 = 4 square_data = 0
Error: i = 3 i^2 = 9 square_data = 0
Error: i = 4 i^2 = 16 square_data = 0
Error: i = 5 i^2 = 25 square_data = 0
Error: i = 6 i^2 = 36 square_data = 0
Error: i = 7 i^2 = 49 square_data = 0
Error: i = 8 i^2 = 64 square_data = 0
Error: i = 9 i^2 = 81 square_data = 0
TEST FAILED
fpga@debian-fpga:~/Vitis_work/array_p$ ./array_p matmul.xclbin
A:
0 1 8 5 5 2 0 7 7 10 …
7 0 4 0 4 7 6 10 9 5 …
2 0 8 3 6 8 10 4 2 10 …
2 4 8 5 2 3 3 1 5 9 …
10 5 2 0 10 0 5 4 3 10 …
9 1 0 7 9 6 8 7 10 9 …
4 9 2 4 5 5 3 1 1 6 …
6 9 6 9 1 2 7 1 1 3 …
1 3 9 7 1 7 4 4 5 1 …
10 4 1 6 2 5 5 10 1 2 …
… … … … … … … … … … ⋱
B:
7 7 2 9 7 9 1 0 8 6 …
4 2 7 3 8 8 4 3 2 0 …
6 1 9 1 10 2 2 1 2 6 …
0 6 2 3 7 1 8 5 6 6 …
8 6 8 3 1 5 3 6 5 4 …
3 0 4 2 7 7 5 8 7 10 …
4 6 10 1 7 3 5 5 9 0 …
2 9 7 5 8 0 1 7 7 4 …
1 0 5 0 1 9 8 8 4 0 …
4 6 7 7 5 3 8 4 7 3 …
… … … … … … … … … … ⋱
Gold:
196 311 428 206 384 291 305 363 405 243 …
286 472 448 296 490 425 382 430 500 367 …
269 439 555 260 529 390 416 425 559 370 …
231 293 419 231 365 385 361 356 384 235 …
307 479 484 313 453 477 368 366 529 295 …
317 474 488 357 472 458 439 457 564 341 …
246 339 385 272 381 424 364 324 386 263 …
234 367 312 217 430 307 334 248 314 284 …
231 370 403 197 453 334 353 410 382 344 …
246 432 363 321 462 324 291 330 436 322 …
… … … … … … … … … … ⋱
Found Platform
Platform Name: Xilinx
INFO: Reading matmul.xclbin
Loading: 'matmul.xclbin'
Trying to program device[0]: edge
Device[0]: program successful!
|-------------------------+-------------------------|
| Kernel | Wall-Clock Time (ns) |
|-------------------------+-------------------------|
| matmul: | 237029 |
| matmul: partition | 65973 |
|-------------------------+-------------------------|
Note: Wall Clock Time is meaningful for real hardware execution only, not for emulation.
Please refer to profile summary for kernel execution time for hardware emulation.
TEST PASSED
に書き換えた。firmware-name = "lap_filter_axis_dma.bit";
[ 1822.071446] fpga_manager fpga0: writing lap_filter_axis_dma.bit to Xilinx ZynqMP FPGA Manager
[ 1825.785632] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-full/firmware-name
[ 1825.824247] fclkcfg: loading out-of-tree module taints kernel.
[ 1825.834937] [drm] Probing for xlnx,zocl
[ 1825.836788] fclkcfg amba_pl@0:fclk0: driver installed.
[ 1825.838900] zocl-drm amba_pl@0:zyxclmm_drm: IRQ index 0 not found
[ 1825.843959] fclkcfg amba_pl@0:fclk0: device name : amba_pl@0:fclk0
[ 1825.850212] [drm] PR Isolation addr 0x0
[ 1825.850723] [drm] Initialized zocl 2018.2.1 20180313 for amba_pl@0:zyxclmm_drm on minor 1
[ 1825.856484] fclkcfg amba_pl@0:fclk0: clock name : pl0_ref
[ 1825.856493] fclkcfg amba_pl@0:fclk0: clock rate : 99999999
[ 1825.856522] fclkcfg amba_pl@0:fclk0: clock enabled : 1
[ 1825.885277] fclkcfg amba_pl@0:fclk0: remove rate : 1000000
[ 1825.891020] fclkcfg amba_pl@0:fclk0: remove enable : 0
#include"LIS3DHTR.h"
LIS3DHTR<TwoWire> lis;
unsigned long time1, time2;
float x_values, y_values, z_values;
void setup() {
Serial.begin(115200);
lis.begin(Wire1);
if (!lis) {
Serial.println("ERROR");
while(1);
}
lis.setOutputDataRate(LIS3DHTR_DATARATE_25HZ); //Data output rate
lis.setFullScaleRange(LIS3DHTR_RANGE_2G); //Scale range set to 2g
time2 = micros();
}
void loop() {
time1 = micros();
x_values = lis.getAccelerationX();
y_values = lis.getAccelerationY();
z_values = lis.getAccelerationZ();
Serial.print(time1-time2);
Serial.print(" "); Serial.print(x_values,3);
Serial.print(" "); Serial.print(y_values,3);
Serial.print(" "); Serial.print(z_values,3);
Serial.println();
delay(96);
time2 = time1;
}
99656 -0.056 -0.720 -0.564
99556 -0.420 -0.888 -0.812
100069 0.484 -0.744 -0.624
100181 -0.056 -0.820 -0.560
99907 -0.012 -0.700 -0.644
100551 -0.152 -0.780 -0.936
99978 0.040 -0.780 -0.684
100634 0.004 -0.792 -0.676
100858 0.008 -0.676 -0.516
//#include "SAMD51_TC.h"
#include <samd.h>
#include <cstdint>
#include <array>
#include"LIS3DHTR.h"
LIS3DHTR<TwoWire> lis;
unsigned long time1, time2;
float x_values, y_values, z_values;
#define GENERIC_CLOCK_GENERATOR_1M 5u
class SAMD51TCInterruptHelper;
class SAMD51TC
{
public:
/**
* @brief Create a new instance of SAM51TC for the TCx peripheral where x == tcUnit.
* @param [in] tcUnit index of TC peripheral.
*/
SAMD51TC(std::uint_least8_t tcUnit) : tcUnit(tcUnit), regs(nullptr), isrCallback(nullptr), microseconds(0)
{
switch(tcUnit)
{
case 0: {this->regs = &TC0->COUNT16; this->irqn = TC0_IRQn; break;}
case 1: {this->regs = &TC1->COUNT16; this->irqn = TC1_IRQn; break;}
case 2: {this->regs = &TC2->COUNT16; this->irqn = TC2_IRQn; break;}
case 3: {this->regs = &TC3->COUNT16; this->irqn = TC3_IRQn; break;}
case 4: {this->regs = &TC4->COUNT16; this->irqn = TC4_IRQn; break;}
case 5: {this->regs = &TC5->COUNT16; this->irqn = TC5_IRQn; break;}
case 6: {this->regs = &TC6->COUNT16; this->irqn = TC6_IRQn; break;}
case 7: {this->regs = &TC7->COUNT16; this->irqn = TC7_IRQn; break;}
}
}
void initialize(std::uint32_t microseconds = 1000000)
{
this->configureClock();
this->regs->CTRLA.bit.SWRST = 1;
while(this->regs->SYNCBUSY.bit.SWRST);
this->setPeriod(microseconds);
}
void setPeriod(std::uint32_t microseconds)
{
this->microseconds = microseconds;
}
void __attribute__((noinline)) start()
{
this->regs->CTRLA.bit.ENABLE = 0;
while(this->regs->SYNCBUSY.bit.ENABLE);
this->regs->COUNT.reg = 0;
while(this->regs->SYNCBUSY.bit.COUNT);
const std::array<uint_fast8_t, 8> prescaler_shifts = { 0, 1, 2, 3, 4, 6, 8, 10 };
for( std::uint_fast8_t index = 0; index < prescaler_shifts.size(); index++ ) {
const auto compare_value = this->microseconds >> prescaler_shifts[index];
if( compare_value <= 65535 ) {
this->regs->CTRLA.bit.PRESCALER = index;
this->regs->CC[0].reg = compare_value;
break;
}
}
while(this->regs->SYNCBUSY.bit.CC0);
this->regs->WAVE.bit.WAVEGEN = TC_WAVE_WAVEGEN_MFRQ_Val;
this->regs->INTENSET.bit.MC0 = 1;
NVIC_EnableIRQ(this->irqn);
this->regs->CTRLA.bit.MODE = TC_CTRLA_MODE_COUNT16_Val;
this->regs->CTRLA.bit.ENABLE = 1;
while(this->regs->SYNCBUSY.bit.ENABLE);
this->regs->CTRLBSET.bit.CMD = TC_CTRLBCLR_CMD_RETRIGGER_Val;
while(this->regs->SYNCBUSY.bit.CTRLB);
}
void stop()
{
this->regs->CTRLA.bit.ENABLE = 0;
while(this->regs->SYNCBUSY.bit.ENABLE);
this->regs->INTENCLR.bit.MC0 = 1;
NVIC_DisableIRQ(this->irqn);
NVIC_ClearPendingIRQ(this->irqn);
}
void restart()
{
this->regs->CTRLBSET.bit.CMD = TC_CTRLBCLR_CMD_RETRIGGER_Val;
while(this->regs->SYNCBUSY.bit.CTRLB);
}
void attachInterrupt(void (*isrCallback)())
{
this->isrCallback = isrCallback;
this->start();
}
void detachInterrupt()
{
this->stop();
this->isrCallback = nullptr;
}
private:
std::uint_least8_t tcUnit;
TcCount16* regs;
IRQn_Type irqn;
std::uint32_t microseconds;
void (*isrCallback)();
void configureClock()
{
switch(this->tcUnit) {
case 0: {MCLK->APBAMASK.bit.TC0_ = 1; GCLK->PCHCTRL[TC0_GCLK_ID].reg = GCLK_PCHCTRL_GEN(GENERIC_CLOCK_GENERATOR_1M) | GCLK_PCHCTRL_CHEN; break;}
case 1: {MCLK->APBAMASK.bit.TC1_ = 1; GCLK->PCHCTRL[TC1_GCLK_ID].reg = GCLK_PCHCTRL_GEN(GENERIC_CLOCK_GENERATOR_1M) | GCLK_PCHCTRL_CHEN; break;}
case 2: {MCLK->APBBMASK.bit.TC2_ = 1; GCLK->PCHCTRL[TC2_GCLK_ID].reg = GCLK_PCHCTRL_GEN(GENERIC_CLOCK_GENERATOR_1M) | GCLK_PCHCTRL_CHEN; break;}
case 3: {MCLK->APBBMASK.bit.TC3_ = 1; GCLK->PCHCTRL[TC3_GCLK_ID].reg = GCLK_PCHCTRL_GEN(GENERIC_CLOCK_GENERATOR_1M) | GCLK_PCHCTRL_CHEN; break;}
case 4: {MCLK->APBCMASK.bit.TC4_ = 1; GCLK->PCHCTRL[TC4_GCLK_ID].reg = GCLK_PCHCTRL_GEN(GENERIC_CLOCK_GENERATOR_1M) | GCLK_PCHCTRL_CHEN; break;}
case 5: {MCLK->APBCMASK.bit.TC5_ = 1; GCLK->PCHCTRL[TC5_GCLK_ID].reg = GCLK_PCHCTRL_GEN(GENERIC_CLOCK_GENERATOR_1M) | GCLK_PCHCTRL_CHEN; break;}
case 6: {MCLK->APBDMASK.bit.TC6_ = 1; GCLK->PCHCTRL[TC6_GCLK_ID].reg = GCLK_PCHCTRL_GEN(GENERIC_CLOCK_GENERATOR_1M) | GCLK_PCHCTRL_CHEN; break;}
case 7: {MCLK->APBDMASK.bit.TC7_ = 1; GCLK->PCHCTRL[TC7_GCLK_ID].reg = GCLK_PCHCTRL_GEN(GENERIC_CLOCK_GENERATOR_1M) | GCLK_PCHCTRL_CHEN; break;}
}
}
public:
void processIsr()
{
if( this->regs->INTFLAG.bit.MC0 ) {
this->regs->INTFLAG.bit.MC0 = 1;
if( this->isrCallback != nullptr ) {
this->isrCallback();
}
}
}
};
SAMD51TC TimerTC3(3);
void TC3_Handler() { TimerTC3.processIsr(); }
bool isLEDOn = false;
char time = 0;
void setup()
{
TimerTC3.initialize(100000); // microseconds
TimerTC3.attachInterrupt(timerIsr);
Serial.begin(115200);
lis.begin(Wire1);
if (!lis) {
Serial.println("ERROR");
while(1);
}
lis.setOutputDataRate(LIS3DHTR_DATARATE_25HZ); //Data output rate
lis.setFullScaleRange(LIS3DHTR_RANGE_2G); //Scale range set to 2g
time2 = micros();
}
void loop()
{
/*
time ++;
if(time == 10)TimerTc3.detachInterrupt();
else if(time == 20)
{
TimerTc3.attachInterrupt(timerIsr);
time = 0;
}
delay(1000);
*/
}
void timerIsr()
{
time1 = micros();
x_values = lis.getAccelerationX();
y_values = lis.getAccelerationY();
z_values = lis.getAccelerationZ();
Serial.print(time1-time2);
Serial.print(" "); Serial.print(x_values,3);
Serial.print(" "); Serial.print(y_values,3);
Serial.print(" "); Serial.print(z_values,3);
Serial.println();
time2 = time1;
}
97002 -0.104 -0.276 -1.088
98002 -0.044 -0.260 -0.856
97002 -0.100 -0.212 -0.932
97002 -0.036 -0.004 -1.020
97002 -0.164 -0.192 -0.980
97002 -0.104 -0.160 -0.928
97002 -0.228 0.000 -1.732
97002 -0.080 -0.212 -1.044
97002 -0.060 -0.184 -1.000
97002 -0.052 -0.096 -0.944
[ 312.988519] fpga_manager fpga0: writing vadd.bit to Xilinx ZynqMP FPGA Manager
[ 316.935028] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-full/firmware-name
[ 316.974780] fclkcfg: loading out-of-tree module taints kernel.
[ 316.982817] fclkcfg amba_pl@0:fclk0: driver installed.
[ 316.988018] fclkcfg amba_pl@0:fclk0: device name : amba_pl@0:fclk0
[ 316.990604] [drm] Probing for xlnx,zocl
[ 316.994490] fclkcfg amba_pl@0:fclk0: clock name : pl0_ref
[ 316.998318] zocl-drm amba_pl@0:zyxclmm_drm: IRQ index 0 not found
[ 317.004039] fclkcfg amba_pl@0:fclk0: clock rate : 99999999
[ 317.010217] [drm] PR Isolation addr 0x0
[ 317.015977] fclkcfg amba_pl@0:fclk0: clock enabled : 1
[ 317.016791] [drm] Initialized zocl 2018.2.1 20180313 for amba_pl@0:zyxclmm_drm on minor 1
[ 317.019815] fclkcfg amba_pl@0:fclk0: remove rate : 1000000
[ 317.038936] fclkcfg amba_pl@0:fclk0: remove enable : 0
[ 363.816677] [drm] Pid 646 opened device
[ 363.820621] [drm] Pid 646 closed device
[ 363.825041] [drm] Pid 646 opened device
[ 363.829060] [drm] Pid 646 closed device
[ 363.833279] [drm] Pid 646 opened device
[ 363.837151] [drm] Pid 646 closed device
[ 363.841011] [drm] Pid 646 opened device
[ 363.844861] [drm] Pid 646 closed device
[ 363.848773] [drm] Pid 646 opened device
[ 364.105518] [drm] Finding IP_LAYOUT section header
[ 364.105522] [drm] Section IP_LAYOUT details:
[ 364.110348] [drm] offset = 0x54fcf8
[ 364.114622] [drm] size = 0x58
[ 364.118291] [drm] Finding DEBUG_IP_LAYOUT section header
[ 364.121423] [drm] AXLF section DEBUG_IP_LAYOUT header not found
[ 364.126735] [drm] Finding CONNECTIVITY section header
[ 364.132644] [drm] Section CONNECTIVITY details:
[ 364.137687] [drm] offset = 0x54fd50
[ 364.142210] [drm] size = 0x28
[ 364.145873] [drm] Finding MEM_TOPOLOGY section header
[ 364.149011] [drm] Section MEM_TOPOLOGY details:
[ 364.154062] [drm] offset = 0x54fc00
[ 364.158590] [drm] size = 0xf8
[ 364.162291] [drm] Download new XCLBIN 94A81AE6-CD68-48BE-A851-24FB31E58964 done.
[ 364.166616] [drm] -> Hold xclbin 94A81AE6-CD68-48BE-A851-24FB31E58964, from ref=0
[ 364.174014] [drm] <- Hold xclbin 94A81AE6-CD68-48BE-A851-24FB31E58964, to ref=1
[ 364.181519] [drm] No ERT scheduler on MPSoC, using KDS
[ 364.193982] [drm] request_irq failed on CU 0 error: -22.Fall back to polling mode.
[ 364.201552] [drm] scheduler config ert(0)
[ 364.201554] [drm] cus(1)
[ 364.205556] [drm] slots(16)
[ 364.208248] [drm] num_cu_masks(1)
[ 364.211208] [drm] cu_shift(16)
[ 364.214696] [drm] cu_base(0xa0000000)
[ 364.217917] [drm] polling(1)
[ 364.221790] [drm] -> Release xclbin 94A81AE6-CD68-48BE-A851-24FB31E58964, from ref=1
[ 364.224847] [drm] now xclbin can be changed
[ 364.232588] [drm] <- Release xclbin 94A81AE6-CD68-48BE-A851-24FB31E58964, to ref=0
[ 364.237036] [drm] -> Hold xclbin 94A81AE6-CD68-48BE-A851-24FB31E58964, from ref=0
[ 364.244608] [drm] <- Hold xclbin 94A81AE6-CD68-48BE-A851-24FB31E58964, to ref=1
[ 364.259443] [drm] -> Release xclbin 94A81AE6-CD68-48BE-A851-24FB31E58964, from ref=1
[ 364.266778] [drm] now xclbin can be changed
[ 364.274525] [drm] <- Release xclbin 94A81AE6-CD68-48BE-A851-24FB31E58964, to ref=0
[ 364.283690] [drm] Pid 646 closed device
all:
{
[destination_device = pl] vadd.bit
}
/dts-v1/; /plugin/;
/ {
fragment@0 {
target-path = "/fpga-full";
__overlay__ {
firmware-name = "vadd.bit";
};
};
fragment@1 {
target-path = "/amba_pl@0";
__overlay__ {
#address-cells = <2>;
#size-cells = <2>;
zyxclmm_drm {
compatible = "xlnx,zocl";
status = "okay";
};
fclk0 {
compatible = "ikwzm,fclkcfg-0.10.a";
clocks = <&zynqmp_clk 0x47>;
insert-rate = "100000000";
insert-enable = <1>;
remove-rate = "1000000";
remove-enable = <0>;
};
};
};
};
fpga@debian-fpga:~/Vitis_work/vadd201$ ./vadd binary_container_1.xclbin
./vadd: error while loading shared libraries: libcrypt.so.2: cannot open shared object file: No such file or directory
[ 291.996977] fpga_manager fpga0: writing streaming_lap_filter5.bin to Xilinx ZynqMP FPGA Manager
[ 292.315190] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-full/firmware-name
[ 292.347674] zocl: loading out-of-tree module taints kernel.
[ 292.356199] [drm] Probing for xlnx,zocl
[ 292.360174] zocl-drm amba_pl@0:zyxclmm_drm: IRQ index 0 not found
[ 292.366416] [drm] PR Isolation addr 0x0
[ 292.366921] [drm] Initialized zocl 2018.2.1 20180313 for amba_pl@0:zyxclmm_drm on minor 1
[ 292.380423] fclkcfg amba_pl@0:fclk0: driver installed.
[ 292.385601] fclkcfg amba_pl@0:fclk0: device name : amba_pl@0:fclk0
[ 292.392061] fclkcfg amba_pl@0:fclk0: clock name : pl0_ref
[ 292.397806] fclkcfg amba_pl@0:fclk0: clock rate : 99999999
[ 292.403660] fclkcfg amba_pl@0:fclk0: clock enabled : 1
[ 292.408880] fclkcfg amba_pl@0:fclk0: remove rate : 1000000
[ 292.414622] fclkcfg amba_pl@0:fclk0: remove enable : 0
fpga@debian-fpga:~/Vitis_work/ZynqMP-FPGA-XRT-Example-1-Ultra96$ ./streaming_lap_filter5.exe streaming_lap_filter5.xclbin
Using FPGA binary file specfied through the command line: streaming_lap_filter5.xclbin
Found Platform
Platform Name: Xilinx
Loading: 'streaming_lap_filter5.xclbin'
total time = 0.000614 sec
Success HW and SW results match
ERROR: [v++ 82-1061] Internal error: SD files options supported only for SD boot mode
ERROR: [v++ 60-702] Failed to finish packaging
INFO: [v++ 60-1653] Closing dispatch client.
makefile:100: recipe for target 'vadd2' failed
make: [vadd2] Error 1 (無視されました)
NOTICE: ATF running on XCZU3EG/silicon v4/RTL5.1 at 0xfffea000
NOTICE: BL31: v2.2(release):v1.1-5588-g5918e656e
NOTICE: BL31: Built : 13:15:27, Jun 11 2020
U-Boot 2020.01 (Jun 11 2020 - 13:14:21 +0000)
Board: Xilinx ZynqMP
DRAM: 2 GiB
usb dr_mode not found
usb dr_mode not found
PMUFW: v1.1
EL Level: EL2
Chip ID: zu3eg
NAND: 0 MiB
MMC: mmc@ff160000: 0, mmc@ff170000: 1
In: serial@ff010000
Out: serial@ff010000
Err: serial@ff010000
Bootmode: SD_MODE
Reset reason: EXTERNAL
Net: No ethernet found.
Hit any key to stop autoboot: 0
switch to partitions #0, OK
mmc0 is current device
Scanning mmc 0:1...
Found U-Boot script /boot.scr
2007 bytes read in 18 ms (108.4 KiB/s)
## Executing script at 20000000
8143156 bytes read in 667 ms (11.6 MiB/s)
## Loading kernel from FIT Image at 10000000 ...
Using 'conf@system-top.dtb' configuration
Trying 'kernel@1' kernel subimage
Description: Linux kernel
Type: Kernel Image
Compression: gzip compressed
Data Start: 0x100000e8
Data Size: 8103786 Bytes = 7.7 MiB
Architecture: AArch64
OS: Linux
Load Address: 0x00080000
Entry Point: 0x00080000
Hash algo: sha256
Hash value: 05cef73deeb6daa19302778d736d979f0f5bd05f7850775578893f9c0094644b
Verifying Hash Integrity ... sha256+ OK
## Loading fdt from FIT Image at 10000000 ...
Using 'conf@system-top.dtb' configuration
Trying 'fdt@system-top.dtb' fdt subimage
Description: Flattened Device Tree blob
Type: Flat Device Tree
Compression: uncompressed
Data Start: 0x107ba964
Data Size: 37477 Bytes = 36.6 KiB
Architecture: AArch64
Hash algo: sha256
Hash value: 489eb046a4ac125018a9763e75cc61e5372457d7fd294ca4b061301d1d3a0ba2
Verifying Hash Integrity ... sha256+ OK
Booting using the fdt blob at 0x107ba964
Uncompressing Kernel Image
Loading Device Tree to 000000000fff3000, end 000000000ffff264 ... OK
Starting kernel ...
[ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
[ 0.000000] Linux version 5.4.0-xilinx-v2020.1 (oe-user@oe-host) (gcc version 9.2.0 (GCC)) #1 SMP Thu Jun 11 13:12:39 UTC 2020
[ 0.000000] Machine model: xlnx,zynqmp
[ 0.000000] earlycon: cdns0 at MMIO 0x00000000ff010000 (options '115200n8')
[ 0.000000] printk: bootconsole [cdns0] enabled
[ 0.000000] efi: Getting EFI parameters from FDT:
[ 0.000000] efi: UEFI not found.
[ 0.000000] cma: Reserved 256 MiB at 0x000000006fc00000
[ 0.000000] psci: probing for conduit method from DT.
[ 0.000000] psci: PSCIv1.1 detected in firmware.
[ 0.000000] psci: Using standard PSCI v0.2 function IDs
[ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
[ 0.000000] psci: SMC Calling Convention v1.1
[ 0.000000] percpu: Embedded 21 pages/cpu s48664 r8192 d29160 u86016
[ 0.000000] Detected VIPT I-cache on CPU0
[ 0.000000] CPU features: detected: ARM erratum 845719
[ 0.000000] Speculative Store Bypass Disable mitigation not required
[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 515844
[ 0.000000] Kernel command line: earlycon console=ttyPS0,115200 clk_ignore_unused root=/dev/mmcblk0p2 rw rootwait
[ 0.000000] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
[ 0.000000] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes, linear)
[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
[ 0.000000] Memory: 1776376K/2096128K available (11580K kernel code, 668K rwdata, 3612K rodata, 704K init, 518K bss, 57608K reserved, 262144K cma-reserved)
[ 0.000000] rcu: Hierarchical RCU implementation.
[ 0.000000] rcu: RCU event tracing is enabled.
[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
[ 0.000000] GIC: Adjusting CPU interface base to 0x00000000f902f000
[ 0.000000] GIC: Using split EOI/Deactivate mode
[ 0.000000] random: get_random_bytes called from start_kernel+0x2a8/0x42c with crng_init=0
[ 0.000000] arch_timer: cp15 timer(s) running at 100.00MHz (phys).
[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x171024e7e0, max_idle_ns: 440795205315 ns
[ 0.000004] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 4398046511100ns
[ 0.008424] Console: colour dummy device 80x25
[ 0.012484] Calibrating delay loop (skipped), value calculated using timer frequency.. 200.00 BogoMIPS (lpj=400000)
[ 0.022839] pid_max: default: 32768 minimum: 301
[ 0.027598] Mount-cache hash table entries: 4096 (order: 3, 32768 bytes, linear)
[ 0.034786] Mountpoint-cache hash table entries: 4096 (order: 3, 32768 bytes, linear)
[ 0.043837] ASID allocator initialised with 32768 entries
[ 0.047995] rcu: Hierarchical SRCU implementation.
[ 0.052893] EFI services will not be available.
[ 0.057347] smp: Bringing up secondary CPUs ...
[ 0.062083] Detected VIPT I-cache on CPU1
[ 0.062130] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
[ 0.062529] Detected VIPT I-cache on CPU2
[ 0.062552] CPU2: Booted secondary processor 0x0000000002 [0x410fd034]
[ 0.062915] Detected VIPT I-cache on CPU3
[ 0.062935] CPU3: Booted secondary processor 0x0000000003 [0x410fd034]
[ 0.062984] smp: Brought up 1 node, 4 CPUs
[ 0.097142] SMP: Total of 4 processors activated.
[ 0.101814] CPU features: detected: 32-bit EL0 Support
[ 0.106917] CPU features: detected: CRC32 instructions
[ 0.112054] CPU: All CPU(s) started at EL2
[ 0.116098] alternatives: patching kernel code
[ 0.121908] devtmpfs: initialized
[ 0.128198] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
[ 0.133489] futex hash table entries: 1024 (order: 4, 65536 bytes, linear)
[ 0.147728] xor: measuring software checksum speed
[ 0.184438] 8regs : 2375.000 MB/sec
[ 0.224467] 32regs : 2725.000 MB/sec
[ 0.264501] arm64_neon: 2365.000 MB/sec
[ 0.264542] xor: using function: 32regs (2725.000 MB/sec)
[ 0.268419] pinctrl core: initialized pinctrl subsystem
[ 0.274497] NET: Registered protocol family 16
[ 0.279527] DMA: preallocated 256 KiB pool for atomic allocations
[ 0.284089] audit: initializing netlink subsys (disabled)
[ 0.289513] audit: type=2000 audit(0.228:1): state=initialized audit_enabled=0 res=1
[ 0.289950] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
[ 0.316406] HugeTLB registered 1.00 GiB page size, pre-allocated 0 pages
[ 0.317463] HugeTLB registered 32.0 MiB page size, pre-allocated 0 pages
[ 0.324132] HugeTLB registered 2.00 MiB page size, pre-allocated 0 pages
[ 0.330796] HugeTLB registered 64.0 KiB page size, pre-allocated 0 pages
[ 1.411690] DRBG: Continuing without Jitter RNG
[ 1.486446] raid6: neonx8 gen() 1541 MB/s
[ 1.554491] raid6: neonx8 xor() 1461 MB/s
[ 1.622529] raid6: neonx4 gen() 1481 MB/s
[ 1.690581] raid6: neonx4 xor() 1419 MB/s
[ 1.758643] raid6: neonx2 gen() 1124 MB/s
[ 1.826677] raid6: neonx2 xor() 1173 MB/s
[ 1.894776] raid6: neonx1 gen() 728 MB/s
[ 1.962777] raid6: neonx1 xor() 880 MB/s
[ 2.030825] raid6: int64x8 gen() 1162 MB/s
[ 2.098882] raid6: int64x8 xor() 760 MB/s
[ 2.166935] raid6: int64x4 gen() 977 MB/s
[ 2.234982] raid6: int64x4 xor() 733 MB/s
[ 2.303083] raid6: int64x2 gen() 678 MB/s
[ 2.371080] raid6: int64x2 xor() 591 MB/s
[ 2.439133] raid6: int64x1 gen() 449 MB/s
[ 2.507180] raid6: int64x1 xor() 450 MB/s
[ 2.507221] raid6: using algorithm neonx8 gen() 1541 MB/s
[ 2.511174] raid6: .... xor() 1461 MB/s, rmw enabled
[ 2.516105] raid6: using neon recovery algorithm
[ 2.521144] iommu: Default domain type: Translated
[ 2.525797] SCSI subsystem initialized
[ 2.529420] usbcore: registered new interface driver usbfs
[ 2.534734] usbcore: registered new interface driver hub
[ 2.540005] usbcore: registered new device driver usb
[ 2.545048] mc: Linux media interface: v0.10
[ 2.549253] videodev: Linux video capture interface: v2.00
[ 2.554703] pps_core: LinuxPPS API ver. 1 registered
[ 2.559615] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[ 2.568710] PTP clock support registered
[ 2.572602] EDAC MC: Ver: 3.0.0
[ 2.576169] zynqmp-ipi-mbox mailbox@ff990400: Registered ZynqMP IPI mbox with TX/RX channels.
[ 2.584386] FPGA manager framework
[ 2.587690] Advanced Linux Sound Architecture Driver Initialized.
[ 2.593944] Bluetooth: Core ver 2.22
[ 2.597175] NET: Registered protocol family 31
[ 2.601568] Bluetooth: HCI device and connection manager initialized
[ 2.607885] Bluetooth: HCI socket layer initialized
[ 2.612728] Bluetooth: L2CAP socket layer initialized
[ 2.617750] Bluetooth: SCO socket layer initialized
[ 2.622970] clocksource: Switched to clocksource arch_sys_counter
[ 2.628766] VFS: Disk quotas dquot_6.6.0
[ 2.632586] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
[ 2.643702] NET: Registered protocol family 2
[ 2.644180] tcp_listen_portaddr_hash hash table entries: 1024 (order: 2, 16384 bytes, linear)
[ 2.652200] TCP established hash table entries: 16384 (order: 5, 131072 bytes, linear)
[ 2.660149] TCP bind hash table entries: 16384 (order: 6, 262144 bytes, linear)
[ 2.667625] TCP: Hash tables configured (established 16384 bind 16384)
[ 2.673911] UDP hash table entries: 1024 (order: 3, 32768 bytes, linear)
[ 2.680494] UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes, linear)
[ 2.687680] NET: Registered protocol family 1
[ 2.692207] RPC: Registered named UNIX socket transport module.
[ 2.697763] RPC: Registered udp transport module.
[ 2.702427] RPC: Registered tcp transport module.
[ 2.707099] RPC: Registered tcp NFSv4.1 backchannel transport module.
[ 2.713769] PCI: CLS 0 bytes, default 64
[ 2.717941] hw perfevents: no interrupt-affinity property for /pmu, guessing.
[ 2.724668] hw perfevents: enabled with armv8_pmuv3 PMU driver, 7 counters available
[ 2.733066] Initialise system trusted keyrings
[ 2.736717] workingset: timestamp_bits=46 max_order=19 bucket_order=0
[ 2.743822] NFS: Registering the id_resolver key type
[ 2.748031] Key type id_resolver registered
[ 2.752164] Key type id_legacy registered
[ 2.756150] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
[ 2.762822] jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
[ 2.782236] NET: Registered protocol family 38
[ 2.782281] Key type asymmetric registered
[ 2.785108] Asymmetric key parser 'x509' registered
[ 2.789972] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 247)
[ 2.797304] io scheduler mq-deadline registered
[ 2.801800] io scheduler kyber registered
[ 2.833169] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[ 2.837375] cacheinfo: Unable to detect cache hierarchy for CPU 0
[ 2.844856] brd: module loaded
[ 2.850370] loop: module loaded
[ 2.851217] mtdoops: mtd device (mtddev=name/number) must be supplied
[ 2.855517] libphy: Fixed MDIO Bus: probed
[ 2.859387] tun: Universal TUN/TAP device driver, 1.6
[ 2.863451] CAN device driver interface
[ 2.867934] usbcore: registered new interface driver asix
[ 2.872591] usbcore: registered new interface driver ax88179_178a
[ 2.878604] usbcore: registered new interface driver cdc_ether
[ 2.884405] usbcore: registered new interface driver net1080
[ 2.890028] usbcore: registered new interface driver cdc_subset
[ 2.895907] usbcore: registered new interface driver zaurus
[ 2.901453] usbcore: registered new interface driver cdc_ncm
[ 2.907845] usbcore: registered new interface driver uas
[ 2.912351] usbcore: registered new interface driver usb-storage
[ 2.918971] rtc_zynqmp ffa60000.rtc: registered as rtc0
[ 2.923537] i2c /dev entries driver
[ 2.928426] usbcore: registered new interface driver uvcvideo
[ 2.932652] USB Video Class driver (1.1.1)
[ 2.937192] Bluetooth: HCI UART driver ver 2.3
[ 2.941132] Bluetooth: HCI UART protocol H4 registered
[ 2.946230] Bluetooth: HCI UART protocol BCSP registered
[ 2.951525] Bluetooth: HCI UART protocol LL registered
[ 2.956608] Bluetooth: HCI UART protocol ATH3K registered
[ 2.961984] Bluetooth: HCI UART protocol Three-wire (H5) registered
[ 2.968234] Bluetooth: HCI UART protocol Intel registered
[ 2.973575] Bluetooth: HCI UART protocol QCA registered
[ 2.978779] usbcore: registered new interface driver bcm203x
[ 2.984400] usbcore: registered new interface driver bpa10x
[ 2.989937] usbcore: registered new interface driver bfusb
[ 2.995386] usbcore: registered new interface driver btusb
[ 3.000849] usbcore: registered new interface driver ath3k
[ 3.006376] EDAC MC: ECC not enabled
[ 3.009936] EDAC DEVICE0: Giving out device to module edac controller cache_err: DEV edac (POLLED)
[ 3.018882] EDAC DEVICE1: Giving out device to module zynqmp-ocm-edac controller zynqmp_ocm: DEV ff960000.memory-controller (INTERRUPT)
[ 3.031055] sdhci: Secure Digital Host Controller Interface driver
[ 3.036967] sdhci: Copyright(c) Pierre Ossman
[ 3.041291] sdhci-pltfm: SDHCI platform and OF driver helper
[ 3.047277] ledtrig-cpu: registered to indicate activity on CPUs
[ 3.052933] zynqmp_firmware_probe Platform Management API v1.1
[ 3.058681] zynqmp_firmware_probe Trustzone version v1.0
[ 3.088759] alg: No test for xilinx-zynqmp-aes (zynqmp-aes)
[ 3.088995] zynqmp_aes zynqmp_aes: AES Successfully Registered
[ 3.088995]
[ 3.096218] alg: No test for xilinx-keccak-384 (zynqmp-keccak-384)
[ 3.102447] alg: No test for xilinx-zynqmp-rsa (zynqmp-rsa)
[ 3.108014] usbcore: registered new interface driver usbhid
[ 3.113264] usbhid: USB HID core driver
[ 3.117291] xlnk xlnk: Major 244
[ 3.120371] xlnk xlnk: xlnk driver loaded
[ 3.124248] xlnk xlnk: xlnk_pdev is not null
[ 3.130898] fpga_manager fpga0: Xilinx ZynqMP FPGA Manager registered
[ 3.135218] usbcore: registered new interface driver snd-usb-audio
[ 3.141902] pktgen: Packet Generator for packet performance testing. Version: 2.75
[ 3.149247] Initializing XFRM netlink socket
[ 3.152896] NET: Registered protocol family 10
[ 3.157711] Segment Routing with IPv6
[ 3.160975] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
[ 3.167115] NET: Registered protocol family 17
[ 3.171144] NET: Registered protocol family 15
[ 3.175558] bridge: filtering via arp/ip/ip6tables is no longer available by default. Update your scripts to load br_netfilter if you need this.
[ 3.188429] can: controller area network core (rev 20170425 abi 9)
[ 3.194604] NET: Registered protocol family 29
[ 3.198983] can: raw protocol (rev 20170425)
[ 3.203221] can: broadcast manager protocol (rev 20170425 t)
[ 3.208845] can: netlink gateway (rev 20190810) max_hops=1
[ 3.214398] Bluetooth: RFCOMM TTY layer initialized
[ 3.219143] Bluetooth: RFCOMM socket layer initialized
[ 3.224251] Bluetooth: RFCOMM ver 1.11
[ 3.227964] Bluetooth: BNEP (Ethernet Emulation) ver 1.3
[ 3.233233] Bluetooth: BNEP filters: protocol multicast
[ 3.238427] Bluetooth: BNEP socket layer initialized
[ 3.243356] Bluetooth: HIDP (Human Interface Emulation) ver 1.2
[ 3.249238] Bluetooth: HIDP socket layer initialized
[ 3.254310] 9pnet: Installing 9P2000 support
[ 3.258434] Key type dns_resolver registered
[ 3.262985] registered taskstats version 1
[ 3.266704] Loading compiled-in X.509 certificates
[ 3.271933] Btrfs loaded, crc32c=crc32c-generic
[ 3.286814] ff000000.serial: ttyPS1 at MMIO 0xff000000 (irq = 40, base_baud = 6249999) is a xuartps
[ 3.290752] ff010000.serial: ttyPS0 at MMIO 0xff010000 (irq = 41, base_baud = 6249999) is a xuartps
[ 3.299519] of-fpga-region fpga-full: FPGA Region probed
[ 3.305872] xilinx-dpdma fd4c0000.dma: Xilinx DPDMA engine is probed
[ 3.311069] xilinx-zynqmp-dma fd500000.dma: ZynqMP DMA driver Probe success
[ 3.317883] xilinx-zynqmp-dma fd510000.dma: ZynqMP DMA driver Probe success
[ 3.324799] xilinx-zynqmp-dma fd520000.dma: ZynqMP DMA driver Probe success
[ 3.331722] xilinx-zynqmp-dma fd530000.dma: ZynqMP DMA driver Probe success
[ 3.338643] xilinx-zynqmp-dma fd540000.dma: ZynqMP DMA driver Probe success
[ 3.345559] xilinx-zynqmp-dma fd550000.dma: ZynqMP DMA driver Probe success
[ 3.352483] xilinx-zynqmp-dma fd560000.dma: ZynqMP DMA driver Probe success
[ 3.359401] xilinx-zynqmp-dma fd570000.dma: ZynqMP DMA driver Probe success
[ 3.366417] xilinx-zynqmp-dma ffa80000.dma: ZynqMP DMA driver Probe success
[ 3.373239] xilinx-zynqmp-dma ffa90000.dma: ZynqMP DMA driver Probe success
[ 3.380165] xilinx-zynqmp-dma ffaa0000.dma: ZynqMP DMA driver Probe success
[ 3.387088] xilinx-zynqmp-dma ffab0000.dma: ZynqMP DMA driver Probe success
[ 3.394002] xilinx-zynqmp-dma ffac0000.dma: ZynqMP DMA driver Probe success
[ 3.400918] xilinx-zynqmp-dma ffad0000.dma: ZynqMP DMA driver Probe success
[ 3.407841] xilinx-zynqmp-dma ffae0000.dma: ZynqMP DMA driver Probe success
[ 3.414763] xilinx-zynqmp-dma ffaf0000.dma: ZynqMP DMA driver Probe success
[ 3.421931] xilinx-psgtr fd400000.zynqmp_phy: Lane:1 type:8 protocol:4 pll_locked:yes
[ 3.432398] xilinx-dp-snd-codec fd4a0000.zynqmp-display:zynqmp_dp_snd_codec0: Xilinx DisplayPort Sound Codec probed
[ 3.439942] xilinx-dp-snd-pcm zynqmp_dp_snd_pcm0: Xilinx DisplayPort Sound PCM probed
[ 3.447691] xilinx-dp-snd-pcm zynqmp_dp_snd_pcm1: Xilinx DisplayPort Sound PCM probed
[ 3.456016] xilinx-dp-snd-card fd4a0000.zynqmp-display:zynqmp_dp_snd_card: xilinx-dp-snd-codec-dai <-> xilinx-dp-snd-codec-dai mapping ok
[ 3.467650] xilinx-dp-snd-card fd4a0000.zynqmp-display:zynqmp_dp_snd_card: xilinx-dp-snd-codec-dai <-> xilinx-dp-snd-codec-dai mapping ok
[ 3.480182] xilinx-dp-snd-card fd4a0000.zynqmp-display:zynqmp_dp_snd_card: Xilinx DisplayPort Sound Card probed
[ 3.489952] OF: graph: no port node found in /amba/zynqmp-display@fd4a0000
[ 3.496831] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[ 3.503265] [drm] No driver support for vblank timestamp query.
[ 3.509258] xlnx-drm xlnx-drm.0: bound fd4a0000.zynqmp-display (ops 0xffffffc010c97038)
[ 3.660422] Console: switching to colour frame buffer device 128x48
[ 3.677696] zynqmp-display fd4a0000.zynqmp-display: fb0: xlnxdrmfb frame buffer device
[ 3.685831] [drm] Initialized xlnx 1.0.0 20130509 for fd4a0000.zynqmp-display on minor 0
[ 3.693645] zynqmp-display fd4a0000.zynqmp-display: ZynqMP DisplayPort Subsystem driver probed
[ 3.703510] xilinx-axipmon ffa00000.perf-monitor: Probed Xilinx APM
[ 3.708701] xilinx-axipmon fd0b0000.perf-monitor: Probed Xilinx APM
[ 3.714873] xilinx-axipmon fd490000.perf-monitor: Probed Xilinx APM
[ 3.721102] xilinx-axipmon ffa10000.perf-monitor: Probed Xilinx APM
[ 3.727351] dwc3-of-simple ff9d0000.usb0: dwc3_simple_set_phydata: Can't find usb3-phy
[ 3.735436] dwc3 fe200000.dwc3: Failed to get clk 'ref': -2
[ 3.740986] dwc3-of-simple ff9e0000.usb1: dwc3_simple_set_phydata: Can't find usb3-phy
[ 3.748728] dwc3 fe300000.dwc3: Failed to get clk 'ref': -2
[ 3.754852] cdns-i2c ff030000.i2c: 400 kHz mmio ff030000 irq 30
[ 3.760449] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
[ 3.765255] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1
[ 3.772985] xhci-hcd xhci-hcd.0.auto: hcc params 0x0238f625 hci version 0x100 quirks 0x0000000202010010
[ 3.782214] xhci-hcd xhci-hcd.0.auto: irq 50, io mem 0xfe300000
[ 3.788327] cdns-wdt fd4d0000.watchdog: Xilinx Watchdog Timer with timeout 60s
[ 3.795543] cdns-wdt ff150000.watchdog: Xilinx Watchdog Timer with timeout 10s
[ 3.803541] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 5.04
[ 3.810664] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[ 3.817832] usb usb1: Product: xHCI Host Controller
[ 3.822674] usb usb1: Manufacturer: Linux 5.4.0-xilinx-v2020.1 xhci-hcd
[ 3.829251] usb usb1: SerialNumber: xhci-hcd.0.auto
[ 3.834617] hub 1-0:1.0: USB hub found
[ 3.837836] hub 1-0:1.0: 1 port detected
[ 3.841933] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
[ 3.847165] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2
[ 3.854777] xhci-hcd xhci-hcd.0.auto: Host supports USB 3.0 SuperSpeed
[ 3.861383] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
[ 3.869374] usb usb2: New USB device found, idVendor=1d6b, idProduct=0003, bcdDevice= 5.04
[ 3.877530] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[ 3.884697] usb usb2: Product: xHCI Host Controller
[ 3.889543] usb usb2: Manufacturer: Linux 5.4.0-xilinx-v2020.1 xhci-hcd
[ 3.896113] usb usb2: SerialNumber: xhci-hcd.0.auto
[ 3.901065] mmc0: SDHCI controller on ff160000.mmc [ff160000.mmc] using ADMA 64-bit
[ 3.910070] hub 2-0:1.0: USB hub found
[ 3.912399] hub 2-0:1.0: 1 port detected
[ 3.938977] mmc1: SDHCI controller on ff170000.mmc [ff170000.mmc] using ADMA 64-bit
[ 3.944277] rtc_zynqmp ffa60000.rtc: setting system clock to 1970-01-01T00:00:07 UTC (7)
[ 3.949039] of_cfs_init
[ 3.951483] of_cfs_init: OK
[ 3.954361] cfg80211: Loading compiled-in X.509 certificates for regulatory database
[ 3.978543] mmc1: new high speed SDIO card at address 0001
[ 4.016658] mmc0: error -110 whilst initialising SD card
[ 4.091103] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
[ 4.091983] clk: Not disabling unused clocks
[ 4.096225] ALSA device list:
[ 4.099161] #0: DisplayPort monitor
[ 4.100978] random: fast init done
[ 4.102882] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
[ 4.114735] cfg80211: failed to load regulatory.db
[ 4.119494] Warning: unable to open an initial console.
[ 4.124851] Waiting for root device /dev/mmcblk0p2...
[ 4.190979] usb 1-1: new high-speed USB device number 2 using xhci-hcd
[ 4.339471] usb 1-1: New USB device found, idVendor=0424, idProduct=2744, bcdDevice= 2.05
[ 4.341991] usb 1-1: New USB device strings: Mfr=1, Product=2, SerialNumber=0
[ 4.349090] usb 1-1: Product: USB2744
[ 4.352721] usb 1-1: Manufacturer: Microchip Tech
[ 4.405406] hub 1-1:1.0: USB hub found
[ 4.405480] hub 1-1:1.0: 4 ports detected
[ 4.754976] usb 1-1.1: new high-speed USB device number 3 using xhci-hcd
[ 4.867790] usb 1-1.1: New USB device found, idVendor=0b95, idProduct=1780, bcdDevice= 0.01
[ 4.870486] usb 1-1.1: New USB device strings: Mfr=1, Product=2, SerialNumber=3
[ 4.877768] usb 1-1.1: Product: GU-1000T
[ 4.881651] usb 1-1.1: Manufacturer: PLANEX COM. Inc.
[ 4.886667] usb 1-1.1: SerialNumber: 020707
[ 5.299475] asix 1-1.1:1.0 eth0: register 'asix' at usb-xhci-hcd.0.auto-1.1, ASIX AX88178 USB 2.0 Ethernet, 00:22:cf:00:0c:37
[ 5.382975] usb 1-1.4: new high-speed USB device number 4 using xhci-hcd
[ 5.483665] usb 1-1.4: New USB device found, idVendor=0424, idProduct=2740, bcdDevice= 2.00
[ 5.486358] usb 1-1.4: New USB device strings: Mfr=1, Product=2, SerialNumber=0
[ 5.493639] usb 1-1.4: Product: Hub Controller
[ 5.498042] usb 1-1.4: Manufacturer: Microchip Tech
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