を Vitis HLS の medianblur プロジェクトのディレクトリにコピーした。xf_median_blur_accel.cpp
xf_median_blur_config.h
xf_median_blur_tb.cpp
も Vitis HLS の medianblur プロジェクトのディレクトリにコピーした。xf_config_params.h
をコメントアウトして、#define PTR_WIDTH 128
を追加した。#define PTR_WIDTH 32
を Vitis HLS の sobelfilter プロジェクトのディレクトリにコピーした。xf_sobel_accel.cpp
xf_sobel_config.h
xf_sobel_tb.cpp
も Vitis HLS の sobelfilter プロジェクトのディレクトリにコピーした。xf_config_params.h
1. xf::cv::Array2xfMat() で配列から DMA したピクセルデータを xf::cv::Mat 形式の画像に変換する。
2. その xf::cv::Mat 形式の画像に対して xf::cv::dilate() で 膨張フィルタ処理を行う。
3. 膨張フィルタ処理された xf::cv::Mat の画像を DMA して配列に書く。
xf_dilation_accel.cpp
xf_dilation_config.h
xf_dilation_tb.cpp
も Vitis HLS の dilation プロジェクトのディレクトリにコピーした。xf_config_params.h
#include "opencv2/opencv.hpp"#include "opencv2/imgproc/imgproc.hpp"#include "opencv2/highgui/highgui.hpp"#include "opencv2/imgcodecs/imgcodecs.hpp"
と指定されている。-I<path-to-L1-include-directory> -std=c++0x -I<path-to-opencv-include-folder>
になった。なお、フルパスで入れたのだが、Vitis HLS の Project Settings (dilation) ダイアログ で見える xf_dilation_tb.cpp の CFLAGS は相対パスになっている。-I/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Libraries/vision/L1/include -std=c++0x -I/usr/local/include
と指定されている。-L<path-to-opencv-lib-folder> -lopencv_core -lopencv_imgcodecs -lopencv_imgproc
とした。-L/usr/local/lib -lopencv_core -lopencv_imgcodecs -lopencv_imgproc
/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Libraries/vision/data/128x128.png
とした。-I/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Libraries/vision/L1/include -std=c++0x
/// WDTimer.cpp
// 2020/12/23 by marsee
//
#include <ap_int.h>
int WDTimer(ap_uint<1> *rst_in, volatile ap_uint<1> *rst_out, ap_uint<1> *enable){
#pragma HLS INTERFACE ap_none register port=rst_out
#pragma HLS INTERFACE ap_ctrl_none port=return
ap_uint<20> i;
*rst_out = 0;
for(i=0; i<1048575; i++){
if(*enable == ap_uint<1>(1)){
i = i;
}else{
--i;
continue;
}
if(*rst_in == ap_uint<1>(1))
i = 0;
else
i = i;
if(i>524287){
*rst_out = 1;
--i;
}else{
*rst_out = 0;
}
}
return(0);
}
// ==============================================================
// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL
// Version: 2020.1
// Copyright (C) 1986-2020 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="WDTimer_WDTimer,hls_ip_2020_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020-clg400-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=6.914250,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=27,HLS_SYN_LUT=210,HLS_VERSION=2020_1}" *)
module WDTimer (
ap_clk,
ap_rst,
rst_in,
rst_out,
enable,
ap_return
);
parameter ap_ST_fsm_state1 = 4'd1;
parameter ap_ST_fsm_state2 = 4'd2;
parameter ap_ST_fsm_pp0_stage0 = 4'd4;
parameter ap_ST_fsm_state5 = 4'd8;
input ap_clk;
input ap_rst;
input [0:0] rst_in;
output [0:0] rst_out;
input [0:0] enable;
output [31:0] ap_return;
reg [0:0] rst_out_1_data_reg;
reg [0:0] rst_out_1_data_in;
reg rst_out_1_vld_reg;
reg rst_out_1_vld_in;
reg rst_out_1_ack_in;
reg [19:0] empty_reg_77;
wire [0:0] enable_read_read_fu_64_p2;
(* fsm_encoding = "none" *) reg [3:0] ap_CS_fsm;
wire ap_CS_fsm_state2;
wire [0:0] icmp_ln882_fu_99_p2;
wire ap_CS_fsm_pp0_stage0;
wire ap_block_state3_pp0_stage0_iter0;
wire ap_block_state4_pp0_stage0_iter1;
wire ap_block_pp0_stage0_11001;
wire [0:0] tmp_fu_120_p3;
wire [19:0] add_ln695_fu_135_p2;
reg ap_enable_reg_pp0_iter0;
wire ap_block_pp0_stage0_subdone;
reg ap_condition_pp0_exit_iter0_state3;
reg ap_enable_reg_pp0_iter1;
reg [19:0] ap_phi_mux_empty_11_phi_fu_91_p6;
wire [19:0] add_ln696_fu_105_p2;
wire [19:0] ap_phi_reg_pp0_iter0_empty_11_reg_88;
wire [19:0] select_ln23_fu_112_p3;
wire [19:0] add_ln696_1_fu_128_p2;
wire ap_CS_fsm_state1;
wire ap_block_pp0_stage0_01001;
wire ap_block_pp0_stage0;
wire ap_CS_fsm_state5;
reg [3:0] ap_NS_fsm;
reg ap_idle_pp0;
wire ap_enable_pp0;
// power-on initialization
initial begin
#0 rst_out_1_data_reg = 1'd0;
#0 rst_out_1_vld_reg = 1'b0;
#0 ap_CS_fsm = 4'd1;
#0 ap_enable_reg_pp0_iter0 = 1'b0;
#0 ap_enable_reg_pp0_iter1 = 1'b0;
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter0 <= 1'b0;
end else begin
if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_condition_pp0_exit_iter0_state3) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
ap_enable_reg_pp0_iter0 <= 1'b0;
end else if ((1'b1 == ap_CS_fsm_state2)) begin
ap_enable_reg_pp0_iter0 <= 1'b1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter1 <= 1'b0;
end else begin
if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_condition_pp0_exit_iter0_state3))) begin
ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state3);
end else if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
end else if ((1'b1 == ap_CS_fsm_state2)) begin
ap_enable_reg_pp0_iter1 <= 1'b0;
end
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state2)) begin
empty_reg_77 <= 20'd0;
end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln882_fu_99_p2 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
empty_reg_77 <= add_ln695_fu_135_p2;
end
end
always @ (posedge ap_clk) begin
if ((((1'b1 == 1'b1) & (rst_out_1_vld_in == 1'b1) & (rst_out_1_vld_reg == 1'b1)) | ((rst_out_1_vld_in == 1'b1) & (rst_out_1_vld_reg == 1'b0)))) begin
rst_out_1_data_reg <= rst_out_1_data_in;
end
end
always @ (*) begin
if ((icmp_ln882_fu_99_p2 == 1'd1)) begin
ap_condition_pp0_exit_iter0_state3 = 1'b1;
end else begin
ap_condition_pp0_exit_iter0_state3 = 1'b0;
end
end
always @ (*) begin
if (((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin
ap_idle_pp0 = 1'b1;
end else begin
ap_idle_pp0 = 1'b0;
end
end
always @ (*) begin
if ((icmp_ln882_fu_99_p2 == 1'd0)) begin
if (((tmp_fu_120_p3 == 1'd1) & (enable_read_read_fu_64_p2 == 1'd1))) begin
ap_phi_mux_empty_11_phi_fu_91_p6 = add_ln696_1_fu_128_p2;
end else if (((tmp_fu_120_p3 == 1'd0) & (enable_read_read_fu_64_p2 == 1'd1))) begin
ap_phi_mux_empty_11_phi_fu_91_p6 = select_ln23_fu_112_p3;
end else if ((enable_read_read_fu_64_p2 == 1'd0)) begin
ap_phi_mux_empty_11_phi_fu_91_p6 = add_ln696_fu_105_p2;
end else begin
ap_phi_mux_empty_11_phi_fu_91_p6 = ap_phi_reg_pp0_iter0_empty_11_reg_88;
end
end else begin
ap_phi_mux_empty_11_phi_fu_91_p6 = ap_phi_reg_pp0_iter0_empty_11_reg_88;
end
end
always @ (*) begin
if (((rst_out_1_vld_reg == 1'b0) | ((1'b1 == 1'b1) & (rst_out_1_vld_reg == 1'b1)))) begin
rst_out_1_ack_in = 1'b1;
end else begin
rst_out_1_ack_in = 1'b0;
end
end
always @ (*) begin
if (((ap_enable_reg_pp0_iter0 == 1'b1) & (tmp_fu_120_p3 == 1'd1) & (1'b0 == ap_block_pp0_stage0_01001) & (icmp_ln882_fu_99_p2 == 1'd0) & (enable_read_read_fu_64_p2 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
rst_out_1_data_in = 1'd1;
end else if (((1'b1 == ap_CS_fsm_state1) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (tmp_fu_120_p3 == 1'd0) & (1'b0 == ap_block_pp0_stage0_01001) & (icmp_ln882_fu_99_p2 == 1'd0) & (enable_read_read_fu_64_p2 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage0)))) begin
rst_out_1_data_in = 1'd0;
end else begin
rst_out_1_data_in = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state1) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (tmp_fu_120_p3 == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln882_fu_99_p2 == 1'd0) & (enable_read_read_fu_64_p2 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage0)) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (tmp_fu_120_p3 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln882_fu_99_p2 == 1'd0) & (enable_read_read_fu_64_p2 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage0)))) begin
rst_out_1_vld_in = 1'b1;
end else begin
rst_out_1_vld_in = 1'b0;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1 : begin
ap_NS_fsm = ap_ST_fsm_state2;
end
ap_ST_fsm_state2 : begin
ap_NS_fsm = ap_ST_fsm_pp0_stage0;
end
ap_ST_fsm_pp0_stage0 : begin
if (~((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (icmp_ln882_fu_99_p2 == 1'd1))) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage0;
end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (icmp_ln882_fu_99_p2 == 1'd1))) begin
ap_NS_fsm = ap_ST_fsm_state5;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage0;
end
end
ap_ST_fsm_state5 : begin
if (((1'b1 == ap_CS_fsm_state5) & (rst_out_1_ack_in == 1'b1))) begin
ap_NS_fsm = ap_ST_fsm_state1;
end else begin
ap_NS_fsm = ap_ST_fsm_state5;
end
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
assign add_ln695_fu_135_p2 = (ap_phi_mux_empty_11_phi_fu_91_p6 + 20'd1);
assign add_ln696_1_fu_128_p2 = ($signed(select_ln23_fu_112_p3) + $signed(20'd1048575));
assign add_ln696_fu_105_p2 = ($signed(empty_reg_77) + $signed(20'd1048575));
assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd2];
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
assign ap_CS_fsm_state5 = ap_CS_fsm[32'd3];
assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage0_01001 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1);
assign ap_block_state3_pp0_stage0_iter0 = ~(1'b1 == 1'b1);
assign ap_block_state4_pp0_stage0_iter1 = ~(1'b1 == 1'b1);
assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1);
assign ap_phi_reg_pp0_iter0_empty_11_reg_88 = 'bx;
assign ap_return = 32'd0;
assign enable_read_read_fu_64_p2 = enable;
assign icmp_ln882_fu_99_p2 = ((empty_reg_77 == 20'd1048575) ? 1'b1 : 1'b0);
assign rst_out = rst_out_1_data_reg;
assign select_ln23_fu_112_p3 = ((rst_in[0:0] === 1'b1) ? 20'd0 : empty_reg_77);
assign tmp_fu_120_p3 = select_ln23_fu_112_p3[32'd19];
endmodule //WDTimer
`default_nettype none
`timescale 100ps / 1ps
// WDTimer_tb.v
// 2020/12/24 by marsee
//
module WDTimer_tb;
parameter DELAY = 10;
wire ap_clk;
wire ap_rst;
reg rst_in;
wire rst_out;
wire ap_rst_0;
wire ap_rst_1;
reg enable;
assign ap_rst = ap_rst_0 | ap_rst_1;
WDTimer WDTimer_i(
.ap_clk(ap_clk),
.ap_rst(ap_rst),
.rst_in(rst_in),
.rst_out(rst_out),
.enable(enable),
.ap_return()
);
// clk_gen のインスタンス(ap_clk)
clk_gen #(
.CLK_PERIOD(100), // 10 nsec, 100 MHz
.CLK_DUTY_CYCLE(0.5),
.CLK_OFFSET(0),
.START_STATE(1'b0)
) ACLKi (
.clk_out(ap_clk)
);
// reset_gen のインスタンス
reset_gen #(
.RESET_STATE(1'b1),
.RESET_TIME(1000) // 100nsec
) RESETi (
.reset_out(ap_rst_0),
.init_done()
);
assign ap_rst_1 = rst_out;
initial begin
rst_in = 1'b0;
enable = 1'b0;
#1000 // wait reset
#10000000 // 1 ms wait
enable = 1'b1;
#30000000 // 3 ms wait
@(posedge ap_clk); // 次のクロックへ
#DELAY;
rst_in = 1'b1;
@(posedge ap_clk); // 次のクロックへ
#DELAY;
rst_in = 1'b0;
#70000000 // 7 ms wait
$stop;
end
endmodule
module clk_gen #(
parameter CLK_PERIOD = 100,
parameter real CLK_DUTY_CYCLE = 0.5,
parameter CLK_OFFSET = 0,
parameter START_STATE = 1'b0 )
(
output reg clk_out
);
begin
initial begin
#CLK_OFFSET;
forever
begin
clk_out = START_STATE;
#(CLK_PERIOD-(CLK_PERIOD*CLK_DUTY_CYCLE)) clk_out = ~START_STATE;
#(CLK_PERIOD*CLK_DUTY_CYCLE);
end
end
end
endmodule
module reset_gen #(
parameter RESET_STATE = 1'b1,
parameter RESET_TIME = 100 )
(
output reg reset_out,
output reg init_done
);
begin
initial begin
reset_out = RESET_STATE;
init_done = 1'b0;
#RESET_TIME;
reset_out = ~RESET_STATE;
init_done = 1'b1;
end
end
endmodule
`default_nettype wire
`default_nettype none
`timescale 100ps / 1ps
// WDTimer_tb.v
// 2020/12/24 by marsee
//
module WDTimer_tb;
parameter DELAY = 10;
wire ap_clk;
wire ap_rst;
reg rst_in;
wire rst_out;
wire ap_rst_0;
wire ap_rst_1;
assign ap_rst = ap_rst_0 | ap_rst_1;
WDTimer WDTimer_i(
.ap_clk(ap_clk),
.ap_rst(ap_rst),
.rst_in(rst_in),
.rst_out(rst_out),
.ap_return()
);
// clk_gen のインスタンス(ap_clk)
clk_gen #(
.CLK_PERIOD(100), // 10 nsec, 100 MHz
.CLK_DUTY_CYCLE(0.5),
.CLK_OFFSET(0),
.START_STATE(1'b0)
) ACLKi (
.clk_out(ap_clk)
);
// reset_gen のインスタンス
reset_gen #(
.RESET_STATE(1'b1),
.RESET_TIME(1000) // 100nsec
) RESETi (
.reset_out(ap_rst_0),
.init_done()
);
assign ap_rst_1 = rst_out;
initial begin
rst_in = 1'b0;
#1000 // wait reset
#30000000 // 3 ms wait
@(posedge ap_clk); // 次のクロックへ
#DELAY;
rst_in = 1'b1;
@(posedge ap_clk); // 次のクロックへ
#DELAY;
rst_in = 1'b0;
#70000000 // 7 ms wait
$stop;
end
endmodule
module clk_gen #(
parameter CLK_PERIOD = 100,
parameter real CLK_DUTY_CYCLE = 0.5,
parameter CLK_OFFSET = 0,
parameter START_STATE = 1'b0 )
(
output reg clk_out
);
begin
initial begin
#CLK_OFFSET;
forever
begin
clk_out = START_STATE;
#(CLK_PERIOD-(CLK_PERIOD*CLK_DUTY_CYCLE)) clk_out = ~START_STATE;
#(CLK_PERIOD*CLK_DUTY_CYCLE);
end
end
end
endmodule
module reset_gen #(
parameter RESET_STATE = 1'b1,
parameter RESET_TIME = 100 )
(
output reg reset_out,
output reg init_done
);
begin
initial begin
reset_out = RESET_STATE;
init_done = 1'b0;
#RESET_TIME;
reset_out = ~RESET_STATE;
init_done = 1'b1;
end
end
endmodule
`default_nettype wire
/// WDTimer.cpp
// 2020/12/23 by marsee
//
#include <ap_int.h>
int WDTimer(ap_uint<1> *rst_in, volatile ap_uint<1> *rst_out){
#pragma HLS INTERFACE ap_none register port=rst_out
#pragma HLS INTERFACE ap_ctrl_none port=return
ap_uint<20> i;
*rst_out = 0;
for(i=0; i<1048575; i++){
if(*rst_in == ap_uint<1>(1))
i = 0;
else
i = i;
if(i>524288){
*rst_out = 1;
--i;
}else{
*rst_out = 0;
}
}
return(0);
}
// ==============================================================
// RTL generated by Vitis HLS - High-Level Synthesis from C, C++ and OpenCL
// Version: 2020.1
// Copyright (C) 1986-2020 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="WDTimer_WDTimer,hls_ip_2020_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020-clg400-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=8.522000,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=27,HLS_SYN_LUT=195,HLS_VERSION=2020_1}" *)
module WDTimer (
ap_clk,
ap_rst,
rst_in,
rst_out,
ap_return
);
parameter ap_ST_fsm_state1 = 4'd1;
parameter ap_ST_fsm_state2 = 4'd2;
parameter ap_ST_fsm_pp0_stage0 = 4'd4;
parameter ap_ST_fsm_state5 = 4'd8;
input ap_clk;
input ap_rst;
input [0:0] rst_in;
output [0:0] rst_out;
output [31:0] ap_return;
reg [0:0] rst_out_1_data_reg;
reg [0:0] rst_out_1_data_in;
reg rst_out_1_vld_reg;
reg rst_out_1_vld_in;
reg rst_out_1_ack_in;
reg [19:0] empty_reg_67;
(* fsm_encoding = "none" *) reg [3:0] ap_CS_fsm;
wire ap_CS_fsm_state2;
wire [0:0] icmp_ln882_fu_87_p2;
wire ap_CS_fsm_pp0_stage0;
wire ap_block_state3_pp0_stage0_iter0;
wire ap_block_state4_pp0_stage0_iter1;
wire ap_block_pp0_stage0_11001;
wire [0:0] icmp_ln890_fu_101_p2;
wire [19:0] add_ln695_fu_114_p2;
reg ap_enable_reg_pp0_iter0;
wire ap_block_pp0_stage0_subdone;
reg ap_condition_pp0_exit_iter0_state3;
reg ap_enable_reg_pp0_iter1;
reg [19:0] ap_phi_mux_empty_8_phi_fu_81_p4;
wire [19:0] select_ln16_fu_93_p3;
wire [19:0] ap_phi_reg_pp0_iter0_empty_8_reg_78;
wire [19:0] add_ln696_fu_107_p2;
wire ap_CS_fsm_state1;
wire ap_block_pp0_stage0_01001;
wire ap_block_pp0_stage0;
wire ap_CS_fsm_state5;
reg [3:0] ap_NS_fsm;
reg ap_idle_pp0;
wire ap_enable_pp0;
// power-on initialization
initial begin
#0 rst_out_1_data_reg = 1'd0;
#0 rst_out_1_vld_reg = 1'b0;
#0 ap_CS_fsm = 4'd1;
#0 ap_enable_reg_pp0_iter0 = 1'b0;
#0 ap_enable_reg_pp0_iter1 = 1'b0;
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter0 <= 1'b0;
end else begin
if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_condition_pp0_exit_iter0_state3) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
ap_enable_reg_pp0_iter0 <= 1'b0;
end else if ((1'b1 == ap_CS_fsm_state2)) begin
ap_enable_reg_pp0_iter0 <= 1'b1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter1 <= 1'b0;
end else begin
if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_condition_pp0_exit_iter0_state3))) begin
ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state3);
end else if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
end else if ((1'b1 == ap_CS_fsm_state2)) begin
ap_enable_reg_pp0_iter1 <= 1'b0;
end
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state2)) begin
empty_reg_67 <= 20'd0;
end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln882_fu_87_p2 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
empty_reg_67 <= add_ln695_fu_114_p2;
end
end
always @ (posedge ap_clk) begin
if ((((1'b1 == 1'b1) & (rst_out_1_vld_in == 1'b1) & (rst_out_1_vld_reg == 1'b1)) | ((rst_out_1_vld_in == 1'b1) & (rst_out_1_vld_reg == 1'b0)))) begin
rst_out_1_data_reg <= rst_out_1_data_in;
end
end
always @ (*) begin
if ((icmp_ln882_fu_87_p2 == 1'd1)) begin
ap_condition_pp0_exit_iter0_state3 = 1'b1;
end else begin
ap_condition_pp0_exit_iter0_state3 = 1'b0;
end
end
always @ (*) begin
if (((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin
ap_idle_pp0 = 1'b1;
end else begin
ap_idle_pp0 = 1'b0;
end
end
always @ (*) begin
if ((icmp_ln882_fu_87_p2 == 1'd0)) begin
if ((icmp_ln890_fu_101_p2 == 1'd1)) begin
ap_phi_mux_empty_8_phi_fu_81_p4 = add_ln696_fu_107_p2;
end else if ((icmp_ln890_fu_101_p2 == 1'd0)) begin
ap_phi_mux_empty_8_phi_fu_81_p4 = select_ln16_fu_93_p3;
end else begin
ap_phi_mux_empty_8_phi_fu_81_p4 = ap_phi_reg_pp0_iter0_empty_8_reg_78;
end
end else begin
ap_phi_mux_empty_8_phi_fu_81_p4 = ap_phi_reg_pp0_iter0_empty_8_reg_78;
end
end
always @ (*) begin
if (((rst_out_1_vld_reg == 1'b0) | ((1'b1 == 1'b1) & (rst_out_1_vld_reg == 1'b1)))) begin
rst_out_1_ack_in = 1'b1;
end else begin
rst_out_1_ack_in = 1'b0;
end
end
always @ (*) begin
if (((ap_enable_reg_pp0_iter0 == 1'b1) & (icmp_ln890_fu_101_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_01001) & (icmp_ln882_fu_87_p2 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
rst_out_1_data_in = 1'd1;
end else if (((1'b1 == ap_CS_fsm_state1) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (icmp_ln890_fu_101_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_01001) & (icmp_ln882_fu_87_p2 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0)))) begin
rst_out_1_data_in = 1'd0;
end else begin
rst_out_1_data_in = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state1) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (icmp_ln890_fu_101_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln882_fu_87_p2 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0)) | ((ap_enable_reg_pp0_iter0 == 1'b1) & (icmp_ln890_fu_101_p2 == 1'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln882_fu_87_p2 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0)))) begin
rst_out_1_vld_in = 1'b1;
end else begin
rst_out_1_vld_in = 1'b0;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1 : begin
ap_NS_fsm = ap_ST_fsm_state2;
end
ap_ST_fsm_state2 : begin
ap_NS_fsm = ap_ST_fsm_pp0_stage0;
end
ap_ST_fsm_pp0_stage0 : begin
if (~((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (icmp_ln882_fu_87_p2 == 1'd1))) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage0;
end else if (((ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone) & (icmp_ln882_fu_87_p2 == 1'd1))) begin
ap_NS_fsm = ap_ST_fsm_state5;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage0;
end
end
ap_ST_fsm_state5 : begin
if (((1'b1 == ap_CS_fsm_state5) & (rst_out_1_ack_in == 1'b1))) begin
ap_NS_fsm = ap_ST_fsm_state1;
end else begin
ap_NS_fsm = ap_ST_fsm_state5;
end
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
assign add_ln695_fu_114_p2 = (ap_phi_mux_empty_8_phi_fu_81_p4 + 20'd1);
assign add_ln696_fu_107_p2 = ($signed(select_ln16_fu_93_p3) + $signed(20'd1048575));
assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd2];
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
assign ap_CS_fsm_state5 = ap_CS_fsm[32'd3];
assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage0_01001 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1);
assign ap_block_state3_pp0_stage0_iter0 = ~(1'b1 == 1'b1);
assign ap_block_state4_pp0_stage0_iter1 = ~(1'b1 == 1'b1);
assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1);
assign ap_phi_reg_pp0_iter0_empty_8_reg_78 = 'bx;
assign ap_return = 32'd0;
assign icmp_ln882_fu_87_p2 = ((empty_reg_67 == 20'd1048575) ? 1'b1 : 1'b0);
assign icmp_ln890_fu_101_p2 = ((select_ln16_fu_93_p3 > 20'd524288) ? 1'b1 : 1'b0);
assign rst_out = rst_out_1_data_reg;
assign select_ln16_fu_93_p3 = ((rst_in[0:0] === 1'b1) ? 20'd0 : empty_reg_67);
endmodule //WDTimer
masaaki@masaaki-H110M4-M01:/media/masaaki/Ubuntu_Disk/OpenCV/src/opencv/build$ sudo make install
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-- Installing: /usr/local/include/opencv2/video.hpp
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-- Installing: /usr/local/lib/libopencv_xphoto.so.3.4.9
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-- Installing: /usr/local/include/opencv2/xphoto.hpp
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-- Installing: /usr/local/share/OpenCV/samples/xphoto/bm3d_image_denoising.cpp
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-- Installing: /usr/local/share/OpenCV/samples/line_descriptor/compute_descriptors.cpp
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-- Installing: /usr/local/include/opencv2/shape/shape_distance.hpp
-- Installing: /usr/local/include/opencv2/shape/shape_transformer.hpp
-- Installing: /usr/local/lib/libopencv_text.so.3.4.9
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-- Installing: /usr/local/lib/libopencv_text.so
-- Installing: /usr/local/include/opencv2/text.hpp
-- Installing: /usr/local/include/opencv2/text/erfilter.hpp
-- Installing: /usr/local/include/opencv2/text/ocr.hpp
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-- Up-to-date: /usr/local/share/OpenCV/samples/text
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-- Installing: /usr/local/lib/libopencv_videoio.so
-- Installing: /usr/local/include/opencv2/videoio.hpp
-- Installing: /usr/local/include/opencv2/videoio/registry.hpp
-- Installing: /usr/local/include/opencv2/videoio/videoio.hpp
-- Installing: /usr/local/include/opencv2/videoio/cap_ios.h
-- Installing: /usr/local/include/opencv2/videoio/videoio_c.h
-- Installing: /usr/local/lib/libopencv_calib3d.so.3.4.9
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-- Installing: /usr/local/share/OpenCV/samples/cpp/detect_mser.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/dft.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/digits.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/distrans.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/drawing.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/edge.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/em.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/facedetect.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/facial_features.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/falsecolor.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/fback.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/ffilldemo.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/filestorage.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/fitellipse.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/grabcut.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/image.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/image_alignment.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/imagelist_creator.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/imagelist_reader.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/inpaint.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/intersectExample.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/kalman.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/kmeans.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/laplace.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/letter_recog.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/lkdemo.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/logistic_regression.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/mask_tmpl.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/matchmethod_orb_akaze_brisk.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/minarea.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/morphology2.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/neural_network.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/npr_demo.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/opencv_version.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/pca.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/peopledetect.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/phase_corr.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/points_classifier.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/polar_transforms.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/qrcode.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/segment_objects.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/select3dobj.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/shape_example.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/simd_basic.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/smiledetect.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/squares.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/stereo_calib.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/stereo_match.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/stitching.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/stitching_detailed.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/train_HOG.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/train_svmsgd.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/travelsalesman.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/tree_engine.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/tvl1_optical_flow.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/videocapture_basic.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/videocapture_camera.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/videocapture_gphoto2_autofocus.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/videocapture_gstreamer_pipeline.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/videocapture_image_sequence.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/videocapture_intelperc.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/videocapture_openni.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/videocapture_starter.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/videostab.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/videowriter_basic.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/warpPerspective_demo.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/watershed.cpp
-- Installing: /usr/local/share/OpenCV/samples/cpp/CMakeLists.txt
-- Installing: /usr/local/share/OpenCV/samples/dnn/classification.cpp
-- Installing: /usr/local/share/OpenCV/samples/dnn/colorization.cpp
-- Installing: /usr/local/share/OpenCV/samples/dnn/object_detection.cpp
-- Installing: /usr/local/share/OpenCV/samples/dnn/openpose.cpp
-- Installing: /usr/local/share/OpenCV/samples/dnn/segmentation.cpp
-- Installing: /usr/local/share/OpenCV/samples/dnn/text_detection.cpp
-- Installing: /usr/local/share/OpenCV/samples/dnn/common.hpp
-- Installing: /usr/local/share/OpenCV/samples/dnn/custom_layers.hpp
-- Installing: /usr/local/share/OpenCV/samples/dnn/CMakeLists.txt
-- Installing: /usr/local/share/OpenCV/samples/gpu/alpha_comp.cpp
-- Installing: /usr/local/share/OpenCV/samples/gpu/bgfg_segm.cpp
-- Installing: /usr/local/share/OpenCV/samples/gpu/cascadeclassifier.cpp
-- Installing: /usr/local/share/OpenCV/samples/gpu/farneback_optical_flow.cpp
-- Installing: /usr/local/share/OpenCV/samples/gpu/generalized_hough.cpp
-- Installing: /usr/local/share/OpenCV/samples/gpu/hog.cpp
-- Installing: /usr/local/share/OpenCV/samples/gpu/houghlines.cpp
-- Installing: /usr/local/share/OpenCV/samples/gpu/morphology.cpp
-- Installing: /usr/local/share/OpenCV/samples/gpu/multi.cpp
-- Installing: /usr/local/share/OpenCV/samples/gpu/optical_flow.cpp
-- Installing: /usr/local/share/OpenCV/samples/gpu/pyrlk_optical_flow.cpp
-- Installing: /usr/local/share/OpenCV/samples/gpu/stereo_match.cpp
-- Installing: /usr/local/share/OpenCV/samples/gpu/stereo_multi.cpp
-- Installing: /usr/local/share/OpenCV/samples/gpu/super_resolution.cpp
-- Installing: /usr/local/share/OpenCV/samples/gpu/surf_keypoint_matcher.cpp
-- Installing: /usr/local/share/OpenCV/samples/gpu/video_reader.cpp
-- Installing: /usr/local/share/OpenCV/samples/gpu/video_writer.cpp
-- Installing: /usr/local/share/OpenCV/samples/gpu/CMakeLists.txt
-- Installing: /usr/local/share/OpenCV/samples/tapi/bgfg_segm.cpp
-- Installing: /usr/local/share/OpenCV/samples/tapi/camshift.cpp
-- Installing: /usr/local/share/OpenCV/samples/tapi/clahe.cpp
-- Installing: /usr/local/share/OpenCV/samples/tapi/dense_optical_flow.cpp
-- Installing: /usr/local/share/OpenCV/samples/tapi/hog.cpp
-- Installing: /usr/local/share/OpenCV/samples/tapi/opencl_custom_kernel.cpp
-- Installing: /usr/local/share/OpenCV/samples/tapi/pyrlk_optical_flow.cpp
-- Installing: /usr/local/share/OpenCV/samples/tapi/squares.cpp
-- Installing: /usr/local/share/OpenCV/samples/tapi/ufacedetect.cpp
-- Installing: /usr/local/share/OpenCV/samples/tapi/CMakeLists.txt
-- Installing: /usr/local/share/OpenCV/samples/opencl/opencl-opencv-interop.cpp
-- Installing: /usr/local/share/OpenCV/samples/opencl/CMakeLists.txt
-- Installing: /usr/local/share/OpenCV/samples/python/_coverage.py
-- Installing: /usr/local/share/OpenCV/samples/python/_doc.py
-- Installing: /usr/local/share/OpenCV/samples/python/asift.py
-- Installing: /usr/local/share/OpenCV/samples/python/browse.py
-- Installing: /usr/local/share/OpenCV/samples/python/calibrate.py
-- Installing: /usr/local/share/OpenCV/samples/python/camera_calibration_show_extrinsics.py
-- Installing: /usr/local/share/OpenCV/samples/python/camshift.py
-- Installing: /usr/local/share/OpenCV/samples/python/coherence.py
-- Installing: /usr/local/share/OpenCV/samples/python/color_histogram.py
-- Installing: /usr/local/share/OpenCV/samples/python/common.py
-- Installing: /usr/local/share/OpenCV/samples/python/contours.py
-- Installing: /usr/local/share/OpenCV/samples/python/deconvolution.py
-- Installing: /usr/local/share/OpenCV/samples/python/demo.py
-- Installing: /usr/local/share/OpenCV/samples/python/dft.py
-- Installing: /usr/local/share/OpenCV/samples/python/digits.py
-- Installing: /usr/local/share/OpenCV/samples/python/digits_adjust.py
-- Installing: /usr/local/share/OpenCV/samples/python/digits_video.py
-- Installing: /usr/local/share/OpenCV/samples/python/distrans.py
-- Installing: /usr/local/share/OpenCV/samples/python/edge.py
-- Installing: /usr/local/share/OpenCV/samples/python/facedetect.py
-- Installing: /usr/local/share/OpenCV/samples/python/feature_homography.py
-- Installing: /usr/local/share/OpenCV/samples/python/find_obj.py
-- Installing: /usr/local/share/OpenCV/samples/python/fitline.py
-- Installing: /usr/local/share/OpenCV/samples/python/floodfill.py
-- Installing: /usr/local/share/OpenCV/samples/python/gabor_threads.py
-- Installing: /usr/local/share/OpenCV/samples/python/gaussian_mix.py
-- Installing: /usr/local/share/OpenCV/samples/python/grabcut.py
-- Installing: /usr/local/share/OpenCV/samples/python/hist.py
-- Installing: /usr/local/share/OpenCV/samples/python/houghcircles.py
-- Installing: /usr/local/share/OpenCV/samples/python/houghlines.py
-- Installing: /usr/local/share/OpenCV/samples/python/inpaint.py
-- Installing: /usr/local/share/OpenCV/samples/python/kalman.py
-- Installing: /usr/local/share/OpenCV/samples/python/kmeans.py
-- Installing: /usr/local/share/OpenCV/samples/python/lappyr.py
-- Installing: /usr/local/share/OpenCV/samples/python/letter_recog.py
-- Installing: /usr/local/share/OpenCV/samples/python/lk_homography.py
-- Installing: /usr/local/share/OpenCV/samples/python/lk_track.py
-- Installing: /usr/local/share/OpenCV/samples/python/logpolar.py
-- Installing: /usr/local/share/OpenCV/samples/python/morphology.py
-- Installing: /usr/local/share/OpenCV/samples/python/mosse.py
-- Installing: /usr/local/share/OpenCV/samples/python/mouse_and_match.py
-- Installing: /usr/local/share/OpenCV/samples/python/mser.py
-- Installing: /usr/local/share/OpenCV/samples/python/opencv_version.py
-- Installing: /usr/local/share/OpenCV/samples/python/opt_flow.py
-- Installing: /usr/local/share/OpenCV/samples/python/peopledetect.py
-- Installing: /usr/local/share/OpenCV/samples/python/plane_ar.py
-- Installing: /usr/local/share/OpenCV/samples/python/plane_tracker.py
-- Installing: /usr/local/share/OpenCV/samples/python/squares.py
-- Installing: /usr/local/share/OpenCV/samples/python/stereo_match.py
-- Installing: /usr/local/share/OpenCV/samples/python/texture_flow.py
-- Installing: /usr/local/share/OpenCV/samples/python/tst_scene_render.py
-- Installing: /usr/local/share/OpenCV/samples/python/turing.py
-- Installing: /usr/local/share/OpenCV/samples/python/video.py
-- Installing: /usr/local/share/OpenCV/samples/python/video_threaded.py
-- Installing: /usr/local/share/OpenCV/samples/python/video_v4l2.py
-- Installing: /usr/local/share/OpenCV/samples/python/watershed.py
// reverse_rgb.h
// 2020/12/16 by marsee
//
#ifndef __REVERSE_RGB_H__
#define __REVERSE_RGB_H__
#define HORIZONTAL_PIXEL_WIDTH 800
#define VERTICAL_PIXEL_WIDTH 600
#define REVERSE_RED false
#define REVERSE_GREEN true
#define REVERSE_BLUE true
#endif
// reverse_rgb.cpp
// 2020/12/16 by marsee
// data format: 8'd0, Red[8:0], Green[8], Blue[8]
//
#include <stdio.h>
#include <string.h>
#include <ap_int.h>
#include <hls_stream.h>
#include <ap_axi_sdata.h>
#include "reverse_rgb.h"
int reverse_rgb(hls::stream<ap_axis<32,1,1,1> >& ins, hls::stream<ap_axis<32,1,1,1> >& outs){
#pragma HLS INTERFACE axis register_mode=both register port=outs
#pragma HLS INTERFACE axis register_mode=both register port=ins
//#pragma HLS INTERFACE ap_ctrl_hs port=return
#pragma HLS INTERFACE ap_ctrl_none port=return
ap_axis<32,1,1,1> pix, rev_pix;
LOOP_WAIT: do{ // wait if user signal = 1
#pragma HLS LOOP_TRIPCOUNT min=1 max=1 avg=1
ins >> pix;
} while(pix.user == 0);
LOOP_Y: for(int y=0; y<VERTICAL_PIXEL_WIDTH; y++){
LOOP_X: for(int x=0; x<HORIZONTAL_PIXEL_WIDTH; x++){
#pragma HLS PIPELINE II=1
if (!(x==0 && y==0)) // The first input has already been entered
ins >> pix; // Input from AXI4-Stream
if(REVERSE_RED == true)
rev_pix.data = (~pix.data) & 0xff0000;
else
rev_pix.data = pix.data & 0xff0000;
if(REVERSE_GREEN == true)
rev_pix.data |= (~pix.data) & 0xff00;
else
rev_pix.data |= pix.data & 0xff00;
if(REVERSE_BLUE == true)
rev_pix.data |= (~pix.data) & 0xff;
else
rev_pix.data |= pix.data & 0xff;
rev_pix.user = pix.user;
rev_pix.last = pix.last;
outs << rev_pix;
}
}
return(0);
}
// reverse_rgb_tb.cpp
// 2020/12/16 by marsee
//
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <ap_int.h>
#include <hls_stream.h>
#include <iostream>
#include <fstream>
#include <ap_axi_sdata.h>
#include "reverse_rgb.h"
int reverse_rgb(hls::stream<ap_axis<32,1,1,1> >& ins, hls::stream<ap_axis<32,1,1,1> >& outs);
int reverse_rgb_soft(hls::stream<ap_axis<32,1,1,1> >& ins, hls::stream<ap_axis<32,1,1,1> >& outs);
int main(){
using namespace std;
hls::stream<ap_axis<32,1,1,1> > ins;
hls::stream<ap_axis<32,1,1,1> > ins_soft;
hls::stream<ap_axis<32,1,1,1> > outs;
hls::stream<ap_axis<32,1,1,1> > outs_soft;
ap_axis<32,1,1,1> pix;
ap_axis<32,1,1,1> vals;
ap_axis<32,1,1,1> vals_soft;
int xy;
// Prepare input data in ins and ins_soft
for(int i=0; i<5; i++){ // dummy data
pix.user = 0;
pix.last = 0;
pix.data = i;
ins << pix;
ins_soft << pix;
}
for(int y=0; y<VERTICAL_PIXEL_WIDTH; y++){
for(int x=0; x<HORIZONTAL_PIXEL_WIDTH; x++){
xy = x*(y+1);
pix.data = xy & 0xffffff;
if(y==0 && x==0)
pix.user = 1;
else
pix.user = 0;
if(x == HORIZONTAL_PIXEL_WIDTH-1)
pix.last = 1;
else
pix.last = 0;
ins << pix;
ins_soft << pix;
}
}
reverse_rgb(ins, outs);
reverse_rgb_soft(ins_soft, outs_soft);
// Checking hardware and software values
cout << endl;
cout << "outs" << endl;
for(int y=0; y<VERTICAL_PIXEL_WIDTH; y++){
for(int x=0; x<HORIZONTAL_PIXEL_WIDTH; x++){
outs >> vals;
outs_soft >> vals_soft;
ap_int<32> val = vals.data;
ap_int<32> val_soft = vals_soft.data;
if(val != val_soft){
printf("ERROR HW and SW results mismatch x = %ld, y = %ld, HW = %x, SW = %x\n", x, y, (int)val, (int)val_soft);
return(1);
}
printf("x = %ld, y = %ld, xy = %x, HW = %x, SW = %x\n", x, y, (x*(y+1)&0xffffff), (int)val, (int)val_soft);
}
}
cout << "Success HW and SW results match" << endl;
cout << endl;
return(0);
}
int reverse_rgb_soft(hls::stream<ap_axis<32,1,1,1> >& ins, hls::stream<ap_axis<32,1,1,1> >& outs){
ap_axis<32,1,1,1> pix, rev_pix;
do{ // wait if user signal = 1
ins >> pix;
} while(pix.user == 0);
for(int y=0; y<VERTICAL_PIXEL_WIDTH; y++){
for(int x=0; x<HORIZONTAL_PIXEL_WIDTH; x++){
if (!(x==0 && y==0)) // The first input has already been entered
ins >> pix; // Input from AXI4-Stream
if(REVERSE_RED == true)
rev_pix.data = (~pix.data) & 0xff0000;
else
rev_pix.data = pix.data & 0xff0000;
if(REVERSE_GREEN == true)
rev_pix.data |= (~pix.data) & 0xff00;
else
rev_pix.data |= pix.data & 0xff00;
if(REVERSE_BLUE == true)
rev_pix.data |= (~pix.data) & 0xff;
else
rev_pix.data |= pix.data & 0xff;
rev_pix.user = pix.user;
rev_pix.last = pix.last;
outs << rev_pix;
}
}
return(0);
}
/*
* lap_filter_axis_test.c
*
* Created on: 2020/12/13
* Author: marsee
*/
#include <stdio.h>
#include "xil_io.h"
#include "xparameters.h"
#include "xlap_filter_axis.h"
#include "xdma2axis.h"
#include "xaxis2dma2st.h"
#include "bmp_data.h"
#define FRAME_BUFFER_ADDRESS 0x8000000
#define DMA_DEST_ADDRESS 0x8200000
#define HORIZONTAL_PIXELS 800
#define VERTICAL_LINES 600
int bmp_write(unsigned int addr);
void Xil_DCacheFlush(void);
int main(){
XLap_filter_axis xlf_axis_ap;
XDma2axis xdma2axis_ap;
XAxis2dma2st xaxis2dma_ap;
int inbyte_in;
XLap_filter_axis_Initialize(&xlf_axis_ap, 0);
XDma2axis_Initialize(&xdma2axis_ap, 0);
XAxis2dma2st_Initialize(&xaxis2dma_ap, 0);
XDma2axis_Set_y_size(&xdma2axis_ap, (u32)VERTICAL_LINES);
XDma2axis_Set_x_size(&xdma2axis_ap, (u32)HORIZONTAL_PIXELS);
XDma2axis_Set_sel(&xdma2axis_ap, (u32)0);
XDma2axis_Set_in_V(&xdma2axis_ap, (u32)FRAME_BUFFER_ADDRESS);
XAxis2dma2st_Set_y_size(&xaxis2dma_ap, (u32)VERTICAL_LINES);
XAxis2dma2st_Set_x_size(&xaxis2dma_ap, (u32)HORIZONTAL_PIXELS);
XAxis2dma2st_Set_sel(&xaxis2dma_ap, (u32)0);
XAxis2dma2st_Set_out_V(&xaxis2dma_ap, (u32)DMA_DEST_ADDRESS);
bmp_write(FRAME_BUFFER_ADDRESS);
Xil_DCacheFlush();
XAxis2dma2st_Start(&xaxis2dma_ap);
XLap_filter_axis_Start(&xlf_axis_ap);
XDma2axis_Start(&xdma2axis_ap);
Xil_Out32(XPAR_BITMAP_DISP_CNTRLER_0_BASEADDR, DMA_DEST_ADDRESS);
while(1){
printf("\nPlease input <0> or <1> (<q> : exit) = ");
fflush(stdout);
inbyte_in = inbyte();
printf("%c", inbyte_in);
fflush(stdout);
switch(inbyte_in) {
case '0': //bmp image
XDma2axis_Set_sel(&xdma2axis_ap, (u32)0);
XAxis2dma2st_Set_sel(&xaxis2dma_ap, (u32)0);
XAxis2dma2st_Start(&xaxis2dma_ap);
XLap_filter_axis_Start(&xlf_axis_ap);
XDma2axis_Start(&xdma2axis_ap);
break;
case '1': // Laplacian filter
XDma2axis_Set_sel(&xdma2axis_ap, (u32)1);
XAxis2dma2st_Set_sel(&xaxis2dma_ap, (u32)1);
XAxis2dma2st_Start(&xaxis2dma_ap);
XLap_filter_axis_Start(&xlf_axis_ap);
XDma2axis_Start(&xdma2axis_ap);
break;
case 'q': // exit
return(0);
}
}
}
int bmp_write(unsigned int addr){
for(int y=0; y<VERTICAL_LINES; y++){
for(int x=0; x<HORIZONTAL_PIXELS; x++){
Xil_Out32(addr+(y*HORIZONTAL_PIXELS+x)*sizeof(int),
((int)bmp_file_array[y][x][2]<<16)+((int)bmp_file_array[y][x][1]<<8)+(int)bmp_file_array[y][x][0]);
}
}
return(0);
}
set_false_path -from [get_clocks -of_objects [get_pins lap_filter_axis_bd_i/bitmap_disp_cntrler_0/inst/dvi_disp_i/BUFR_pixel_clk_io/O]] -to [get_clocks clk_fpga_0]
//
// lap_filter_axis.cpp
// 2015/05/01
// 2015/06/25 : 修正、ラプラシアンフィルタの値が青だけになっていたので、RGBに拡張した
// 2020/12/12 : 修正、ラプラシアンフィルタをマイナスのエッジを表示するように変更した
//
#include <stdio.h>
#include <string.h>
#include <ap_int.h>
#include <hls_stream.h>
#include <ap_axi_sdata.h>
#include "lap_filter_axis.h"
int laplacian_fil(int x0y0, int x1y0, int x2y0, int x0y1, int x1y1, int x2y1, int x0y2, int x1y2, int x2y2);
int conv_rgb2y(int rgb);
int lap_filter_axis(hls::stream<ap_axis<32,1,1,1> >& ins, hls::stream<ap_axis<32,1,1,1> >& outs){
#pragma HLS INTERFACE axis register both port=ins
#pragma HLS INTERFACE axis register both port=outs
#pragma HLS INTERFACE s_axilite port=return
ap_axis<32,1,1,1> pix;
ap_axis<32,1,1,1> lap;
unsigned int line_buf[2][HORIZONTAL_PIXEL_WIDTH];
#pragma HLS array_partition variable=line_buf block factor=2 dim=1
#pragma HLS resource variable=line_buf core=RAM_2P
int pix_mat[3][3];
#pragma HLS array_partition variable=pix_mat complete
int lap_fil_val;
Loop1 : do { // user が 1になった時にフレームがスタートする
#pragma HLS LOOP_TRIPCOUNT min=1 max=1 avg=1
ins >> pix;
} while(pix.user == 0);
Loop2 : for (int y=0; y<VERTICAL_PIXEL_WIDTH; y++){
Loop3 : for (int x=0; x<HORIZONTAL_PIXEL_WIDTH; x++){
#pragma HLS PIPELINE II=1
if (!(x==0 && y==0)) // 最初の入力はすでに入力されている
ins >> pix; // AXI4-Stream からの入力
Loop4 : for (int k=0; k<3; k++){
Loop5 : for (int m=0; m<2; m++){
#pragma HLS UNROLL
pix_mat[k][m] = pix_mat[k][m+1];
}
}
pix_mat[0][2] = line_buf[0][x];
pix_mat[1][2] = line_buf[1][x];
int y_val = conv_rgb2y(pix.data);
pix_mat[2][2] = y_val;
line_buf[0][x] = line_buf[1][x]; // 行の入れ替え
line_buf[1][x] = y_val;
lap_fil_val = laplacian_fil( pix_mat[0][0], pix_mat[0][1], pix_mat[0][2],
pix_mat[1][0], pix_mat[1][1], pix_mat[1][2],
pix_mat[2][0], pix_mat[2][1], pix_mat[2][2]);
lap.data = (lap_fil_val<<16)+(lap_fil_val<<8)+lap_fil_val; // RGB同じ値を入れる
if (x<2 || y<2) // 最初の2行とその他の行の最初の2列は無効データなので0とする
lap.data = 0;
if (x==0 && y==0) // 最初のデータでは、TUSERをアサートする
lap.user = 1;
else
lap.user = 0;
if (x == (HORIZONTAL_PIXEL_WIDTH-1)) // 行の最後で TLAST をアサートする
lap.last = 1;
else
lap.last = 0;
outs << lap; // AXI4-Stream へ出力
}
}
return 0;
}
// RGBからYへの変換
// RGBのフォーマットは、{8'd0, R(8bits), G(8bits), B(8bits)}, 1pixel = 32bits
// 輝度信号Yのみに変換する。変換式は、Y = 0.299R + 0.587G + 0.114B
// "YUVフォーマット及び YUV<->RGB変換"を参考にした。http://vision.kuee.kyoto-u.ac.jp/~hiroaki/firewire/yuv.html
// 2013/09/27 : float を止めて、すべてint にした
int conv_rgb2y(int rgb){
int r, g, b, y_f;
int y;
b = rgb & 0xff;
g = (rgb>>8) & 0xff;
r = (rgb>>16) & 0xff;
y_f = 77*r + 150*g + 29*b; //y_f = 0.299*r + 0.587*g + 0.114*b;の係数に256倍した
y = y_f >> 8; // 256で割る
return(y);
}
// ラプラシアンフィルタ
// x0y0 x1y0 x2y0 -1 -1 -1
// x0y1 x1y1 x2y1 -1 8 -1
// x0y2 x1y2 x2y2 -1 -1 -1
int laplacian_fil(int x0y0, int x1y0, int x2y0, int x0y1, int x1y1, int x2y1, int x0y2, int x1y2, int x2y2)
{
int y;
y = -x0y0 -x1y0 -x2y0 -x0y1 +8*x1y1 -x2y1 -x0y2 -x1y2 -x2y2;
if (y<0)
y = -y;
else if (y>255)
y = 255;
return(y);
}
// lap_filter_axis.h
// 2015/05/01
//#define HORIZONTAL_PIXEL_WIDTH 800
//#define VERTICAL_PIXEL_WIDTH 600
#define HORIZONTAL_PIXEL_WIDTH 64
#define VERTICAL_PIXEL_WIDTH 48
#define ALL_PIXEL_VALUE (HORIZONTAL_PIXEL_WIDTH*VERTICAL_PIXEL_WIDTH)
// bmp_header.h
// BMP ファイルフォーマットから引用させて頂きました
// http://www.kk.iij4u.or.jp/~kondo/bmp/
//
// 2017/05/04 : takseiさんのご指摘によりintX_tを使った宣言に変更。takseiさんありがとうございました
// 変数の型のサイズの違いによってLinuxの64ビット版では動作しなかったためです
// http://marsee101.blog19.fc2.com/blog-entry-3354.html#comment2808
//
#include <stdio.h>
#include <stdint.h>
// BITMAPFILEHEADER 14bytes
typedef struct tagBITMAPFILEHEADER {
uint16_t bfType;
uint32_t bfSize;
uint16_t bfReserved1;
uint16_t bfReserved2;
uint32_t bfOffBits;
} BITMAPFILEHEADER;
// BITMAPINFOHEADER 40bytes
typedef struct tagBITMAPINFOHEADER{
uint32_t biSize;
int32_t biWidth;
int32_t biHeight;
uint16_t biPlanes;
uint16_t biBitCount;
uint32_t biCompression;
uint32_t biSizeImage;
int32_t biXPixPerMeter;
int32_t biYPixPerMeter;
uint32_t biClrUsed;
uint32_t biClrImporant;
} BITMAPINFOHEADER;
typedef struct BMP24bitsFORMAT {
uint8_t blue;
uint8_t green;
uint8_t red;
} BMP24FORMAT;
// lap_filter_axis_tb.cpp
// 2015/05/01
// 2015/08/17 : BMPファイルを読み書きするように変更した
// 2020/12/12 : 修正、ラプラシアンフィルタをマイナスのエッジを表示するように変更した
//
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <ap_int.h>
#include <hls_stream.h>
#include <iostream>
#include <fstream>
#include <ap_axi_sdata.h>
#include "lap_filter_axis.h"
#include "bmp_header.h"
int lap_filter_axis(hls::stream<ap_axis<32,1,1,1> >& ins, hls::stream<ap_axis<32,1,1,1> >& outs);
int laplacian_fil_soft(int x0y0, int x1y0, int x2y0, int x0y1, int x1y1, int x2y1, int x0y2, int x1y2, int x2y2);
int conv_rgb2y_soft(int rgb);
int lap_filter_axis_soft(hls::stream<ap_axis<32,1,1,1> >& ins, hls::stream<ap_axis<32,1,1,1> >& outs, int width, int height);
#define CLOCK_PERIOD 10
int main()
{
using namespace std;
hls::stream<ap_axis<32,1,1,1> > ins;
hls::stream<ap_axis<32,1,1,1> > ins_soft;
hls::stream<ap_axis<32,1,1,1> > outs;
hls::stream<ap_axis<32,1,1,1> > outs_soft;
ap_axis<32,1,1,1> pix;
ap_axis<32,1,1,1> vals;
ap_axis<32,1,1,1> vals_soft;
BITMAPFILEHEADER bmpfhr; // BMPファイルのファイルヘッダ(for Read)
BITMAPINFOHEADER bmpihr; // BMPファイルのINFOヘッダ(for Read)
FILE *fbmpr, *fbmpw;
int *rd_bmp, *hw_lapd;
int blue, green, red;
if ((fbmpr = fopen("test.bmp", "rb")) == NULL){ // test.bmp をオープン
fprintf(stderr, "Can't open test.bmp by binary read mode\n");
exit(1);
}
// bmpヘッダの読み出し
fread(&bmpfhr.bfType, sizeof(uint16_t), 1, fbmpr);
fread(&bmpfhr.bfSize, sizeof(uint32_t), 1, fbmpr);
fread(&bmpfhr.bfReserved1, sizeof(uint16_t), 1, fbmpr);
fread(&bmpfhr.bfReserved2, sizeof(uint16_t), 1, fbmpr);
fread(&bmpfhr.bfOffBits, sizeof(uint32_t), 1, fbmpr);
fread(&bmpihr, sizeof(BITMAPINFOHEADER), 1, fbmpr);
// ピクセルを入れるメモリをアロケートする
if ((rd_bmp =(int *)malloc(sizeof(int) * (bmpihr.biWidth * bmpihr.biHeight))) == NULL){
fprintf(stderr, "Can't allocate rd_bmp memory\n");
exit(1);
}
if ((hw_lapd =(int *)malloc(sizeof(int) * (bmpihr.biWidth * bmpihr.biHeight))) == NULL){
fprintf(stderr, "Can't allocate hw_lapd memory\n");
exit(1);
}
// rd_bmp にBMPのピクセルを代入。その際に、行を逆転する必要がある
for (int y=0; y<bmpihr.biHeight; y++){
for (int x=0; x<bmpihr.biWidth; x++){
blue = fgetc(fbmpr);
green = fgetc(fbmpr);
red = fgetc(fbmpr);
rd_bmp[((bmpihr.biHeight-1)-y)*bmpihr.biWidth+x] = (blue & 0xff) | ((green & 0xff)<<8) | ((red & 0xff)<<16);
}
}
fclose(fbmpr);
// ins に入力データを用意する
for(int i=0; i<5; i++){ // dummy data
pix.user = 0;
pix.data = i;
ins << pix;
}
for(int j=0; j < bmpihr.biHeight; j++){
for(int i=0; i < bmpihr.biWidth; i++){
pix.data = (ap_int<32>)rd_bmp[(j*bmpihr.biWidth)+i];
if (j==0 && i==0) // 最初のデータの時に TUSER を 1 にする
pix.user = 1;
else
pix.user = 0;
if (i == bmpihr.biWidth-1) // 行の最後でTLASTをアサートする
pix.last = 1;
else
pix.last = 0;
ins << pix;
ins_soft << pix;
}
}
lap_filter_axis(ins, outs);
lap_filter_axis_soft(ins_soft, outs_soft, bmpihr.biWidth, bmpihr.biHeight);
// ハードウェアとソフトウェアのラプラシアン・フィルタの値のチェック
cout << endl;
cout << "outs" << endl;
for(int j=0; j < bmpihr.biHeight; j++){
for(int i=0; i < bmpihr.biWidth; i++){
outs >> vals;
outs_soft >> vals_soft;
ap_int<32> val = vals.data;
ap_int<32> val_soft = vals_soft.data;
hw_lapd[(j*bmpihr.biWidth)+i] = (int)val;
if (val != val_soft){
printf("ERROR HW and SW results mismatch i = %ld, j = %ld, HW = %d, SW = %d\n", i, j, (int)val, (int)val_soft);
return(1);
}
}
}
cout << "Success HW and SW results match" << endl;
cout << endl;
// ハードウェアのラプラシアンフィルタの結果を temp_lap.bmp へ出力する
if ((fbmpw=fopen("temp_lap.bmp", "wb")) == NULL){
fprintf(stderr, "Can't open temp_lap.bmp by binary write mode\n");
exit(1);
}
// BMPファイルヘッダの書き込み
fwrite(&bmpfhr.bfType, sizeof(uint16_t), 1, fbmpw);
fwrite(&bmpfhr.bfSize, sizeof(uint32_t), 1, fbmpw);
fwrite(&bmpfhr.bfReserved1, sizeof(uint16_t), 1, fbmpw);
fwrite(&bmpfhr.bfReserved2, sizeof(uint16_t), 1, fbmpw);
fwrite(&bmpfhr.bfOffBits, sizeof(uint32_t), 1, fbmpw);
fwrite(&bmpihr, sizeof(BITMAPINFOHEADER), 1, fbmpw);
// RGB データの書き込み、逆順にする
for (int y=0; y<bmpihr.biHeight; y++){
for (int x=0; x<bmpihr.biWidth; x++){
blue = hw_lapd[((bmpihr.biHeight-1)-y)*bmpihr.biWidth+x] & 0xff;
green = (hw_lapd[((bmpihr.biHeight-1)-y)*bmpihr.biWidth+x] >> 8) & 0xff;
red = (hw_lapd[((bmpihr.biHeight-1)-y)*bmpihr.biWidth+x]>>16) & 0xff;
fputc(blue, fbmpw);
fputc(green, fbmpw);
fputc(red, fbmpw);
}
}
fclose(fbmpw);
free(rd_bmp);
free(hw_lapd);
return 0;
}
int lap_filter_axis_soft(hls::stream<ap_axis<32,1,1,1> >& ins, hls::stream<ap_axis<32,1,1,1> >& outs, int width, int height){
ap_axis<32,1,1,1> pix;
ap_axis<32,1,1,1> lap;
unsigned int **line_buf;
int pix_mat[3][3];
int lap_fil_val;
int i;
// line_buf の1次元目の配列をアロケートする
if ((line_buf =(unsigned int **)malloc(sizeof(unsigned int *) * 2)) == NULL){
fprintf(stderr, "Can't allocate line_buf[3][]\n");
exit(1);
}
// メモリをアロケートする
for (i=0; i<2; i++){
if ((line_buf[i]=(unsigned int *)malloc(sizeof(unsigned int) * width)) == NULL){
fprintf(stderr, "Can't allocate line_buf[%d]\n", i);
exit(1);
}
}
do { // user が 1になった時にフレームがスタートする
ins >> pix;
} while(pix.user == 0);
for (int y=0; y<height; y++){
for (int x=0; x<width; x++){
if (!(x==0 && y==0)) // 最初の入力はすでに入力されている
ins >> pix; // AXI4-Stream からの入力
for (int k=0; k<3; k++){
for (int m=0; m<2; m++){
pix_mat[k][m] = pix_mat[k][m+1];
}
}
pix_mat[0][2] = line_buf[0][x];
pix_mat[1][2] = line_buf[1][x];
int y_val = conv_rgb2y_soft(pix.data);
pix_mat[2][2] = y_val;
line_buf[0][x] = line_buf[1][x]; // 行の入れ替え
line_buf[1][x] = y_val;
lap_fil_val = laplacian_fil_soft( pix_mat[0][0], pix_mat[0][1], pix_mat[0][2],
pix_mat[1][0], pix_mat[1][1], pix_mat[1][2],
pix_mat[2][0], pix_mat[2][1], pix_mat[2][2]);
lap.data = (lap_fil_val<<16)+(lap_fil_val<<8)+lap_fil_val; // RGB同じ値を入れる
if (x<2 || y<2) // 最初の2行とその他の行の最初の2列は無効データなので0とする
lap.data = 0;
if (x==0 && y==0) // 最初のデータでは、TUSERをアサートする
lap.user = 1;
else
lap.user = 0;
if (x == (HORIZONTAL_PIXEL_WIDTH-1)) // 行の最後で TLAST をアサートする
lap.last = 1;
else
lap.last = 0;
outs << lap; // AXI4-Stream へ出力
}
}
for (i=0; i<2; i++)
free(line_buf[i]);
free(line_buf);
return 0;
}
// RGBからYへの変換
// RGBのフォーマットは、{8'd0, R(8bits), G(8bits), B(8bits)}, 1pixel = 32bits
// 輝度信号Yのみに変換する。変換式は、Y = 0.299R + 0.587G + 0.114B
// "YUVフォーマット及び YUV<->RGB変換"を参考にした。http://vision.kuee.kyoto-u.ac.jp/~hiroaki/firewire/yuv.html
// 2013/09/27 : float を止めて、すべてint にした
int conv_rgb2y_soft(int rgb){
int r, g, b, y_f;
int y;
b = rgb & 0xff;
g = (rgb>>8) & 0xff;
r = (rgb>>16) & 0xff;
y_f = 77*r + 150*g + 29*b; //y_f = 0.299*r + 0.587*g + 0.114*b;の係数に256倍した
y = y_f >> 8; // 256で割る
return(y);
}
// ラプラシアンフィルタ
// x0y0 x1y0 x2y0 -1 -1 -1
// x0y1 x1y1 x2y1 -1 8 -1
// x0y2 x1y2 x2y2 -1 -1 -1
int laplacian_fil_soft(int x0y0, int x1y0, int x2y0, int x0y1, int x1y1, int x2y1, int x0y2, int x1y2, int x2y2)
{
int y;
y = -x0y0 -x1y0 -x2y0 -x0y1 +8*x1y1 -x2y1 -x0y2 -x1y2 -x2y2;
if (y<0)
y = -y;
else if (y>255)
y = 255;
return(y);
}
#include <stdio.h>
#include <stdint.h>
#include <unistd.h>
#include "platform.h"
#include "xil_printf.h"
#include "xparameters.h"
int main()
{
volatile uint32_t *axi_gpio_0;
init_platform();
axi_gpio_0 = (volatile uint32_t *)XPAR_AXI_GPIO_0_BASEADDR;
print("Hello World\n\r");
print("Successfully ran Hello World application");
cleanup_platform();
for(int i=0; i<1000; i++){
axi_gpio_0[0] = 0;
usleep(500000); // 500 ms
axi_gpio_0[0] = 1;
usleep(500000); // 500 ms
}
return 0;
}
PS C:\Users\marse\Documents\HDL\ZynqBerryZero\zbzerodemo1> .\_create_win_setup.cmd
C:\Users\marse\Documents\HDL\ZynqBerryZero\zbzerodemo1>setlocal
------------------------Set design paths----------------------------
-- Run Design with: _create_win_setup
-- Use Design Path: C:\Users\marse\Documents\HDL\ZynqBerryZero\zbzerodemo1\
--------------------------------------------------------------------
-------------------------TE Reference Design---------------------------
--------------------------------------------------------------------
-- (c) Go to CMD-File Generation (Manual setup)
-- (d) Go to Documentation (Web Documentation)
-- (x) Exit Batch (nothing is done!)
-- (0) Module selection guide, project creation...prebuilt export...
-- (1) Create minimum setup of CMD-Files and exit Batch
-- (2) Create maximum setup of CMD-Files and exit Batch
-- (3) (internal only) Dev
-- (4) (internal only) Prod
----
Select (ex.:'0' for module selection guide):0
1 個のファイルをコピーしました。
1 個のファイルをコピーしました。
-----------------------------------------
--------------------------------------------------------------------
------------------Set Xilinx environment variables------------------
--Info: Configure Xilinx Vivado Settings --
--Excecute: C:/Xilinx\Vivado\2019.2\settings64.bat --
--Info: Configure Xilinx VITIS Settings --
--Excecute: C:/Xilinx\Vitis\2019.2\settings64.bat --
-----------------------------------------
--------------------------------------------------------------------
------------------Set Xilinx environment variables------------------
--Info: Configure Xilinx Vivado Settings --
--Excecute: C:/Xilinx\Vivado\2019.2\settings64.bat --
--Info: Configure Xilinx VITIS Settings --
--Excecute: C:/Xilinx\Vitis\2019.2\settings64.bat --
-----------------------------------------
-----------------------------------------
Use Xilinx installation from 'C:/Xilinx\Vivado\2019.2\'
1 個のファイルをコピーしました。
1 個のファイルをコピーしました。
----------------------check old project exists--------------------------
Start create project..."
----------------------Change to log folder--------------------------
C:\Users\marse\Documents\HDL\ZynqBerryZero\zbzerodemo1\v_log
--------------------------------------------------------------------
-------------------------Start VIVADO scripts -----------------------
-------------------------scripts finished----------------------------
--------------------------------------------------------------------
--------------------Change to design folder-------------------------
------------------------Design finished-----------------------------
---------------------------Minimal Setup----------------------------
--- 0. (optional) use "_use_viartual_drive.cm" , see Xilinx "AR# 52787"
--- Note:Use to reduce path length
--- 1. Open "design_basic_settings.cmd" with text editor
--- Note: "Module selection guide" modifies this file automatically
--- 1.1 Set Xilinx Installation path, default: @set XILDIR=C:/Xilinx
--- 1.2 Set the Board Part you bought, example: @set PARTNUMBER=2
--- For available names see: ./board_files/TExxxx_board_files.csv
--- 1.3 Save "design_basic_settings.cmd"
--- Create and open Vivado Project with batch files:
--- 2. To create vivado project, execute: ./vivado_create_project_guimode.cmd
--- Open existing Vivado Project with batch files:
--- 3. To open existing vivado project, execute: ./vivado_open_existing_project_guimode.cmd
--- Use Trenz Electronic Wiki for more information:
--- https://wiki.trenz-electronic.de/display/PD/Project+Delivery+-+Xilinx+devices
--- https://wiki.trenz-electronic.de/pages/viewpage.action?pageId=14746264
--------------------------------------------------------------------
------------------------------Finished------------------------------
--------------------------------------------------------------------
****** Vivado v2019.2 (64-bit)
**** SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019
**** IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
source ../scripts/script_main.tcl -notrace
-----------------------------------------------------------------------
INFO:(TE) Load Settings Script finished
INFO:(TE) Load environment script finished
INFO:(TE) Load Vivado script finished
INFO:(TE) Load Utilities script finished
INFO:(TE) Load Vivado script finished
INFO:(TE) Load Designs script finished
INFO:(TE) Load User Command scripts finished
INFO:(TE) Load SDSoC script finished
-----------------------------------------------------------------------
-----------------------------------------------------------------------
INFO: [TE_INIT-3] Initial project names and paths:
TE::VPROJ_NAME: zbzerodemo1
TE::VPROJ_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/vivado
TE::VLABPROJ_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/vivado_lab
TE::BOARDDEF_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/board_files
TE::FIRMWARE_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/firmware
TE::IP_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/ip_lib
TE::BD_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/block_design
TE::XDC_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/constraints
TE::HDL_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/hdl
TE::SET_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/settings
TE::WORKSPACE_HSI_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/workspace/hsi
TE::WORKSPACE_SDK_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/workspace/sdk
TE::LIB_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/sw_lib
TE::SCRIPT_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/scripts
TE::DOC_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/doc
TE::PREBUILT_BI_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/prebuilt/boot_images
TE::PREBUILT_HW_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/prebuilt/hardware
TE::PREBUILT_SW_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/prebuilt/software
TE::PREBUILT_OS_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/prebuilt/os
TE::PREBUILT_EXPORT_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/../export
TE::LOG_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/v_log
TE::BACKUP_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/backup
TE::ZIP_PATH: C:/Program Files/7-Zip/7z.exe
TE::XRT_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/xrt
TE::XRT_USED: false
TE::SDSOC_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/../SDSoC_PFM
TE::ADD_SD_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/misc/sd
TE::TMP_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/tmp
TE::XILINXGIT_DEVICETREE: B:/xilinx_git/device-tree-xlnx
TE::XILINXGIT_UBOOT:
TE::XILINXGIT_LINUX:
------
-----------------------------------------------------------------------
INFO:(TE) Parameter Index: 0
INFO:(TE) Parameter Option: --run_board_selection
-----------------------------------------------------------------------
INFO: [TE_INIT-89] Run TE::INIT::run_board_selection
INFO: [TE_INIT-182] Source C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/settings/design_settings.tcl.
INFO: [TE_INIT-0] Script Info:
Xilinx Directory: C:/Xilinx
Vivado Version: Vivado v2019.2 (64-bit)
TE Script Version: 2019.2.15
Board Part (Definition Files) CSV Version: 1.4
Software IP CSV Version: 2.3
Board Design Modify CSV Version: 1.1
ZIP ignore CSV Version: 1.0
---
Start project with: _create_win_setup
------
INFO: [TE_INIT-1] Script Environment:
Vivado Setting: 1
LabTools Setting: 0
VITIS Setting: 1
SDSOC Setting: 0
------
INFO: [TE_INIT-3] Initial project names and paths:
TE::VPROJ_NAME: zbzerodemo1
TE::VPROJ_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/vivado
TE::VLABPROJ_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/vivado_lab
TE::BOARDDEF_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/board_files
TE::FIRMWARE_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/firmware
TE::IP_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/ip_lib
TE::BD_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/block_design
TE::XDC_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/constraints
TE::HDL_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/hdl
TE::SET_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/settings
TE::WORKSPACE_HSI_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/workspace/hsi
TE::WORKSPACE_SDK_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/workspace/sdk
TE::LIB_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/sw_lib
TE::SCRIPT_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/scripts
TE::DOC_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/doc
TE::PREBUILT_BI_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/prebuilt/boot_images
TE::PREBUILT_HW_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/prebuilt/hardware
TE::PREBUILT_SW_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/prebuilt/software
TE::PREBUILT_OS_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/prebuilt/os
TE::PREBUILT_EXPORT_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/../export
TE::LOG_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/v_log
TE::BACKUP_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/backup
TE::ZIP_PATH: C:/Program Files/7-Zip/7z.exe
TE::XRT_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/xrt
TE::XRT_USED: false
TE::SDSOC_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/../SDSoC_PFM
TE::ADD_SD_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/misc/sd
TE::TMP_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/tmp
TE::XILINXGIT_DEVICETREE: B:/xilinx_git/device-tree-xlnx
TE::XILINXGIT_UBOOT:
TE::XILINXGIT_LINUX:
------
INFO: [TE_INIT-16] Read board part definition list (File C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/board_files/TE0727_board_files.csv).
INFO: [TE_INIT-18] Read Software list (File: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/sw_lib/apps_list.csv).
INFO: [TE_INIT-189] Software Definition CSV version passed
INFO: [TE_INIT-191] Software Definition CSV Version analyze platform table header
INFO: [TE_INIT-193] Software Definition CSV Version analyze bsp table header
INFO: [TE_INIT-197] Software Definition CSV Version analyze app table header
INFO: [TE_INIT-22] Read ZIP ignore list (File: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/sw_lib/apps_list.csv).
INFO: [TE_UTIL-2] Following block designs were found:
C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/block_design/zsys_bd.tcl
------
Last Input:<L>
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|ID |Product ID |SoC/FPGA Typ |SHORT DIR |PCB REV |DDR Size |Flash Size|EMMC Size |Others |Notes |
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|1 |TE0727-01-010-1C |xc7z010clg225-1 |10_512MB |REV01 |512MB |16MB |NA |NA |FSBL changes are need for I2C |
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|2 |TE0727-02-41C34 |xc7z010clg225-1 |10_512MB |REV02 |512MB |16MB |NA |NA | |
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------
For better table view please resize windows to full screen!
------------------------------------------------------------------------
------------------
Select Module will be done in 2 steps:
-----
Step 1: (select column filter):
-Change module list size (for small monitors only), press: 'full' or 'small'
-Display current module list, press: 'L' or 'l'
-Restore whole module list, press: 'R' or 'r'
-Reduce List by ID, press: 'ID' or 'id' or insert ID columns value directly(filter step is bypassed and id number is used)
-Reduce List by Article Number, press: 'AN' or 'an'
-Reduce List by SoC/FPGA, press: 'FPGA' or 'fpga'
-Reduce List by PCB REV, press: 'PCB' or 'pcb'
-Reduce List by DDR, press: 'DDR' or 'ddr'
-Reduce List by Flash, press: 'FLASH' or 'flash'
-Reduce List by EMMC, press: 'EMMC' or 'emmc'
-Reduce List by Others, press: 'OTHERS' or 'others'
-Reduce List by Notes, press: 'NOTES' or 'notes'
-Exit without selection, press: 'Q' or 'q'
-----------------------
Please Enter Option:
q
Exit
-----------------------------------------------------------------------
INFO: [Common 17-206] Exiting Vivado at Sat Dec 5 13:59:52 2020...
PS C:\Users\marse\Documents\HDL\ZynqBerryZero\zbzerodemo1> .\_create_win_setup.cmd
C:\Users\marse\Documents\HDL\ZynqBerryZero\zbzerodemo1>setlocal
------------------------Set design paths----------------------------
-- Run Design with: _create_win_setup
-- Use Design Path: C:\Users\marse\Documents\HDL\ZynqBerryZero\zbzerodemo1\
--------------------------------------------------------------------
-------------------------TE Reference Design---------------------------
--------------------------------------------------------------------
-- (c) Go to CMD-File Generation (Manual setup)
-- (d) Go to Documentation (Web Documentation)
-- (x) Exit Batch (nothing is done!)
-- (0) Module selection guide, project creation...prebuilt export...
-- (1) Create minimum setup of CMD-Files and exit Batch
-- (2) Create maximum setup of CMD-Files and exit Batch
-- (3) (internal only) Dev
-- (4) (internal only) Prod
----
Select (ex.:'0' for module selection guide):0
-----------------------------------------
--------------------------------------------------------------------
------------------Set Xilinx environment variables------------------
--Info: Configure Xilinx Vivado Settings --
--Excecute: C:/Xilinx\Vivado\2019.2\settings64.bat --
--Info: Configure Xilinx VITIS Settings --
--Excecute: C:/Xilinx\Vitis\2019.2\settings64.bat --
-----------------------------------------
--------------------------------------------------------------------
------------------Set Xilinx environment variables------------------
--Info: Configure Xilinx Vivado Settings --
--Excecute: C:/Xilinx\Vivado\2019.2\settings64.bat --
--Info: Configure Xilinx VITIS Settings --
--Excecute: C:/Xilinx\Vitis\2019.2\settings64.bat --
-----------------------------------------
-----------------------------------------
Use Xilinx installation from 'C:/Xilinx\Vivado\2019.2\'
1 個のファイルをコピーしました。
1 個のファイルをコピーしました。
----------------------check old project exists--------------------------
Start create project..."
----------------------Change to log folder--------------------------
C:\Users\marse\Documents\HDL\ZynqBerryZero\zbzerodemo1\v_log
--------------------------------------------------------------------
-------------------------Start VIVADO scripts -----------------------
-------------------------scripts finished----------------------------
--------------------------------------------------------------------
--------------------Change to design folder-------------------------
------------------------Design finished-----------------------------
---------------------------Minimal Setup----------------------------
--- 0. (optional) use "_use_viartual_drive.cm" , see Xilinx "AR# 52787"
--- Note:Use to reduce path length
--- 1. Open "design_basic_settings.cmd" with text editor
--- Note: "Module selection guide" modifies this file automatically
--- 1.1 Set Xilinx Installation path, default: @set XILDIR=C:/Xilinx
--- 1.2 Set the Board Part you bought, example: @set PARTNUMBER=2
--- For available names see: ./board_files/TExxxx_board_files.csv
--- 1.3 Save "design_basic_settings.cmd"
--- Create and open Vivado Project with batch files:
--- 2. To create vivado project, execute: ./vivado_create_project_guimode.cmd
--- Open existing Vivado Project with batch files:
--- 3. To open existing vivado project, execute: ./vivado_open_existing_project_guimode.cmd
--- Use Trenz Electronic Wiki for more information:
--- https://wiki.trenz-electronic.de/display/PD/Project+Delivery+-+Xilinx+devices
--- https://wiki.trenz-electronic.de/pages/viewpage.action?pageId=14746264
--------------------------------------------------------------------
------------------------------Finished------------------------------
--------------------------------------------------------------------
PS C:\Users\marse\Documents\HDL\ZynqBerryZero\zbzerodemo1> ls
ディレクトリ: C:\Users\marse\Documents\HDL\ZynqBerryZero\zbzerodemo1
Mode LastWriteTime Length Name
---- ------------- ------ ----
d----- 2020/12/05 13:49 block_design
d----- 2020/12/05 13:49 board_files
d----- 2020/12/05 13:49 console
d----- 2020/12/05 13:49 constraints
d----- 2020/12/05 13:49 doc
d----- 2020/12/05 13:49 ip_lib
d----- 2020/12/05 13:49 misc
d----- 2020/12/05 13:49 os
d----- 2020/12/05 13:49 prebuilt
d----- 2020/12/05 13:49 scripts
d----- 2020/12/05 13:49 settings
d----- 2020/12/05 13:49 sw_lib
d----- 2020/12/05 13:59 v_log
-a---- 2020/04/20 13:41 7590 design_basic_settings.cmd
-a---- 2020/04/20 13:41 4248 vivado_create_project_guimode.cmd
-a---- 2020/04/20 13:41 4073 vivado_open_existing_project_guimode.cmd
-a---- 2020/04/20 13:41 20075 _create_linux_setup.sh
-a---- 2020/05/05 15:22 26384 _create_win_setup.cmd
-a---- 2019/11/22 13:31 4157 _readme.txt
-a---- 2020/04/20 13:41 2754 _use_virtual_drive.cmd
PS C:\Users\marse\Documents\HDL\ZynqBerryZero\zbzerodemo1> .\vivado_create_project_guimode.cmd
C:\Users\marse\Documents\HDL\ZynqBerryZero\zbzerodemo1>setlocal
------------------------Set design paths----------------------------
-- Run Design with: vivado_create_project_guimode
-- Use Design Path: C:\Users\marse\Documents\HDL\ZynqBerryZero\zbzerodemo1\
---------------------Load basic design settings---------------------
-----------------------------------------
--------------------------------------------------------------------
------------------Set Xilinx environment variables------------------
--Info: Configure Xilinx Vivado Settings --
--Excecute: C:/Xilinx\Vivado\2019.2\settings64.bat --
--Info: Configure Xilinx VITIS Settings --
--Excecute: C:/Xilinx\Vitis\2019.2\settings64.bat --
--------------------------------------------------------------------
----------------------check old project exists--------------------------
Start create project..."
----------------------Change to log folder--------------------------
C:\Users\marse\Documents\HDL\ZynqBerryZero\zbzerodemo1\v_log
--------------------------------------------------------------------
-------------------------Start VIVADO scripts -----------------------
****** Vivado v2019.2 (64-bit)
**** SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019
**** IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
source ../scripts/script_main.tcl -notrace
-----------------------------------------------------------------------
INFO:(TE) Load Settings Script finished
INFO:(TE) Load environment script finished
INFO:(TE) Load Vivado script finished
INFO:(TE) Load Utilities script finished
INFO:(TE) Load Vivado script finished
INFO:(TE) Load Designs script finished
INFO:(TE) Load User Command scripts finished
INFO:(TE) Load SDSoC script finished
-----------------------------------------------------------------------
-----------------------------------------------------------------------
INFO: [TE_INIT-3] Initial project names and paths:
TE::VPROJ_NAME: zbzerodemo1
TE::VPROJ_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/vivado
TE::VLABPROJ_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/vivado_lab
TE::BOARDDEF_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/board_files
TE::FIRMWARE_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/firmware
TE::IP_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/ip_lib
TE::BD_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/block_design
TE::XDC_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/constraints
TE::HDL_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/hdl
TE::SET_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/settings
TE::WORKSPACE_HSI_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/workspace/hsi
TE::WORKSPACE_SDK_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/workspace/sdk
TE::LIB_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/sw_lib
TE::SCRIPT_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/scripts
TE::DOC_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/doc
TE::PREBUILT_BI_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/prebuilt/boot_images
TE::PREBUILT_HW_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/prebuilt/hardware
TE::PREBUILT_SW_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/prebuilt/software
TE::PREBUILT_OS_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/prebuilt/os
TE::PREBUILT_EXPORT_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/../export
TE::LOG_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/v_log
TE::BACKUP_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/backup
TE::ZIP_PATH: C:/Program Files/7-Zip/7z.exe
TE::XRT_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/xrt
TE::XRT_USED: false
TE::SDSOC_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/../SDSoC_PFM
TE::ADD_SD_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/misc/sd
TE::TMP_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/tmp
TE::XILINXGIT_DEVICETREE: B:/xilinx_git/device-tree-xlnx
TE::XILINXGIT_UBOOT:
TE::XILINXGIT_LINUX:
------
-----------------------------------------------------------------------
INFO:(TE) Parameter Index: 0
INFO:(TE) Parameter Option: --run
INFO:(TE) Parameter Option Value: 1
INFO:(TE) Parameter Index: 2
INFO:(TE) Parameter Option: --gui
INFO:(TE) Parameter Option Value: 1
INFO:(TE) Parameter Index: 4
INFO:(TE) Parameter Option: --clean
INFO:(TE) Parameter Option Value: 2
INFO:(TE) Parameter Index: 6
INFO:(TE) Parameter Option: --boardpart
INFO:(TE) Parameter Option Value: LAST_ID
-----------------------------------------------------------------------
INFO: [TE_INIT-129] Run TE::INIT::run_project LAST_ID 1 1 2
INFO: [TE_INIT-182] Source C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/settings/design_settings.tcl.
INFO: [TE_INIT-0] Script Info:
Xilinx Directory: C:/Xilinx
Vivado Version: Vivado v2019.2 (64-bit)
TE Script Version: 2019.2.15
Board Part (Definition Files) CSV Version: 1.4
Software IP CSV Version: 2.3
Board Design Modify CSV Version: 1.1
ZIP ignore CSV Version: 1.0
---
Start project with: vivado_create_project_guimode
------
INFO: [TE_INIT-1] Script Environment:
Vivado Setting: 1
LabTools Setting: 0
VITIS Setting: 1
SDSOC Setting: 0
------
INFO: [TE_INIT-3] Initial project names and paths:
TE::VPROJ_NAME: zbzerodemo1
TE::VPROJ_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/vivado
TE::VLABPROJ_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/vivado_lab
TE::BOARDDEF_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/board_files
TE::FIRMWARE_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/firmware
TE::IP_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/ip_lib
TE::BD_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/block_design
TE::XDC_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/constraints
TE::HDL_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/hdl
TE::SET_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/settings
TE::WORKSPACE_HSI_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/workspace/hsi
TE::WORKSPACE_SDK_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/workspace/sdk
TE::LIB_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/sw_lib
TE::SCRIPT_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/scripts
TE::DOC_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/doc
TE::PREBUILT_BI_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/prebuilt/boot_images
TE::PREBUILT_HW_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/prebuilt/hardware
TE::PREBUILT_SW_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/prebuilt/software
TE::PREBUILT_OS_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/prebuilt/os
TE::PREBUILT_EXPORT_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/../export
TE::LOG_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/v_log
TE::BACKUP_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/backup
TE::ZIP_PATH: C:/Program Files/7-Zip/7z.exe
TE::XRT_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/xrt
TE::XRT_USED: false
TE::SDSOC_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/../SDSoC_PFM
TE::ADD_SD_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/misc/sd
TE::TMP_PATH: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/tmp
TE::XILINXGIT_DEVICETREE: B:/xilinx_git/device-tree-xlnx
TE::XILINXGIT_UBOOT:
TE::XILINXGIT_LINUX:
------
INFO: [TE_INIT-16] Read board part definition list (File C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/board_files/TE0727_board_files.csv).
INFO: [TE_INIT-18] Read Software list (File: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/sw_lib/apps_list.csv).
INFO: [TE_INIT-189] Software Definition CSV version passed
INFO: [TE_INIT-191] Software Definition CSV Version analyze platform table header
INFO: [TE_INIT-193] Software Definition CSV Version analyze bsp table header
INFO: [TE_INIT-197] Software Definition CSV Version analyze app table header
INFO: [TE_INIT-22] Read ZIP ignore list (File: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/sw_lib/apps_list.csv).
Found ID: 2
Board part csv name check: 2 is unique on position 0.
INFO: [TE_INIT-4] Board Part definition:
TE::ID: 2
TE::PRODID: TE0727-02-41C34
TE::PARTNAME: xc7z010clg225-1
TE::BOARDPART: trenz.biz:te0727_10_1c:part0:1.0
TE::SHORTDIR: 10_512MB
TE::ZYNQFLASHTYP: qspi-x4-single
TE::FPGAFLASHTYP: s25fl128s-3.3v-qspi-x4-single
TE::PCB_REV: REV02
TE::DDR_SIZE: 512MB
TE::FLASH_SIZE: 16MB
TE::EMMC_SIZE: NA
TE::OTHERS: NA
TE::NOTES:
------
Generate new project (Path: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/vivado).
INFO: [TE_INIT-69] Set Board Definition path: C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/board_files
create_project: Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 439.430 ; gain = 137.789
INFO: [TE_INIT-70] Set IP path : C:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/ip_lib
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Users/marse/Documents/HDL/ZynqBerryZero/zbzerodemo1/ip_lib'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2019.2/data/ip'.
Start GUI...all other messages will be print inside the GUI TCL console of Vivado
になっていた。#! /bin/sh
じゃないのということで、変更した。#! /bin/bash
を選択し、0 を入力した。(0) Module selection guide, project creation...
-- Run Design with: _create_linux_setup.sh
-- Use Design Path: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1
---------------------Load basic design settings---------------------
-- 2019.2 -- 2019.2
-----------------------------------------
Use Xilinx installation from '/opt/Xilinx'
--------------------------------------------------------------------
------------------Set Xilinx environment variables------------------
-- Use Xilinx Version: 2019.2 --
--Info: Configure Xilinx Vivado Settings --
-- Critical Warning: /opt/Xilinx/Vivado/2019.2/.settings64-Vivado.sh not found --
--Info: Configure Xilinx Vitis Settings --
-- Critical Warning: /opt/Xilinx/Vitis/2019.2/.settings64-Vitis.sh not found --
--Info: Configure Xilinx LabTools Settings --
-- Note : /opt/Xilinx/Vivado_Lab/2019.2/.settings64.sh not found --
--------------------------------------------------------------------
-- Error: Need Vivado to run. --
---------------------------Error occurs-----------------------------
--------------------------------------------------------------------
---------------------------Minimal Setup----------------------------
--- 1. Open design_basic_settings.sh with text editor
--- -- Note: Module selection guide modifies this file automatically
--- 1.1 Set Xilinx Installation path, default: XILDIR=/opt/Xilinx/
--- 1.2 Set the Board Part you bought, example: PARTNUMBER=te0726-3m
--- --- For available names see: ./board_files/TExxxx_board_files.csv
--- 1.3 Save design_basic_settings.sh
--- Create and open Vivado Project with batch files:
--- 2. To create vivado project, execute: ./vivado_create_project_guimode.sh
--- Open existing Vivado Project with batch files:
--- 3. To open existing vivado project, execute: ./vivado_open_existing_project_guimode.sh
--- Use Trenz Electronic Wiki for more information:
--- https://wiki.trenz-electronic.de/display/PD/Project+Delivery
--------------------------------------------------------------------
Press [Enter] key to continue...
./_create_linux_setup.sh
------------------------Set design paths----------------------------
-- Run Design with: _create_linux_setup.sh
-- Use Design Path: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1
--------------------------------------------------------------------
------------------------TE Reference Design-------------------------
--------------------------------------------------------------------
-- (c) Go to CMD-File Generation (Manual setup)
-- (d) Go to Documentation (Web Documentation)
-- (x) Exit Batch (nothing is done!)
-- (0) Module selection guide, project creation...
-- (1) Create minimum setup of CMD-Files and exit Batch
-- (2) Create maximum setup of CMD-Files and exit Batch
----
Select (ex.:'0' for module selection guide):
0
-- Run Design with: _create_linux_setup.sh
-- Use Design Path: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1
---------------------Load basic design settings---------------------
-- 2019.2 -- 2019.2
-----------------------------------------
Use Xilinx installation from '/media/masaaki/Ubuntu_Disk/tools/Xilinx'
--------------------------------------------------------------------
------------------Set Xilinx environment variables------------------
-- Use Xilinx Version: 2019.2 --
--Info: Configure Xilinx Vivado Settings --
--Info: Configure Xilinx Vitis Settings --
--------------------------------------------------------------------
----------------------check old project exists--------------------------
----------------------Change to log folder--------------------------
/media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/v_log
--------------------------------------------------------------------
-------------------------Start VIVADO scripts -----------------------
****** Vivado v2019.2 (64-bit)
**** SW Build 2700185 on Thu Oct 24 18:45:48 MDT 2019
**** IP Build 2699827 on Thu Oct 24 21:16:38 MDT 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
source ../scripts/script_main.tcl -notrace
-----------------------------------------------------------------------
INFO:(TE) Load Settings Script finished
INFO:(TE) Load environment script finished
INFO:(TE) Load Vivado script finished
INFO:(TE) Load Utilities script finished
INFO:(TE) Load Vivado script finished
INFO:(TE) Load Designs script finished
INFO:(TE) Load User Command scripts finished
INFO:(TE) Load SDSoC script finished
-----------------------------------------------------------------------
-----------------------------------------------------------------------
INFO: [TE_INIT-3] Initial project names and paths:
TE::VPROJ_NAME: zbzerodemo1
TE::VPROJ_PATH: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/vivado
TE::VLABPROJ_PATH: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/vivado_lab
TE::BOARDDEF_PATH: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/board_files
TE::FIRMWARE_PATH: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/firmware
TE::IP_PATH: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/ip_lib
TE::BD_PATH: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/block_design
TE::XDC_PATH: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/constraints
TE::HDL_PATH: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/hdl
TE::SET_PATH: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/settings
TE::WORKSPACE_HSI_PATH: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/workspace/hsi
TE::WORKSPACE_SDK_PATH: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/workspace/sdk
TE::LIB_PATH: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/sw_lib
TE::SCRIPT_PATH: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/scripts
TE::DOC_PATH: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/doc
TE::PREBUILT_BI_PATH: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/prebuilt/boot_images
TE::PREBUILT_HW_PATH: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/prebuilt/hardware
TE::PREBUILT_SW_PATH: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/prebuilt/software
TE::PREBUILT_OS_PATH: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/prebuilt/os
TE::PREBUILT_EXPORT_PATH: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/../export
TE::LOG_PATH: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/v_log
TE::BACKUP_PATH: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/backup
TE::ZIP_PATH: /usr/bin/zip
TE::XRT_PATH: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/xrt
TE::XRT_USED: false
TE::SDSOC_PATH: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/../SDSoC_PFM
TE::ADD_SD_PATH: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/misc/sd
TE::TMP_PATH: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/tmp
TE::XILINXGIT_DEVICETREE: /home/xilinx_git/device-tree-xlnx
TE::XILINXGIT_UBOOT:
TE::XILINXGIT_LINUX:
------
-----------------------------------------------------------------------
INFO:(TE) Parameter Index: 0
INFO:(TE) Parameter Option: --run_board_selection
-----------------------------------------------------------------------
INFO: [TE_INIT-89] Run TE::INIT::run_board_selection
INFO: [TE_INIT-182] Source /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/settings/design_settings.tcl.
INFO: [TE_INIT-0] Script Info:
Xilinx Directory: /media/masaaki/Ubuntu_Disk/tools/Xilinx
Vivado Version: Vivado v2019.2 (64-bit)
TE Script Version: 2019.2.15
Board Part (Definition Files) CSV Version: 1.4
Software IP CSV Version: 2.3
Board Design Modify CSV Version: 1.1
ZIP ignore CSV Version: 1.0
---
Start project with: Unknown
------
INFO: [TE_INIT-1] Script Environment:
Vivado Setting: 1
LabTools Setting: 0
VITIS Setting: 1
SDSOC Setting: 0
------
INFO: [TE_INIT-3] Initial project names and paths:
TE::VPROJ_NAME: zbzerodemo1
TE::VPROJ_PATH: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/vivado
TE::VLABPROJ_PATH: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/vivado_lab
TE::BOARDDEF_PATH: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/board_files
TE::FIRMWARE_PATH: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/firmware
TE::IP_PATH: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/ip_lib
TE::BD_PATH: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/block_design
TE::XDC_PATH: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/constraints
TE::HDL_PATH: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/hdl
TE::SET_PATH: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/settings
TE::WORKSPACE_HSI_PATH: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/workspace/hsi
TE::WORKSPACE_SDK_PATH: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/workspace/sdk
TE::LIB_PATH: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/sw_lib
TE::SCRIPT_PATH: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/scripts
TE::DOC_PATH: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/doc
TE::PREBUILT_BI_PATH: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/prebuilt/boot_images
TE::PREBUILT_HW_PATH: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/prebuilt/hardware
TE::PREBUILT_SW_PATH: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/prebuilt/software
TE::PREBUILT_OS_PATH: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/prebuilt/os
TE::PREBUILT_EXPORT_PATH: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/../export
TE::LOG_PATH: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/v_log
TE::BACKUP_PATH: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/backup
TE::ZIP_PATH: /usr/bin/zip
TE::XRT_PATH: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/xrt
TE::XRT_USED: false
TE::SDSOC_PATH: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/../SDSoC_PFM
TE::ADD_SD_PATH: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/misc/sd
TE::TMP_PATH: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/tmp
TE::XILINXGIT_DEVICETREE: /home/xilinx_git/device-tree-xlnx
TE::XILINXGIT_UBOOT:
TE::XILINXGIT_LINUX:
------
INFO: [TE_INIT-16] Read board part definition list (File /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/board_files/TE0727_board_files.csv).
INFO: [TE_INIT-18] Read Software list (File: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/sw_lib/apps_list.csv).
INFO: [TE_INIT-189] Software Definition CSV version passed
INFO: [TE_INIT-191] Software Definition CSV Version analyze platform table header
INFO: [TE_INIT-193] Software Definition CSV Version analyze bsp table header
INFO: [TE_INIT-197] Software Definition CSV Version analyze app table header
INFO: [TE_INIT-22] Read ZIP ignore list (File: /media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/sw_lib/apps_list.csv).
INFO: [TE_UTIL-2] Following block designs were found:
/media/masaaki/Ubuntu_Disk/ZynqBerryZero/zbzerodemo1/block_design/zsys_bd.tcl
------
Last Input:<L>
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|ID |Product ID |SoC/FPGA Typ |SHORT DIR |PCB REV |DDR Size |Flash Size|EMMC Size |Others |Notes |
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|1 |TE0727-01-010-1C |xc7z010clg225-1 |10_512MB |REV01 |512MB |16MB |NA |NA |FSBL changes are need for I2C |
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|2 |TE0727-02-41C34 |xc7z010clg225-1 |10_512MB |REV02 |512MB |16MB |NA |NA | |
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------
For better table view please resize windows to full screen!
------------------------------------------------------------------------
------------------
Select Module will be done in 2 steps:
-----
Step 1: (select column filter):
-Change module list size (for small monitors only), press: 'full' or 'small'
-Display current module list, press: 'L' or 'l'
-Restore whole module list, press: 'R' or 'r'
-Reduce List by ID, press: 'ID' or 'id' or insert ID columns value directly(filter step is bypassed and id number is used)
-Reduce List by Article Number, press: 'AN' or 'an'
-Reduce List by SoC/FPGA, press: 'FPGA' or 'fpga'
-Reduce List by PCB REV, press: 'PCB' or 'pcb'
-Reduce List by DDR, press: 'DDR' or 'ddr'
-Reduce List by Flash, press: 'FLASH' or 'flash'
-Reduce List by EMMC, press: 'EMMC' or 'emmc'
-Reduce List by Others, press: 'OTHERS' or 'others'
-Reduce List by Notes, press: 'NOTES' or 'notes'
-Exit without selection, press: 'Q' or 'q'
-----------------------
Please Enter Option:
q
Exit
-----------------------------------------------------------------------
INFO: [Common 17-206] Exiting Vivado at Sat Dec 5 04:56:12 2020...
-------------------------scripts finished----------------------------
--------------------------------------------------------------------
--------------------Change to design folder-------------------------
------------------------Design finished-----------------------------
ERROR:(TE) Read Parameter failed
{
"target" : "DPUCZDX8G",
"dcf" : "./dpu-06-18-2020-12-00.dcf",
"cpu_arch" : "arm64"
}
に変更した。ARCH=./u96v2.json
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